/*
 * Copyright (c) 2003, 2019, Oracle and/or its affiliates. All rights reserved.
 * Copyright 2007, 2009 Red Hat, Inc.
 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
 *
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 * published by the Free Software Foundation.
 *
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
 * You should have received a copy of the GNU General Public License version
 * 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef CPU_ZERO_ICACHE_ZERO_HPP
#define CPU_ZERO_ICACHE_ZERO_HPP

// Interface for updating the instruction cache.  Whenever the VM
// modifies code, part of the processor instruction cache potentially
// has to be flushed.  This implementation is empty: Zero never deals
// with code.

class ICache : public AbstractICache {
 public:
  static void initialize(int phase) {}
  static void invalidate_word(address addr) {}
  static void invalidate_range(address start, int nbytes) {}
};

#endif // CPU_ZERO_ICACHE_ZERO_HPP