)]}'
{
  "commit": "0c24dec550ddb7d86b8bfdd8645b18479f73e6e2",
  "tree": "96f0477552ff68214b03adb54ff14152220ea239",
  "parents": [
    "d65e34d12514de2bbe3b8f519761d641c081bad0"
  ],
  "author": {
    "name": "Felix Radensky",
    "email": "felix@embedded-sol.com",
    "time": "Sun May 31 20:44:15 2009 +0300"
  },
  "committer": {
    "name": "Ben Warren",
    "email": "biggerbadderben@gmail.com",
    "time": "Mon Jun 08 22:57:21 2009 -0700"
  },
  "message": "ppc4xx/net: Fix MDIO clock setup\n\nThis patch fixes MDIO clock setup in case when OPB frequency is 100MHz.\nCurrent code assumes that the value of sysinfo.freqOPB is 100000000\nwhen OPB frequency is 100MHz. In reality it is 100000001. As a result\nMDIO clock is set to incorrect value, larger than 2.5MHz, thus violating\nthe standard. This in not a problem on boards equipped with Marvell PHYs\n(e.g. Canyonlands), since those PHYs support MDIO clocks up to 8.3MHz,\nbut can be a problem for other PHYs (e.g. Realtek ones).\n\nSigned-off-by: Felix Radensky \u003cfelix@embedded-sol.com\u003e\nSigned-off-by: Ben Warren \u003cbiggerbadderben@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "918373bd1f77b899ac162175e9f23c73291e999c",
      "old_mode": 33188,
      "old_path": "drivers/net/4xx_enet.c",
      "new_id": "7bf3e0a96d1a032f486531d8da3659af8f9ea1c8",
      "new_mode": 33188,
      "new_path": "drivers/net/4xx_enet.c"
    }
  ]
}