)]}'
{
  "commit": "14f73ca679f6fdb44cff0b7304d419db41a0ab69",
  "tree": "632812cee1bce6fcd1acd604a0c901d34f21b12d",
  "parents": [
    "c664bf8c3c9bb9e236891f0d8dfda883e86d159b"
  ],
  "author": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Wed Mar 26 10:14:11 2008 +0100"
  },
  "committer": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Thu Mar 27 10:12:07 2008 +0100"
  },
  "message": "ppc: Add CFG_MEM_TOP_HIDE option to hide memory area that doesn\u0027t get \"touched\"\n\nIf CFG_MEM_TOP_HIDE is defined in the board config header, this specified\nmemory area will get subtracted from the top (end) of ram and won\u0027t get\n\"touched\" at all by U-Boot. By fixing up gd-\u003eram_size the Linux kernel\nshould gets passed the now \"corrected\" memory size and won\u0027t touch it\neither. This should work for arch/ppc and arch/powerpc. Only Linux board\nports in arch/powerpc with bootwrapper support, which recalculate the\nmemory size from the SDRAM controller setup, will have to get fixed\nin Linux additionally.\n\nThis patch enables this config option on some PPC440EPx boards as a workaround\nfor the CHIP 11 errata. Here the description from the AMCC documentation:\n\nCHIP_11: End of memory range area restricted access.\nCategory: 3\n\nOverview:\nThe 440EPx DDR controller does not acknowledge any\ntransaction which is determined to be crossing over the\nend-of-memory-range boundary, even if the starting address is\nwithin valid memory space. Any such transaction from any PLB4\nmaster will result in a PLB time-out on PLB4 bus.\n\nImpact:\nIn case of such misaligned bursts, PLB4 masters will not\nretrieve any data at all, just the available data up to the\nend of memory, especially the 440 CPU. For example, if a CPU\ninstruction required an operand located in memory within the\nlast 7 words of memory, the DCU master would burst read 8\nwords to update the data cache and cross over the\nend-of-memory-range boundary. Such a DCU read would not be\nanswered by the DDR controller, resulting in a PLB4 time-out\nand ultimately in a Machine Check interrupt. The data would\nbe inaccessible to the CPU.\n\nWorkaround:\nForbid any application to access the last 256 bytes of DDR\nmemory. For example, make your operating system believe that\nthe last 256 bytes of DDR memory are absent. AMCC has a patch\nthat does this, available for Linux.\n\nThis patch sets CFG_MEM_TOP_HIDE for the following 440EPx boards:\nlwmon5, korat, sequoia\n\nThe other remaining 440EPx board were intentionally not included\nsince it is not clear to me, if they use the end of ram for some\nother purpose. This is unclear, since these boards have CONFIG_PRAM\ndefined and even comments like this:\n\nPMC440.h:\n/* esd expects pram at end of physical memory.\n * So no logbuffer at the moment.\n */\n\nIt is strongly recommended to not use the last 256 bytes on those\nboards too. Patches from the board maintainers are welcome.\n\nSigned-off-by: Stefan Roese \u003csr@denx.de\u003e\n",
  "tree_diff": [
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    },
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      "new_path": "include/configs/korat.h"
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      "old_path": "include/configs/lwmon5.h",
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      "new_path": "include/configs/lwmon5.h"
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      "old_mode": 33188,
      "old_path": "include/configs/sequoia.h",
      "new_id": "555316ff63811598d64e6f365cd8c7330fd564d9",
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      "new_path": "include/configs/sequoia.h"
    },
    {
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      "old_id": "30383027c78d33d310c9468340ec635d7c4aed4a",
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      "old_path": "lib_ppc/board.c",
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      "new_path": "lib_ppc/board.c"
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}