)]}'
{
  "commit": "1e41f5ad455e75d3985a0e4670ba1338c2e8faca",
  "tree": "48c3538f33268a49e35268dc9b05416e1995d050",
  "parents": [
    "3620f860eff02722aa559e568f4ca87f4c304901"
  ],
  "author": {
    "name": "Anton Staaf",
    "email": "robotboy@chromium.org",
    "time": "Mon Oct 17 16:46:13 2011 -0700"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Sun Oct 23 20:50:43 2011 +0200"
  },
  "message": "cache: include asm/cache.h for ARCH_DMA_MINALIGN definition\n\nARCH_DMA_MINALIGN will be used to allocate DMA buffers that are\naligned correctly.  In all current cases this means that the DMA\nbuffer will be aligned to at least the L1 data cache line size of\nthe configured architecture.  If the board configuration file\ndoes not specify the architecture L1 data cache line size then the\nmaximum line size of the architecture is used to align DMA buffers.\n\nSigned-off-by: Anton Staaf \u003crobotboy@chromium.org\u003e\nCc: Mike Frysinger \u003cvapier@gentoo.org\u003e\nCc: Lukasz Majewski \u003cl.majewski@samsung.com\u003e\nCc: Wolfgang Denk \u003cwd@denx.de\u003e\nCc: Stefano Babic \u003csbabic@denx.de\u003e\nCc: Ilya Yanok \u003cyanok@emcraft.com\u003e\nCc: Laurence Withers \u003clwithers@guralp.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ccd3dd785af7bba27808838424f61e7c5c56f132",
      "old_mode": 33188,
      "old_path": "include/common.h",
      "new_id": "db1c7d0f51356f6d388560adbfdff47db2ce5d02",
      "new_mode": 33188,
      "new_path": "include/common.h"
    }
  ]
}