)]}'
{
  "commit": "21fae8b2b4e4e6e648796e07e20ab13e9cb18923",
  "tree": "280445d2d3f54d770a75c717247f6d014afb7fd4",
  "parents": [
    "347b7938d3e561eb215aa386c37fb5acb5a383c6"
  ],
  "author": {
    "name": "Andy Fleming",
    "email": "afleming@freescale.com",
    "time": "Wed Feb 27 14:29:58 2008 -0600"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Wed Feb 27 16:28:48 2008 -0600"
  },
  "message": "Invalidate INIT_RAM TLB mappings\n\nCommit 0db37dc...  (and some others) changed the INIT_RAM TLB\nmappings to be unguarded.  This collided with an existing \"bug\"\nwhere the mappings for the INIT_RAM were being kept around.\nThis meant that speculative loads to those addresses were\nsucceeding in the TLB, and going out to the bus, where they\nwere causing an exception (there\u0027s nothing at that address). The\nFlash code was coincidentally causing such a speculative load.\nRather than go back to mapping the INIT RAM as guarded, we fix\nit so that the entries for the INIT_RAM are invalidated.  Thus\nthe speculative loads will fail in the TLB, and have no effect.\n\nSigned-off-by: Andy Fleming \u003cafleming@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "eb24dbc430715294feea0aeac3aa49a864f0ca2c",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/start.S",
      "new_id": "636ef5da63f296046e9c2eeb67a342f1d69f79f5",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/start.S"
    }
  ]
}