)]}'
{
  "commit": "22ff3d01348e0a2dc369b7efcbac30e4ce86d178",
  "tree": "e3ed66edb226e004cc85cdc4d4a966c55ce4f141",
  "parents": [
    "80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106"
  ],
  "author": {
    "name": "Dave Liu",
    "email": "daveliu@freescale.com",
    "time": "Fri Nov 21 16:31:29 2008 +0800"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Fri Jan 23 17:03:13 2009 -0600"
  },
  "message": "fsl-ddr: clean up the ddr code for DDR3 controller\n\n- The DDR3 controller is expanding the bits for timing config\n- Add the DDR3 32-bit bus mode support\n\nSigned-off-by: Dave Liu \u003cdaveliu@freescale.com\u003e\nAcked-by: Andy Fleming \u003cafleming@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d5cdc362f2791d722887e60495e34fa99de00bfb",
      "old_mode": 33188,
      "old_path": "cpu/mpc8xxx/ddr/ctrl_regs.c",
      "new_id": "eae794c76f44f177880ae2f7c7fac78658d09b59",
      "new_mode": 33188,
      "new_path": "cpu/mpc8xxx/ddr/ctrl_regs.c"
    },
    {
      "type": "modify",
      "old_id": "c1ea7cd6bb16a3ff3ec68fa951e28f04dee6fbd5",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/fsl_ddr_sdram.h",
      "new_id": "0006c21a0236be5ff600f7a7ef3caad19df76a3e",
      "new_mode": 33188,
      "new_path": "include/asm-ppc/fsl_ddr_sdram.h"
    }
  ]
}