)]}'
{
  "commit": "2c451f7831208741d0ff7ca6046cffcd9ee49def",
  "tree": "ec885d6ce9bc97eca3128e83e9af35c5b063ffe1",
  "parents": [
    "4c93da7c392737f2036130c240e2b4bea773d703"
  ],
  "author": {
    "name": "Aneesh V",
    "email": "aneesh@ti.com",
    "time": "Thu Jun 16 23:30:47 2011 +0000"
  },
  "committer": {
    "name": "Albert ARIBAUD",
    "email": "albert.u.boot@aribaud.net",
    "time": "Mon Jul 04 10:55:25 2011 +0200"
  },
  "message": "armv7: cache maintenance operations for armv7\n\n- Add a framework for layered cache maintenance\n\t- separate out SOC specific outer cache maintenance from\n\t  maintenance of caches known to CPU\n\n- Add generic ARMv7 cache maintenance operations that affect all\n  caches known to ARMv7 CPUs. For instance in Cortex-A8 these\n  opertions will affect both L1 and L2 caches. In Cortex-A9\n  these will affect only L1 cache\n\n- D-cache operations supported:\n\t- Invalidate entire D-cache\n\t- Invalidate D-cache range\n\t- Flush(clean \u0026 invalidate) entire D-cache\n\t- Flush D-cache range\n- I-cache operations supported:\n\t- Invalidate entire I-cache\n\n- Add maintenance functions for TLB, branch predictor array etc.\n\n- Enable -march\u003darmv7-a so that armv7 assembly instructions can be\n  used\n\nSigned-off-by: Aneesh V \u003caneesh@ti.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a760cf356757493230009118e2248b5acf8dd3dc",
      "old_mode": 33188,
      "old_path": "README",
      "new_id": "7ee16323d1c0c814085f1569058d52705b60c202",
      "new_mode": 33188,
      "new_path": "README"
    },
    {
      "type": "modify",
      "old_id": "8c0e9150037714ddd07eb12fc2cd8b03787d73ec",
      "old_mode": 33188,
      "old_path": "arch/arm/cpu/armv7/Makefile",
      "new_id": "299792ac5a1b50d30c639ef568c270c34b34ec81",
      "new_mode": 33188,
      "new_path": "arch/arm/cpu/armv7/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "3e1e1bf8779bc5d88eb5e9c8e9b67159c0962099",
      "new_mode": 33188,
      "new_path": "arch/arm/cpu/armv7/cache_v7.c"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "88b9c62dd3d873a29cbc8fcd0ecb7b535f6daa1a",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/armv7.h"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "828b86cb360ca69864f2a992583571898f1d9d05",
      "new_mode": 33188,
      "new_path": "arch/arm/include/asm/utils.h"
    },
    {
      "type": "modify",
      "old_id": "1e21b7a3d5c39ebee1ad6491c75055bc01f6d41a",
      "old_mode": 33188,
      "old_path": "include/common.h",
      "new_id": "2c8513ae18d1f29d2aff2758dc4af51007c73b1c",
      "new_mode": 33188,
      "new_path": "include/common.h"
    }
  ]
}