)]}'
{
  "commit": "32c8cfb23cd8beb814edd217c02e6aa5c7a64acf",
  "tree": "f7ce54174e4505b24df46aad21aa0dbbca53bacd",
  "parents": [
    "2a9fab82b74d59aa9150e905aa06a6bff32c5059"
  ],
  "author": {
    "name": "Priyanka Jain",
    "email": "Priyanka.Jain@freescale.com",
    "time": "Wed Feb 09 09:24:10 2011 +0530"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Sun Apr 10 11:17:55 2011 -0500"
  },
  "message": "fsl_esdhc: Deal with watermark level register related changes\n\nP1010 and P1014 has v2.3 version of FSL eSDHC controller in which watermark\nlevel register description has been changed:\n\n9-15 bits represent WR_WML[0:6], Max value \u003d 128 represented by 0x00\n25-31 bits represent RD_WML[0:6], Max value \u003d 128 represented by 0x00\n\nSigned-off-by: Priyanka Jain \u003cPriyanka.Jain@freescale.com\u003e\nSigned-off-by: Poonam Aggrwal \u003cPoonam.Aggrwal@freescale.com\u003e\nTested-by: Stefano Babic \u003csbabic@denx.de\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "59aeb31087ff5831c5f10f1c34830346c038b232",
      "old_mode": 33188,
      "old_path": "arch/powerpc/include/asm/config_mpc85xx.h",
      "new_id": "41fd86c4e222bf648a910b01a0dc93cdd1ffaea0",
      "new_mode": 33188,
      "new_path": "arch/powerpc/include/asm/config_mpc85xx.h"
    },
    {
      "type": "modify",
      "old_id": "0962ac4476aaef82b51616c08add152330fccb78",
      "old_mode": 33188,
      "old_path": "drivers/mmc/fsl_esdhc.c",
      "new_id": "4f1b5150c942b7d64d435c677a58aed75cfef051",
      "new_mode": 33188,
      "new_path": "drivers/mmc/fsl_esdhc.c"
    },
    {
      "type": "modify",
      "old_id": "477bbd792e81f4066c4f6d0b4239d798f82afc28",
      "old_mode": 33188,
      "old_path": "include/fsl_esdhc.h",
      "new_id": "8418bf7f47aa177af9bcd029276646c5525e15b9",
      "new_mode": 33188,
      "new_path": "include/fsl_esdhc.h"
    }
  ]
}