)]}'
{
  "commit": "33f57bd553edf29dffef5a6c7d76e169c79a6049",
  "tree": "cae931b06803cf6ff873209a52e5e7dd706beb26",
  "parents": [
    "060f28532b09dd3d2c78423bdd809ac768a27629"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Fri Mar 26 15:14:43 2010 -0500"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Tue Mar 30 10:48:30 2010 -0500"
  },
  "message": "85xx: Fix enabling of L1 cache parity on secondary cores\n\nUse the same code between primary and secondary cores to init the\nL1 cache.  We were not enabling cache parity on the secondary cores.\n\nAlso, reworked the L1 cache init code to match the e500mc L2 init code\nthat first invalidates the cache and locks.  Than enables the cache and\nmakes sure its enabled before continuing.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
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      "old_path": "cpu/mpc85xx/release.S",
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      "new_path": "cpu/mpc85xx/release.S"
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      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/start.S"
    },
    {
      "type": "modify",
      "old_id": "c6da4116308c28c1cb198eb30b7c75b7ebdfe267",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/processor.h",
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      "new_mode": 33188,
      "new_path": "include/asm-ppc/processor.h"
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}