)]}'
{
  "commit": "3c2a67eec8a0facc865b400caca52e7f6b7adf01",
  "tree": "131a11003534635f5ae7a948ee4202e1e2d1c711",
  "parents": [
    "7e4259bba4c56536760e42d32dacfb3233f216fd"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Sep 17 01:52:37 2009 -0500"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Sep 24 12:05:29 2009 -0500"
  },
  "message": "ppc/p4080: Handle timebase enabling and frequency reporting\n\nOn CoreNet style platforms the timebase frequency is the bus frequency\ndefined by 16 (on PQ3 it is divide by 8).  Also on the CoreNet platforms\nthe core not longer controls the enabling of the timebase.  We now need\nto enable the boot core\u0027s timebase via CCSR register writes.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "bdd9ee4c83348ec8ba018373d7c529bddb36e667",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/cpu.c",
      "new_id": "25c04169fd940aa6f31e8c3584f0a1ff5b8bd746",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/cpu.c"
    },
    {
      "type": "modify",
      "old_id": "a8d83b1c8a3d73f4c000beee5a8ca2ff981a6a45",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/cpu_init.c",
      "new_id": "53369349d13a3d19fd2adc83ee58c4941b69e77a",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/cpu_init.c"
    },
    {
      "type": "modify",
      "old_id": "61e0fb0636dc78b14374217a8c852933c0e852d3",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/fdt.c",
      "new_id": "efb651882260266dafcd1328a9c80272e178c6f3",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/fdt.c"
    }
  ]
}