)]}'
{
  "commit": "54652991caedc39b2ec2e5b49e750669bfcd1e2e",
  "tree": "1b85ac8491f1394a9ff10bef4de7074f39520076",
  "parents": [
    "70084df7125a0b67de707b999982ec67adfdc35c"
  ],
  "author": {
    "name": "Philippe De Muyter",
    "email": "phdm@macqel.be",
    "time": "Tue Aug 17 18:40:25 2010 +0200"
  },
  "committer": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Wed Aug 18 09:09:00 2010 +0200"
  },
  "message": "Work around bug in Numonyx P33/P30 256-Mbit 65nm flash chips.\n\nI have \"ported\" U-boot to a in house made board with Numonyx Axcell P33/P30\n256-Mbit 65nm flash chips.\n\nAfter some time :( searching for bugs in our board or soft, we have\ndiscovered that those chips have a small but annoying bug, documented in\n\"Numonyx Axcell P33/P30 256-Mbit Specification Update\"\n\nIt states :\nWhen customer uses [...] block unlock, the block lock status might be\naltered inadvertently. Lock status might be set to either 01h or 03h\nunexpectedly (00h as expected data), which leads to program/erase failure\non certain blocks.\n\nA working workaround is given, which I have applied and tested with success :\n\nWorkaround:  If the interval between 60h and its subsequent command\n\t     can be guaranteed within 20us, Option I is recommended,\n\t     otherwise Option II (involves hardware) should be selected.\nOption I: The table below lists the detail command sequences:\nCommand\n\t      Data bus           Address bus       Remarks\nSequence\n  1              90h            Block Address\n\t\t\t\t\t\t   Read Lock Status\n  2             Read         Block Address + 02h\n (2)(3)                                      (1)\n3                60h           Block Address\n (2)(3)                                      (1)   Lock/Unlock/RCR Configuration\n4           D0h/01h/03h        Block Address\nNotes:\n(1) Block Address refers to RCR configuration data only when the 60h\n    command sequence is used to set RCR register combined with 03h\n    subsequent command.\n(2) For the third and fourth command sequences, the Block Address must\n    be the same.\n(3) The interval between 60h command and its subsequent D0h/01h/2Fh/03h\n    commands should be less than 20us.\n\nAnd here is a log comparison of a simple (destructive) flash test without\nand with the workaround.\n\n diff without-numonyx-workaround.log with-numonyx-workaround.log\n -U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:07:47)\n +U-Boot 2010.06-00696-g22b002c-dirty (Aug 16 2010 - 15:25:19)\n\n  CPU:   Freescale MCF5484\n         CPU CLK 200 MHz BUS CLK 100 MHz\n  Board: Macq Electronique ME2060\n  I2C:   ready\n  DRAM:  64 MiB\n  FLASH: 32 MiB\n  In:    serial\n  Out:   serial\n  Err:   serial\n  Net:   FEC0, FEC1\n  -\u003e flinfo\n\n  Bank # 1: CFI conformant FLASH (16 x 16)  Size: 32 MB in 259 Sectors\n    Intel Extended command set, Manufacturer ID: 0x89, Device ID: 0x8922\n    Erase timeout: 4096 ms, write timeout: 1 ms\n    Buffer write timeout: 5 ms, buffer size: 1024 bytes\n\n    Sector Start Addresses:\n    FE000000 RO   FE008000 RO   FE010000 RO   FE018000 RO   FE020000 RO\n    FE040000 RO   FE060000 RO   FE080000 RO   FE0A0000 RO   FE0C0000 RO\n    ...\n    FFF80000 RO   FFFA0000 RO   FFFC0000 RO   FFFE0000 RO\n  -\u003e protect off all\n  Un-Protect Flash Bank # 1\n  ................... done\n  -\u003e erase all\n  Erase Flash Bank # 1\n  ................... done\n  -\u003e cp.b 1000000 fe000000 2000000\n -Copy to Flash... Flash not Erased\n +Copy to Flash... done\n  -\u003e\n\nSigned-off-by: Philippe De Muyter \u003cphdm@macqel.be\u003e\nSigned-off-by: Stefan Roese \u003csr@denx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1191ef02f80b3ed5647e5aea1efb4c8dd66b2cc4",
      "old_mode": 33188,
      "old_path": "drivers/mtd/cfi_flash.c",
      "new_id": "44ebb9d06aadca4898cf97f85c40e36b57dbf3c2",
      "new_mode": 33188,
      "new_path": "drivers/mtd/cfi_flash.c"
    }
  ]
}