)]}'
{
  "commit": "59d63f7d2cad78382574beea01c85cbca96925df",
  "tree": "9f562e244aca6609ba2bb01358189f4658dcde57",
  "parents": [
    "5675b509165b67465a20e5cf71e07f40b449ef0c"
  ],
  "author": {
    "name": "Stephen Warren",
    "email": "swarren@wwwdotorg.org",
    "time": "Sat Sep 01 16:27:56 2012 +0000"
  },
  "committer": {
    "name": "Tom Rini",
    "email": "trini@ti.com",
    "time": "Tue Sep 25 13:27:58 2012 -0700"
  },
  "message": "ARM: arm1176: Define arch_cpu_init() at the SoC level\n\nCommit 86c6326 \"ARM: arm1176: enable instruction cache in\narch_cpu_init()\" defined arch_cpu_init() in a file that is shared across\nall arm1176 SoCs. tnetv107x already implemented this function, which\ncaused linking to break. Move the new conflicting arch_cpu_init() into\narm1176/bcm2835/init.c so that it doesn\u0027t conflict; grep indicates this\nfunction is usually defined at the SoC-level, not the CPU-level, at least\nfor ARM.\n\nSigned-off-by: Stephen Warren \u003cswarren@wwwdotorg.org\u003e\nAcked-by: Marek Vasut \u003cmarex@denx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "4ea6d6b89ffb470ed2ad63e39ea89dc9c787db82",
      "old_mode": 33188,
      "old_path": "arch/arm/cpu/arm1176/bcm2835/Makefile",
      "new_id": "95da6a822a113bd24afa09f01d10fa86de838c64",
      "new_mode": 33188,
      "new_path": "arch/arm/cpu/arm1176/bcm2835/Makefile"
    },
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "e90d3bba1f9246350afb427a92dd35d761e7dbb7",
      "new_mode": 33188,
      "new_path": "arch/arm/cpu/arm1176/bcm2835/init.c"
    },
    {
      "type": "modify",
      "old_id": "532a90b546f838dbc6df1e8491f6f7749c3c401d",
      "old_mode": 33188,
      "old_path": "arch/arm/cpu/arm1176/cpu.c",
      "new_id": "c0fd114e16305fab9f5f5f9aa688b5396ad9efd4",
      "new_mode": 33188,
      "new_path": "arch/arm/cpu/arm1176/cpu.c"
    }
  ]
}