)]}'
{
  "commit": "64852d09e06dd6db2b2db2a3c59bc2db176a54d6",
  "tree": "9a55c856efb307be7fd5a95432f0f3c79ce9191c",
  "parents": [
    "8a24c07ba5da2c72ad1f05e3eb8a463750200c98"
  ],
  "author": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Mon Jun 02 14:35:44 2008 +0200"
  },
  "committer": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Tue Jun 03 20:21:49 2008 +0200"
  },
  "message": "ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.S\n\nThis patch consolidates the 405 and 440 parts of the NAND booting code\nselected via CONFIG_NAND_SPL. Now common code is used to initialize the\nSDRAM by calling initdram() and to \"copy/relocate\" to SDRAM/OCM/etc.\nOnly *after* running from this location, nand_boot() is called.\n\nPlease note that the initsdram() call is now moved from nand_boot.c\nto start.S. I experienced problems with some boards like Kilauea\n(405EX), which don\u0027t have internal SRAM (OCM) and relocation needs to\nbe done to SDRAM before the NAND controller can get accessed. When\ninitdram() is called later on in nand_boot(), this can lead to problems\nwith variables in the bss sections like nand_ecc_pos[].\n\nSigned-off-by: Stefan Roese \u003csr@denx.de\u003e\nAcked-by: Scott Wood \u003cscottwood@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a5d9ec96e0decb354fdba92075c7f868da547fff",
      "old_mode": 33188,
      "old_path": "cpu/ppc4xx/start.S",
      "new_id": "25ee36932f963ba3806a56c65906172d35ede557",
      "new_mode": 33188,
      "new_path": "cpu/ppc4xx/start.S"
    },
    {
      "type": "modify",
      "old_id": "bc577252cf754fe695e5061ce51da6fd13104390",
      "old_mode": 33188,
      "old_path": "nand_spl/nand_boot.c",
      "new_id": "563a80b9537705e88019c582c0fdb4e2072490e1",
      "new_mode": 33188,
      "new_path": "nand_spl/nand_boot.c"
    }
  ]
}