)]}'
{
  "commit": "6677876181cc8772bca8a372479a500d160f3993",
  "tree": "47919055c6d6de9e7a0a84c922a13d0161c394b2",
  "parents": [
    "8b34557c546e5e9f34ebf83c93413dad973d93df"
  ],
  "author": {
    "name": "Scott Wood",
    "email": "scottwood@freescale.com",
    "time": "Tue Jan 20 11:56:11 2009 -0600"
  },
  "committer": {
    "name": "Kim Phillips",
    "email": "kim.phillips@freescale.com",
    "time": "Wed Jan 21 18:43:57 2009 -0600"
  },
  "message": "83xx: Use the proper sequence for updating IMMR.\n\nThis ensures that subsequent accesses properly hit the new window.\n\nThe dcbi during the NAND loop was accidentally working around this;\nit\u0027s no longer necessary, as the cache is not enabled.\n\nReported-by: Suchit Lepcha \u003cSuchit.Lepcha@freescale.com\u003e\nSigned-off-by: Scott Wood \u003cscottwood@freescale.com\u003e\nSigned-off-by: Kim Phillips \u003ckim.phillips@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "beebc9951c5fe2ea48927214c142e38e915fa175",
      "old_mode": 33188,
      "old_path": "cpu/mpc83xx/start.S",
      "new_id": "26e31061f41f268ecf65cdc082398fd844aa10ea",
      "new_mode": 33188,
      "new_path": "cpu/mpc83xx/start.S"
    }
  ]
}