diff --git a/cpu/arm_cortexa8/cpu.c b/cpu/arm_cortexa8/cpu.c
index ad2085b..506dbec 100644
--- a/cpu/arm_cortexa8/cpu.c
+++ b/cpu/arm_cortexa8/cpu.c
@@ -34,6 +34,7 @@
 #include <common.h>
 #include <command.h>
 #include <asm/arch/sys_proto.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_USE_IRQ
 DECLARE_GLOBAL_DATA_PTR;
@@ -45,27 +46,6 @@
 
 static void cache_flush(void);
 
-/* read co-processor 15, register #1 (control register) */
-static unsigned long read_p15_c1(void)
-{
-	unsigned long value;
-
-	__asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\
-			     @ read control reg\n":"=r"(value)
-			     ::"memory");
-	return value;
-}
-
-/* write to co-processor 15, register #1 (control register) */
-static void write_p15_c1(unsigned long value)
-{
-	__asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\
-			     @ write it back\n"::"r"(value)
-			     : "memory");
-
-	read_p15_c1();
-}
-
 static void cp_delay(void)
 {
 	/* Many OMAP regs need at least 2 nops */
@@ -73,18 +53,6 @@
 	asm("nop");
 }
 
-/* See also ARM Ref. Man. */
-#define C1_MMU		(1<<0)	/* mmu off/on */
-#define C1_ALIGN	(1<<1)	/* alignment faults off/on */
-#define C1_DC		(1<<2)	/* dcache off/on */
-#define C1_WB		(1<<3)	/* merging write buffer on/off */
-#define C1_BIG_ENDIAN	(1<<7)	/* big endian off/on */
-#define C1_SYS_PROT	(1<<8)	/* system protection */
-#define C1_ROM_PROT	(1<<9)	/* ROM protection */
-#define C1_IC		(1<<12)	/* icache off/on */
-#define C1_HIGH_VECTORS	(1<<13)	/* location of vectors: low/high addresses */
-#define RESERVED_1	(0xf << 3)	/* must be 111b for R/W */
-
 int cpu_init(void)
 {
 	/*
@@ -147,27 +115,27 @@
 {
 	ulong reg;
 
-	reg = read_p15_c1();	/* get control reg. */
+	reg = get_cr();	/* get control reg. */
 	cp_delay();
-	write_p15_c1(reg | C1_IC);
+	set_cr(reg | CR_I);
 }
 
 void icache_disable(void)
 {
 	ulong reg;
 
-	reg = read_p15_c1();
+	reg = get_cr();
 	cp_delay();
-	write_p15_c1(reg & ~C1_IC);
+	set_cr(reg & ~CR_I);
 }
 
 void dcache_disable (void)
 {
 	ulong reg;
 
-	reg = read_p15_c1 ();
+	reg = get_cr ();
 	cp_delay ();
-	write_p15_c1 (reg & ~C1_DC);
+	set_cr (reg & ~CR_C);
 }
 
 void l2cache_enable()
@@ -231,7 +199,7 @@
 
 int icache_status(void)
 {
-	return (read_p15_c1() & C1_IC) != 0;
+	return (get_cr() & CR_I) != 0;
 }
 
 static void cache_flush(void)