diff --git a/board/AtmarkTechno/suzaku/flash.c b/board/AtmarkTechno/suzaku/flash.c
index 49a0673..ce6fae0 100644
--- a/board/AtmarkTechno/suzaku/flash.c
+++ b/board/AtmarkTechno/suzaku/flash.c
@@ -24,7 +24,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 unsigned long flash_init(void)
 {
diff --git a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
index 39c97b1..d509a8f 100644
--- a/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
+++ b/board/BuS/EB+MCF-EV123/EB+MCF-EV123.c
@@ -32,7 +32,7 @@
 int checkboard (void)
 {
 	puts ("Board: MCF-EV1 + MCF-EV23 (BuS Elektronik GmbH & Co. KG)\n");
-#if (TEXT_BASE ==  CFG_INT_FLASH_BASE)
+#if (TEXT_BASE ==  CONFIG_SYS_INT_FLASH_BASE)
 	puts ("       Boot from Internal FLASH\n");
 #endif
 
@@ -45,10 +45,10 @@
 
 	size = 0;
 	MCFSDRAMC_DCR = MCFSDRAMC_DCR_RTIM_6
-			| MCFSDRAMC_DCR_RC ((15 * CFG_CLK) >> 4);
-#ifdef CFG_SDRAM_BASE0
+			| MCFSDRAMC_DCR_RC ((15 * CONFIG_SYS_CLK) >> 4);
+#ifdef CONFIG_SYS_SDRAM_BASE0
 
-	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE0)
+	MCFSDRAMC_DACR0 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE0)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -57,17 +57,17 @@
 
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE0) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE0) = 0xA5A5;
 	MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 	mbar_writeLong (MCFSDRAMC_DACR0,
 			mbar_readLong (MCFSDRAMC_DACR0) | MCFSDRAMC_DACR_IMRS);
-	*(unsigned int *) (CFG_SDRAM_BASE0 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE * 1024 * 1024;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE0 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 #endif
-#ifdef CFG_SDRAM_BASE1
-	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CFG_SDRAM_BASE1)
+#ifdef CONFIG_SYS_SDRAM_BASE1
+	MCFSDRAMC_DACR1 = MCFSDRAMC_DACR_BASE (CONFIG_SYS_SDRAM_BASE1)
 			| MCFSDRAMC_DACR_CASL (1)
 			| MCFSDRAMC_DACR_CBM (3)
 			| MCFSDRAMC_DACR_PS_16;
@@ -76,25 +76,25 @@
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IP;
 
-	*(unsigned short *) (CFG_SDRAM_BASE1) = 0xA5A5;
+	*(unsigned short *) (CONFIG_SYS_SDRAM_BASE1) = 0xA5A5;
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_RE;
 
 	for (i = 0; i < 2000; i++)
 		asm (" nop");
 
 	MCFSDRAMC_DACR1 |= MCFSDRAMC_DACR_IMRS;
-	*(unsigned int *) (CFG_SDRAM_BASE1 + 0x220) = 0xA5A5;
-	size += CFG_SDRAM_SIZE1 * 1024 * 1024;
+	*(unsigned int *) (CONFIG_SYS_SDRAM_BASE1 + 0x220) = 0xA5A5;
+	size += CONFIG_SYS_SDRAM_SIZE1 * 1024 * 1024;
 #endif
 	return size;
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
diff --git a/board/BuS/EB+MCF-EV123/VCxK.c b/board/BuS/EB+MCF-EV123/VCxK.c
index 4b46b7c..f2fe353 100644
--- a/board/BuS/EB+MCF-EV123/VCxK.c
+++ b/board/BuS/EB+MCF-EV123/VCxK.c
@@ -25,7 +25,7 @@
 #include <asm/m5282.h>
 #include "VCxK.h"
 
-vu_char *vcxk_bws = (vu_char *)(CFG_CS3_BASE);
+vu_char *vcxk_bws = (vu_char *)(CONFIG_SYS_CS3_BASE);
 #define VCXK_BWS vcxk_bws
 
 static ulong vcxk_driver;
diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.c b/board/BuS/EB+MCF-EV123/cfm_flash.c
index 98e563f..fe03b17 100644
--- a/board/BuS/EB+MCF-EV123/cfm_flash.c
+++ b/board/BuS/EB+MCF-EV123/cfm_flash.c
@@ -28,14 +28,14 @@
 
 #if defined(CONFIG_M5281) || defined(CONFIG_M5282)
 
-#if (CFG_CLK>20000000)
-	#define CFM_CLK  (((long) CFG_CLK / (400000 * 8) + 1) | 0x40)
+#if (CONFIG_SYS_CLK>20000000)
+	#define CFM_CLK  (((long) CONFIG_SYS_CLK / (400000 * 8) + 1) | 0x40)
 #else
-	#define CFM_CLK  ((long) CFG_CLK / 400000 + 1)
+	#define CFM_CLK  ((long) CONFIG_SYS_CLK / 400000 + 1)
 #endif
 
 #define cmf_backdoor_address(addr)	(((addr) & 0x0007FFFF) | 0x04000000 | \
-					 (CFG_MBAR & 0xC0000000))
+					 (CONFIG_SYS_MBAR & 0xC0000000))
 
 void cfm_flash_print_info (flash_info_t * info)
 {
@@ -60,8 +60,8 @@
 	MCFCFM_MCR = 0;
 	MCFCFM_CLKD = CFM_CLK;
 	debug ("CFM Clock divider: %ld (%d Hz @ %ld Hz)\n",CFM_CLK,\
-		CFG_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
-		CFG_CLK);
+		CONFIG_SYS_CLK / (2* ((CFM_CLK & 0x3F)+1) * (1+((CFM_CLK & 0x40)>>6)*7)),\
+		CONFIG_SYS_CLK);
 	MCFCFM_SACC = 0;
 	MCFCFM_DACC = 0;
 
@@ -86,7 +86,7 @@
 	{
 		if (sector == 0)
 		{
-			info->start[sector] = CFG_INT_FLASH_BASE;
+			info->start[sector] = CONFIG_SYS_INT_FLASH_BASE;
 		}
 		else
 		{
@@ -187,7 +187,7 @@
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int cfm_flash_protect(flash_info_t * info,long sector,int prot)
 {
diff --git a/board/BuS/EB+MCF-EV123/cfm_flash.h b/board/BuS/EB+MCF-EV123/cfm_flash.h
index cc8cdbd..ed4e794 100644
--- a/board/BuS/EB+MCF-EV123/cfm_flash.h
+++ b/board/BuS/EB+MCF-EV123/cfm_flash.h
@@ -33,7 +33,7 @@
 extern int cfm_flash_erase_sector (flash_info_t * info, int sector);
 extern void cfm_flash_init (flash_info_t * info);
 extern int cfm_flash_write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt);
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 extern int cfm_flash_protect(flash_info_t * info,long sector,int prot);
 #endif
 
diff --git a/board/BuS/EB+MCF-EV123/flash.c b/board/BuS/EB+MCF-EV123/flash.c
index c2a1b6f..3c36367 100644
--- a/board/BuS/EB+MCF-EV123/flash.c
+++ b/board/BuS/EB+MCF-EV123/flash.c
@@ -27,10 +27,10 @@
 #include <common.h>
 #include  "cfm_flash.h"
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -83,7 +83,7 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		switch (i)
@@ -93,8 +93,8 @@
 				(AMD_MANUFACT & FLASH_VENDMASK) |
 				(AMD_ID_LV160B & FLASH_TYPEMASK);
 			flash_info[i].size = FLASH_BANK_SIZE;
-			flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-			memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+			flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+			memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 			flashbase = PHYS_FLASH_1;
 			for (j = 0; j < flash_info[i].sector_count; j++) {
 				if (j == 0) {
@@ -128,8 +128,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0xffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0xffff, &flash_info[0]);
 
 	return size;
 }
@@ -177,7 +177,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 			state = ERR_TIMOUT;
 		}
@@ -303,7 +303,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				state = ERR_TIMOUT;
 		}
 		if (!state && ((result & BIT_RDY_MASK) == (data & BIT_RDY_MASK)))
@@ -390,7 +390,7 @@
 	return rc;
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 
 int flash_real_protect(flash_info_t * info,long sector,int prot)
 {
diff --git a/board/BuS/EB+MCF-EV123/mii.c b/board/BuS/EB+MCF-EV123/mii.c
index 8ae2ec6..7f92514 100644
--- a/board/BuS/EB+MCF-EV123/mii.c
+++ b/board/BuS/EB+MCF-EV123/mii.c
@@ -38,15 +38,15 @@
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 	} else {
 		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 	}
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -132,9 +132,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -199,7 +199,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/LEOX/elpt860/elpt860.c b/board/LEOX/elpt860/elpt860.c
index 5f50631..905df92 100644
--- a/board/LEOX/elpt860/elpt860.c
+++ b/board/LEOX/elpt860/elpt860.c
@@ -138,23 +138,23 @@
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PC4    0x0800
+#define CONFIG_SYS_PC4    0x0800
 
-#define CFG_DS1    CFG_PC4
+#define CONFIG_SYS_DS1    CONFIG_SYS_PC4
 
 /*
  * Very early board init code (fpga boot, etc.)
  */
 int board_early_init_f (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Light up the red led on ELPT860 pcb (DS1) (PCDAT)
 	 */
-	immr->im_ioport.iop_pcdat &= ~CFG_DS1;	/* PCDAT (DS1 = 0)                */
-	immr->im_ioport.iop_pcpar &= ~CFG_DS1;	/* PCPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_pcdir |= CFG_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_pcdat &= ~CONFIG_SYS_DS1;	/* PCDAT (DS1 = 0)                */
+	immr->im_ioport.iop_pcpar &= ~CONFIG_SYS_DS1;	/* PCPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_DS1;	/* PCDIR (I/O: 0=input, 1=output) */
 
 	return (0);		/* success */
 }
@@ -181,7 +181,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -207,7 +207,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	/*
 	 * The following value is used as an address (i.e. opcode) for
@@ -229,10 +229,10 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -252,7 +252,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -260,7 +260,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE1_PRELIM, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns       */
@@ -269,7 +269,7 @@
 	} else {		/* back to 8 columns                      */
 
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 		/* debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20); */
 	}
@@ -282,22 +282,22 @@
 	 */
 	if (size_b0 < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping: map bigger bank first
 	 */
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	{
 		unsigned long reg;
 
 		/* adjust refresh rate depending on SDRAM type, one bank */
 		reg = memctl->memc_mptpr;
-		reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+		reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 		memctl->memc_mptpr = reg;
 	}
 
@@ -319,7 +319,7 @@
 static long int
 dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -329,20 +329,20 @@
 
 /* ------------------------------------------------------------------------- */
 
-#define CFG_PA1     0x4000
-#define CFG_PA2     0x2000
+#define CONFIG_SYS_PA1     0x4000
+#define CONFIG_SYS_PA2     0x2000
 
-#define CFG_LBKs    (CFG_PA2 | CFG_PA1)
+#define CONFIG_SYS_LBKs    (CONFIG_SYS_PA2 | CONFIG_SYS_PA1)
 
 void reset_phy (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Ensure LBK LXT901 ethernet 1 & 2 = 0 ... for normal loopback in effect
 	 *                                          and no AUI loopback
 	 */
-	immr->im_ioport.iop_padat &= ~CFG_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
-	immr->im_ioport.iop_papar &= ~CFG_LBKs;	/* PAPAR (0=general purpose I/O)  */
-	immr->im_ioport.iop_padir |= CFG_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
+	immr->im_ioport.iop_padat &= ~CONFIG_SYS_LBKs;	/* PADAT (LBK eth 1&2 = 0)        */
+	immr->im_ioport.iop_papar &= ~CONFIG_SYS_LBKs;	/* PAPAR (0=general purpose I/O)  */
+	immr->im_ioport.iop_padir |= CONFIG_SYS_LBKs;	/* PADIR (I/O: 0=input, 1=output) */
 }
diff --git a/board/LEOX/elpt860/flash.c b/board/LEOX/elpt860/flash.c
index 668aee2..9a75aad 100644
--- a/board/LEOX/elpt860/flash.c
+++ b/board/LEOX/elpt860/flash.c
@@ -33,7 +33,7 @@
 /*
 ** Note 1: In this file, you have to provide the following variable:
 ** ------
-**              flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]
+**              flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]
 ** 'flash_info_t' structure is defined into 'include/flash.h'
 ** and defined as extern into 'common/cmd_flash.c'
 **
@@ -62,10 +62,10 @@
 
 
 #ifndef	CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Internal Functions
@@ -82,13 +82,13 @@
 unsigned long
 flash_init (void)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile memctl8xx_t *memctl = &immap->im_memctl;
   unsigned long         size_b0;
   int i;
 
   /* Init: no FLASHes known */
-  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
     {
       flash_info[i].flash_id = FLASH_UNKNOWN;
     }
@@ -105,20 +105,20 @@
     }
 
   /* Remap FLASH according to real size */
-  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_PS_8 | BR_V;
 
   /* Re-do sizing to get full correct info */
-  size_b0 = flash_get_size ((volatile unsigned char *)CFG_FLASH_BASE,
+  size_b0 = flash_get_size ((volatile unsigned char *)CONFIG_SYS_FLASH_BASE,
 			    &flash_info[0]);
 
-  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
   /* monitor protection ON by default */
   flash_protect (FLAG_PROTECT_SET,
-		 CFG_MONITOR_BASE,
-		 CFG_MONITOR_BASE + monitor_flash_len-1,
+		 CONFIG_SYS_MONITOR_BASE,
+		 CONFIG_SYS_MONITOR_BASE + monitor_flash_len-1,
 		 &flash_info[0]);
 #endif
 
@@ -383,7 +383,7 @@
   addr = (volatile unsigned char *)(info->start[l_sect]);
   while ( (addr[0] & 0x80) != 0x80 )
     {
-      if ( (now = get_timer(start)) > CFG_FLASH_ERASE_TOUT )
+      if ( (now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT )
 	{
 	  printf ("Timeout\n");
 	  return ( 1 );
@@ -556,7 +556,7 @@
   start = get_timer (0);
   while ( (*((vu_long *)dest) & 0x00800080) != (data & 0x00800080) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}
@@ -602,7 +602,7 @@
   start = get_timer (0);
   while ( (*((volatile unsigned char *)dest) & 0x80) != (data & 0x80) )
     {
-      if ( get_timer(start) > CFG_FLASH_WRITE_TOUT )
+      if ( get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT )
 	{
 	  return (1);
 	}
diff --git a/board/MAI/AmigaOneG3SE/cmd_boota.c b/board/MAI/AmigaOneG3SE/cmd_boota.c
index 40c951d..949af18 100644
--- a/board/MAI/AmigaOneG3SE/cmd_boota.c
+++ b/board/MAI/AmigaOneG3SE/cmd_boota.c
@@ -27,7 +27,7 @@
 
 int do_boota (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-	unsigned char *load_address = (unsigned char *) CFG_LOAD_ADDR;
+	unsigned char *load_address = (unsigned char *) CONFIG_SYS_LOAD_ADDR;
 	unsigned char *base_address;
 	unsigned long offset;
 
diff --git a/board/MAI/AmigaOneG3SE/flash.c b/board/MAI/AmigaOneG3SE/flash.c
index 409b955..a96d5ba 100644
--- a/board/MAI/AmigaOneG3SE/flash.c
+++ b/board/MAI/AmigaOneG3SE/flash.c
@@ -1,14 +1,14 @@
 #include <common.h>
 #include <flash.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 unsigned long flash_init(void)
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;
diff --git a/board/MAI/AmigaOneG3SE/flash_new.c b/board/MAI/AmigaOneG3SE/flash_new.c
index 3efee7e..7b7ea16 100644
--- a/board/MAI/AmigaOneG3SE/flash_new.c
+++ b/board/MAI/AmigaOneG3SE/flash_new.c
@@ -39,7 +39,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static ulong flash_get_size (ulong addr, flash_info_t *info);
 static int flash_get_offsets (ulong base, flash_info_t *info);
@@ -80,7 +80,7 @@
 {
     int i;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
 	flash_info[i].sector_count = 0;
@@ -101,25 +101,25 @@
 	flash_to_xd();
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = 0;
 		flash_info[i].size = 0;
 	}
 
-	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
 
-	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
 
 	DEBUGF("## Flash bank size: %08lx\n", flash_size);
 
 	if (flash_size) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
-    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 
@@ -286,10 +286,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if (! flash_get_offsets (addr, info)) {
@@ -418,10 +418,10 @@
 	last  = start;
 	addr = info->start[l_sect];
 
-	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
 
 	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			flash_reset (info->start[0]);
 			flash_to_mem();
@@ -562,7 +562,7 @@
 		/* data polling for D7 */
 		start = get_timer (0);
 		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flash_reset (addr);
 				flash_to_mem();
 				return (1);
diff --git a/board/MAI/AmigaOneG3SE/i8259.h b/board/MAI/AmigaOneG3SE/i8259.h
index 05c4052..eb08e13 100644
--- a/board/MAI/AmigaOneG3SE/i8259.h
+++ b/board/MAI/AmigaOneG3SE/i8259.h
@@ -21,20 +21,20 @@
  * MA 02111-1307 USA
  */
 
-#define ICW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
-#define ICW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
-#define ICW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
-#define ICW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
-#define ICW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
-#define ICW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
-#define ICW4_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
-#define ICW4_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
-#define OCW1_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
-#define OCW1_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
-#define OCW2_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
-#define OCW2_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
-#define OCW3_1  CFG_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
-#define OCW3_2  CFG_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
+#define ICW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW1
+#define ICW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW1
+#define ICW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW2
+#define ICW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW2
+#define ICW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW3
+#define ICW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW3
+#define ICW4_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_ICW4
+#define ICW4_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_ICW4
+#define OCW1_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW1
+#define OCW1_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW1
+#define OCW2_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW2
+#define OCW2_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW2
+#define OCW3_1  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT1_OCW3
+#define OCW3_2  CONFIG_SYS_ISA_IO_BASE_ADDRESS + ISA_INT2_OCW3
 
 #define IMR_1   OCW1_1
 #define IMR_2   OCW1_2
diff --git a/board/MAI/AmigaOneG3SE/interrupts.c b/board/MAI/AmigaOneG3SE/interrupts.c
index 86b4415..de46d6e 100644
--- a/board/MAI/AmigaOneG3SE/interrupts.c
+++ b/board/MAI/AmigaOneG3SE/interrupts.c
@@ -119,12 +119,12 @@
 #ifdef DEBUG
 	puts("interrupt_init: setting decrementer_count\n");
 #endif
-	decrementer_count = get_tbclk() / CFG_HZ;
+	decrementer_count = get_tbclk() / CONFIG_SYS_HZ;
 
 #ifdef DEBUG
 	puts("interrupt_init: setting actual decremter\n");
 #endif
-	set_dec (get_tbclk() / CFG_HZ);
+	set_dec (get_tbclk() / CONFIG_SYS_HZ);
 
 #ifdef DEBUG
 	puts("interrupt_init: clearing external interrupt table\n");
diff --git a/board/MAI/AmigaOneG3SE/ps2kbd.c b/board/MAI/AmigaOneG3SE/ps2kbd.c
index 724a44d..a297005 100644
--- a/board/MAI/AmigaOneG3SE/ps2kbd.c
+++ b/board/MAI/AmigaOneG3SE/ps2kbd.c
@@ -214,7 +214,7 @@
 	}
 }
 
-#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 extern int overwrite_console (void);
 #else
 int overwrite_console (void)
@@ -492,22 +492,22 @@
  */
 unsigned char kbd_read_status(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
 }
 
 unsigned char kbd_read_input(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
 }
 
 void kbd_write_command(unsigned char cmd)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
 }
 
 void kbd_write_output(unsigned char data)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
 }
 
 int kbd_read_data(void)
diff --git a/board/MAI/AmigaOneG3SE/serial.c b/board/MAI/AmigaOneG3SE/serial.c
index b6f57c7..88039f3 100644
--- a/board/MAI/AmigaOneG3SE/serial.c
+++ b/board/MAI/AmigaOneG3SE/serial.c
@@ -6,7 +6,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_NS16550
+#ifndef CONFIG_SYS_NS16550
 static uint32 ComPort1;
 
 uint16 SerialEcho = 1;
@@ -147,8 +147,8 @@
 
 #else
 
-const NS16550_t Com0 = (NS16550_t) CFG_NS16550_COM1;
-const NS16550_t Com1 = (NS16550_t) CFG_NS16550_COM2;
+const NS16550_t Com0 = (NS16550_t) CONFIG_SYS_NS16550_COM1;
+const NS16550_t Com1 = (NS16550_t) CONFIG_SYS_NS16550_COM2;
 
 int serial_init (void)
 {
diff --git a/board/MAI/AmigaOneG3SE/usb_uhci.c b/board/MAI/AmigaOneG3SE/usb_uhci.c
index 26cdcdf..6d1133f 100644
--- a/board/MAI/AmigaOneG3SE/usb_uhci.c
+++ b/board/MAI/AmigaOneG3SE/usb_uhci.c
@@ -627,7 +627,7 @@
 	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
 	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
 	usb_base_addr&=0xFFFFFFF0;
-	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
 	rh.devnum = 0;
 	usb_init_skel();
 	reset_hc();
diff --git a/board/Marvell/common/flash.c b/board/Marvell/common/flash.c
index 3603372..21eae0e 100644
--- a/board/Marvell/common/flash.c
+++ b/board/Marvell/common/flash.c
@@ -48,7 +48,7 @@
 int flash_erase_intel (flash_info_t * info, int s_first, int s_last);
 int write_word_intel (bank_addr_t addr, bank_word_t value);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -68,14 +68,14 @@
 	unsigned long base, flash_size;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* the boot flash */
-	base = CFG_FLASH_BASE;
+	base = CONFIG_SYS_FLASH_BASE;
 	size_b0 =
-		flash_get_size (CFG_BOOT_FLASH_WIDTH, (vu_long *) base,
+		flash_get_size (CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *) base,
 				&flash_info[0]);
 
 	printf ("[%ldkB@%lx] ", size_b0 / 1024, base);
@@ -84,11 +84,11 @@
 		printf ("## Unknown FLASH at %08lx: Size = 0x%08lx = %ld MB\n", base, size_b0, size_b0 << 20);
 	}
 
-	base = memoryGetDeviceBaseAddress (CFG_EXTRA_FLASH_DEVICE);
+	base = memoryGetDeviceBaseAddress (CONFIG_SYS_EXTRA_FLASH_DEVICE);
 /*	base = memoryGetDeviceBaseAddress(DEV_CS3_BASE_ADDR);*/
-	for (i = 1; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		unsigned long size =
-			flash_get_size (CFG_EXTRA_FLASH_WIDTH,
+			flash_get_size (CONFIG_SYS_EXTRA_FLASH_WIDTH,
 					(vu_long *) base, &flash_info[i]);
 
 		printf ("[%ldMB@%lx] ", size >> 20, base);
@@ -617,7 +617,7 @@
 							/* has the timeout limit been reached? */
 							if (get_timer (start)
 							    >
-							    CFG_FLASH_ERASE_TOUT)
+							    CONFIG_SYS_FLASH_ERASE_TOUT)
 							{
 								/* timeout limit reached */
 								printf ("Time out limit reached erasing sector at address %08lx\n", info->start[sect]);
@@ -776,7 +776,7 @@
 	addr = (volatile unsigned char *) (info->start[l_sect]);
 	/* broken for 2x16: TODO */
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -956,7 +956,7 @@
 				{
 					/* has the timeout limit been reached? */
 					if (get_timer (start) >
-					    CFG_FLASH_WRITE_TOUT) {
+					    CONFIG_SYS_FLASH_WRITE_TOUT) {
 						/* timeout limit reached */
 						printf ("Time out limit reached programming address %08lx with data %08lx\n", dest, data);
 						/* reset the flash */
@@ -1064,7 +1064,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *) dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/Marvell/common/i2c.c b/board/Marvell/common/i2c.c
index 32b2b30..d426044 100644
--- a/board/Marvell/common/i2c.c
+++ b/board/Marvell/common/i2c.c
@@ -48,7 +48,7 @@
 	unsigned int actualN = 0, actualM = 0;
 	unsigned int control, status;
 	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CFG_TCLK;
+	unsigned int tclk = CONFIG_SYS_TCLK;
 	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
 
 	DP (puts ("i2c_init\n"));
@@ -372,7 +372,7 @@
 	  int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_read\n"));
 
@@ -447,7 +447,7 @@
 	   int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_write\n"));
 
@@ -500,7 +500,7 @@
 	unsigned int i2c_status;
 #endif
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_probe\n"));
 
diff --git a/board/Marvell/common/intel_flash.c b/board/Marvell/common/intel_flash.c
index d26f883..42b3ee1 100644
--- a/board/Marvell/common/intel_flash.c
+++ b/board/Marvell/common/intel_flash.c
@@ -152,7 +152,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -227,7 +227,7 @@
 			do {
 				now = get_timer (start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					break;
diff --git a/board/Marvell/common/intel_flash.h b/board/Marvell/common/intel_flash.h
index 666a4cd..bd8941e 100644
--- a/board/Marvell/common/intel_flash.h
+++ b/board/Marvell/common/intel_flash.h
@@ -68,7 +68,7 @@
 /* ID and Lock Configuration */
 #define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
 #define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
 
 /* dimensions */
 #define CHIP_WIDTH		2		/* chips are in 16 bit mode */
diff --git a/board/Marvell/common/misc.S b/board/Marvell/common/misc.S
index 41c3a95..b3a0898 100644
--- a/board/Marvell/common/misc.S
+++ b/board/Marvell/common/misc.S
@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */
diff --git a/board/Marvell/common/ns16550.c b/board/Marvell/common/ns16550.c
index 475445b..7fbf28a 100644
--- a/board/Marvell/common/ns16550.c
+++ b/board/Marvell/common/ns16550.c
@@ -1,7 +1,7 @@
 /*
  * COM1 NS16550 support
  * originally from linux source (arch/ppc/boot/ns16550.c)
- * modified to use CFG_ISA_MEM and new defines
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
  *
  * further modified by Josh Huber <huber@mclx.com> to support
  * the DUART on the Galileo Eval board. (db64360)
@@ -13,8 +13,8 @@
 #ifdef ZUMA_NTL
 /* no 16550 device */
 #else
-const NS16550_t COM_PORTS[] = { (NS16550_t) (CFG_DUART_IO + 0),
-	(NS16550_t) (CFG_DUART_IO + 0x20)
+const NS16550_t COM_PORTS[] = { (NS16550_t) (CONFIG_SYS_DUART_IO + 0),
+	(NS16550_t) (CONFIG_SYS_DUART_IO + 0x20)
 };
 
 volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
diff --git a/board/Marvell/common/ns16550.h b/board/Marvell/common/ns16550.h
index f2ed2ab..b9691ab 100644
--- a/board/Marvell/common/ns16550.h
+++ b/board/Marvell/common/ns16550.h
@@ -2,7 +2,7 @@
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2
diff --git a/board/Marvell/common/serial.c b/board/Marvell/common/serial.c
index 01efbea..3e7f406 100644
--- a/board/Marvell/common/serial.c
+++ b/board/Marvell/common/serial.c
@@ -52,17 +52,17 @@
 
 int serial_init (void)
 {
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
 	int clock_divisor = 230400 / gd->baudrate;
 #endif
 
 	mpsc_init (gd->baudrate);
 
 	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 	return (0);
@@ -97,10 +97,10 @@
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	(void) NS16550_init (0, clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	(void) NS16550_init (1, clock_divisor);
 #endif
 	return (0);
@@ -109,29 +109,29 @@
 void serial_putc (const char c)
 {
 	if (c == '\n')
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int serial_getc (void)
 {
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int serial_tstc (void)
 {
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void serial_setbrg (void)
 {
 	int clock_divisor = 230400 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }
diff --git a/board/Marvell/db64360/db64360.c b/board/Marvell/db64360/db64360.c
index c03d03d..35b695e 100644
--- a/board/Marvell/db64360/db64360.c
+++ b/board/Marvell/db64360/db64360.c
@@ -55,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -64,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -127,7 +127,7 @@
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -136,7 +136,7 @@
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -154,21 +154,21 @@
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -184,7 +184,7 @@
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -200,7 +200,7 @@
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -251,7 +251,7 @@
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -297,56 +297,56 @@
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -359,7 +359,7 @@
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -380,9 +380,9 @@
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -402,7 +402,7 @@
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -415,34 +415,34 @@
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -513,7 +513,7 @@
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -544,7 +544,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -607,7 +607,7 @@
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -634,9 +634,9 @@
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -661,8 +661,8 @@
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -679,9 +679,9 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -739,7 +739,7 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -771,8 +771,8 @@
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -848,9 +848,9 @@
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -860,7 +860,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -870,7 +870,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -886,7 +886,7 @@
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -925,7 +925,7 @@
 /* MV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0x0000ff00); */
 
 /* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
diff --git a/board/Marvell/db64360/mpsc.c b/board/Marvell/db64360/mpsc.c
index 923d955..7ad6ae8 100644
--- a/board/Marvell/db64360/mpsc.c
+++ b/board/Marvell/db64360/mpsc.c
@@ -426,7 +426,7 @@
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
diff --git a/board/Marvell/db64360/pci.c b/board/Marvell/db64360/pci.c
index 5637284..a7e3c95 100644
--- a/board/Marvell/db64360/pci.c
+++ b/board/Marvell/db64360/pci.c
@@ -859,14 +859,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
diff --git a/board/Marvell/db64360/sdram_init.c b/board/Marvell/db64360/sdram_init.c
index ecadaf2..d0817d7 100644
--- a/board/Marvell/db64360/sdram_init.c
+++ b/board/Marvell/db64360/sdram_init.c
@@ -312,7 +312,7 @@
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1290,37 +1290,37 @@
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1807,7 +1807,7 @@
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;
diff --git a/board/Marvell/db64460/db64460.c b/board/Marvell/db64460/db64460.c
index 8a05cd2..14e6355 100644
--- a/board/Marvell/db64460/db64460.c
+++ b/board/Marvell/db64460/db64460.c
@@ -55,7 +55,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -64,7 +64,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -127,7 +127,7 @@
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -136,7 +136,7 @@
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -154,21 +154,21 @@
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_BASE >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_BASE >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -184,7 +184,7 @@
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -200,7 +200,7 @@
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64460 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -251,7 +251,7 @@
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -297,56 +297,56 @@
 	 * on-board sram on the eval board, and updates the correct
 	 * registers to boot from the sram. (device0)
 	 */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE)
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE)
 		sram_boot = 1;
 	if (!sram_boot)
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR		/* set port parameters for SRAM device module access */
+#ifdef CONFIG_SYS_DEV0_PAR		/* set port parameters for SRAM device module access */
 	if (!sram_boot)
-		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR		/* set port parameters for RTC device module access */
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#ifdef CONFIG_SYS_DEV1_PAR		/* set port parameters for RTC device module access */
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR		/* set port parameters for DUART device module access */
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#ifdef CONFIG_SYS_DEV2_PAR		/* set port parameters for DUART device module access */
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -359,7 +359,7 @@
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -380,9 +380,9 @@
 	/* check to see if we booted from the sram.  If so, move things
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
-	if (memoryGetDeviceBaseAddress (DEVICE0) == CFG_DFL_BOOTCS_BASE) {
-		memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace (BOOT_DEVICE, CFG_DFL_BOOTCS_BASE, _8M);
+	if (memoryGetDeviceBaseAddress (DEVICE0) == CONFIG_SYS_DFL_BOOTCS_BASE) {
+		memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_DFL_BOOTCS_BASE, _8M);
 	}
 	display_mem_map ();
 	/* now, jump to the main ppcboot board init code */
@@ -402,7 +402,7 @@
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -415,34 +415,34 @@
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x08000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x0c000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x14000);
 			break;
 
 		case 1:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x18000);
 			break;
 
 		case 2:
-			addr = (int *) ((unsigned int) CFG_DEV1_SPACE |
+			addr = (int *) ((unsigned int) CONFIG_SYS_DEV1_SPACE |
 					0x1c000);
 			break;
 		}
@@ -513,7 +513,7 @@
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -544,7 +544,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -607,7 +607,7 @@
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -634,9 +634,9 @@
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -661,8 +661,8 @@
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -679,9 +679,9 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -739,7 +739,7 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -771,8 +771,8 @@
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -848,9 +848,9 @@
 /*    runwalk = 0; */
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -860,7 +860,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -870,7 +870,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -886,7 +886,7 @@
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -925,7 +925,7 @@
 	GT_REG_WRITE (MV64460_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00);
 
 /* Relocate MV64460 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, BRIDGE_REG_BASE_BOOTM);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, BRIDGE_REG_BASE_BOOTM);
 
 	icache_disable ();
 	dcache_disable ();
diff --git a/board/Marvell/db64460/mpsc.c b/board/Marvell/db64460/mpsc.c
index 359b831..303a636 100644
--- a/board/Marvell/db64460/mpsc.c
+++ b/board/Marvell/db64460/mpsc.c
@@ -426,7 +426,7 @@
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -516,9 +516,9 @@
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
diff --git a/board/Marvell/db64460/pci.c b/board/Marvell/db64460/pci.c
index 5637284..a7e3c95 100644
--- a/board/Marvell/db64460/pci.c
+++ b/board/Marvell/db64460/pci.c
@@ -859,14 +859,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -901,14 +901,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
diff --git a/board/Marvell/db64460/sdram_init.c b/board/Marvell/db64460/sdram_init.c
index f36f348..6d6b126 100644
--- a/board/Marvell/db64460/sdram_init.c
+++ b/board/Marvell/db64460/sdram_init.c
@@ -312,7 +312,7 @@
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -690,16 +690,16 @@
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     <
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 <
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							dimmInfo->
 								maxClSupported_DDR
@@ -714,16 +714,16 @@
 						if ((dimmInfo->
 						     minimumCycleTimeAtMaxCasLatancy_LoP
 						     >
-						     CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						     CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						    ||
 						    ((dimmInfo->
 						      minimumCycleTimeAtMaxCasLatancy_LoP
 						      ==
-						      CFG_DDR_SDRAM_CYCLE_COUNT_LOP)
+						      CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_LOP)
 						     && (dimmInfo->
 							 minimumCycleTimeAtMaxCasLatancy_RoP
 							 >
-							 CFG_DDR_SDRAM_CYCLE_COUNT_ROP)))
+							 CONFIG_SYS_DDR_SDRAM_CYCLE_COUNT_ROP)))
 						{
 							printf ("*********************************************************\n");
 							printf ("*** sysClock is higher than SDRAM's allowed frequency ***\n");
@@ -1289,37 +1289,37 @@
 	case 0x0:
 	case 0x80:		/* refresh period is 15.625 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 15.625 * (float) CFG_BUS_HZ)
+			(unsigned int) (((float) 15.625 * (float) CONFIG_SYS_BUS_HZ)
 					/ (float) 1000000.0);
 		break;
 	case 0x1:
 	case 0x81:		/* refresh period is 3.9 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 3.9 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 3.9 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x2:
 	case 0x82:		/* refresh period is 7.8 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 7.8 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 7.8 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x3:
 	case 0x83:		/* refresh period is 31.3 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 31.3 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 31.3 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x4:
 	case 0x84:		/* refresh period is 62.5 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 62.5 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 62.5 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	case 0x5:
 	case 0x85:		/* refresh period is 125 usec */
 		sdram_config_reg =
-			(unsigned int) (((float) 125 * (float) CFG_BUS_HZ) /
+			(unsigned int) (((float) 125 * (float) CONFIG_SYS_BUS_HZ) /
 					(float) 1000000.0);
 		break;
 	default:		/* refresh period undefined */
@@ -1816,7 +1816,7 @@
 
 	printf ("-- DIMM2 has %d banks\n", dimmInfo2.numOfModuleBanks);
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;
diff --git a/board/MigoR/migo_r.c b/board/MigoR/migo_r.c
index b31f37d..204ca78 100644
--- a/board/MigoR/migo_r.c
+++ b/board/MigoR/migo_r.c
@@ -42,9 +42,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/RPXClassic/RPXClassic.c b/board/RPXClassic/RPXClassic.c
index 804635a..9fdf700 100644
--- a/board/RPXClassic/RPXClassic.c
+++ b/board/RPXClassic/RPXClassic.c
@@ -111,7 +111,7 @@
 	char buff[256], *cp;
 
 	/* Initialize I2C					*/
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read 256 bytes in EEPROM				*/
 	i2c_read (0x54, 0, 1, (uchar *)buff, 128);
@@ -167,7 +167,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -175,15 +175,15 @@
 			   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -200,7 +200,7 @@
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 						SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -218,7 +218,7 @@
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/RPXClassic/eccx.c b/board/RPXClassic/eccx.c
index cc76bbd..e1f3f9d 100644
--- a/board/RPXClassic/eccx.c
+++ b/board/RPXClassic/eccx.c
@@ -299,7 +299,7 @@
  */
 unsigned int board_video_init (void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Program ECCX registers                                                */
diff --git a/board/RPXClassic/flash.c b/board/RPXClassic/flash.c
index 2e0b8f9..f07d960 100644
--- a/board/RPXClassic/flash.c
+++ b/board/RPXClassic/flash.c
@@ -33,7 +33,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -51,20 +51,20 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -313,7 +313,7 @@
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -436,7 +436,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/RPXlite/RPXlite.c b/board/RPXlite/RPXlite.c
index bca31e4..dca53a4 100644
--- a/board/RPXlite/RPXlite.c
+++ b/board/RPXlite/RPXlite.c
@@ -104,7 +104,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size10;
 
@@ -112,15 +112,15 @@
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000000;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_10COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -137,7 +137,7 @@
 	 * try 10 column mode
 	 */
 
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE_PRELIM,
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE_PRELIM,
 			    SDRAM_MAX_SIZE);
 
 	return (size10);
@@ -156,7 +156,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/RPXlite/flash.c b/board/RPXlite/flash.c
index 659d60a..788fcdf 100644
--- a/board/RPXlite/flash.c
+++ b/board/RPXlite/flash.c
@@ -38,7 +38,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -52,13 +52,13 @@
 
 unsigned long flash_init (void)
 {
-/*	volatile immap_t     *immap  = (immap_t *)CFG_IMMR; */
+/*	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR; */
 /*	volatile memctl8xx_t *memctl = &immap->im_memctl; */
 	unsigned long size_b0 ;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -73,19 +73,19 @@
 */
 	/* Remap FLASH according to real size */
 /*%%%
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 %%%*/
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -390,7 +390,7 @@
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -513,7 +513,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/RPXlite_dw/RPXlite_dw.c b/board/RPXlite_dw/RPXlite_dw.c
index d6fabf0..364a316 100644
--- a/board/RPXlite_dw/RPXlite_dw.c
+++ b/board/RPXlite_dw/RPXlite_dw.c
@@ -106,22 +106,22 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size9;
 
 	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR ;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR ;
 
 	memctl->memc_mar  = 0x00000088;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE)); /* no refresh yet */
 	/*Disable Periodic timer A. */
 
 	udelay(200);
@@ -142,13 +142,13 @@
 	  * try 9 column mode
 	  */
 
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE_PRELIM, SDRAM_MAX_SIZE);
 
 	/*
 	 * Final mapping:
 	 */
 
-	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 
 	udelay (1000);
 
@@ -171,7 +171,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/RPXlite_dw/flash.c b/board/RPXlite_dw/flash.c
index 41cb036..91788af 100644
--- a/board/RPXlite_dw/flash.c
+++ b/board/RPXlite_dw/flash.c
@@ -49,7 +49,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions   vu_long : volatile unsigned long IN include/common.h
@@ -64,22 +64,22 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* If Monitor is in the cope of FLASH,then
 	 * protect this area by default in case for
 	 * other occupation. [SAM] */
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 	flash_info[0].size = size_b0;
@@ -360,7 +360,7 @@
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -482,7 +482,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/RRvision/RRvision.c b/board/RRvision/RRvision.c
index c0b772d..9d016c5 100644
--- a/board/RRvision/RRvision.c
+++ b/board/RRvision/RRvision.c
@@ -112,7 +112,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long reg;
 	long int size8, size9;
@@ -126,17 +126,17 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 1 the SDRAM bank 2 at physical address 0.
 	 */
-	memctl->memc_or1 = CFG_OR2_PRELIM;
-	memctl->memc_br1 = CFG_BR2_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -156,7 +156,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -165,7 +165,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -174,7 +174,7 @@
 /*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {			/* back to 8 columns            */
 		size = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -187,15 +187,15 @@
 	 */
 	if (size < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping
 	 */
-	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/*
 	 * No bank 1
@@ -206,7 +206,7 @@
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -227,7 +227,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/RRvision/flash.c b/board/RRvision/flash.c
index 6608bca..fdbe928 100644
--- a/board/RRvision/flash.c
+++ b/board/RRvision/flash.c
@@ -27,10 +27,10 @@
 #include <mpc8xx.h>
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -43,13 +43,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -63,17 +63,17 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -388,7 +388,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			puts ("Timeout\n");
 			return 1;
 		}
@@ -511,7 +511,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/a3000/a3000.c b/board/a3000/a3000.c
index 1ba21ed..ce2cf28 100644
--- a/board/a3000/a3000.c
+++ b/board/a3000/a3000.c
@@ -46,7 +46,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
diff --git a/board/a3000/flash.c b/board/a3000/flash.c
index add2a28..b671ce7 100644
--- a/board/a3000/flash.c
+++ b/board/a3000/flash.c
@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
@@ -48,7 +48,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -65,13 +65,13 @@
 
 unsigned long flash_init (void)
 {
-	unsigned long flash_banks[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS;
-	unsigned long size, size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long flash_banks[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS;
+	unsigned long size, size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
@@ -99,12 +99,12 @@
 	}
 
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, CFG_MONITOR_LEN);
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN);
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 
@@ -119,7 +119,7 @@
 
 	size = 0;
 	DEBUGF("## Final Flash bank sizes: ");
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		DEBUGF("%08lx ", size_b[i]);
 		size += size_b[i];
@@ -285,10 +285,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = BS(0xFF);		/* restore read mode */
@@ -356,7 +356,7 @@
 			udelay (1000);
 
 			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = BS(0xB0); /* suspend erase	  */
 					*addr = BS(0xFF); /* reset to read mode */
@@ -439,7 +439,7 @@
 	start = get_timer (0);
 
 	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = BS(0xFF);	/* restore read mode */
 			return 1;
 		}
diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c
index d1d7f6c..399be23 100644
--- a/board/actux1/actux1.c
+++ b/board/actux1/actux1.c
@@ -49,16 +49,16 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* Setup GPIO's for PCI INTA */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI1_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI1_INTA);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS5: Debug port */
@@ -69,7 +69,7 @@
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	ACTUX1_LED1 (2);
 	ACTUX1_LED2 (2);
diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h
index bb3b7f9..fe454c5 100644
--- a/board/actux1/actux1_hw.h
+++ b/board/actux1/actux1_hw.h
@@ -42,16 +42,16 @@
 #define ACTUX1_BOARDREL	(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F)
 
 /* GPIO settings */
-#define CFG_GPIO_PCI1_INTA		2
-#define CFG_GPIO_PCI2_INTA		3
-#define CFG_GPIO_I2C_SDA		4
-#define CFG_GPIO_I2C_SCL		5
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_PCI1_INTA		2
+#define CONFIG_SYS_GPIO_PCI2_INTA		3
+#define CONFIG_SYS_GPIO_I2C_SDA		4
+#define CONFIG_SYS_GPIO_I2C_SCL		5
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif
diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c
index 99daef6..d6aaad6 100644
--- a/board/actux2/actux2.c
+++ b/board/actux2/actux2.c
@@ -50,24 +50,24 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/* Setup GPIO's for 33MHz clock output */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -80,8 +80,8 @@
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX2_LED1 (1);
 	ACTUX2_LED2 (0);
diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h
index 8ffb82a..0f5ebcb 100644
--- a/board/actux2/actux2_hw.h
+++ b/board/actux2/actux2_hw.h
@@ -39,21 +39,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_UNUSED4		4
-#define CFG_GPIO_UNUSED5		5
-#define CFG_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_IPAC_INT		8
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_UNUSED4		4
+#define CONFIG_SYS_GPIO_UNUSED5		5
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_IPAC_INT		8
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif
diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c
index 812bc2b..63bf365 100644
--- a/board/actux3/actux3.c
+++ b/board/actux3/actux3.c
@@ -50,35 +50,35 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_ETHRST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_DCD);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED6_GN);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_ETHRST);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR);
-	GPIO_OUTPUT_SET (CFG_GPIO_DCD);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_DSR);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_DCD);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED5_GN);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_RT);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_LED6_GN);
 
 	/*
 	 * Setup GPIO's for Interrupt inputs
 	 */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_DBGINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_ETHINT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
 
 	/* CS1: IPAC-X */
@@ -91,8 +91,8 @@
 	*IXP425_EXP_CS7 = 0x80900003;
 
 	udelay (533);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
-	GPIO_OUTPUT_SET (CFG_GPIO_ETHRST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_ETHRST);
 
 	ACTUX3_LED1_RT (1);
 	ACTUX3_LED1_GN (0);
diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h
index 9b7cbce..c3c0cfc 100644
--- a/board/actux3/actux3_hw.h
+++ b/board/actux3/actux3_hw.h
@@ -41,20 +41,20 @@
 #define ACTUX3_OPTION		(readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0)
 
 /* GPIO settings */
-#define CFG_GPIO_DBGINT			0
-#define CFG_GPIO_ETHINT			1
-#define CFG_GPIO_ETHRST			2	/* Out */
-#define CFG_GPIO_LED5_GN		3	/* Out */
-#define CFG_GPIO_LED6_RT		4	/* Out */
-#define CFG_GPIO_LED6_GN		5	/* Out */
-#define CFG_GPIO_DSR			6	/* Out */
-#define CFG_GPIO_DCD			7	/* Out */
-#define CFG_GPIO_DBGJUMPER		9
-#define CFG_GPIO_BUTTON1		10
-#define CFG_GPIO_DBGSENSE		11
-#define CFG_GPIO_DTR			12
-#define CFG_GPIO_IORST			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_DBGINT			0
+#define CONFIG_SYS_GPIO_ETHINT			1
+#define CONFIG_SYS_GPIO_ETHRST			2	/* Out */
+#define CONFIG_SYS_GPIO_LED5_GN		3	/* Out */
+#define CONFIG_SYS_GPIO_LED6_RT		4	/* Out */
+#define CONFIG_SYS_GPIO_LED6_GN		5	/* Out */
+#define CONFIG_SYS_GPIO_DSR			6	/* Out */
+#define CONFIG_SYS_GPIO_DCD			7	/* Out */
+#define CONFIG_SYS_GPIO_DBGJUMPER		9
+#define CONFIG_SYS_GPIO_BUTTON1		10
+#define CONFIG_SYS_GPIO_DBGSENSE		11
+#define CONFIG_SYS_GPIO_DTR			12
+#define CONFIG_SYS_GPIO_IORST			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif
diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c
index 84037fa..f373b58 100644
--- a/board/actux4/actux4.c
+++ b/board/actux4/actux4.c
@@ -49,53 +49,53 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_nPWRON);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_nPWRON);
 
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_IORST);
 
 	/* led not populated on board*/
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED3);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED3);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED3);
 
 	/* middle LED */
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED2);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_LED2);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED2);
 
 	/* right LED */
 	/* weak pulldown = LED weak on */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1);
-	GPIO_OUTPUT_SET (CFG_GPIO_LED1);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_LED1);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_LED1);
 
 	/* Setup GPIO's for Interrupt inputs */
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE (CONFIG_SYS_GPIO_PCI_INTB);
 
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTB);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_USBINTC);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_RTCINT);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET (CONFIG_SYS_GPIO_PCI_INTB);
 
 	/* Setup GPIO's for 33MHz clock output */
 	*IXP425_GPIO_GPCLKR = 0x011001FF;
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK);
-	GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE (CONFIG_SYS_GPIO_PCI_CLK);
 
 	*IXP425_EXP_CS1 = 0xbd113c42;
 
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST);
+	GPIO_OUTPUT_CLEAR (CONFIG_SYS_GPIO_IORST);
 	udelay (10000);
-	GPIO_OUTPUT_SET (CFG_GPIO_IORST);
+	GPIO_OUTPUT_SET (CONFIG_SYS_GPIO_IORST);
 
 	return 0;
 }
diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h
index 8b3ecf3..afd1c06 100644
--- a/board/actux4/actux4_hw.h
+++ b/board/actux4/actux4_hw.h
@@ -29,21 +29,21 @@
 /*
  * GPIO settings
  */
-#define CFG_GPIO_USBINTA		0
-#define CFG_GPIO_USBINTB		1
-#define CFG_GPIO_USBINTC		2
-#define CFG_GPIO_nPWRON			3	/* Out */
-#define CFG_GPIO_I2C_SCL		4
-#define CFG_GPIO_I2C_SDA		5
-#define CFG_GPIO_PCI_INTB		6
-#define CFG_GPIO_BUTTON1		7
-#define CFG_GPIO_LED1			8	/* Out */
-#define CFG_GPIO_RTCINT			9
-#define CFG_GPIO_LED2			10	/* Out */
-#define CFG_GPIO_PCI_INTA		11
-#define CFG_GPIO_IORST			12	/* Out */
-#define CFG_GPIO_LED3			13	/* Out */
-#define CFG_GPIO_PCI_CLK		14	/* Out */
-#define CFG_GPIO_EXTBUS_CLK		15	/* Out */
+#define CONFIG_SYS_GPIO_USBINTA		0
+#define CONFIG_SYS_GPIO_USBINTB		1
+#define CONFIG_SYS_GPIO_USBINTC		2
+#define CONFIG_SYS_GPIO_nPWRON			3	/* Out */
+#define CONFIG_SYS_GPIO_I2C_SCL		4
+#define CONFIG_SYS_GPIO_I2C_SDA		5
+#define CONFIG_SYS_GPIO_PCI_INTB		6
+#define CONFIG_SYS_GPIO_BUTTON1		7
+#define CONFIG_SYS_GPIO_LED1			8	/* Out */
+#define CONFIG_SYS_GPIO_RTCINT			9
+#define CONFIG_SYS_GPIO_LED2			10	/* Out */
+#define CONFIG_SYS_GPIO_PCI_INTA		11
+#define CONFIG_SYS_GPIO_IORST			12	/* Out */
+#define CONFIG_SYS_GPIO_LED3			13	/* Out */
+#define CONFIG_SYS_GPIO_PCI_CLK		14	/* Out */
+#define CONFIG_SYS_GPIO_EXTBUS_CLK		15	/* Out */
 
 #endif
diff --git a/board/adder/adder.c b/board/adder/adder.c
index e8a5737..87791de 100644
--- a/board/adder/adder.c
+++ b/board/adder/adder.c
@@ -68,7 +68,7 @@
 phys_size_t initdram (int board_type)
 {
 	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@@ -76,7 +76,7 @@
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV32; /* BRGCLK/32 */
 
-	memctl->memc_mamr = (94 << 24) | CFG_MAMR; /* No refresh */
+	memctl->memc_mamr = (94 << 24) | CONFIG_SYS_MAMR; /* No refresh */
 	udelay(200);
 
 	/* Run precharge from location 0x15 */
@@ -94,10 +94,10 @@
 	udelay(200);
 
 	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
 
-	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
 	memctl->memc_or1  |= ~(msize - 1);
 
 	return msize;
diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c
index deaa292..0610928 100644
--- a/board/ads5121/ads5121.c
+++ b/board/ads5121/ads5121.c
@@ -53,16 +53,16 @@
 
 int board_early_init_f (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 lpcaw;
 
 	/*
 	 * Initialize Local Window for the CPLD registers access (CS2 selects
 	 * the CPLD chip)
 	 */
-	im->sysconf.lpcs2aw = CSAW_START(CFG_CPLD_BASE) |
-			      CSAW_STOP(CFG_CPLD_BASE, CFG_CPLD_SIZE);
-	im->lpc.cs_cfg[2] = CFG_CS2_CFG;
+	im->sysconf.lpcs2aw = CSAW_START(CONFIG_SYS_CPLD_BASE) |
+			      CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE);
+	im->lpc.cs_cfg[2] = CONFIG_SYS_CS2_CFG;
 
 	/*
 	 * According to MPC5121e RM, configuring local access windows should
@@ -80,21 +80,21 @@
 	 */
 
 #ifdef CONFIG_ADS5121_REV2
-	*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+	*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 #else
-	if (*((u8 *)(CFG_CPLD_BASE + 0x08)) & 0x04) {
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0xC1;
+	if (*((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0xC1;
 	} else {
 		/* running from Backup flash */
-		*((volatile u8 *)(CFG_CPLD_BASE + 0x08)) = 0x32;
+		*((volatile u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) = 0x32;
 	}
 #endif
 	/*
 	 * Configure Flash Speed
 	 */
-	*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG;
+	*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS0_CONFIG)) = CONFIG_SYS_CS0_CFG;
 	if (SVR_MJREV (im->sysconf.spridr) >= 2) {
-		*((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING;
+		*((volatile u32 *)(CONFIG_SYS_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CONFIG_SYS_CS_ALETIMING;
 	}
 	/*
 	 * Enable clocks
@@ -120,8 +120,8 @@
  */
 long int fixed_sdram (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2 (msize);
 	u32 i;
 
@@ -129,7 +129,7 @@
 	im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR;
 
 	/* Initialize DDR Local Window */
-	im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000;
+	im->sysconf.ddrlaw.bar = CONFIG_SYS_DDR_BASE & 0xFFFFF000;
 	im->sysconf.ddrlaw.ar = msize_log2 - 1;
 
 	/*
@@ -141,68 +141,68 @@
 	__asm__ __volatile__ ("isync");
 
 	/* Enable DDR */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_EN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_EN;
 
 	/* Initialize DDR Priority Manager */
-	im->mddrc.prioman_config1 = CFG_MDDRCGRP_PM_CFG1;
-	im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2;
-	im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG;
-	im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU;
-	im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML;
-	im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU;
-	im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML;
-	im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU;
-	im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML;
-	im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU;
-	im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML;
-	im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU;
-	im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML;
-	im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU;
-	im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL;
-	im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU;
-	im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL;
-	im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU;
-	im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL;
-	im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU;
-	im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL;
-	im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU;
-	im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL;
+	im->mddrc.prioman_config1 = CONFIG_SYS_MDDRCGRP_PM_CFG1;
+	im->mddrc.prioman_config2 = CONFIG_SYS_MDDRCGRP_PM_CFG2;
+	im->mddrc.hiprio_config = CONFIG_SYS_MDDRCGRP_HIPRIO_CFG;
+	im->mddrc.lut_table0_main_upper = CONFIG_SYS_MDDRCGRP_LUT0_MU;
+	im->mddrc.lut_table0_main_lower = CONFIG_SYS_MDDRCGRP_LUT0_ML;
+	im->mddrc.lut_table1_main_upper = CONFIG_SYS_MDDRCGRP_LUT1_MU;
+	im->mddrc.lut_table1_main_lower = CONFIG_SYS_MDDRCGRP_LUT1_ML;
+	im->mddrc.lut_table2_main_upper = CONFIG_SYS_MDDRCGRP_LUT2_MU;
+	im->mddrc.lut_table2_main_lower = CONFIG_SYS_MDDRCGRP_LUT2_ML;
+	im->mddrc.lut_table3_main_upper = CONFIG_SYS_MDDRCGRP_LUT3_MU;
+	im->mddrc.lut_table3_main_lower = CONFIG_SYS_MDDRCGRP_LUT3_ML;
+	im->mddrc.lut_table4_main_upper = CONFIG_SYS_MDDRCGRP_LUT4_MU;
+	im->mddrc.lut_table4_main_lower = CONFIG_SYS_MDDRCGRP_LUT4_ML;
+	im->mddrc.lut_table0_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT0_AU;
+	im->mddrc.lut_table0_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT0_AL;
+	im->mddrc.lut_table1_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT1_AU;
+	im->mddrc.lut_table1_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT1_AL;
+	im->mddrc.lut_table2_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT2_AU;
+	im->mddrc.lut_table2_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT2_AL;
+	im->mddrc.lut_table3_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT3_AU;
+	im->mddrc.lut_table3_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT3_AL;
+	im->mddrc.lut_table4_alternate_upper = CONFIG_SYS_MDDRCGRP_LUT4_AU;
+	im->mddrc.lut_table4_alternate_lower = CONFIG_SYS_MDDRCGRP_LUT4_AL;
 
 	/* Initialize MDDRC */
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG;
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0;
-	im->mddrc.ddr_time_config1 = CFG_MDDRC_TIME_CFG1;
-	im->mddrc.ddr_time_config2 = CFG_MDDRC_TIME_CFG2;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0;
+	im->mddrc.ddr_time_config1 = CONFIG_SYS_MDDRC_TIME_CFG1;
+	im->mddrc.ddr_time_config2 = CONFIG_SYS_MDDRC_TIME_CFG2;
 
 	/* Initialize DDR */
 	for (i = 0; i < 10; i++)
-		im->mddrc.ddr_command = CFG_MICRON_NOP;
+		im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_EM2;
-	im->mddrc.ddr_command = CFG_MICRON_EM3;
-	im->mddrc.ddr_command = CFG_MICRON_EN_DLL;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_RFSH;
-	im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP;
-	im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT;
-	im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL;
-	im->mddrc.ddr_command = CFG_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM2;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EM3;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_EN_DLL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_RFSH;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_INIT_DEV_OP;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_OCD_DEFAULT;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_PCHG_ALL;
+	im->mddrc.ddr_command = CONFIG_SYS_MICRON_NOP;
 
 	/* Start MDDRC */
-	im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN;
-	im->mddrc.ddr_sys_config = CFG_MDDRC_SYS_CFG_RUN;
+	im->mddrc.ddr_time_config0 = CONFIG_SYS_MDDRC_TIME_CFG0_RUN;
+	im->mddrc.ddr_sys_config = CONFIG_SYS_MDDRC_SYS_CFG_RUN;
 
 	return msize;
 }
@@ -292,8 +292,8 @@
 
 int checkboard (void)
 {
-	ushort brd_rev = *(vu_short *) (CFG_CPLD_BASE + 0x00);
-	uchar cpld_rev = *(vu_char *) (CFG_CPLD_BASE + 0x02);
+	ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
+	uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
 
 	printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
 		brd_rev, cpld_rev);
diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c
index 26628d3..11450aa 100644
--- a/board/ads5121/ads5121_diu.c
+++ b/board/ads5121/ads5121_diu.c
@@ -43,7 +43,7 @@
 
 void diu_set_pixel_clock(unsigned int pixclock)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile clk512x_t *clk = &immap->clk;
 	volatile unsigned int *clkdvdr = &clk->scfr[0];
 	unsigned long speed_ccb, temp, pixval;
@@ -100,7 +100,7 @@
 }
 
 U_BOOT_CMD(
-	diufb, CFG_MAXARGS, 1, ads5121diu_init_show_bmp,
+	diufb, CONFIG_SYS_MAXARGS, 1, ads5121diu_init_show_bmp,
 	"diufb init | addr - Init or Display BMP file\n",
 	"init\n    - initialize DIU\n"
 	"addr\n    - display bmp at address 'addr'\n"
diff --git a/board/ads5121/pci.c b/board/ads5121/pci.c
index a338604..b747e81 100644
--- a/board/ads5121/pci.c
+++ b/board/ads5121/pci.c
@@ -33,8 +33,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 
 static struct pci_controller pci_hose;
 
@@ -46,7 +46,7 @@
 void
 pci_init_board(void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile law512x_t *pci_law;
 	volatile pot512x_t *pci_pot;
 	volatile pcictrl512x_t *pci_ctrl;
@@ -87,10 +87,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
 	/*
@@ -98,18 +98,18 @@
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | POCMR_PRE | POCMR_CM_256M;
 
 	/* PCI IO space */
-	pci_pot[1].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
 
 	/*
@@ -129,23 +129,23 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI_MEM_BASE,
-		       CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE,
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE,
 		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI_MMIO_BASE,
-		       CFG_PCI_MMIO_PHYS,
-		       CFG_PCI_MMIO_SIZE,
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS,
+		       CONFIG_SYS_PCI_MMIO_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI_IO_BASE,
-		       CFG_PCI_IO_PHYS,
-		       CFG_PCI_IO_SIZE,
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS,
+		       CONFIG_SYS_PCI_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -158,8 +158,8 @@
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR + 0x8300),
-			   (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300),
+			   (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 
diff --git a/board/alaska/alaska.c b/board/alaska/alaska.c
index 49a8f71..33b4a6e 100644
--- a/board/alaska/alaska.c
+++ b/board/alaska/alaska.c
@@ -32,48 +32,48 @@
 	int blocksize = 0;
 
 	/* Flash 0 */
-#if defined (CFG_AMD_BOOT)
-	batu = CFG_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH0_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH0_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH0_BASE | 0x22;
 	write_bat (IBAT0, batu, batl);
 	write_bat (DBAT0, batu, batl);
 
 	/* Flash 1 */
-#if defined (CFG_AMD_BOOT)
-	batu = CFG_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
+#if defined (CONFIG_SYS_AMD_BOOT)
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_16M << 2) | BPP_RW | BPP_RX;
 #else
-	batu = CFG_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batu = CONFIG_SYS_FLASH1_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
 #endif
-	batl = CFG_FLASH1_BASE | 0x22;
+	batl = CONFIG_SYS_FLASH1_BASE | 0x22;
 	write_bat (IBAT1, batu, batl);
 	write_bat (DBAT1, batu, batl);
 
 	/* CPLD */
-	batu = CFG_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_CPLD_BASE | 0x22;
+	batu = CONFIG_SYS_CPLD_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_CPLD_BASE | 0x22;
 	write_bat (IBAT2, 0, 0);
 	write_bat (DBAT2, batu, batl);
 
 	/* FPGA */
-	batu = CFG_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
-	batl = CFG_FPGA_BASE | 0x22;
+	batu = CONFIG_SYS_FPGA_BASE | (BL_512K << 2) | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_FPGA_BASE | 0x22;
 	write_bat (IBAT3, 0, 0);
 	write_bat (DBAT3, batu, batl);
 
 	/* MBAR - Data only */
-	batu = CFG_MBAR | BPP_RW | BPP_RX;
-	batl = CFG_MBAR | 0x22;
+	batu = CONFIG_SYS_MBAR | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_MBAR | 0x22;
 	mtspr (IBAT4L, 0);
 	mtspr (IBAT4U, 0);
 	mtspr (DBAT4L, batl);
 	mtspr (DBAT4U, batu);
 
 	/* MBAR - SRAM */
-	batu = CFG_SRAM_BASE | BPP_RW | BPP_RX;
-	batl = CFG_SRAM_BASE | 0x42;
+	batu = CONFIG_SYS_SRAM_BASE | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SRAM_BASE | 0x42;
 	mtspr (IBAT5L, batl);
 	mtspr (IBAT5U, batu);
 	mtspr (DBAT5L, batl);
@@ -93,8 +93,8 @@
 		blocksize = BL_256M << 2;
 
 	/* Memory */
-	batu = CFG_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
-	batl = CFG_SDRAM_BASE | 0x42;
+	batu = CONFIG_SYS_SDRAM_BASE | blocksize | BPP_RW | BPP_RX;
+	batl = CONFIG_SYS_SDRAM_BASE | 0x42;
 	mtspr (IBAT6L, batl);
 	mtspr (IBAT6U, batu);
 	mtspr (DBAT6L, batl);
@@ -120,9 +120,9 @@
 		else if (size <= 0x10000000)	/* 256MB */
 			blocksize = BL_256M << 2;
 
-		batu = (CFG_SDRAM_BASE +
+		batu = (CONFIG_SYS_SDRAM_BASE +
 			0x10000000) | blocksize | BPP_RW | BPP_RX;
-		batl = (CFG_SDRAM_BASE + 0x10000000) | 0x42;
+		batl = (CONFIG_SYS_SDRAM_BASE + 0x10000000) | 0x42;
 	}
 
 	mtspr (IBAT7L, batl);
diff --git a/board/alaska/flash.c b/board/alaska/flash.c
index 556c168..aed3b6f 100644
--- a/board/alaska/flash.c
+++ b/board/alaska/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH8
@@ -86,30 +86,30 @@
 	ulong size = 0;
 	ulong fsize = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		memset (&flash_info[i], 0, sizeof (flash_info_t));
 
 		switch (i) {
 		case 0:
-			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
 					&flash_info[i]);
-			flash_get_offsets (CFG_FLASH1_BASE, &flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH1_BASE, &flash_info[i]);
 			break;
 		case 1:
-			flash_get_size ((FPW *) CFG_FLASH1_BASE,
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH1_BASE,
 					&flash_info[i]);
-			fsize = CFG_FLASH1_BASE + flash_info[i - 1].size;
+			fsize = CONFIG_SYS_FLASH1_BASE + flash_info[i - 1].size;
 			flash_get_offsets (fsize, &flash_info[i]);
 			break;
 		case 2:
-			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
 					&flash_info[i]);
-			flash_get_offsets (CFG_FLASH0_BASE, &flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH0_BASE, &flash_info[i]);
 			break;
 		case 3:
-			flash_get_size ((FPW *) CFG_FLASH0_BASE,
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE,
 					&flash_info[i]);
-			fsize = CFG_FLASH0_BASE + flash_info[i - 1].size;
+			fsize = CONFIG_SYS_FLASH0_BASE + flash_info[i - 1].size;
 			flash_get_offsets (fsize, &flash_info[i]);
 			break;
 		default:
@@ -124,23 +124,23 @@
 
 	/* Protect monitor and environment sectors
 	 */
-#if defined (CFG_AMD_BOOT)
+#if defined (CONFIG_SYS_AMD_BOOT)
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		       &flash_info[2]);
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_INTEL_BASE,
-		       CFG_INTEL_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_INTEL_BASE,
+		       CONFIG_SYS_INTEL_BASE + monitor_flash_len - 1,
 		       &flash_info[1]);
 #else
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		       &flash_info[3]);
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_AMD_BASE,
-		       CFG_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
+		       CONFIG_SYS_AMD_BASE,
+		       CONFIG_SYS_AMD_BASE + monitor_flash_len - 1, &flash_info[0]);
 #endif
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -294,10 +294,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if (value == (FPW) INTEL_ID_28F128J3A)
@@ -348,7 +348,7 @@
 	/*
 	 * first, wait for the WSM to be finished. The rationale for
 	 * waiting for the WSM to become idle for at most
-	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
 	 * because of: (1) erase, (2) program or (3) lock bit
 	 * configuration. So we just wait for the longest timeout of
 	 * the (1)-(3), i.e. the erase timeout.
@@ -361,7 +361,7 @@
 
 	start = get_timer (0);
 	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			*addr = (FPW) INTEL_RESET; /* restore read mode */
 			printf("WSM busy too long, can't get prot status\n");
 			return 1;
@@ -391,7 +391,7 @@
  */
 static unsigned char same_chip_banks (int bank1, int bank2)
 {
-	unsigned char same_chip[CFG_MAX_FLASH_BANKS][CFG_MAX_FLASH_BANKS] = {
+	unsigned char same_chip[CONFIG_SYS_MAX_FLASH_BANKS][CONFIG_SYS_MAX_FLASH_BANKS] = {
 		{1, 1, 0, 0},
 		{1, 1, 0, 0},
 		{0, 0, 1, 1},
@@ -467,7 +467,7 @@
 			} else {
 				FPWV *base;	/* first address in bank */
 
-				base = (FPWV *) (CFG_AMD_BASE);
+				base = (FPWV *) (CONFIG_SYS_AMD_BASE);
 				base[FLASH_CYCLE1] = (FPW) 0x00AA00AA;	/* unlock */
 				base[FLASH_CYCLE2] = (FPW) 0x00550055;	/* unlock */
 				base[FLASH_CYCLE1] = (FPW) 0x00800080;	/* erase mode */
@@ -479,7 +479,7 @@
 			while (((status =
 				 *addr) & (FPW) 0x00800080) !=
 			       (FPW) 0x00800080) {
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					if (intel) {
 						*addr = (FPW) 0x00B000B0;	/* suspend erase     */
@@ -684,7 +684,7 @@
 
 	/* wait while polling the status register */
 	while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -728,7 +728,7 @@
 
 	/* wait while polling the status register */
 	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -746,7 +746,7 @@
 
 	/* wait while polling the status register */
 	while ((*dstaddr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dstaddr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -779,7 +779,7 @@
 		return (2);
 	}
 
-	base = (FPWV *) (CFG_AMD_BASE);
+	base = (FPWV *) (CONFIG_SYS_AMD_BASE);
 
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
@@ -799,7 +799,7 @@
 	/* data polling for D7 */
 	while (res == 0
 	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00F000F0;	/* reset bank */
 			res = 1;
 		}
@@ -856,7 +856,7 @@
 	start = get_timer (0);
 
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf ("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -886,17 +886,17 @@
 		 */
 
 		/* find the current bank number */
-		curr_bank = CFG_MAX_FLASH_BANKS + 1;
-		for (j = 0; j < CFG_MAX_FLASH_BANKS; ++j) {
+		curr_bank = CONFIG_SYS_MAX_FLASH_BANKS + 1;
+		for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; ++j) {
 			if (&flash_info[j] == info) {
 				curr_bank = j;
 			}
 		}
-		if (curr_bank == CFG_MAX_FLASH_BANKS + 1) {
+		if (curr_bank == CONFIG_SYS_MAX_FLASH_BANKS + 1) {
 			printf("Error: can't determine bank number!\n");
 		}
 
-		for (bank = 0; bank < CFG_MAX_FLASH_BANKS; ++bank) {
+		for (bank = 0; bank < CONFIG_SYS_MAX_FLASH_BANKS; ++bank) {
 			if (!same_chip_banks(curr_bank, bank)) {
 				continue;
 			}
@@ -910,7 +910,7 @@
 					while ((*addr & INTEL_FINISHED) !=
 					       INTEL_FINISHED) {
 						if (get_timer (start) >
-						    CFG_FLASH_UNLOCK_TOUT) {
+						    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 							printf ("Flash lock bit operation timed out\n");
 							rc = 1;
 							break;
diff --git a/board/altera/common/AMDLV065D.c b/board/altera/common/AMDLV065D.c
index 8a7b14e..0fcf354 100644
--- a/board/altera/common/AMDLV065D.c
+++ b/board/altera/common/AMDLV065D.c
@@ -30,7 +30,7 @@
 #endif
 
 #define SECTSZ		(64 * 1024)
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*----------------------------------------------------------------------*/
 unsigned long flash_init (void)
@@ -39,18 +39,18 @@
 	unsigned long addr;
 	flash_info_t *fli = &flash_info[0];
 
-	fli->size = CFG_FLASH_SIZE;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->size = CONFIG_SYS_FLASH_SIZE;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
 
-	addr = CFG_FLASH_BASE;
+	addr = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < fli->sector_count; ++i) {
 		fli->start[i] = addr;
 		addr += SECTSZ;
 		fli->protect[i] = 1;
 	}
 
-	return (CFG_FLASH_SIZE);
+	return (CONFIG_SYS_FLASH_SIZE);
 }
 /*--------------------------------------------------------------------*/
 void flash_print_info (flash_info_t * info)
@@ -135,7 +135,7 @@
 			while ( readb (addr2) != 0xff) {
 				udelay (1000 * 1000);
 				putc ('.');
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("timeout\n");
 					return 1;
 				}
@@ -177,7 +177,7 @@
 		/* Verify write */
 		start = get_timer (0);
 		while (readb (dst) != b) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return 1;
 			}
 		}
diff --git a/board/altera/common/epled.c b/board/altera/common/epled.c
index c75fe8c..e5e7705 100644
--- a/board/altera/common/epled.c
+++ b/board/altera/common/epled.c
@@ -33,7 +33,7 @@
 
 void __led_init (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
@@ -44,7 +44,7 @@
 
 void __led_set (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
@@ -55,7 +55,7 @@
 
 void __led_toggle (led_id_t mask)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	val ^= mask;
 	writel (&pio->data, val);
diff --git a/board/altera/common/flash.c b/board/altera/common/flash.c
index 2638ea8..83bb7c2 100644
--- a/board/altera/common/flash.c
+++ b/board/altera/common/flash.c
@@ -25,7 +25,7 @@
 #include <common.h>
 #include <nios.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*--------------------------------------------------------------------*/
 void flash_print_info (flash_info_t * info)
@@ -68,8 +68,8 @@
 
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int prot, sect;
 	unsigned oldpri;
 	ulong start;
@@ -112,7 +112,7 @@
 	 */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 			*addr = 0xaa;
 			*addr = 0x55;
 			*addr = 0x80;
@@ -128,7 +128,7 @@
 			while (*addr2 != 0xff) {
 				udelay (1000 * 1000);
 				putc ('.');
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("timeout\n");
 					return 1;
 				}
@@ -181,7 +181,7 @@
 		/* Verify write */
 		start = get_timer (0);
 		while (*dst != b) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				ipri (oldpri);
 				return 1;
 			}
diff --git a/board/altera/dk1c20/dk1c20.c b/board/altera/dk1c20/dk1c20.c
index 46695be..11c19b7 100644
--- a/board/altera/dk1c20/dk1c20.c
+++ b/board/altera/dk1c20/dk1c20.c
@@ -58,9 +58,9 @@
 #if defined(CONFIG_CMD_IDE)
 int ide_preinit (void)
 {
-	nios_pio_t *present = (nios_pio_t *) CFG_CF_PRESENT;
-	nios_pio_t *power = (nios_pio_t *) CFG_CF_POWER;
-	nios_pio_t *atasel = (nios_pio_t *) CFG_CF_ATASEL;
+	nios_pio_t *present = (nios_pio_t *) CONFIG_SYS_CF_PRESENT;
+	nios_pio_t *power = (nios_pio_t *) CONFIG_SYS_CF_POWER;
+	nios_pio_t *atasel = (nios_pio_t *) CONFIG_SYS_CF_ATASEL;
 
 	/* setup data direction registers */
 	present->direction = NIOS_PIO_IN;
diff --git a/board/altera/dk1c20/flash.c b/board/altera/dk1c20/flash.c
index 1f344dd..8bddd38 100644
--- a/board/altera/dk1c20/flash.c
+++ b/board/altera/dk1c20/flash.c
@@ -31,7 +31,7 @@
 #include "../common/flash.c"
 
 /*----------------------------------------------------------------------*/
-#define BANKSZ		CFG_FLASH_SIZE
+#define BANKSZ		CONFIG_SYS_FLASH_SIZE
 #define SECTSZ		(64 * 1024)
 #define USERFLASH	(2 * 1024 * 1024)	/* bottom 2 MB for user	*/
 
@@ -43,16 +43,16 @@
 	flash_info_t *fli = &flash_info[0];
 
 	fli->size = BANKSZ;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
 
-	addr = CFG_FLASH_BASE;
+	addr = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < fli->sector_count; ++i) {
 		fli->start[i] = addr;
 		addr += SECTSZ;
 
 		/* Protect all but 2 MByte user area */
-		if (addr < (CFG_FLASH_BASE + USERFLASH))
+		if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH))
 			fli->protect[i] = 0;
 		else
 			fli->protect[i] = 1;
diff --git a/board/altera/dk1s10/flash.c b/board/altera/dk1s10/flash.c
index 5c70933..d1f2db1 100644
--- a/board/altera/dk1s10/flash.c
+++ b/board/altera/dk1s10/flash.c
@@ -43,16 +43,16 @@
 	flash_info_t *fli = &flash_info[0];
 
 	fli->size = BANKSZ;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
 
-	addr = CFG_FLASH_BASE;
+	addr = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < fli->sector_count; ++i) {
 		fli->start[i] = addr;
 		addr += SECTSZ;
 
 		/* Protect all but 2 MByte user area */
-		if (addr < (CFG_FLASH_BASE + USERFLASH))
+		if (addr < (CONFIG_SYS_FLASH_BASE + USERFLASH))
 			fli->protect[i] = 0;
 		else
 			fli->protect[i] = 1;
diff --git a/board/altera/dk1s10/vectors.S b/board/altera/dk1s10/vectors.S
index 2f44875..226f65b 100644
--- a/board/altera/dk1s10/vectors.S
+++ b/board/altera/dk1s10/vectors.S
@@ -58,12 +58,12 @@
 	.align	4
 _vectors:
 
-#if	defined(CFG_NIOS_CPU_OCI_BASE)
+#if	defined(CONFIG_SYS_NIOS_CPU_OCI_BASE)
 	/* OCI does the reset job */
 	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
 #else
 	/* there is no OCI, so we have to do a direct reset jump here */
-	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+	.long	CONFIG_SYS_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
 #endif
 	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
@@ -81,7 +81,7 @@
 	.long	_def_xhandler@h		/* Vector 13 - future reserved */
 	.long	_def_xhandler@h		/* Vector 14 - future reserved */
 	.long	_def_xhandler@h		/* Vector 15 - future reserved */
-#if	(CFG_NIOS_TMRIRQ == 16)
+#if	(CONFIG_SYS_NIOS_TMRIRQ == 16)
 	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
 #else
 	.long	_def_xhandler@h		/* Vector 16 */
@@ -119,7 +119,7 @@
 	.long	_def_xhandler@h		/* Vector 47 */
 	.long	_def_xhandler@h		/* Vector 48 */
 	.long	_def_xhandler@h		/* Vector 49 */
-#if	(CFG_NIOS_TMRIRQ == 50)
+#if	(CONFIG_SYS_NIOS_TMRIRQ == 50)
 	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
 #else
 	.long	_def_xhandler@h		/* Vector 50 */
diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c
index 8b82ea4..8d79be2 100644
--- a/board/amcc/acadia/acadia.c
+++ b/board/amcc/acadia/acadia.c
@@ -31,24 +31,24 @@
 	/*
 	 * GPIO0 setup (select GPIO or alternate function)
 	 */
-	out32(GPIO0_OSRL, CFG_GPIO0_OSRL);
-	out32(GPIO0_OSRH, CFG_GPIO0_OSRH);	/* output select */
-	out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L);
-	out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H);	/* input select */
-	out32(GPIO0_TSRL, CFG_GPIO0_TSRL);
-	out32(GPIO0_TSRH, CFG_GPIO0_TSRH);	/* three-state select */
-	out32(GPIO0_TCR, CFG_GPIO0_TCR);  /* enable output driver for outputs */
+	out32(GPIO0_OSRL, CONFIG_SYS_GPIO0_OSRL);
+	out32(GPIO0_OSRH, CONFIG_SYS_GPIO0_OSRH);	/* output select */
+	out32(GPIO0_ISR1L, CONFIG_SYS_GPIO0_ISR1L);
+	out32(GPIO0_ISR1H, CONFIG_SYS_GPIO0_ISR1H);	/* input select */
+	out32(GPIO0_TSRL, CONFIG_SYS_GPIO0_TSRL);
+	out32(GPIO0_TSRH, CONFIG_SYS_GPIO0_TSRH);	/* three-state select */
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO0_TCR);  /* enable output driver for outputs */
 
 	/*
 	 * Ultra (405EZ) was nice enough to add another GPIO controller
 	 */
-	out32(GPIO1_OSRH, CFG_GPIO1_OSRH);	/* output select */
-	out32(GPIO1_OSRL, CFG_GPIO1_OSRL);
-	out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H);	/* input select */
-	out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L);
-	out32(GPIO1_TSRH, CFG_GPIO1_TSRH);	/* three-state select */
-	out32(GPIO1_TSRL, CFG_GPIO1_TSRL);
-	out32(GPIO1_TCR, CFG_GPIO1_TCR);  /* enable output driver for outputs */
+	out32(GPIO1_OSRH, CONFIG_SYS_GPIO1_OSRH);	/* output select */
+	out32(GPIO1_OSRL, CONFIG_SYS_GPIO1_OSRL);
+	out32(GPIO1_ISR1H, CONFIG_SYS_GPIO1_ISR1H);	/* input select */
+	out32(GPIO1_ISR1L, CONFIG_SYS_GPIO1_ISR1L);
+	out32(GPIO1_TSRH, CONFIG_SYS_GPIO1_TSRH);	/* three-state select */
+	out32(GPIO1_TSRL, CONFIG_SYS_GPIO1_TSRL);
+	out32(GPIO1_TCR, CONFIG_SYS_GPIO1_TCR);  /* enable output driver for outputs */
 }
 
 int board_early_init_f(void)
@@ -68,7 +68,7 @@
 	mtsdr(sdrnand0, SDR_NAND0_NDEN | SDR_NAND0_NDAREN | SDR_NAND0_NDRBEN);
 	mfsdr(sdrultra0, reg);
 	reg &= ~SDR_ULTRA0_CSN_MASK;
-	reg |= (SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS) |
+	reg |= (SDR_ULTRA0_CSNSEL0 >> CONFIG_SYS_NAND_CS) |
 		SDR_ULTRA0_NDGPIOBP |
 		SDR_ULTRA0_EBCRDYEN |
 		SDR_ULTRA0_NFSRSTEN;
@@ -91,7 +91,7 @@
 int misc_init_f(void)
 {
 	/* Set EPLD to take PHY out of reset */
-	out8(CFG_CPLD_BASE + 0x05, 0x00);
+	out8(CONFIG_SYS_CPLD_BASE + 0x05, 0x00);
 	udelay(100000);
 
 	return 0;
@@ -105,7 +105,7 @@
 	char *s = getenv("serial#");
 	u8 rev;
 
-	rev = in8(CFG_CPLD_BASE + 0);
+	rev = in8(CONFIG_SYS_CPLD_BASE + 0);
 	printf("Board: Acadia - AMCC PPC405EZ Evaluation Board, Rev. %X", rev);
 
 	if (s != NULL) {
diff --git a/board/amcc/acadia/cmd_acadia.c b/board/amcc/acadia/cmd_acadia.c
index fb7ea35..052cf61 100644
--- a/board/amcc/acadia/cmd_acadia.c
+++ b/board/amcc/acadia/cmd_acadia.c
@@ -84,7 +84,7 @@
 
 	if (i2c_write(chip, 0, 1, buf, 16) != 0)
 		printf("Error writing to EEPROM at address 0x%x\n", chip);
-	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 	if (i2c_write(chip, 0x10, 1, buf+16, 4) != 0)
 		printf("Error2 writing to EEPROM at address 0x%x\n", chip);
 
diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c
index 48a6725..3e5c80e 100644
--- a/board/amcc/acadia/memory.c
+++ b/board/amcc/acadia/memory.c
@@ -39,7 +39,7 @@
 	wr_val <<= 2;
 
 	/* set CRAM_CRE to 1 */
-	gpio_write_bit(CFG_GPIO_CRAM_CRE, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 1);
 
 	/* Write BCR to CRAM on CS1 */
 	out32(wr_val + 0x00200000, 0);
@@ -53,7 +53,7 @@
 	eieio();
 
 	/* set CRAM_CRE back to 0 (normal operation) */
-	gpio_write_bit(CFG_GPIO_CRAM_CRE, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_CRAM_CRE, 0);
 
 	return;
 }
@@ -75,10 +75,10 @@
 	u32 val;
 
 	/* 1. EBC need to program READY, CLK, ADV for ASync mode */
-	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
-	gpio_config(CFG_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CRE, GPIO_OUT, GPIO_SEL, GPIO_OUT_0);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_WAIT, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG);
 
 	/* 2. EBC in Async mode */
 	mtebc(pb1ap, 0x078F1EC0);
@@ -94,8 +94,8 @@
 	mtebc(pb2ap, 0x9C0201C0);
 
 	/* Set GPIO pins back to alternate function */
-	gpio_config(CFG_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
-	gpio_config(CFG_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_CLK, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
+	gpio_config(CONFIG_SYS_GPIO_CRAM_ADV, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG);
 
 	/* Config EBC to use RDY */
 	mfsdr(sdrultra0, val);
@@ -106,5 +106,5 @@
 		;
 #endif
 
-	return (CFG_MBYTES_RAM << 20);
+	return (CONFIG_SYS_MBYTES_RAM << 20);
 }
diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c
index f415701..febc61a 100644
--- a/board/amcc/bamboo/bamboo.c
+++ b/board/amcc/bamboo/bamboo.c
@@ -462,7 +462,7 @@
 
 	return dram_size;
 #else
-	return CFG_MBYTES_SDRAM << 20;
+	return CONFIG_SYS_MBYTES_SDRAM << 20;
 #endif
 }
 
@@ -529,7 +529,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -543,14 +543,14 @@
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
@@ -565,8 +565,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -580,13 +580,13 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -601,7 +601,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
diff --git a/board/amcc/bamboo/config.mk b/board/amcc/bamboo/config.mk
index b46527d..a37636a 100644
--- a/board/amcc/bamboo/config.mk
+++ b/board/amcc/bamboo/config.mk
@@ -34,5 +34,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c
index d004ed7..001348a 100644
--- a/board/amcc/bamboo/flash.c
+++ b/board/amcc/bamboo/flash.c
@@ -45,12 +45,12 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 /*
  * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
  */
-static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0x87800001, 0xFFF00000, 0xFFF80000}, /* 0:boot from small flash */
 	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
 	{0x87800001, 0x00000000, 0x00000000}, /* 0:boot from nand flash  */
@@ -79,7 +79,7 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 	unsigned long val;
@@ -128,7 +128,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -150,8 +150,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[i]);
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/bamboo/init.S b/board/amcc/bamboo/init.S
index f4d2ae3..a5c9d6d 100644
--- a/board/amcc/bamboo/init.S
+++ b/board/amcc/bamboo/init.S
@@ -48,29 +48,29 @@
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
 #ifndef CONFIG_NAND_SPL
-	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #else
-	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 #endif
 
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 
 	/* PCI base & peripherals */
-	tlbentry(CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
-	tlbentry(CFG_NAND_ADDR, SZ_4K, CFG_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+	tlbentry(CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
+	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_4K, CONFIG_SYS_NAND_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I)
 
 	/* PCI */
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I)
 
 	/* USB 2.0 Device */
-	tlbentry(CFG_USB_DEVICE, SZ_1K, CFG_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_USB_DEVICE, SZ_1K, CONFIG_SYS_USB_DEVICE, 0, AC_R|AC_W|SA_G|SA_I)
 
 	tlbtab_end
 
@@ -79,8 +79,8 @@
 	 * For NAND booting the first TLB has to be reconfigured to full size
 	 * and with caching disabled after running from RAM!
 	 */
-#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 0)
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 0)
 #define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	.globl	reconfig_tlb0
diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c
index d71cc29..a10babb 100644
--- a/board/amcc/bubinga/flash.c
+++ b/board/amcc/bubinga/flash.c
@@ -32,7 +32,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 #undef DEBUG
 #ifdef DEBUG
@@ -60,7 +60,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -75,14 +75,14 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
 		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
 
 		/* Monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[0]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
@@ -133,7 +133,7 @@
 
 		/* monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    base_b0 + size_b0 - CFG_MONITOR_LEN,
+				    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
 				    base_b0 + size_b0 - 1, &flash_info[0]);
 		/* Also protect sector containing initial power-up instruction */
 		/* (flash_protect() checks address range - other call ignored) */
@@ -151,12 +151,12 @@
 
 			/* monitor protection ON by default */
 			(void)flash_protect(FLAG_PROTECT_SET,
-					    base_b1 + size_b1 - CFG_MONITOR_LEN,
+					    base_b1 + size_b1 - CONFIG_SYS_MONITOR_LEN,
 					    base_b1 + size_b1 - 1,
 					    &flash_info[1]);
 			/* monitor protection OFF by default (one is enough) */
 			(void)flash_protect(FLAG_PROTECT_CLEAR,
-					    base_b0 + size_b0 - CFG_MONITOR_LEN,
+					    base_b0 + size_b0 - CONFIG_SYS_MONITOR_LEN,
 					    base_b0 + size_b0 - 1,
 					    &flash_info[0]);
 		} else {
diff --git a/board/amcc/canyonlands/bootstrap.c b/board/amcc/canyonlands/bootstrap.c
index 1d125b6..6b74743 100644
--- a/board/amcc/canyonlands/bootstrap.c
+++ b/board/amcc/canyonlands/bootstrap.c
@@ -168,7 +168,7 @@
 
 	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
 		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
-	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 
 	printf("Done\n");
 	printf("Please power-cycle the board for the changes to take effect\n");
diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c
index 47667ee..e9186f8 100644
--- a/board/amcc/canyonlands/canyonlands.c
+++ b/board/amcc/canyonlands/canyonlands.c
@@ -29,11 +29,11 @@
 #include <asm/4xx_pcie.h>
 #include <asm/gpio.h>
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#define CFG_BCSR3_PCIE		0x10
+#define CONFIG_SYS_BCSR3_PCIE		0x10
 
 #define BOARD_CANYONLANDS_PCIE	1
 #define BOARD_CANYONLANDS_SATA	2
@@ -86,7 +86,7 @@
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
 		SDR0_CUST0_NDFC_BAC_ENCODE(3)	|
-		(0x80000000 >> (28 + CFG_NAND_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	/*
@@ -99,13 +99,13 @@
 	mtsdr(SDR0_PCI0, 0xe0000000);
 
 	/* Enable ethernet and take out of reset */
-	out_8((void *)CFG_BCSR_BASE + 6, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 6, 0);
 
 	/* Remove NOR-FLASH, NAND-FLASH & EEPROM hardware write protection */
-	out_8((void *)CFG_BCSR_BASE + 5, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 5, 0);
 
 	/* Enable USB host & USB-OTG */
-	out_8((void *)CFG_BCSR_BASE + 7, 0);
+	out_8((void *)CONFIG_SYS_BCSR_BASE + 7, 0);
 
 	mtsdr(SDR0_SRST1, 0);	/* Pull AHB out of reset default=1 */
 
@@ -158,7 +158,7 @@
 		gd->board_type = BOARD_GLACIER;
 	} else {
 		printf("Board: Canyonlands - AMCC PPC460EX Evaluation Board");
-		if (in_8((void *)(CFG_BCSR_BASE + 3)) & CFG_BCSR3_PCIE)
+		if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 3)) & CONFIG_SYS_BCSR3_PCIE)
 			gd->board_type = BOARD_CANYONLANDS_PCIE;
 		else
 			gd->board_type = BOARD_CANYONLANDS_SATA;
@@ -175,7 +175,7 @@
 		break;
 	}
 
-	printf(", Rev. %X", in_8((void *)(CFG_BCSR_BASE + 0)));
+	printf(", Rev. %X", in_8((void *)(CONFIG_SYS_BCSR_BASE + 0)));
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -208,7 +208,7 @@
  */
 phys_size_t initdram(int board_type)
 {
-	return CFG_MBYTES_SDRAM << 20;
+	return CONFIG_SYS_MBYTES_SDRAM << 20;
 }
 #endif
 
@@ -219,7 +219,7 @@
  *	inbound map (PIM). But the bootstrap config choices are limited and
  *	may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*
@@ -234,7 +234,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 */
-	out_le32((void *)PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out_le32((void *)PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 	out_le32((void *)PCIX0_PIM0LAH, 0);
 	out_le32((void *)PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 	out_le32((void *)PCIX0_BAR0, 0);
@@ -242,12 +242,12 @@
 	/*
 	 * Program the board's subsystem id/vendor id
 	 */
-	out_le16((void *)PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-	out_le16((void *)PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+	out_le16((void *)PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out_le16((void *)PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
 	out_le16((void *)PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 #if defined(CONFIG_PCI)
 /*
@@ -314,9 +314,9 @@
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMSIZE,
 			       PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
@@ -362,16 +362,16 @@
 
 	/* Remap the NOR FLASH to 0xcc00.0000 ... 0xcfff.ffff */
 #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
-	mtebc(pb3cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+	mtebc(pb3cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 #else
-	mtebc(pb0cr, CFG_FLASH_BASE_PHYS_L | 0xda000);
+	mtebc(pb0cr, CONFIG_SYS_FLASH_BASE_PHYS_L | 0xda000);
 #endif
 
 	/* Remove TLB entry of boot EBC mapping */
-	remove_tlb(CFG_BOOT_BASE_ADDR, 16 << 20);
+	remove_tlb(CONFIG_SYS_BOOT_BASE_ADDR, 16 << 20);
 
 	/* Add TLB entry for 0xfc00.0000 -> 0x4.cc00.0000 */
-	program_tlb(CFG_FLASH_BASE_PHYS, CFG_FLASH_BASE, CFG_FLASH_SIZE,
+	program_tlb(CONFIG_SYS_FLASH_BASE_PHYS, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE,
 		    TLB_WORD2_I_ENABLE);
 
 	/*
@@ -427,9 +427,9 @@
 	 * Disable square wave output: Batterie will be drained
 	 * quickly, when this output is not disabled
 	 */
-	val = i2c_reg_read(CFG_I2C_RTC_ADDR, 0xa);
+	val = i2c_reg_read(CONFIG_SYS_I2C_RTC_ADDR, 0xa);
 	val &= ~0x40;
-	i2c_reg_write(CFG_I2C_RTC_ADDR, 0xa, val);
+	i2c_reg_write(CONFIG_SYS_I2C_RTC_ADDR, 0xa, val);
 
 	return 0;
 }
@@ -445,7 +445,7 @@
 	/* Fixup NOR mapping */
 	val[0] = 0;				/* chip select number */
 	val[1] = 0;				/* always 0 */
-	val[2] = CFG_FLASH_BASE_PHYS_L;		/* we fixed up this address */
+	val[2] = CONFIG_SYS_FLASH_BASE_PHYS_L;		/* we fixed up this address */
 	val[3] = gd->bd->bi_flashsize;
 	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 				  val, sizeof(val), 1);
diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk
index 2330cae..551a817 100644
--- a/board/amcc/canyonlands/config.mk
+++ b/board/amcc/canyonlands/config.mk
@@ -37,5 +37,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/canyonlands/init.S b/board/amcc/canyonlands/init.S
index 258fb5d..179dd32 100644
--- a/board/amcc/canyonlands/init.S
+++ b/board/amcc/canyonlands/init.S
@@ -47,10 +47,10 @@
 	 * enable SA_I
 	 */
 #ifndef CONFIG_NAND_SPL
-	tlbentry(CFG_BOOT_BASE_ADDR, SZ_16M, CFG_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_16M, CONFIG_SYS_BOOT_BASE_ADDR, 4, AC_R|AC_W|AC_X|SA_G) /* TLB 0 */
 #else
-	tlbentry(CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
-	tlbentry(CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 4, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 	tlbentry(256 << 20, SZ_256M, 256 << 20, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
 #endif
 
@@ -60,37 +60,37 @@
 	 * routine.
 	 */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
 	/* PCIe UTL register */
-	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x08010000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
 	/* TLB-entry for NAND */
-	tlbentry(CFG_NAND_ADDR, SZ_16M, CFG_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_NAND_ADDR, SZ_16M, CONFIG_SYS_NAND_ADDR, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	/* TLB-entry for CPLD */
-	tlbentry(CFG_BCSR_BASE, SZ_1K, CFG_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_BCSR_BASE, SZ_1K, CONFIG_SYS_BCSR_BASE, 4, AC_R|AC_W|SA_G|SA_I)
 
 	/* TLB-entry for OCM */
-	tlbentry(CFG_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_OCM_BASE, SZ_16K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
 
 	/* TLB-entry for Local Configuration registers => peripherals */
-	tlbentry(CFG_LOCAL_CONF_REGS, SZ_16M, CFG_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_LOCAL_CONF_REGS, SZ_16M, CONFIG_SYS_LOCAL_CONF_REGS, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	/* AHB: Internal USB Peripherals (USB, SATA) */
-	tlbentry(CFG_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_AHB_BASE, SZ_1M, 0xbff00000, 4, AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	tlbtab_end
 
@@ -99,8 +99,8 @@
 	 * For NAND booting the first TLB has to be reconfigured to full size
 	 * and with caching disabled after running from RAM!
 	 */
-#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 #define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	.globl	reconfig_tlb0
diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c
index eba0511..9943c74 100644
--- a/board/amcc/common/flash.c
+++ b/board/amcc/common/flash.c
@@ -35,13 +35,13 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
  */
 static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word_1(flash_info_t * info, ulong dest, ulong data);
 static int write_word_2(flash_info_t * info, ulong dest, ulong data);
 static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
@@ -171,7 +171,7 @@
 /*
  * The following code cannot be run from FLASH!
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 {
 	/* bit 0 used for big flash marking */
@@ -188,32 +188,32 @@
 #endif
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
 	default:
@@ -227,67 +227,67 @@
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;		/* => 512 KiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
 		info->flash_id += FLASH_AMD016;
 		info->sector_count = 32;
 		info->size = 0x00200000;	/* => 2 MiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
 		info->size = 0x00400000;	/* => 4 MiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;	/* => 512 KiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;	/* => 512 KiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;	/* => 1 MiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;	/* => 1 MiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;	/* => 2 MiB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;	/* => 2 MiB */
@@ -331,14 +331,14 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@@ -348,7 +348,7 @@
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -356,14 +356,14 @@
 static int wait_for_DQ7_1(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -376,7 +376,7 @@
 	return 0;
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
 	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@@ -394,8 +394,8 @@
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -435,24 +435,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -474,8 +474,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -557,7 +557,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 {
 	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@@ -575,9 +575,9 @@
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
@@ -586,15 +586,15 @@
 		return (2);
 	}
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -604,10 +604,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -616,10 +616,10 @@
 	return (0);
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 
-#undef  CFG_FLASH_WORD_SIZE
-#define CFG_FLASH_WORD_SIZE unsigned short
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
 
 /*
  * The following code cannot be run from FLASH!
@@ -628,35 +628,35 @@
 {
 	short i;
 	int n;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
-	case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
 		info->flash_id = FLASH_MAN_MX;
 		break;
 	default:
@@ -672,22 +672,22 @@
 
 	switch (value) {
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
-	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
 		info->flash_id += FLASH_STMW320DT;
 		info->sector_count = 67;
 		info->size = 0x00400000;  break;	/* => 4 MiB	*/
 
-	case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
 		info->flash_id += FLASH_MXLV320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;
@@ -776,14 +776,14 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@@ -793,7 +793,7 @@
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -801,14 +801,14 @@
 static int wait_for_DQ7_2(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -823,8 +823,8 @@
 
 static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -864,24 +864,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -903,8 +903,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -912,9 +912,9 @@
 
 static int write_word_2(flash_info_t * info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
@@ -923,15 +923,15 @@
 		return (2);
 	}
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -941,10 +941,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -952,4 +952,4 @@
 
 	return (0);
 }
-#endif /* CFG_FLASH_2ND_16BIT_DEV */
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
diff --git a/board/amcc/ebony/config.mk b/board/amcc/ebony/config.mk
index e5722dd..60d3bf4 100644
--- a/board/amcc/ebony/config.mk
+++ b/board/amcc/ebony/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/ebony/ebony.c b/board/amcc/ebony/ebony.c
index 9bcdf59..ad09e62 100644
--- a/board/amcc/ebony/ebony.c
+++ b/board/amcc/ebony/ebony.c
@@ -35,7 +35,7 @@
 int board_early_init_f(void)
 {
 	uint reg;
-	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
 	unsigned char status;
 
 	/*--------------------------------------------------------------------
@@ -204,7 +204,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -219,7 +219,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
      * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 	out32r(PCIX0_PIM0LAH, 0);
 	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
@@ -228,12 +228,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+	out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
 	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host
diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c
index d9c6974..8fe3ba1 100644
--- a/board/amcc/ebony/flash.c
+++ b/board/amcc/ebony/flash.c
@@ -50,7 +50,7 @@
 #define     FLASH_ONBD_N_VAL        2
 #define     FLASH_SRAM_SEL_VAL      1
 
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xffc00000, 0xffe00000, 0xff880000},	/* 0:000: configuraton 3 */
 	{0xffc00000, 0xffe00000, 0xff800000},	/* 1:001: configuraton 4 */
 	{0xffc00000, 0xffe00000, 0x00000000},	/* 2:010: configuraton 7 */
@@ -74,8 +74,8 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
-	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
 	unsigned char switch_status;
 	unsigned short index = 0;
 	int i;
@@ -98,7 +98,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -121,8 +121,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[2]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S
index c86076e..811a96a 100644
--- a/board/amcc/ebony/init.S
+++ b/board/amcc/ebony/init.S
@@ -49,9 +49,9 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
-	tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/katmai/config.mk b/board/amcc/katmai/config.mk
index c512b53..ef0cf96 100644
--- a/board/amcc/katmai/config.mk
+++ b/board/amcc/katmai/config.mk
@@ -34,5 +34,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S
index e3f3da6..1c74a82 100644
--- a/board/amcc/katmai/init.S
+++ b/board/amcc/katmai/init.S
@@ -59,20 +59,20 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
 
 /**************************************************************************
@@ -99,20 +99,20 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
 
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_ACE_BASE, SZ_1K, CFG_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_ACE_BASE, SZ_1K, CONFIG_SYS_ACE_BASE, 4,AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c
index 172b581..b6c0c11 100644
--- a/board/amcc/katmai/katmai.c
+++ b/board/amcc/katmai/katmai.c
@@ -224,11 +224,11 @@
 	mfr |= SDR0_MFR_FIXD;		/* Workaround for PCI/DMA */
 	mtsdr(sdr_mfr, mfr);
 
-	mtsdr(SDR0_PFC0, CFG_PFC0);
+	mtsdr(SDR0_PFC0, CONFIG_SYS_PFC0);
 
-	out32(GPIO0_OR, CFG_GPIO_OR);
-	out32(GPIO0_ODR, CFG_GPIO_ODR);
-	out32(GPIO0_TCR, CFG_GPIO_TCR);
+	out32(GPIO0_OR, CONFIG_SYS_GPIO_OR);
+	out32(GPIO0_ODR, CONFIG_SYS_GPIO_ODR);
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO_TCR);
 
 	return 0;
 }
@@ -298,7 +298,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*-------------------------------------------------------------------+
@@ -313,7 +313,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 	out32r( PCIX0_BAR0, 0 );
@@ -321,12 +321,12 @@
 	/*-------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *-------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 #if defined(CONFIG_PCI)
 /*************************************************************************
@@ -357,11 +357,11 @@
 	val = in32(GPIO0_IR);
 	switch (port) {
 	case 0:
-		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT0));
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0));
 	case 1:
-		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT1));
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1));
 	case 2:
-		return !(val & GPIO_VAL(CFG_GPIO_PCIE_PRESENT2));
+		return !(val & GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2));
 	default:
 		return 0;
 	}
@@ -404,9 +404,9 @@
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMSIZE,
 			       PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
diff --git a/board/amcc/kilauea/cmd_pll.c b/board/amcc/kilauea/cmd_pll.c
index 0d2f27f..0f571fe 100644
--- a/board/amcc/kilauea/cmd_pll.c
+++ b/board/amcc/kilauea/cmd_pll.c
@@ -48,7 +48,7 @@
 	do {								\
 		int __i;						\
 		for (__i = 0; __i < 2; __i++)				\
-			eeprom_write (CFG_I2C_EEPROM_ADDR,		\
+			eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR,		\
 				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
 				      pll_select[freq],			\
 				      BUF_STEP + __i*BUF_STEP);		\
@@ -151,7 +151,7 @@
 	uchar buffer[EEPROM_SDSTP_PARAM];
 
 	memset(buffer, 0, sizeof(buffer));
-	eeprom_read(CFG_I2C_EEPROM_ADDR, off,
+	eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
 		    buffer, EEPROM_SDSTP_PARAM);
 
 	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
@@ -168,9 +168,9 @@
 	/*
 	 * Write twice, 8 bytes per write
 	 */
-	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
 		      testbuf, 8);
-	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
 		      testbuf, 16);
 	printf("done\n");
 
@@ -236,7 +236,7 @@
 }
 
 U_BOOT_CMD(
-	pllalter, CFG_MAXARGS, 1,        do_pll_alter,
+	pllalter, CONFIG_SYS_MAXARGS, 1,        do_pll_alter,
 	"pllalter- change pll frequence \n",
 	"pllalter <selection>      - change pll frequence \n\n\
 	** New freq take effect after reset. ** \n\
diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c
index f407e19..7e84a61 100644
--- a/board/amcc/kilauea/kilauea.c
+++ b/board/amcc/kilauea/kilauea.c
@@ -36,7 +36,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*
  * Board early initialization function
@@ -197,7 +197,7 @@
 		SDR0_CUST0_NDFC_ENABLE |
 		SDR0_CUST0_NDFC_BW_8_BIT |
 		SDR0_CUST0_NRB_BUSY |
-		(0x80000000 >> (28 + CFG_NAND_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 	mtsdr(SDR0_CUST0, val);
 
 	/*
@@ -210,9 +210,9 @@
 	/*
 	 * Configure FPGA register with PCIe reset
 	 */
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
+	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc4);	/* assert PCIe reset */
 	mdelay(50);
-	out_be32((void *)CFG_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
+	out_be32((void *)CONFIG_SYS_FPGA_BASE, 0xff570cc7);	/* deassert PCIe reset */
 
 	return 0;
 }
@@ -222,7 +222,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      -CFG_MONITOR_LEN,
+		      -CONFIG_SYS_MONITOR_LEN,
 		      0xffffffff,
 		      &flash_info[0]);
 #endif
@@ -330,9 +330,9 @@
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMSIZE,
 			       PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk
index f52c206..cd02aab 100644
--- a/board/amcc/luan/config.mk
+++ b/board/amcc/luan/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c
index d28bf9d..2d3b154 100644
--- a/board/amcc/luan/flash.c
+++ b/board/amcc/luan/flash.c
@@ -42,7 +42,7 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-static unsigned long flash_addr_table[1][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[1][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xff900000, 0xff980000, 0xffc00000},	/* 0:000: configuraton 3 */
 };
 
@@ -59,7 +59,7 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 
@@ -69,7 +69,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -92,8 +92,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[2]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S
index d5ee117..fb54dea 100644
--- a/board/amcc/luan/init.S
+++ b/board/amcc/luan/init.S
@@ -54,7 +54,7 @@
 	tlbentry(0xffd00000, SZ_1M, 0xffd00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 	tlbentry(0xffe00000, SZ_1M, 0xffe00000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
 	tlbentry(0xff900000, SZ_1M, 0xff900000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_EPLD_BASE, SZ_256K, 0xff000000, 1, AC_R|AC_W|SA_G|SA_I)
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -63,12 +63,12 @@
 	 */
 
 	/* internal ram (l2 cache) */
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_I)
 
 	/* peripherals at f0000000 */
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, CFG_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, CONFIG_SYS_PERIPHERAL_BASE, 1, AC_R|AC_W|SA_G|SA_I)
 
 	/* PCI */
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 9, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 9, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c
index b14b6e1..b28ebf9 100644
--- a/board/amcc/luan/luan.c
+++ b/board/amcc/luan/luan.c
@@ -30,7 +30,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 
 /*************************************************************************
@@ -80,7 +80,7 @@
  ************************************************************************/
 int misc_init_r(void)
 {
-	volatile epld_t *x = (epld_t *) CFG_EPLD_BASE;
+	volatile epld_t *x = (epld_t *) CONFIG_SYS_EPLD_BASE;
 
 	/* set modes of operation */
 	x->ethuart |= EPLD2_ETH_MODE_10 | EPLD2_ETH_MODE_100 |
@@ -166,7 +166,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -181,7 +181,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -190,12 +190,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 
 /*************************************************************************
diff --git a/board/amcc/makalu/cmd_pll.c b/board/amcc/makalu/cmd_pll.c
index 0d2f27f..0f571fe 100644
--- a/board/amcc/makalu/cmd_pll.c
+++ b/board/amcc/makalu/cmd_pll.c
@@ -48,7 +48,7 @@
 	do {								\
 		int __i;						\
 		for (__i = 0; __i < 2; __i++)				\
-			eeprom_write (CFG_I2C_EEPROM_ADDR,		\
+			eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR,		\
 				      EEPROM_CONF_OFFSET + __i*BUF_STEP, \
 				      pll_select[freq],			\
 				      BUF_STEP + __i*BUF_STEP);		\
@@ -151,7 +151,7 @@
 	uchar buffer[EEPROM_SDSTP_PARAM];
 
 	memset(buffer, 0, sizeof(buffer));
-	eeprom_read(CFG_I2C_EEPROM_ADDR, off,
+	eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, off,
 		    buffer, EEPROM_SDSTP_PARAM);
 
 	printf("Debug: SDSTP[0-3] at offset \"0x%02x\" lists as follows: \n", off);
@@ -168,9 +168,9 @@
 	/*
 	 * Write twice, 8 bytes per write
 	 */
-	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET,
 		      testbuf, 8);
-	eeprom_write (CFG_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
+	eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, EEPROM_TEST_OFFSET+8,
 		      testbuf, 16);
 	printf("done\n");
 
@@ -236,7 +236,7 @@
 }
 
 U_BOOT_CMD(
-	pllalter, CFG_MAXARGS, 1,        do_pll_alter,
+	pllalter, CONFIG_SYS_MAXARGS, 1,        do_pll_alter,
 	"pllalter- change pll frequence \n",
 	"pllalter <selection>      - change pll frequence \n\n\
 	** New freq take effect after reset. ** \n\
diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c
index fc79907..9fc0ec6 100644
--- a/board/amcc/makalu/makalu.c
+++ b/board/amcc/makalu/makalu.c
@@ -37,7 +37,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*
  * Board early initialization function
@@ -194,9 +194,9 @@
 	mtsdr(SDR0_SRST, 0);
 
 	/* Reset PCIe slots */
-	gpio_write_bit(CFG_GPIO_PCIE_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 0);
 	udelay(100);
-	gpio_write_bit(CFG_GPIO_PCIE_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PCIE_RST, 1);
 
 	/*
 	 * Configure PFC (Pin Function Control) registers
@@ -213,7 +213,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      -CFG_MONITOR_LEN,
+		      -CONFIG_SYS_MONITOR_LEN,
 		      0xffffffff,
 		      &flash_info[0]);
 #endif
@@ -286,9 +286,9 @@
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			       CFG_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			       CONFIG_SYS_PCIE_MEMSIZE,
 			       PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
diff --git a/board/amcc/ocotea/config.mk b/board/amcc/ocotea/config.mk
index 9e18335..b62e776 100644
--- a/board/amcc/ocotea/config.mk
+++ b/board/amcc/ocotea/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c
index 46c6946..a83f93a 100644
--- a/board/amcc/ocotea/flash.c
+++ b/board/amcc/ocotea/flash.c
@@ -53,9 +53,9 @@
 #define     FLASH_ONBD_N_VAL        2
 #define     FLASH_SRAM_SEL_VAL      1
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xFF800000, 0xFF880000, 0xFFC00000},	/* 0:000: configuraton 4 */
 	{0xFF900000, 0xFF980000, 0xFFC00000},	/* 1:001: configuraton 3 */
 	{0x00000000, 0x00000000, 0x00000000},	/* 2:010: configuraton 8 */
@@ -83,8 +83,8 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
-	unsigned char *fpga_base = (unsigned char *)CFG_FPGA_BASE;
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
+	unsigned char *fpga_base = (unsigned char *)CONFIG_SYS_FPGA_BASE;
 	unsigned char switch_status;
 	unsigned short index = 0;
 	int i;
@@ -107,7 +107,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -131,8 +131,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[i]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S
index d211c71..8bcfbb1 100644
--- a/board/amcc/ocotea/init.S
+++ b/board/amcc/ocotea/init.S
@@ -49,9 +49,9 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
-	tlbentry(CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c
index 4d1d093..fe45408 100644
--- a/board/amcc/ocotea/ocotea.c
+++ b/board/amcc/ocotea/ocotea.c
@@ -42,7 +42,7 @@
 int board_early_init_f (void)
 {
 	unsigned long mfr;
-	unsigned char *fpga_base = (unsigned char *) CFG_FPGA_BASE;
+	unsigned char *fpga_base = (unsigned char *) CONFIG_SYS_FPGA_BASE;
 	unsigned char switch_status;
 	unsigned long cs0_base;
 	unsigned long cs0_size;
@@ -315,7 +315,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*--------------------------------------------------------------------------+
@@ -330,7 +330,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -339,12 +339,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 
 /*************************************************************************
diff --git a/board/amcc/ocotea/ocotea.h b/board/amcc/ocotea/ocotea.h
index 95ce1fd..400852a 100644
--- a/board/amcc/ocotea/ocotea.h
+++ b/board/amcc/ocotea/ocotea.h
@@ -22,7 +22,7 @@
  */
 
 /* Board specific FPGA stuff ... */
-#define FPGA_REG0                       (CFG_FPGA_BASE + 0x00)
+#define FPGA_REG0                       (CONFIG_SYS_FPGA_BASE + 0x00)
 #define   FPGA_REG0_SSCG_MASK             0x80
 #define   FPGA_REG0_SSCG_DISABLE          0x00
 #define   FPGA_REG0_SSCG_ENABLE           0x80
@@ -48,7 +48,7 @@
 #define   FPGA_REG0_ONBOARD_FLASH_ENABLE  0x00
 #define   FPGA_REG0_ONBOARD_FLASH_DISABLE 0x02
 #define   FPGA_REG0_FLASH                 0x01
-#define FPGA_REG1                       (CFG_FPGA_BASE + 0x01)
+#define FPGA_REG1                       (CONFIG_SYS_FPGA_BASE + 0x01)
 #define   FPGA_REG1_9772_FSELFBX_MASK     0x80
 #define   FPGA_REG1_9772_FSELFBX_6        0x00
 #define   FPGA_REG1_9772_FSELFBX_10       0x80
@@ -71,7 +71,7 @@
 #define   FPGA_REG1_SOURCE_SSDIV1         0x05
 #define   FPGA_REG1_SOURCE_SSDIV2         0x06
 #define   FPGA_REG1_SOURCE_SSDIV4         0x07
-#define FPGA_REG2                       (CFG_FPGA_BASE + 0x02)
+#define FPGA_REG2                       (CONFIG_SYS_FPGA_BASE + 0x02)
 #define   FPGA_REG2_TC0                   0x80
 #define   FPGA_REG2_TC1                   0x40
 #define   FPGA_REG2_TC2                   0x20
@@ -82,7 +82,7 @@
 #define   FPGA_REG2_EXT_INTFACE_DISABLE   0x04
 #define   FPGA_REG2_SMII_RESET_DISABLE    0x02   /*Use on Ocotea pass 3 boards*/
 #define   FPGA_REG2_DEFAULT_UART1_N       0x01
-#define FPGA_REG3                       (CFG_FPGA_BASE + 0x03)
+#define FPGA_REG3                       (CONFIG_SYS_FPGA_BASE + 0x03)
 #define   FPGA_REG3_GIGABIT_RESET_DISABLE 0x80   /*Use on Ocotea pass 1 boards*/
 #define   FPGA_REG3_ENET_MASK1            0x70   /*Use on Ocotea pass 1 boards*/
 #define   FPGA_REG3_ENET_MASK2            0xF0   /*Use on Ocotea pass 2 boards*/
@@ -108,7 +108,7 @@
 #define   FPGA_REG3_STAT_LED4_DISAB       0x00
 #define   FPGA_REG3_STAT_LED2_DISAB       0x00
 #define   FPGA_REG3_STAT_LED1_DISAB       0x00
-#define FPGA_REG4                       (CFG_FPGA_BASE + 0x04)
+#define FPGA_REG4                       (CONFIG_SYS_FPGA_BASE + 0x04)
 #define   FPGA_REG4_GPHY_MODE10           0x80
 #define   FPGA_REG4_GPHY_MODE100          0x40
 #define   FPGA_REG4_GPHY_MODE1000         0x20
diff --git a/board/amcc/redwood/config.mk b/board/amcc/redwood/config.mk
index f33336d..381f2b2 100644
--- a/board/amcc/redwood/config.mk
+++ b/board/amcc/redwood/config.mk
@@ -38,5 +38,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S
index fcffada..363d793 100644
--- a/board/amcc/redwood/init.S
+++ b/board/amcc/redwood/init.S
@@ -54,24 +54,24 @@
 	 */
 
 	/* Although 512 KB, map 256k at a time */
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-	tlbentry(CFG_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE + 0x40000, SZ_256K, 0x00040000, 4, AC_R|AC_W|AC_X|SA_I)
 
-	tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	/*
 	 * Peripheral base
 	 */
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_16K, 0xEF600000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE,SZ_16M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE,SZ_16M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE,SZ_16M, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_MEMBASE, SZ_256M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_MEMBASE, SZ_256M, 0x00000000, 0xE, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_REGBASE, SZ_64K, 0x30000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_REGBASE, SZ_64K, 0x30010000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_REGBASE, SZ_64K, 0x30020000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index 6b9043a..3402f84 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -46,7 +46,7 @@
 #define NAND_COMPATIBLE	0x01
 #define NOR_COMPATIBLE  0x02
 
-/* check with Stefan on CFG_I2C_EEPROM_ADDR */
+/* check with Stefan on CONFIG_SYS_I2C_EEPROM_ADDR */
 #define I2C_EEPROM_ADDR 0x52
 
 static char *config_labels[] = {
@@ -207,7 +207,7 @@
 	}
 
 	/* check CPLD register +5 for PCI 66MHz flag */
-	if ((in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN) == 0)
+	if ((in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN) == 0)
 		/*
 		 * PLB-to-PCI divisor = 3 for 33MHz sync PCI
 		 * instead of 2 for 66MHz systems
@@ -216,7 +216,7 @@
 
 	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
 		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
-	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 
 	printf("Done\n");
 	printf("Please power-cycle the board for the changes to take effect\n");
diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk
index 5e04ee4..6c748c9 100644
--- a/board/amcc/sequoia/config.mk
+++ b/board/amcc/sequoia/config.mk
@@ -41,5 +41,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/sequoia/init.S b/board/amcc/sequoia/init.S
index 46a37c6..bd346bf 100644
--- a/board/amcc/sequoia/init.S
+++ b/board/amcc/sequoia/init.S
@@ -45,36 +45,36 @@
 
 	/* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
 #else
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
 
 	/* TLB-entry for EBC */
-	tlbentry( CFG_BCSR_BASE, SZ_256M, CFG_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_BCSR_BASE, SZ_256M, CONFIG_SYS_BCSR_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* BOOT_CS (FLASH) must be forth. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
 #ifndef CONFIG_NAND_SPL
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
 #else
-	tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
 #endif
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for NAND */
-	tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
 	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
@@ -95,8 +95,8 @@
 	 * For NAND booting the first TLB has to be reconfigured to full size
 	 * and with caching disabled after running from RAM!
 	 */
-#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 #define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	.globl	reconfig_tlb0
diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c
index 77e6c7b..64eb063 100644
--- a/board/amcc/sequoia/sdram.c
+++ b/board/amcc/sequoia/sdram.c
@@ -113,5 +113,5 @@
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c
index e439fb9..d6668e2 100644
--- a/board/amcc/sequoia/sequoia.c
+++ b/board/amcc/sequoia/sequoia.c
@@ -33,7 +33,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size (ulong base, int banknum);
 
@@ -74,16 +74,16 @@
 	mtdcr(uic2sr, 0xffffffff);	/* clear all */
 
 	/* 50MHz tmrclk */
-	out_8((u8 *) CFG_BCSR_BASE + 0x04, 0x00);
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
 
 	/* clear write protects */
-	out_8((u8 *) CFG_BCSR_BASE + 0x07, 0x00);
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
 
 	/* enable Ethernet */
-	out_8((u8 *) CFG_BCSR_BASE + 0x08, 0x00);
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
 
 	/* enable USB device */
-	out_8((u8 *) CFG_BCSR_BASE + 0x09, 0x20);
+	out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
 
 	/* select Ethernet (and optionally IIC1) pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -113,7 +113,7 @@
 		SDR0_CUST0_NDFC_ENABLE		|
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
-		(0x80000000 >> (28 + CFG_NAND_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	return 0;
@@ -160,7 +160,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -320,8 +320,8 @@
 	printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 #endif
 
-	rev = in_8((void *)(CFG_BCSR_BASE + 0));
-	val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
+	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
@@ -407,7 +407,7 @@
  * inbound map (PIM). But the bootstrap config choices are limited and
  * may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*
@@ -423,16 +423,16 @@
 	 */
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
@@ -448,8 +448,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -463,9 +463,9 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -480,7 +480,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*
  * is_pci_host
diff --git a/board/amcc/sequoia/u-boot.lds b/board/amcc/sequoia/u-boot.lds
index b20fb1c..3cfec83 100644
--- a/board/amcc/sequoia/u-boot.lds
+++ b/board/amcc/sequoia/u-boot.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c
index ae92bb2..110cbe5 100644
--- a/board/amcc/taihu/flash.c
+++ b/board/amcc/taihu/flash.c
@@ -32,7 +32,7 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 #undef DEBUG
 #ifdef DEBUG
@@ -41,9 +41,9 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-#define CFG_FLASH_CHAR_SIZE unsigned char
-#define CFG_FLASH_CHAR_ADDR0 (0x0aaa)
-#define CFG_FLASH_CHAR_ADDR1 (0x0555)
+#define CONFIG_SYS_FLASH_CHAR_SIZE unsigned char
+#define CONFIG_SYS_FLASH_CHAR_ADDR0 (0x0aaa)
+#define CONFIG_SYS_FLASH_CHAR_ADDR1 (0x0555)
 /*-----------------------------------------------------------------------
  * Functions
  */
@@ -65,7 +65,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -84,8 +84,8 @@
 		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
 		/* Monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[0]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
@@ -299,32 +299,32 @@
 #endif
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
 	default:
@@ -338,67 +338,67 @@
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
 		info->flash_id += FLASH_AMD016;
 		info->sector_count = 32;
 		info->size = 0x00200000;
 		break;		/* => 2 MB              */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
 		info->size = 0x00400000;
 		break;		/* => 4 MB              */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;		/* => 0.5 MB            */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;		/* => 0.5 MB            */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;		/* => 1 MB              */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;		/* => 1 MB              */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;		/* => 2 MB              */
 
-	case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
@@ -445,14 +445,14 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@@ -462,7 +462,7 @@
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return info->size;
 }
@@ -470,14 +470,14 @@
 static int wait_for_DQ7_1(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-	       (CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -509,8 +509,8 @@
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -550,24 +550,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -589,8 +589,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -691,9 +691,9 @@
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
@@ -702,15 +702,15 @@
 		return 2;
 	}
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -720,10 +720,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return 1;
 			}
 		}
@@ -740,32 +740,32 @@
 static ulong flash_get_size_2(vu_long * addr, flash_info_t * info)
 {
 	short i;
-	CFG_FLASH_CHAR_SIZE value;
+	CONFIG_SYS_FLASH_CHAR_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-	addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-	addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+	addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 	udelay(1000);
 
-	value = (CFG_FLASH_CHAR_SIZE)addr2[0];
+	value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_CHAR_SIZE) AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_CHAR_SIZE) FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_CHAR_SIZE) SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_CHAR_SIZE) STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
 	default:
@@ -775,83 +775,83 @@
 		return 0;		/* no or unknown flash */
 	}
 
-	value = (CFG_FLASH_CHAR_SIZE)addr2[2];	/* device ID */
+	value = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[2];	/* device ID */
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV040B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F040B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_CHAR_SIZE) STM_ID_M29W040B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) STM_ID_M29W040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;	/* => 512 ko */
 		break;
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_F016D:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_F016D:
 		info->flash_id += FLASH_AMD016;
 		info->sector_count = 32;
 		info->size = 0x00200000;
 		break;			/* => 2 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV033C:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV033C:
 		info->flash_id += FLASH_AMDLV033C;
 		info->sector_count = 64;
 		info->size = 0x00400000;
 		break;			/* => 4 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;			/* => 0.5 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;			/* => 0.5 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;			/* => 1 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;			/* => 1 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;			/* => 2 MB */
 
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;			/* => 2 MB */
-	case (CFG_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
-		if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
-				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
+	case (CONFIG_SYS_FLASH_CHAR_SIZE) AMD_ID_MIRROR:
+		if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_2
+				&& (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_LV128U_3) {
 			info->flash_id += FLASH_AMLV128U;
 			info->sector_count = 256;
 			info->size = 0x01000000;
-		} else if ((CFG_FLASH_CHAR_SIZE)addr2[0x1c] == (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
-				&& (CFG_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CFG_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
+		} else if ((CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1c] == (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_2
+				&& (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[0x1e] ==  (CONFIG_SYS_FLASH_CHAR_SIZE)AMD_ID_GL128N_3 ) {
 			info->flash_id += FLASH_S29GL128N;
 			info->sector_count = 128;
 			info->size = 0x01000000;
@@ -904,38 +904,38 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 			info->protect[i] = 0;
 		else
-			info->protect[i] = (CFG_FLASH_CHAR_SIZE)addr2[4] & 1;
+			info->protect[i] = (CONFIG_SYS_FLASH_CHAR_SIZE)addr2[4] & 1;
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0;
 	return info->size;
 }
 
 static int wait_for_DQ7_2(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-	    (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+	    (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while (((CFG_FLASH_WORD_SIZE)addr[0] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
-	       (CFG_FLASH_WORD_SIZE) 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while (((CONFIG_SYS_FLASH_WORD_SIZE)addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+	       (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -950,8 +950,8 @@
 
 static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -991,24 +991,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x50505050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x50505050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80808080;
-				addr[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-				addr[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30303030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+				addr[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30303030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -1030,8 +1030,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF0F0F0F0; /* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -1039,9 +1039,9 @@
 
 static int write_word_2(flash_info_t * info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
@@ -1050,15 +1050,15 @@
 		return 2;
 	}
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-		addr2[CFG_FLASH_CHAR_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-		addr2[CFG_FLASH_CHAR_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA0A0A0A0;
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+		addr2[CONFIG_SYS_FLASH_CHAR_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA0A0A0A0;
 
 		dest2[i] = data2[i];
 
@@ -1068,10 +1068,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE) 0x80808080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80808080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return 1;
 			}
 		}
diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c
index ee0939a..6e9330f 100644
--- a/board/amcc/taihu/taihu.c
+++ b/board/amcc/taihu/taihu.c
@@ -48,8 +48,8 @@
 	mtdcr(uicsr, 0xFFFFFFFF);	/* clear all ints */
 	mtdcr(uicvcr, 0x00000001);	/* set vect base=0,INT0 highest priority */
 
-	mtebc(pb3ap, CFG_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
-	mtebc(pb3cr, CFG_EBC_PB3CR);
+	mtebc(pb3ap, CONFIG_SYS_EBC_PB3AP);	/* memory bank 3 (CPLD_LCM) initialization */
+	mtebc(pb3cr, CONFIG_SYS_EBC_PB3CR);
 
 	/*
 	 * Configure CPC0_PCI to enable PerWE as output
diff --git a/board/amcc/taihu/update.c b/board/amcc/taihu/update.c
index 55ad535..52bad56 100644
--- a/board/amcc/taihu/update.c
+++ b/board/amcc/taihu/update.c
@@ -101,7 +101,7 @@
 static int update_boot_eeprom(cmd_tbl_t* cmdtp, int flag, int argc, char *argv[])
 {
 	ulong len = 0x20;
-	uchar chip = CFG_I2C_EEPROM_ADDR;
+	uchar chip = CONFIG_SYS_I2C_EEPROM_ADDR;
 	uchar *pbuf;
 	uchar base;
 	int i;
diff --git a/board/amcc/taishan/config.mk b/board/amcc/taishan/config.mk
index 4eefff2..ee5eb1b 100644
--- a/board/amcc/taishan/config.mk
+++ b/board/amcc/taishan/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S
index 8db043b..748ec0a 100644
--- a/board/amcc/taishan/init.S
+++ b/board/amcc/taishan/init.S
@@ -89,9 +89,9 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/amcc/taishan/lcd.c b/board/amcc/taishan/lcd.c
index 8d2dce3..624ae40 100644
--- a/board/amcc/taishan/lcd.c
+++ b/board/amcc/taishan/lcd.c
@@ -31,9 +31,9 @@
 
 #define LCD_DELAY_NORMAL_US	100
 #define LCD_DELAY_NORMAL_MS	2
-#define LCD_CMD_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE))
-#define LCD_DATA_ADDR		((volatile char *)(CFG_EBC2_LCM_BASE+1))
-#define LCD_BLK_CTRL		((volatile char *)(CFG_EBC1_FPGA_BASE+0x2))
+#define LCD_CMD_ADDR		((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE))
+#define LCD_DATA_ADDR		((volatile char *)(CONFIG_SYS_EBC2_LCM_BASE+1))
+#define LCD_BLK_CTRL		((volatile char *)(CONFIG_SYS_EBC1_FPGA_BASE+0x2))
 
 #define mdelay(t)	({unsigned long msec=(t); while (msec--) { udelay(1000);}})
 
@@ -359,7 +359,7 @@
 static int do_led_test_off(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	volatile unsigned int *GpioOr =
-		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+		(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
 	*GpioOr |= 0x00300000;
 	return 0;
 }
@@ -367,7 +367,7 @@
 static int do_led_test_on(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	volatile unsigned int *GpioOr =
-		(volatile unsigned int *)(CFG_PERIPHERAL_BASE + 0x700);
+		(volatile unsigned int *)(CONFIG_SYS_PERIPHERAL_BASE + 0x700);
 	*GpioOr &= ~0x00300000;
 	return 0;
 }
diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c
index cd432cb..28bdab5 100644
--- a/board/amcc/taishan/taishan.c
+++ b/board/amcc/taishan/taishan.c
@@ -29,7 +29,7 @@
 #include <ppc4xx_enet.h>
 #include <netdev.h>
 
-#ifdef CFG_INIT_SHOW_RESET_REG
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
 void show_reset_reg(void);
 #endif
 
@@ -63,7 +63,7 @@
 	      EBC_BXAP_TH_ENCODE(3) | EBC_BXAP_RE_DISABLED |
 	      EBC_BXAP_BEM_WRITEONLY |
 	      EBC_BXAP_PEN_DISABLED);
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 	      EBC_BXCR_BS_64MB | EBC_BXCR_BU_RW|EBC_BXCR_BW_32BIT);
 
 	/*-------------------------------------------------------------------------+
@@ -173,9 +173,9 @@
 	mtsdr(sdr_pfc1,reg);
 
 	/* Set GPIO 10 and 11 as output */
-	GpioOdr	= (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x718);
-	GpioTcr = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x704);
-	GpioOr  = (volatile unsigned int*)(CFG_PERIPHERAL_BASE+0x700);
+	GpioOdr	= (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x718);
+	GpioTcr = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x704);
+	GpioOr  = (volatile unsigned int*)(CONFIG_SYS_PERIPHERAL_BASE+0x700);
 
 	*GpioOdr &= ~(0x00300000);
 	*GpioTcr |= 0x00300000;
@@ -202,7 +202,7 @@
 	}
 	putc ('\n');
 
-#ifdef CFG_INIT_SHOW_RESET_REG
+#ifdef CONFIG_SYS_INIT_SHOW_RESET_REG
 	show_reset_reg();
 #endif
 
@@ -248,7 +248,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*--------------------------------------------------------------------------+
@@ -263,7 +263,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -272,12 +272,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host
diff --git a/board/amcc/taishan/update.c b/board/amcc/taishan/update.c
index ed2c196..96b918b 100644
--- a/board/amcc/taishan/update.c
+++ b/board/amcc/taishan/update.c
@@ -51,7 +51,7 @@
 static int update_boot_eeprom(void)
 {
 	ulong len = 0x10;
-	uchar chip = CFG_BOOTSTRAP_IIC_ADDR;
+	uchar chip = CONFIG_SYS_BOOTSTRAP_IIC_ADDR;
 	uchar *pbuf = (uchar *)bootstrap_buf;
 	int ii, jj;
 
diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c
index fe6ca6c..d363564 100644
--- a/board/amcc/walnut/flash.c
+++ b/board/amcc/walnut/flash.c
@@ -58,7 +58,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -73,14 +73,14 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
 		flash_get_offsets(FLASH_BASE0_PRELIM, &flash_info[0]);
 
 		/* Monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[0]);
 #ifdef CONFIG_ENV_IS_IN_FLASH
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/yosemite/config.mk b/board/amcc/yosemite/config.mk
index 4ab0ea0..df5466e 100644
--- a/board/amcc/yosemite/config.mk
+++ b/board/amcc/yosemite/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/yosemite/init.S b/board/amcc/yosemite/init.S
index 425ad08..f938236 100644
--- a/board/amcc/yosemite/init.S
+++ b/board/amcc/yosemite/init.S
@@ -91,22 +91,22 @@
      * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
      * speed up boot process. It is patched after relocation to enable SA_I
      */
-    tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+    tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
 
     /* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-    tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+    tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_NVRAM_BASE_ADDR, SZ_256M, CFG_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_NVRAM_BASE_ADDR, SZ_256M, CONFIG_SYS_NVRAM_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_W|SA_I )
 
     /* PCI */
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
 
     /* USB 2.0 Device */
-    tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
 
     tlbtab_end
diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c
index 05be40a..3982896 100644
--- a/board/amcc/yosemite/yosemite.c
+++ b/board/amcc/yosemite/yosemite.c
@@ -31,7 +31,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 int board_early_init_f(void)
 {
@@ -107,18 +107,18 @@
 	mtsdr(sdr_pfc1, 0x00048000);	/* Pin function: UART0 has 4 pins */
 
 	/*clear tmrclk divisor */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x04) = 0x00;
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x04) = 0x00;
 
 	/*enable ethernet */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x08) = 0xf0;
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x08) = 0xf0;
 
 #ifdef CONFIG_440EP
 	/*enable usb 1.1 fs device and remove usb 2.0 reset */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x09) = 0x00;
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x09) = 0x00;
 #endif
 
 	/*get rid of flash write protect */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x07) = 0x00;
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x07) = 0x00;
 
 	return 0;
 }
@@ -167,7 +167,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -186,8 +186,8 @@
 	printf("Board: Yellowstone - AMCC PPC440GR Evaluation Board");
 #endif
 
-	rev = in_8((void *)(CFG_BCSR_BASE + 0));
-	val = in_8((void *)(CFG_BCSR_BASE + 5)) & CFG_BCSR5_PCI66EN;
+	rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
+	val = in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) & CONFIG_SYS_BCSR5_PCI66EN;
 	printf(", Rev. %X, PCI=%d MHz", rev, val ? 66 : 33);
 
 	if (s != NULL) {
@@ -329,7 +329,7 @@
 	sdram_tr1_set(0x08000000, &tr1_bank2);
 	mtsdram(mem_tr1, (((tr1_bank1+tr1_bank2)/2) | 0x80800800));
 
-	return CFG_SDRAM_BANKS * (CFG_KBYTES_SDRAM * 1024);	/* return bytes */
+	return CONFIG_SYS_SDRAM_BANKS * (CONFIG_SYS_KBYTES_SDRAM * 1024);	/* return bytes */
 }
 
 /*************************************************************************
@@ -395,7 +395,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -409,14 +409,14 @@
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
@@ -431,8 +431,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -446,13 +446,13 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -467,7 +467,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -508,5 +508,5 @@
 void board_reset(void)
 {
 	/* give reset to BCSR */
-	*(unsigned char *)(CFG_BCSR_BASE | 0x06) = 0x09;
+	*(unsigned char *)(CONFIG_SYS_BCSR_BASE | 0x06) = 0x09;
 }
diff --git a/board/amcc/yucca/config.mk b/board/amcc/yucca/config.mk
index ff454eb..3ce3cc1 100644
--- a/board/amcc/yucca/config.mk
+++ b/board/amcc/yucca/config.mk
@@ -38,5 +38,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c
index c405346..eda49eb 100644
--- a/board/amcc/yucca/flash.c
+++ b/board/amcc/yucca/flash.c
@@ -43,12 +43,12 @@
 #define DEBUGF(x...)
 #endif				/* DEBUG */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*
  * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0
  */
-static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xfff00000, 0xfff80000, 0xe7c00001}, /* 0:boot from small flash */
 	{0x00000000, 0x00000000, 0x00000000}, /* 1:boot from pci 66      */
 	{0x00000000, 0x00000000, 0x00000000}, /* 2:boot from nand flash  */
@@ -67,7 +67,7 @@
  * Functions
  */
 static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word_1(flash_info_t * info, ulong dest, ulong data);
 static int write_word_2(flash_info_t * info, ulong dest, ulong data);
 static int flash_erase_1(flash_info_t * info, int s_first, int s_last);
@@ -198,7 +198,7 @@
 /*
  * The following code cannot be run from FLASH!
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 {
 	/* bit 0 used for big flash marking */
@@ -214,32 +214,32 @@
 #endif
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 			info->flash_id = FLASH_MAN_AMD;
 			break;
-		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 			info->flash_id = FLASH_MAN_FUJ;
 			break;
-		case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
 			info->flash_id = FLASH_MAN_SST;
 			break;
-		case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
 			info->flash_id = FLASH_MAN_STM;
 			break;
 		default:
@@ -253,67 +253,67 @@
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV040B:
 			info->flash_id += FLASH_AM040;
 			info->sector_count = 8;
 			info->size = 0x0080000;	/* => 512 ko */
 			break;
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F040B:
 			info->flash_id += FLASH_AM040;
 			info->sector_count = 8;
 			info->size = 0x0080000;	/* => 512 ko */
 			break;
 
-		case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_ID_M29W040B:
 			info->flash_id += FLASH_AM040;
 			info->sector_count = 8;
 			info->size = 0x0080000;	/* => 512 ko */
 			break;
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_F016D:
 			info->flash_id += FLASH_AMD016;
 			info->sector_count = 32;
 			info->size = 0x00200000;
 			break;		/* => 2 MB              */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV033C:
 			info->flash_id += FLASH_AMDLV033C;
 			info->sector_count = 64;
 			info->size = 0x00400000;
 			break;		/* => 4 MB              */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400T:
 			info->flash_id += FLASH_AM400T;
 			info->sector_count = 11;
 			info->size = 0x00080000;
 			break;		/* => 0.5 MB            */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV400B:
 			info->flash_id += FLASH_AM400B;
 			info->sector_count = 11;
 			info->size = 0x00080000;
 			break;		/* => 0.5 MB            */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800T:
 			info->flash_id += FLASH_AM800T;
 			info->sector_count = 19;
 			info->size = 0x00100000;
 			break;		/* => 1 MB              */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV800B:
 			info->flash_id += FLASH_AM800B;
 			info->sector_count = 19;
 			info->size = 0x00100000;
 			break;		/* => 1 MB              */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160T:
 			info->flash_id += FLASH_AM160T;
 			info->sector_count = 35;
 			info->size = 0x00200000;
 			break;		/* => 2 MB              */
 
-		case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_ID_LV160B:
 			info->flash_id += FLASH_AM160B;
 			info->sector_count = 35;
 			info->size = 0x00200000;
@@ -357,14 +357,14 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@@ -374,7 +374,7 @@
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -382,14 +382,14 @@
 static int wait_for_DQ7_1(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-			(CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -402,7 +402,7 @@
 	return 0;
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
 	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@@ -420,8 +420,8 @@
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -457,24 +457,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -496,8 +496,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -577,7 +577,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 {
 	if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) ||
@@ -595,9 +595,9 @@
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i, flag;
 
@@ -605,13 +605,13 @@
 	if ((*((vu_long *)dest) & data) != data)
 		return (2);
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -621,10 +621,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 	}
@@ -632,10 +632,10 @@
 	return (0);
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 
-#undef  CFG_FLASH_WORD_SIZE
-#define CFG_FLASH_WORD_SIZE unsigned short
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
 
 /*
  * The following code cannot be run from FLASH!
@@ -644,37 +644,37 @@
 {
 	short i;
 	int n;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 			info->flash_id = FLASH_MAN_AMD;
 			break;
-		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 			info->flash_id = FLASH_MAN_FUJ;
 			break;
-		case (CFG_FLASH_WORD_SIZE) SST_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) SST_MANUFACT:
 			info->flash_id = FLASH_MAN_SST;
 			break;
-		case (CFG_FLASH_WORD_SIZE) STM_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) STM_MANUFACT:
 			info->flash_id = FLASH_MAN_STM;
 			break;
-		case (CFG_FLASH_WORD_SIZE) MX_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) MX_MANUFACT:
 			info->flash_id = FLASH_MAN_MX;
 			break;
 		default:
@@ -688,22 +688,22 @@
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 			info->flash_id += FLASH_AM320T;
 			info->sector_count = 71;
 			info->size = 0x00400000;
 			break;	/* => 4 MB	*/
-		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 			info->flash_id += FLASH_AM320B;
 			info->sector_count = 71;
 			info->size = 0x00400000;
 			break;	/* => 4 MB	*/
-		case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
 			info->flash_id += FLASH_STMW320DT;
 			info->sector_count = 67;
 			info->size = 0x00400000;
 			break;	/* => 4 MB	*/
-		case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)MX_ID_LV320T:
 			info->flash_id += FLASH_MXLV320T;
 			info->sector_count = 71;
 			info->size = 0x00400000;
@@ -782,14 +782,14 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		/* For AMD29033C flash we need to resend the command of *
 		 * reading flash protection for upper 8 Mb of flash     */
 		if (i == 32) {
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA;
-			addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555;
-			addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAAAAAAAA;
+			addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55555555;
+			addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90909090;
 		}
 
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
@@ -799,7 +799,7 @@
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -807,14 +807,14 @@
 static int wait_for_DQ7_2(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-			(CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -829,8 +829,8 @@
 
 static int flash_erase_2(flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	int i;
 
@@ -866,24 +866,24 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00500050;	/* block erase */
 				for (i = 0; i < 50; i++)
 					udelay(1000);	/* wait 1 ms */
 			} else {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 			}
 			l_sect = sect;
 			/*
@@ -905,8 +905,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -914,9 +914,9 @@
 
 static int write_word_2(flash_info_t * info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
@@ -924,15 +924,15 @@
 	if ((*((vu_long *)dest) & data) != data)
 		return (2);
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -942,17 +942,17 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 	}
 
 	return (0);
 }
-#endif /* CFG_FLASH_2ND_16BIT_DEV */
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -966,7 +966,7 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 	unsigned long val;
@@ -1011,7 +1011,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -1034,8 +1034,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[i]);
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S
index 67e8f8f..9308fda 100644
--- a/board/amcc/yucca/init.S
+++ b/board/amcc/yucca/init.S
@@ -59,23 +59,23 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-	tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
 
-	tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_BASE, SZ_16K, 0x20000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x40000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x80000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0xC0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x50000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x90000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0xD0000000, 0xC, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
 
 /**************************************************************************
@@ -102,20 +102,20 @@
 	 * routine.
 	 */
 
-	tlbentry(CFG_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
-	tlbentry(CFG_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
+	tlbentry(CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x00000000, 4, AC_R|AC_W|AC_X|SA_I)
+	tlbentry(CONFIG_SYS_FPGA_BASE, SZ_1K, 0xE2000000, 4,AC_R|AC_W|SA_I)
 
-	tlbentry(CFG_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry(CFG_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_OPER_FLASH, SZ_16M, 0xE7000000, 4,AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PERIPHERAL_BASE, SZ_4K, 0xF0000000, 4, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x10000000, 0xC, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE_MEMBASE, SZ_256M, 0xB0000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 
-	tlbentry(CFG_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_CFGBASE, SZ_16M, 0x00000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_CFGBASE, SZ_16M, 0x20000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_CFGBASE, SZ_16M, 0x40000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE0_XCFGBASE, SZ_1K, 0x10000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE1_XCFGBASE, SZ_1K, 0x30000000, 0xD, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCIE2_XCFGBASE, SZ_1K, 0x50000000, 0xD, AC_R|AC_W|SA_G|SA_I)
 	tlbtab_end
diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c
index e0c1268..c805568 100644
--- a/board/amcc/yucca/yucca.c
+++ b/board/amcc/yucca/yucca.c
@@ -626,7 +626,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*-------------------------------------------------------------------+
@@ -641,7 +641,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440
 	 * strapping options to not support sizes such as 128/256 MB.
 	 *-------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 	out32r( PCIX0_BAR0, 0 );
@@ -649,12 +649,12 @@
 	/*-------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *-------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif	/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 #if defined(CONFIG_PCI)
 /*************************************************************************
@@ -843,9 +843,9 @@
 
 		/* setup mem resource */
 		pci_set_region(hose->regions + 0,
-			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			CFG_PCIE_MEMBASE + i * CFG_PCIE_MEMSIZE,
-			CFG_PCIE_MEMSIZE,
+			CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			CONFIG_SYS_PCIE_MEMBASE + i * CONFIG_SYS_PCIE_MEMSIZE,
+			CONFIG_SYS_PCIE_MEMSIZE,
 			PCI_REGION_MEM);
 		hose->region_count = 1;
 		pci_register_hose(hose);
diff --git a/board/amirix/ap1000/flash.c b/board/amirix/ap1000/flash.c
index 1a3b252..1e742e5 100644
--- a/board/amirix/ap1000/flash.c
+++ b/board/amirix/ap1000/flash.c
@@ -110,7 +110,7 @@
 
 #define NUM_ERASE_REGIONS 4
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -130,7 +130,7 @@
 				cfiword_t cword);
 static int flash_full_status_check (flash_info_t * info, ulong sector,
 				    ulong tout, char *prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer (flash_info_t * info, ulong dest, uchar * cp,
 				  int len);
 #endif
@@ -270,7 +270,7 @@
 	flash_info[0].flash_id = FLASH_UNKNOWN;
 	flash_info[0].portwidth = FLASH_CFI_16BIT;
 	flash_info[0].chipwidth = FLASH_CFI_16BIT;
-	size += flash_info[0].size = flash_get_size (CFG_PROGFLASH_BASE, 0);
+	size += flash_info[0].size = flash_get_size (CONFIG_SYS_PROGFLASH_BASE, 0);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 1, flash_info[0].size, flash_info[0].size << 20);
 	};
@@ -278,7 +278,7 @@
 	flash_info[1].flash_id = FLASH_UNKNOWN;
 	flash_info[1].portwidth = FLASH_CFI_8BIT;
 	flash_info[1].chipwidth = FLASH_CFI_16BIT;
-	size += flash_info[1].size = flash_get_size (CFG_CONFFLASH_BASE, 1);
+	size += flash_info[1].size = flash_get_size (CONFIG_SYS_CONFFLASH_BASE, 1);
 	if (flash_info[1].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", 2, flash_info[1].size, flash_info[1].size << 20);
 	};
@@ -398,7 +398,7 @@
 			return rc;
 		wp = cp;
 	}
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while (cnt >= info->portwidth) {
 		i = info->buffer_size > cnt ? cnt : info->buffer_size;
 		if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK)
@@ -419,7 +419,7 @@
 		wp += info->portwidth;
 		cnt -= info->portwidth;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 	if (cnt == 0) {
 		return (0);
 	}
@@ -824,7 +824,7 @@
 	return flash_full_status_check (info, 0, info->write_tout, "write");
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* loop through the sectors from the highest address
  * when the passed address is greater or equal to the sector address
@@ -900,4 +900,4 @@
 	flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c
index a6436ac..a9b3fd8 100644
--- a/board/amirix/ap1000/pci.c
+++ b/board/amirix/ap1000/pci.c
@@ -267,10 +267,10 @@
 static struct pci_config_table ap1000_config_table[] = {
 #ifdef CONFIG_AP1000
 	{PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-	 PCI_BUS (CFG_ETH_DEV_FN), PCI_DEV (CFG_ETH_DEV_FN),
-	 PCI_FUNC (CFG_ETH_DEV_FN),
+	 PCI_BUS (CONFIG_SYS_ETH_DEV_FN), PCI_DEV (CONFIG_SYS_ETH_DEV_FN),
+	 PCI_FUNC (CONFIG_SYS_ETH_DEV_FN),
 	 pci_cfgfunc_config_device,
-	 {CFG_ETH_IOBASE, CFG_ETH_MEMBASE,
+	 {CONFIG_SYS_ETH_IOBASE, CONFIG_SYS_ETH_MEMBASE,
 	  PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}},
 #endif
 	{}
diff --git a/board/amirix/ap1000/serial.c b/board/amirix/ap1000/serial.c
index 508e880..87003be 100644
--- a/board/amirix/ap1000/serial.c
+++ b/board/amirix/ap1000/serial.c
@@ -30,15 +30,15 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 const NS16550_t COM_PORTS[] =
-	{ (NS16550_t) CFG_NS16550_COM1, (NS16550_t) CFG_NS16550_COM2 };
+	{ (NS16550_t) CONFIG_SYS_NS16550_COM1, (NS16550_t) CONFIG_SYS_NS16550_COM2 };
 
-#undef CFG_DUART_CHAN
-#define CFG_DUART_CHAN gComPort
+#undef CONFIG_SYS_DUART_CHAN
+#define CONFIG_SYS_DUART_CHAN gComPort
 static int gComPort = 0;
 
 int serial_init (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
 	(void) NS16550_init (COM_PORTS[0], clock_divisor);
 	gComPort = 0;
@@ -49,30 +49,30 @@
 void serial_putc (const char c)
 {
 	if (c == '\n') {
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 	}
 
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int serial_getc (void)
 {
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int serial_tstc (void)
 {
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void serial_setbrg (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }
diff --git a/board/ap325rxa/ap325rxa.c b/board/ap325rxa/ap325rxa.c
index cfa0261..9f1112a 100644
--- a/board/ap325rxa/ap325rxa.c
+++ b/board/ap325rxa/ap325rxa.c
@@ -144,9 +144,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/apollon/apollon.c b/board/apollon/apollon.c
index 8efa703..8964eba 100644
--- a/board/apollon/apollon.c
+++ b/board/apollon/apollon.c
@@ -245,7 +245,7 @@
 	__raw_writel(v, CM_CLKSEL2_CORE);
 	__raw_writel(0x1, CM_CLKSEL_WKUP);
 
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
 	/* Enable UART1 clock */
 	func_clks |= BIT21;
 	if_clks |= BIT21;
diff --git a/board/apollon/lowlevel_init.S b/board/apollon/lowlevel_init.S
index 8381fea..64550f6 100644
--- a/board/apollon/lowlevel_init.S
+++ b/board/apollon/lowlevel_init.S
@@ -51,7 +51,7 @@
 .globl lowlevel_init
 lowlevel_init:
 
-#ifdef CFG_NOR_BOOT
+#ifdef CONFIG_SYS_NOR_BOOT
 	/* Check running in SDRAM */
 	mov	r0, pc, lsr #28
 	cmp	r0, #8
diff --git a/board/apollon/mem.c b/board/apollon/mem.c
index 0211c6a..36bf6e9 100644
--- a/board/apollon/mem.c
+++ b/board/apollon/mem.c
@@ -146,7 +146,7 @@
 	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
 	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
 	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);	/* timeout disable */
-#ifdef CFG_NAND_BOOT
+#ifdef CONFIG_SYS_NAND_BOOT
 	/* set nWP, disable limited addr */
 	__raw_writel(0x001, GPMC_CONFIG);
 #else
@@ -164,7 +164,7 @@
 	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
 	sdelay(1000);
 
-#ifdef CFG_NOR_BOOT
+#ifdef CONFIG_SYS_NOR_BOOT
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG1_3, GPMC_CONFIG1_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG2_3, GPMC_CONFIG2_0);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG3_3, GPMC_CONFIG3_0);
@@ -208,13 +208,13 @@
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG4_0, GPMC_CONFIG4_2);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG5_0, GPMC_CONFIG5_2);
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG6_0, GPMC_CONFIG6_2);
-#ifdef CFG_NOR_BOOT
+#ifdef CONFIG_SYS_NOR_BOOT
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_0, GPMC_CONFIG7_2);
 #else
 	__raw_writel(APOLLON_24XX_GPMC_CONFIG7_2, GPMC_CONFIG7_2);
 #endif
 
-#ifndef CFG_NOR_BOOT
+#ifndef CONFIG_SYS_NOR_BOOT
 	/* setup cs3 */
 	__raw_writel(0, GPMC_CONFIG7_3);	/* disable any mapping */
 	sdelay(1000);
diff --git a/board/apollon/mem.h b/board/apollon/mem.h
index d4636f4..09c4ea4 100644
--- a/board/apollon/mem.h
+++ b/board/apollon/mem.h
@@ -142,7 +142,7 @@
 #endif /* endif PRCM_CONFIG_II */
 
 #ifdef PRCM_CONFIG_III		/* L3 at 133MHz */
-# ifdef CFG_NAND_BOOT
+# ifdef CONFIG_SYS_NAND_BOOT
 #  define APOLLON_24XX_GPMC_CONFIG1_0   0x0
 #  define APOLLON_24XX_GPMC_CONFIG2_0   0x00141400
 #  define APOLLON_24XX_GPMC_CONFIG3_0   0x00141400
@@ -156,7 +156,7 @@
 #  define APOLLON_24XX_GPMC_CONFIG4_0   0x10081008
 #  define APOLLON_24XX_GPMC_CONFIG5_0   0x01131F1F
 #  define APOLLON_24XX_GPMC_CONFIG6_0   0x000004c4
-# endif	/* endif CFG_NAND_BOOT */
+# endif	/* endif CONFIG_SYS_NAND_BOOT */
 # define APOLLON_24XX_GPMC_CONFIG7_0	(0x00000C40|(APOLLON_CS0_BASE >> 24))
 # define APOLLON_24XX_GPMC_CONFIG1_1	0x00011000
 # define APOLLON_24XX_GPMC_CONFIG2_1	0x001f1f01
@@ -165,6 +165,6 @@
 # define APOLLON_24XX_GPMC_CONFIG5_1	0x041f1F1F
 # define APOLLON_24XX_GPMC_CONFIG6_1	0x000004C4
 # define APOLLON_24XX_GPMC_CONFIG7_1	(0x00000F40|(APOLLON_CS1_BASE >> 24))
-#endif /* endif CFG_PRCM_III */
+#endif /* endif CONFIG_SYS_PRCM_III */
 
 #endif /* endif _APOLLON_OMAP24XX_MEM_H_ */
diff --git a/board/armadillo/flash.c b/board/armadillo/flash.c
index 6ed88f4..cdbbfd0 100644
--- a/board/armadillo/flash.c
+++ b/board/armadillo/flash.c
@@ -37,7 +37,7 @@
 #define FL_WORD(addr) (*(volatile unsigned short*)(addr))
 #define FLASH_TIMEOUT 20000000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -47,14 +47,14 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id = (FUJ_MANUFACT & FLASH_VENDMASK);
 		/*(INTEL_ID_28F128J3 & FLASH_TYPEMASK); */
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -69,8 +69,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
diff --git a/board/atc/atc.c b/board/atc/atc.c
index b627c1c..936c031 100644
--- a/board/atc/atc.c
+++ b/board/atc/atc.c
@@ -281,7 +281,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -306,7 +306,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -317,7 +317,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -331,7 +331,7 @@
 
 int misc_init_r(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, (uint *)rtc_table, sizeof(rtc_table) / sizeof(uint));
@@ -342,37 +342,37 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9;
 #endif
 	long psize;
 
 	psize = 8 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL) ");
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	}
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -382,7 +382,7 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/atc/config.mk b/board/atc/config.mk
index eee7a60..dd854e7 100644
--- a/board/atc/config.mk
+++ b/board/atc/config.mk
@@ -25,7 +25,7 @@
 # ATC boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_atc.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_atc.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/atc/flash.c b/board/atc/flash.c
index 7835e8f..fd76723 100644
--- a/board/atc/flash.c
+++ b/board/atc/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -67,11 +67,11 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 #if 0
 		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
 #else
-		ulong flashbase = CFG_FLASH_BASE;
+		ulong flashbase = CONFIG_SYS_FLASH_BASE;
 #endif
 
 		memset(&flash_info[i], 0, sizeof(flash_info_t));
@@ -87,12 +87,12 @@
 		size += flash_info[i].size;
 	}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -164,13 +164,13 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->start[0] <= base && base < info->start[0] + info->size)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -476,7 +476,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -490,14 +490,14 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
 		}
 
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
 			putc ('.');
 			last = get_timer(0);
 		}
@@ -601,7 +601,7 @@
 
 	/* data polling for D7 */
 	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW)0x00F000F0;	/* reset bank */
 			res = 1;
 		}
@@ -647,7 +647,7 @@
 	start = get_timer (0);
 
 	while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW)0x00B000B0;	/* Suspend program	*/
 			res = 1;
 		}
diff --git a/board/atc/ti113x.c b/board/atc/ti113x.c
index e112eca..473bb10 100644
--- a/board/atc/ti113x.c
+++ b/board/atc/ti113x.c
@@ -526,8 +526,8 @@
 	mem.map = 0;
 	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
 	mem.speed = 300;
-	mem.sys_start = CFG_PCMCIA_MEM_ADDR;
-	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
 	mem.card_start = 0;
 	i365_set_mem_map (&socket, &mem);
 
@@ -613,8 +613,8 @@
 {
 	u_int tmp[2];
 	u_int *mem = (void *) socket.cb_phys;
-	u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
-	u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+	u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+	u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
 
 	pci_read_config_dword (dev, 0x00, tmp + 0);
 	pci_read_config_dword (dev, 0x80, tmp + 1);
diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c
index 787d64d..544c932 100644
--- a/board/atmel/at91cap9adk/at91cap9adk.c
+++ b/board/atmel/at91cap9adk/at91cap9adk.c
@@ -147,9 +147,9 @@
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
 		       AT91_SMC_TDF_(1));
diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c
index 1dec558..cc2263b 100644
--- a/board/atmel/at91cap9adk/nand.c
+++ b/board/atmel/at91cap9adk/nand.c
@@ -62,7 +62,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91cap9adk_nand_hwcontrol;
diff --git a/board/atmel/at91cap9adk/partition.c b/board/atmel/at91cap9adk/partition.c
index eb1a724..7e1d46f 100644
--- a/board/atmel/at91cap9adk/partition.c
+++ b/board/atmel/at91cap9adk/partition.c
@@ -23,10 +23,10 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/at91rm9200dk/flash.c b/board/atmel/at91rm9200dk/flash.c
index ef8d9a8..902c3c4 100644
--- a/board/atmel/at91rm9200dk/flash.c
+++ b/board/atmel/at91rm9200dk/flash.c
@@ -59,7 +59,7 @@
 	{ 127, 64*1024 },	/* 127 * 64 kBytes sectors */
 };
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /* AT49BV1614A Codes */
 #define FLASH_CODE1		0xAA
@@ -77,8 +77,8 @@
 #define CMD_UNLOCK_BYPASS	0x0020
 #define CMD_SECTOR_UNLOCK	0x0070
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00005555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00002AAA<<1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00005555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00002AAA<<1)))
 
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
@@ -99,9 +99,9 @@
 	MEM_FLASH_ADDR2 = FLASH_CODE2;
 	MEM_FLASH_ADDR1 = ID_IN_CODE;
 
-	manuf_code = *(volatile u16 *) CFG_FLASH_BASE;
-	device_code = *(volatile u16 *) (CFG_FLASH_BASE + 2);
-	add_device_code = *(volatile u16 *) (CFG_FLASH_BASE + (3 << 1));
+	manuf_code = *(volatile u16 *) CONFIG_SYS_FLASH_BASE;
+	device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + 2);
+	add_device_code = *(volatile u16 *) (CONFIG_SYS_FLASH_BASE + (3 << 1));
 
 	MEM_FLASH_ADDR1 = FLASH_CODE1;
 	MEM_FLASH_ADDR2 = FLASH_CODE2;
@@ -157,7 +157,7 @@
 
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_identification (&flash_info[i]);
@@ -216,8 +216,8 @@
 
 	/* Protect binary boot image */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + CFG_BOOT_SIZE - 1, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + CONFIG_SYS_BOOT_SIZE - 1, &flash_info[0]);
 
 	/* Protect environment variables */
 	flash_protect (FLAG_PROTECT_SET,
@@ -226,8 +226,8 @@
 
 	/* Protect U-Boot gzipped image */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_U_BOOT_BASE,
-		       CFG_U_BOOT_BASE + CFG_U_BOOT_SIZE - 1, &flash_info[0]);
+		       CONFIG_SYS_U_BOOT_BASE,
+		       CONFIG_SYS_U_BOOT_BASE + CONFIG_SYS_U_BOOT_SIZE - 1, &flash_info[0]);
 
 	return size;
 }
@@ -345,7 +345,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip1 = TMO;
 					break;
@@ -433,7 +433,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip1 = ERR | TMO;
 			break;
 		}
diff --git a/board/atmel/at91rm9200dk/partition.c b/board/atmel/at91rm9200dk/partition.c
index 975be17..c739b11 100644
--- a/board/atmel/at91rm9200dk/partition.c
+++ b/board/atmel/at91rm9200dk/partition.c
@@ -23,11 +23,11 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
-	{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c
index 913e3fb..372cfb2 100644
--- a/board/atmel/at91sam9260ek/at91sam9260ek.c
+++ b/board/atmel/at91sam9260ek/at91sam9260ek.c
@@ -92,9 +92,9 @@
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
 		       AT91_SMC_TDF_(2));
diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c
index 665e35c..c5ac634 100644
--- a/board/atmel/at91sam9260ek/nand.c
+++ b/board/atmel/at91sam9260ek/nand.c
@@ -67,7 +67,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol;
diff --git a/board/atmel/at91sam9260ek/partition.c b/board/atmel/at91sam9260ek/partition.c
index 557d695..2629c67 100644
--- a/board/atmel/at91sam9260ek/partition.c
+++ b/board/atmel/at91sam9260ek/partition.c
@@ -23,11 +23,11 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
-	{CFG_DATAFLASH_LOGIC_ADDR_CS1, 1}
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS1, 1}
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/at91sam9261ek/at91sam9261ek.c b/board/atmel/at91sam9261ek/at91sam9261ek.c
index 647aab5..76f56d6 100644
--- a/board/atmel/at91sam9261ek/at91sam9261ek.c
+++ b/board/atmel/at91sam9261ek/at91sam9261ek.c
@@ -92,9 +92,9 @@
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
 		       AT91_SMC_TDF_(2));
diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c
index fccb9d7..06395ee 100644
--- a/board/atmel/at91sam9261ek/nand.c
+++ b/board/atmel/at91sam9261ek/nand.c
@@ -67,7 +67,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol;
diff --git a/board/atmel/at91sam9261ek/partition.c b/board/atmel/at91sam9261ek/partition.c
index 975be17..c739b11 100644
--- a/board/atmel/at91sam9261ek/partition.c
+++ b/board/atmel/at91sam9261ek/partition.c
@@ -23,11 +23,11 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
-	{CFG_DATAFLASH_LOGIC_ADDR_CS3, 3}
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS3, 3}
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c
index c705074..dd513b9 100644
--- a/board/atmel/at91sam9263ek/at91sam9263ek.c
+++ b/board/atmel/at91sam9263ek/at91sam9263ek.c
@@ -95,9 +95,9 @@
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
 		       AT91_SMC_TDF_(2));
diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c
index 250ec7f..3c247f6 100644
--- a/board/atmel/at91sam9263ek/nand.c
+++ b/board/atmel/at91sam9263ek/nand.c
@@ -67,7 +67,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol;
diff --git a/board/atmel/at91sam9263ek/partition.c b/board/atmel/at91sam9263ek/partition.c
index eb1a724..7e1d46f 100644
--- a/board/atmel/at91sam9263ek/partition.c
+++ b/board/atmel/at91sam9263ek/partition.c
@@ -23,10 +23,10 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/at91sam9rlek/at91sam9rlek.c b/board/atmel/at91sam9rlek/at91sam9rlek.c
index 509e7c3..7bf1f43 100644
--- a/board/atmel/at91sam9rlek/at91sam9rlek.c
+++ b/board/atmel/at91sam9rlek/at91sam9rlek.c
@@ -92,9 +92,9 @@
 	at91_sys_write(AT91_SMC_MODE(3),
 		       AT91_SMC_READMODE | AT91_SMC_WRITEMODE |
 		       AT91_SMC_EXNWMODE_DISABLE |
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 		       AT91_SMC_DBW_16 |
-#else /* CFG_NAND_DBW_8 */
+#else /* CONFIG_SYS_NAND_DBW_8 */
 		       AT91_SMC_DBW_8 |
 #endif
 		       AT91_SMC_TDF_(2));
diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c
index eb342b8..625f6ec 100644
--- a/board/atmel/at91sam9rlek/nand.c
+++ b/board/atmel/at91sam9rlek/nand.c
@@ -67,7 +67,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
-#ifdef CFG_NAND_DBW_16
+#ifdef CONFIG_SYS_NAND_DBW_16
 	nand->options = NAND_BUSWIDTH_16;
 #endif
 	nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol;
diff --git a/board/atmel/at91sam9rlek/partition.c b/board/atmel/at91sam9rlek/partition.c
index eb1a724..7e1d46f 100644
--- a/board/atmel/at91sam9rlek/partition.c
+++ b/board/atmel/at91sam9rlek/partition.c
@@ -23,10 +23,10 @@
 #include <asm/hardware.h>
 #include <dataflash.h>
 
-AT91S_DATAFLASH_INFO dataflash_info[CFG_MAX_DATAFLASH_BANKS];
+AT91S_DATAFLASH_INFO dataflash_info[CONFIG_SYS_MAX_DATAFLASH_BANKS];
 
-struct dataflash_addr cs[CFG_MAX_DATAFLASH_BANKS] = {
-	{CFG_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
+struct dataflash_addr cs[CONFIG_SYS_MAX_DATAFLASH_BANKS] = {
+	{CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0, 0},	/* Logical adress, CS */
 };
 
 /*define the area offsets*/
diff --git a/board/atmel/atstk1000/flash.c b/board/atmel/atstk1000/flash.c
index e2bfd4a..4d380f3 100644
--- a/board/atmel/atstk1000/flash.c
+++ b/board/atmel/atstk1000/flash.c
@@ -55,17 +55,17 @@
 	unsigned long addr;
 	unsigned int i;
 
-	flash_info[0].size = CFG_FLASH_SIZE;
+	flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
 	flash_info[0].sector_count = 135;
 
-	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+	flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
 
 	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
 		flash_info[0].start[i] = addr;
 	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
 		flash_info[0].start[i] = addr;
 
-	return CFG_FLASH_SIZE;
+	return CONFIG_SYS_FLASH_SIZE;
 }
 
 void flash_print_info(flash_info_t *info)
diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c
index 337cf31..2ef19ce 100644
--- a/board/atum8548/atum8548.c
+++ b/board/atum8548/atum8548.c
@@ -50,9 +50,9 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
@@ -73,15 +73,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -90,13 +90,13 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
@@ -127,17 +127,17 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("Testing DRAM from 0x%08x to 0x%08x\n",
-	       CFG_MEMTEST_START,
-	       CFG_MEMTEST_END);
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
 
 	printf("DRAM test phase 1:\n");
 	for (p = pstart; p < pend; p++) {
@@ -185,7 +185,7 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
@@ -210,7 +210,7 @@
 
 #ifdef CONFIG_PCIE1
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
@@ -228,32 +228,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE1_MEM_BASE,
-			       CFG_PCIE1_MEM_PHYS,
-			       CFG_PCIE1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE1_IO_BASE,
-			       CFG_PCIE1_IO_PHYS,
-			       CFG_PCIE1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE1_MEM_BASE2,
-			       CFG_PCIE1_MEM_PHYS2,
-			       CFG_PCIE1_MEM_SIZE2,
+			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_PHYS2,
+			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -278,7 +278,7 @@
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -301,23 +301,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
 		hose->first_busno=first_free_busno;
@@ -337,27 +337,27 @@
 
 #ifdef CONFIG_PCI2
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci2_hose;
 
 	if (!(devdisr & MPC85xx_DEVDISR_PCI2)) {
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI2_MEM_BASE,
-			       CFG_PCI2_MEM_PHYS,
-			       CFG_PCI2_MEM_SIZE,
+			       CONFIG_SYS_PCI2_MEM_BASE,
+			       CONFIG_SYS_PCI2_MEM_PHYS,
+			       CONFIG_SYS_PCI2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI2_IO_BASE,
-			       CFG_PCI2_IO_PHYS,
-			       CFG_PCI2_IO_SIZE,
+			       CONFIG_SYS_PCI2_IO_BASE,
+			       CONFIG_SYS_PCI2_IO_PHYS,
+			       CONFIG_SYS_PCI2_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
 		hose->first_busno=first_free_busno;
diff --git a/board/atum8548/law.c b/board/atum8548/law.c
index b66fd7b..b70b091 100644
--- a/board/atum8548/law.c
+++ b/board/atum8548/law.c
@@ -48,14 +48,14 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAWAR_SIZE_1M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CFG_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_CACHE_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c
index 1ef4de4..ef7942c 100644
--- a/board/atum8548/tlb.c
+++ b/board/atum8548/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -47,11 +47,11 @@
 	 * 0xf8000000	128M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000, CONFIG_SYS_FLASH_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_64M, 1),
 
@@ -59,7 +59,7 @@
 	 * TLB 2:	1G	Non-cacheable, guarded
 	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_1G, 1),
 
@@ -67,11 +67,11 @@
 	 * TLB 3, 4:	512M	Non-cacheable, guarded
 	 * 0xc0000000	1G	PCI2
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -82,7 +82,7 @@
 	 * 0xe210_0000	1M	PCI2 IO
 	 * 0xe300_0000	1M	PCIe IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 };
diff --git a/board/barco/barco.c b/board/barco/barco.c
index f8b2084..ed35572 100644
--- a/board/barco/barco.c
+++ b/board/barco/barco.c
@@ -90,7 +90,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size (CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size (CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg (MEAR1);
@@ -188,14 +188,14 @@
 unsigned scan_flash (void)
 {
 	char section[] =  "kernel";
-	int cfgFileLen  =  (CFG_FLASH_ERASE_SECTOR_LENGTH >> 1);
+	int cfgFileLen  =  (CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH >> 1);
 	int sectionPtr  = 0;
 	int foundItem   = 0; /* 0: None, 1: section found, 2: "=" found */
 	int bufPtr;
 	unsigned char *buf;
 
-	buf = (unsigned char*)(CFG_FLASH_RANGE_BASE + CFG_FLASH_RANGE_SIZE \
-			- CFG_FLASH_ERASE_SECTOR_LENGTH);
+	buf = (unsigned char*)(CONFIG_SYS_FLASH_RANGE_BASE + CONFIG_SYS_FLASH_RANGE_SIZE \
+			- CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH);
 	for (bufPtr = 0; bufPtr < cfgFileLen; ++bufPtr) {
 		if ((buf[bufPtr]==0xFF) && (*(int*)(buf+bufPtr)==0xFFFFFFFF)) {
 			return BOOT_DEFAULT;
@@ -236,14 +236,14 @@
 
 	switch (bootimage) {
 	case TRY_WORKING:
-		info->address = CFG_WORKING_KERNEL_ADDRESS;
+		info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
 		break;
 	case BOOT_WORKING :
-		info->address = CFG_WORKING_KERNEL_ADDRESS;
+		info->address = CONFIG_SYS_WORKING_KERNEL_ADDRESS;
 		break;
 	case BOOT_DEFAULT:
 	default:
-		info->address= CFG_DEFAULT_KERNEL_ADDRESS;
+		info->address= CONFIG_SYS_DEFAULT_KERNEL_ADDRESS;
 
 	}
 	info->size = *((unsigned int *)(info->address ));
diff --git a/board/barco/barco_svc.h b/board/barco/barco_svc.h
index bd924f2..e103260 100644
--- a/board/barco/barco_svc.h
+++ b/board/barco/barco_svc.h
@@ -38,16 +38,16 @@
 #include <asm/io.h>
 
 /* Defines for the barcohydra board */
-#ifndef CFG_FLASH_ERASE_SECTOR_LENGTH
-#define CFG_FLASH_ERASE_SECTOR_LENGTH (0x10000)
+#ifndef CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH
+#define CONFIG_SYS_FLASH_ERASE_SECTOR_LENGTH (0x10000)
 #endif
 
-#ifndef CFG_DEFAULT_KERNEL_ADDRESS
-#define CFG_DEFAULT_KERNEL_ADDRESS (CFG_FLASH_BASE + 0x30000)
+#ifndef CONFIG_SYS_DEFAULT_KERNEL_ADDRESS
+#define CONFIG_SYS_DEFAULT_KERNEL_ADDRESS (CONFIG_SYS_FLASH_BASE + 0x30000)
 #endif
 
-#ifndef CFG_WORKING_KERNEL_ADDRESS
-#define CFG_WORKING_KERNEL_ADDRESS (0xFFE00000)
+#ifndef CONFIG_SYS_WORKING_KERNEL_ADDRESS
+#define CONFIG_SYS_WORKING_KERNEL_ADDRESS (0xFFE00000)
 #endif
 
 
diff --git a/board/barco/early_init.S b/board/barco/early_init.S
index 07dafb7..531dcdf 100644
--- a/board/barco/early_init.S
+++ b/board/barco/early_init.S
@@ -32,68 +32,68 @@
 
 #if defined(USE_DINK32)
   /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
-  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
 #else
-  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
 #endif
 
 	.text
 
 	/* Values to program into memory controller registers */
 tbl:	.long	MCCR1, MCCR1VAL
-	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
 	.long	MCCR3
-	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
-		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
-		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
 	.long	MCCR4
-	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
-		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
-		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
-		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
-		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
-		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
-		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
 	.long	MSAR1
-	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR1
-	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MSAR2
-	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR2
-	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR1
-	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR1
-	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR2
-	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR2
-	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	0
 
 
@@ -123,7 +123,7 @@
 	/* set bank enable bits */
 	lis	r0, MBER@h
 	ori	r0, 0, MBER@l
-	li	r1, CFG_BANK_ENABLE
+	li	r1, CONFIG_SYS_BANK_ENABLE
 	stwbrx	r0, 0, r3
 	eieio
 	stb	r1, 0(r4)
@@ -145,8 +145,8 @@
 	eieio
 
 	/* set up stack pointer */
-	lis	r1, CFG_INIT_SP_OFFSET@h
-	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
 	mtlr	r10
 	blr
diff --git a/board/barco/flash.c b/board/barco/flash.c
index 53fc58c..c9efb15 100644
--- a/board/barco/flash.c
+++ b/board/barco/flash.c
@@ -56,11 +56,11 @@
 #define ROM_CS0_START	0xFF800000
 #define ROM_CS1_START	0xFF000000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
@@ -140,10 +140,10 @@
 {
 	unsigned long i;
 	unsigned char j;
-	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++){
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++){
 		flash_info_t * const pflinfo = &flash_info[i];
 		pflinfo->flash_id = FLASH_UNKNOWN;
 		pflinfo->size = 0;
@@ -217,10 +217,10 @@
 				break;
 		}
 		/* Protect monitor and environment sectors */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		flash_protect(FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 				&flash_info[0]);
 #endif
 
@@ -458,7 +458,7 @@
 	addr = (FLASH_WORD_SIZE *)(info->start[0] + (
 				(info->start[l_sect] - info->start[0]) << sh8b));
 	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -599,7 +599,7 @@
 		start = get_timer (0);
 		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
 				(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/bc3450/bc3450.c b/board/bc3450/bc3450.c
index 7ddf74c..6fb0096 100644
--- a/board/bc3450/bc3450.c
+++ b/board/bc3450/bc3450.c
@@ -53,7 +53,7 @@
 void ps2mult_early_init(void);
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -100,7 +100,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
@@ -109,7 +109,7 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -130,9 +130,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -158,9 +158,9 @@
 
 	/* find RAM size using SDRAM CS1 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize2 = test1;
@@ -181,7 +181,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -199,7 +199,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -209,7 +209,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup and enable SDRAM chip selects */
@@ -228,9 +228,9 @@
 
 	/* find RAM size */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -241,12 +241,12 @@
 	/* set SDRAM end address according to size */
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* Retrieve amount of SDRAM available */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -405,34 +405,34 @@
 	 */
 
 	/* save original SRAM content  */
-	save = *(volatile u16 *)CFG_CS2_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
 	restore = 1;
 
 	/* write test pattern to SRAM */
-	*(volatile u16 *)CFG_CS2_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in SRAM detection\n");
 
-	if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
 		/* no SRAM at all, disable cs */
 		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 		restore = 0;
 		__asm__ volatile ("sync");
-	} else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
 		/* make sure that we access a mirrored address */
-		*(volatile u16 *)CFG_CS2_START = 0x1111;
+		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
 		__asm__ volatile ("sync");
-		if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
 			/* SRAM size = 512 kByte */
-			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
 								0x80000);
 			__asm__ volatile ("sync");
 			puts ("SRAM:  512 kB\n");
@@ -444,7 +444,7 @@
 	}
 	/* restore origianl SRAM content  */
 	if (restore) {
-		*(volatile u16 *)CFG_CS2_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
 		__asm__ volatile ("sync");
 	}
 
@@ -453,21 +453,21 @@
 	 */
 
 	/* save origianl FB content  */
-	save = *(volatile u16 *)CFG_CS1_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 	restore = 1;
 
 	/* write test pattern to FB memory */
-	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in grafic controller detection\n");
 
-	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 		/* no grafic controller at all, disable cs */
 		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
@@ -479,7 +479,7 @@
 	}
 	/* restore origianl FB content	*/
 	if (restore) {
-		*(volatile u16 *)CFG_CS1_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
 		__asm__ volatile ("sync");
 	}
 
@@ -607,21 +607,21 @@
 	 */
 
 	/* save origianl FB content  */
-	save = *(volatile u16 *)CFG_CS1_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 	restore = 1;
 
 	/* write test pattern to FB memory */
-	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in grafic controller detection\n");
 
-	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 		/* no grafic controller found */
 		restore = 0;
 		ret = 0;
@@ -630,7 +630,7 @@
 	}
 
 	if (restore) {
-		*(volatile u16 *)CFG_CS1_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
 		__asm__ volatile ("sync");
 	}
 	return ret;
diff --git a/board/bc3450/cmd_bc3450.c b/board/bc3450/cmd_bc3450.c
index 48bc65d..ae5061f 100644
--- a/board/bc3450/cmd_bc3450.c
+++ b/board/bc3450/cmd_bc3450.c
@@ -52,9 +52,9 @@
 #define THERM_WRITE_TL		0x02
 #define THERM_WRITE_TH		0x01
 
-#define CFG_CPU			2
-#define CFG_1SHOT		1
-#define CFG_STANDALONE		0
+#define CONFIG_SYS_CPU			2
+#define CONFIG_SYS_1SHOT		1
+#define CONFIG_SYS_STANDALONE		0
 
 struct therm {
 	int hi;
@@ -513,7 +513,7 @@
 			therm.hi <<= 1;
 			therm.lo <<= 1;
 			ds1620_write_state (&therm);
-			ds1620_out (THERM_WRITE_CONFIG, 8, CFG_STANDALONE);
+			ds1620_out (THERM_WRITE_CONFIG, 8, CONFIG_SYS_STANDALONE);
 			return 0;
 		}
 	}
@@ -538,9 +538,9 @@
 	static int init_done = 0;
 	int i;
 	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900);
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
 	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980);
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
 
 	/* GPIO configuration of the CAN pins is done in BC3450.h */
 
@@ -686,9 +686,9 @@
 {
 	int i;
 	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *) (CFG_MBAR + 0x0900);
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0900);
 	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *) (CFG_MBAR + 0x0980);
+		(struct mpc5xxx_mscan *) (CONFIG_SYS_MBAR + 0x0980);
 
 	/* send a message on CAN1 */
 	can1->cantbsel = 0x01;
diff --git a/board/bf533-ezkit/bf533-ezkit.c b/board/bf533-ezkit/bf533-ezkit.c
index 583560a..42c4b50 100644
--- a/board/bf533-ezkit/bf533-ezkit.c
+++ b/board/bf533-ezkit/bf533-ezkit.c
@@ -50,12 +50,12 @@
 	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
 	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
 	       3, 3, 6, 2, 3);
-	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
-	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+	printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
 #endif
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
-	return CFG_MAX_RAM_SIZE;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	return CONFIG_SYS_MAX_RAM_SIZE;
 }
 
 #if defined(CONFIG_MISC_INIT_R)
@@ -63,10 +63,10 @@
 int misc_init_r(void)
 {
 	/* Set direction bits for Video en/decoder reset as output      */
-	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DIR) =
+	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DIR) =
 	    PSDA_VDEC_RST | PSDA_VENC_RST;
 	/* Deactivate Video en/decoder reset lines                      */
-	*(volatile unsigned char *)(CFG_FLASH1_BASE + PSD_PORTA_DOUT) =
+	*(volatile unsigned char *)(CONFIG_SYS_FLASH1_BASE + PSD_PORTA_DOUT) =
 	    PSDA_VDEC_RST | PSDA_VENC_RST;
 
 	return 0;
diff --git a/board/bf533-ezkit/flash-defines.h b/board/bf533-ezkit/flash-defines.h
index 4e043e0..1a4aa5f 100644
--- a/board/bf533-ezkit/flash-defines.h
+++ b/board/bf533-ezkit/flash-defines.h
@@ -49,10 +49,10 @@
 #define FLASH_TOT_SECT		40
 #define FLASH_SIZE		0x220000
 #define FLASH_MAN_ST		2
-#define CFG_FLASH0_BASE		0x20000000
+#define CONFIG_SYS_FLASH0_BASE		0x20000000
 #define RESET_VAL		0xF0
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 int get_codes(void);
 int poll_toggle_bit(long lOffset);
diff --git a/board/bf533-ezkit/flash.c b/board/bf533-ezkit/flash.c
index cdf4dc6..a861e16 100644
--- a/board/bf533-ezkit/flash.c
+++ b/board/bf533-ezkit/flash.c
@@ -82,7 +82,7 @@
 
 	size_b0 = size_b1 = size_b2 = 0;
 #ifdef DEBUG
-	printf("Flash Memory Start 0x%x\n", CFG_FLASH_BASE);
+	printf("Flash Memory Start 0x%x\n", CONFIG_SYS_FLASH_BASE);
 	printf("Memory Map for the Flash\n");
 	printf("0x20000000 - 0x200FFFFF Flash A Primary (1MB)\n");
 	printf("0x20100000 - 0x201FFFFF Flash B Primary (1MB)\n");
@@ -90,20 +90,20 @@
 	printf("0x20280000 - 0x2028FFFF Flash B Secondary (64KB)\n");
 	printf("Please type command flinfo for information on Sectors \n");
 #endif
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0], 0);
-	size_b1 = flash_get_size(CFG_FLASH0_BASE, &flash_info[1], 1);
-	size_b2 = flash_get_size(CFG_FLASH0_BASE, &flash_info[2], 2);
+	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0], 0);
+	size_b1 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[1], 1);
+	size_b2 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[2], 2);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 		       size_b0, size_b0 >> 20);
 	}
 
-	(void)flash_protect(FLAG_PROTECT_SET, CFG_FLASH0_BASE,
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_FLASH0_BASE,
 			    (flash_info[0].start[2] - 1), &flash_info[0]);
 
 	return (size_b0 + size_b1 + size_b2);
@@ -180,7 +180,7 @@
 	int ret;
 	int d;
 	if (addr % 2) {
-		read_flash(addr - 1 - CFG_FLASH_BASE, &d);
+		read_flash(addr - 1 - CONFIG_SYS_FLASH_BASE, &d);
 		d = (int)((d & 0x00FF) | (*src++ << 8));
 		ret = write_data(addr - 1, 2, (uchar *) & d);
 		if (ret == FLASH_FAIL)
@@ -196,7 +196,7 @@
 int write_data(long lStart, long lCount, uchar * pnData)
 {
 	long i = 0;
-	unsigned long ulOffset = lStart - CFG_FLASH_BASE;
+	unsigned long ulOffset = lStart - CONFIG_SYS_FLASH_BASE;
 	int d;
 	int nSector = 0;
 	int flag = 0;
@@ -285,7 +285,7 @@
 {
 	long addr;
 
-	addr = (CFG_FLASH_BASE + nOffset);
+	addr = (CONFIG_SYS_FLASH_BASE + nOffset);
 	SSYNC();
 	*(unsigned volatile short *)addr = nValue;
 	SSYNC();
@@ -297,7 +297,7 @@
 int read_flash(long nOffset, int *pnValue)
 {
 	int nValue = 0x0;
-	long addr = (CFG_FLASH_BASE + nOffset);
+	long addr = (CONFIG_SYS_FLASH_BASE + nOffset);
 
 	if (nOffset != 0x2)
 		reset_flash();
@@ -396,7 +396,7 @@
 	if ((nBlock < 0) || (nBlock > AFP_NumSectors))
 		return FALSE;
 
-	ulSectorOff = (address - CFG_FLASH_BASE);
+	ulSectorOff = (address - CONFIG_SYS_FLASH_BASE);
 
 	write_flash((WRITESEQ1 | ulSectorOff), WRITEDATA1);
 	write_flash((WRITESEQ2 | ulSectorOff), WRITEDATA2);
diff --git a/board/bf533-ezkit/psd4256.h b/board/bf533-ezkit/psd4256.h
index cc654b8..9b381d2 100644
--- a/board/bf533-ezkit/psd4256.h
+++ b/board/bf533-ezkit/psd4256.h
@@ -27,8 +27,8 @@
 
 /*
  * Flash A/B Port A configuration registers.
- * Addresses are offset values to CFG_FLASH1_BASE
- * for Flash A and CFG_FLASH2_BASE for Flash B.
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
  */
 
 #define	PSD_PORTA_DIN	0x070000
@@ -37,8 +37,8 @@
 
 /*
  * Flash A/B Port B configuration registers
- * Addresses are offset values to CFG_FLASH1_BASE
- * for Flash A and CFG_FLASH2_BASE for Flash B.
+ * Addresses are offset values to CONFIG_SYS_FLASH1_BASE
+ * for Flash A and CONFIG_SYS_FLASH2_BASE for Flash B.
  */
 
 #define	PSD_PORTB_DIN	0x070001
diff --git a/board/bf533-ezkit/u-boot.lds.S b/board/bf533-ezkit/u-boot.lds.S
index 1fedbc5..538a19f 100644
--- a/board/bf533-ezkit/u-boot.lds.S
+++ b/board/bf533-ezkit/u-boot.lds.S
@@ -36,7 +36,7 @@
  * for different CPU's which may lack non-cache L1 data.
  */
 #ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
 # define L1_DATA_B_SRAM_SIZE 0
 #endif
 
@@ -45,7 +45,7 @@
 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
 MEMORY
 {
-	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
 	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
diff --git a/board/bf533-stamp/bf533-stamp.c b/board/bf533-stamp/bf533-stamp.c
index 7a17dfa..a113c40 100644
--- a/board/bf533-stamp/bf533-stamp.c
+++ b/board/bf533-stamp/bf533-stamp.c
@@ -56,11 +56,11 @@
 	    ("  tRCD:%d Cycles; tRP:%d Cycles; tRAS:%d Cycles; tWR:%d Cycles; "
 	     "CAS Latency:%d cycles\n", (SDRAM_tRCD >> 15), (SDRAM_tRP >> 11),
 	     (SDRAM_tRAS >> 6), (SDRAM_tWR >> 19), (SDRAM_CL >> 2));
-	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
+	printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
 	printf("Bank size = %d MB\n", 128);
 #endif
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
 	return (gd->bd->bi_memsize);
 }
 
diff --git a/board/bf533-stamp/u-boot.lds.S b/board/bf533-stamp/u-boot.lds.S
index 4e7fd7c..97ebd79 100644
--- a/board/bf533-stamp/u-boot.lds.S
+++ b/board/bf533-stamp/u-boot.lds.S
@@ -36,7 +36,7 @@
  * for different CPU's which may lack non-cache L1 data.
  */
 #ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
 # define L1_DATA_B_SRAM_SIZE 0
 #endif
 
@@ -45,7 +45,7 @@
 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
 MEMORY
 {
-	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
 	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
diff --git a/board/bf537-stamp/bf537-stamp.c b/board/bf537-stamp/bf537-stamp.c
index 4567213..7303f1b 100644
--- a/board/bf537-stamp/bf537-stamp.c
+++ b/board/bf537-stamp/bf537-stamp.c
@@ -109,12 +109,12 @@
 	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
 	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
 	       3, 3, 6, 2, 3);
-	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
-	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+	printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
 #endif
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
-	return CFG_MAX_RAM_SIZE;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	return CONFIG_SYS_MAX_RAM_SIZE;
 }
 
 #if defined(CONFIG_MISC_INIT_R)
@@ -236,11 +236,11 @@
 		erase_block_flash(n);
 		printf("OK\r");
 		printf("--------Program block:%2d...", n);
-		write_data(CFG_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
+		write_data(CONFIG_SYS_FLASH_BASE + offset, BLOCK_SIZE, pbuf);
 		printf("OK\r");
 		printf("--------Verify  block:%2d...", n);
 		for (i = 0; i < BLOCK_SIZE; i += 2) {
-			if (*(unsigned short *)(CFG_FLASH_BASE + offset + i) !=
+			if (*(unsigned short *)(CONFIG_SYS_FLASH_BASE + offset + i) !=
 			    *temp++) {
 				value = 1;
 				result = 1;
diff --git a/board/bf537-stamp/nand.c b/board/bf537-stamp/nand.c
index 9800083..c597f2d 100644
--- a/board/bf537-stamp/nand.c
+++ b/board/bf537-stamp/nand.c
@@ -44,13 +44,13 @@
 
 	if (ctrl & NAND_CTRL_CHANGE) {
 		if( ctrl & NAND_CLE )
-			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_CLE;
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_CLE;
 		else
-			IO_ADDR_W = CFG_NAND_BASE;
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE;
 		if( ctrl & NAND_ALE )
-			IO_ADDR_W = CFG_NAND_BASE + BFIN_NAND_ALE;
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE + BFIN_NAND_ALE;
 		else
-			IO_ADDR_W = CFG_NAND_BASE;
+			IO_ADDR_W = CONFIG_SYS_NAND_BASE;
 		this->IO_ADDR_W = (void __iomem *) IO_ADDR_W;
 	}
 	this->IO_ADDR_R = this->IO_ADDR_W;
diff --git a/board/bf537-stamp/post-memory.c b/board/bf537-stamp/post-memory.c
index fa11991..7c36c81 100644
--- a/board/bf537-stamp/post-memory.c
+++ b/board/bf537-stamp/post-memory.c
@@ -6,7 +6,7 @@
 #include <post.h>
 #include <watchdog.h>
 
-#if CONFIG_POST & CFG_POST_MEMORY
+#if CONFIG_POST & CONFIG_SYS_POST_MEMORY
 #define CLKIN 25000000
 #define PATTERN1 0x5A5A5A5A
 #define PATTERN2 0xAAAAAAAA
@@ -71,10 +71,10 @@
 			post_init_uart(sclk);
 			post_out_buff("\n\r\0");
 			post_out_buff(log[m][n]);
-			for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4)
+			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4)
 				*(unsigned long *)addr = PATTERN1;
 			post_out_buff("Reading...\0");
-			for (addr = 0x0; addr < CFG_MAX_RAM_SIZE; addr += 4) {
+			for (addr = 0x0; addr < CONFIG_SYS_MAX_RAM_SIZE; addr += 4) {
 				if ((*(unsigned long *)addr) != PATTERN1) {
 					post_out_buff("Error\n\r\0");
 					ret = 0;
@@ -318,5 +318,5 @@
 	return mem_SDRRC;
 }
 
-#endif				/* CONFIG_POST & CFG_POST_MEMORY */
+#endif				/* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
 #endif				/* CONFIG_POST */
diff --git a/board/bf537-stamp/spi_flash.c b/board/bf537-stamp/spi_flash.c
index 7c73ddd..11a2803 100644
--- a/board/bf537-stamp/spi_flash.c
+++ b/board/bf537-stamp/spi_flash.c
@@ -412,7 +412,7 @@
  */
 void spi_init_r(void)
 {
-#if defined(CONFIG_POST) && (CONFIG_POST & CFG_POST_SPI)
+#if defined(CONFIG_POST) && (CONFIG_POST & CONFIG_SYS_POST_SPI)
 	/* Our testing strategy here is pretty basic:
 	 *  - fill src memory with an 8-bit pattern
 	 *  - write the src memory to the SPI flash
diff --git a/board/bf537-stamp/u-boot.lds.S b/board/bf537-stamp/u-boot.lds.S
index 4e7fd7c..97ebd79 100644
--- a/board/bf537-stamp/u-boot.lds.S
+++ b/board/bf537-stamp/u-boot.lds.S
@@ -36,7 +36,7 @@
  * for different CPU's which may lack non-cache L1 data.
  */
 #ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
 # define L1_DATA_B_SRAM_SIZE 0
 #endif
 
@@ -45,7 +45,7 @@
 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
 MEMORY
 {
-	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
 	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
diff --git a/board/bf561-ezkit/bf561-ezkit.c b/board/bf561-ezkit/bf561-ezkit.c
index 7345b42..a74ff0d 100644
--- a/board/bf561-ezkit/bf561-ezkit.c
+++ b/board/bf561-ezkit/bf561-ezkit.c
@@ -50,12 +50,12 @@
 	printf("tRCD %d SCLK Cycles,tRP %d SCLK Cycles,tRAS %d SCLK Cycles"
 	       "tWR %d SCLK Cycles,CAS Latency %d SCLK cycles \n",
 	       3, 3, 6, 2, 3);
-	printf("SDRAM Begin: 0x%x\n", CFG_SDRAM_BASE);
-	printf("Bank size = %d MB\n", CFG_MAX_RAM_SIZE >> 20);
+	printf("SDRAM Begin: 0x%x\n", CONFIG_SYS_SDRAM_BASE);
+	printf("Bank size = %d MB\n", CONFIG_SYS_MAX_RAM_SIZE >> 20);
 #endif
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_MAX_RAM_SIZE;
-	return CFG_MAX_RAM_SIZE;
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	return CONFIG_SYS_MAX_RAM_SIZE;
 }
 
 #if defined(CONFIG_MISC_INIT_R)
diff --git a/board/bf561-ezkit/u-boot.lds.S b/board/bf561-ezkit/u-boot.lds.S
index ab5ef08..3defef4 100644
--- a/board/bf561-ezkit/u-boot.lds.S
+++ b/board/bf561-ezkit/u-boot.lds.S
@@ -36,7 +36,7 @@
  * for different CPU's which may lack non-cache L1 data.
  */
 #ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      CFG_MONITOR_BASE
+# define L1_DATA_B_SRAM      CONFIG_SYS_MONITOR_BASE
 # define L1_DATA_B_SRAM_SIZE 0
 #endif
 
@@ -45,7 +45,7 @@
 /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
 MEMORY
 {
-	ram     : ORIGIN = CFG_MONITOR_BASE, LENGTH = CFG_MONITOR_LEN
+	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
 	l1_code : ORIGIN = L1_INST_SRAM+0xC, LENGTH = L1_INST_SRAM_SIZE
 	l1_data : ORIGIN = L1_DATA_B_SRAM,   LENGTH = L1_DATA_B_SRAM_SIZE
 }
diff --git a/board/bmw/README b/board/bmw/README
index 1f04b1b..1fbef79 100644
--- a/board/bmw/README
+++ b/board/bmw/README
@@ -62,26 +62,26 @@
 The following Block-Address-Translation (BAT) configuration
 is recommended to access all I/O devices.
 
-#define CFG_IBAT0L  (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
-#define CFG_IBAT0U  (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT0L  (0x00000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
+#define CONFIG_SYS_IBAT0U  (0x00000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
-#define CFG_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
+#define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
+#define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 
-#define CFG_DBAT0L  CFG_IBAT0L
-#define CFG_DBAT0U  CFG_IBAT0U
-#define CFG_DBAT1L  CFG_IBAT1L
-#define CFG_DBAT1U  CFG_IBAT1U
-#define CFG_DBAT2L  CFG_IBAT2L
-#define CFG_DBAT2U  CFG_IBAT2U
-#define CFG_DBAT3L  CFG_IBAT3L
-#define CFG_DBAT3U  CFG_IBAT3U
+#define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
+#define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
+#define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
+#define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
+#define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
+#define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
+#define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
+#define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 
 
 Interrupt Mappings
diff --git a/board/bmw/early_init.S b/board/bmw/early_init.S
index 57a06a9..63c29d5 100644
--- a/board/bmw/early_init.S
+++ b/board/bmw/early_init.S
@@ -86,10 +86,10 @@
 /*
  *  Set up I/D BAT0
  */
-	lis     r4, CFG_DBAT0L@h
-	ori     r4, r4, CFG_DBAT0L@l
-	lis     r3, CFG_DBAT0U@h
-	ori     r3, r3, CFG_DBAT0U@l
+	lis     r4, CONFIG_SYS_DBAT0L@h
+	ori     r4, r4, CONFIG_SYS_DBAT0L@l
+	lis     r3, CONFIG_SYS_DBAT0U@h
+	ori     r3, r3, CONFIG_SYS_DBAT0U@l
 
 	mtdbat0l(r4)
 	isync
@@ -97,10 +97,10 @@
 	isync
 	sync
 
-	lis     r4, CFG_IBAT0L@h
-	ori     r4, r4, CFG_IBAT0L@l
-	lis     r3, CFG_IBAT0U@h
-	ori     r3, r3, CFG_IBAT0U@l
+	lis     r4, CONFIG_SYS_IBAT0L@h
+	ori     r4, r4, CONFIG_SYS_IBAT0L@l
+	lis     r3, CONFIG_SYS_IBAT0U@h
+	ori     r3, r3, CONFIG_SYS_IBAT0U@l
 
 	isync
 	mtibat0l(r4)
@@ -111,10 +111,10 @@
 /*
  *  Set up I/D BAT1
  */
-	lis     r4, CFG_IBAT1L@h
-	ori     r4, r4, CFG_IBAT1L@l
-	lis     r3, CFG_IBAT1U@h
-	ori     r3, r3, CFG_IBAT1U@l
+	lis     r4, CONFIG_SYS_IBAT1L@h
+	ori     r4, r4, CONFIG_SYS_IBAT1L@l
+	lis     r3, CONFIG_SYS_IBAT1U@h
+	ori     r3, r3, CONFIG_SYS_IBAT1U@l
 
 	isync
 	mtibat1l(r4)
@@ -130,10 +130,10 @@
 /*
  *  Set up I/D BAT2
  */
-	lis     r4, CFG_IBAT2L@h
-	ori     r4, r4, CFG_IBAT2L@l
-	lis     r3, CFG_IBAT2U@h
-	ori     r3, r3, CFG_IBAT2U@l
+	lis     r4, CONFIG_SYS_IBAT2L@h
+	ori     r4, r4, CONFIG_SYS_IBAT2L@l
+	lis     r3, CONFIG_SYS_IBAT2U@h
+	ori     r3, r3, CONFIG_SYS_IBAT2U@l
 
 	isync
 	mtibat2l(r4)
@@ -149,10 +149,10 @@
 /*
  *  Setup I/D BAT3
  */
-	lis     r4, CFG_IBAT3L@h
-	ori     r4, r4, CFG_IBAT3L@l
-	lis     r3, CFG_IBAT3U@h
-	ori     r3, r3, CFG_IBAT3U@l
+	lis     r4, CONFIG_SYS_IBAT3L@h
+	ori     r4, r4, CONFIG_SYS_IBAT3L@l
+	lis     r3, CONFIG_SYS_IBAT3U@h
+	ori     r3, r3, CONFIG_SYS_IBAT3U@l
 
 	isync
 	mtibat3l(r4)
@@ -466,7 +466,7 @@
 
 	LOADPTR (r3, EUMBBAR)
 	stwbrx	r3,0,r5
-	LOADPTR (r4, CFG_EUMB_ADDR)
+	LOADPTR (r4, CONFIG_SYS_EUMB_ADDR)
 	stwbrx	r4,0,r6
 
 L1not8245:
diff --git a/board/bmw/flash.c b/board/bmw/flash.c
index 0d0bc2f..57ffe08 100644
--- a/board/bmw/flash.c
+++ b/board/bmw/flash.c
@@ -29,11 +29,11 @@
 #define ROM_CS0_START	0xFF800000
 #define ROM_CS1_START	0xFF000000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
@@ -141,10 +141,10 @@
 {
 	unsigned long i;
 	unsigned char j;
-	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		flash_info_t *const pflinfo = &flash_info[i];
 
 		pflinfo->flash_id = FLASH_UNKNOWN;
@@ -217,10 +217,10 @@
 		}
 		/* Protect monitor and environment sectors
 		 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			       &flash_info[0]);
 #endif
 
@@ -627,7 +627,7 @@
 						       start[0]) << sh8b));
 	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
 	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -766,7 +766,7 @@
 		start = get_timer (0);
 		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/bmw/ns16550.c b/board/bmw/ns16550.c
index 7064567..7250591 100644
--- a/board/bmw/ns16550.c
+++ b/board/bmw/ns16550.c
@@ -1,7 +1,7 @@
 /*
  * COM1 NS16550 support
  * originally from linux source (arch/ppc/boot/ns16550.c)
- * modified to use CFG_ISA_MEM and new defines
+ * modified to use CONFIG_SYS_ISA_MEM and new defines
  */
 
 #include <config.h>
@@ -10,8 +10,8 @@
 typedef struct NS16550 *NS16550_t;
 
 const NS16550_t COM_PORTS[] =
-	{ (NS16550_t) ((CFG_EUMB_ADDR) + 0x4500),
-(NS16550_t) ((CFG_EUMB_ADDR) + 0x4600) };
+	{ (NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4500),
+(NS16550_t) ((CONFIG_SYS_EUMB_ADDR) + 0x4600) };
 
 volatile struct NS16550 *NS16550_init (int chan, int baud_divisor)
 {
diff --git a/board/bmw/ns16550.h b/board/bmw/ns16550.h
index 104f45b..210aea4 100644
--- a/board/bmw/ns16550.h
+++ b/board/bmw/ns16550.h
@@ -2,7 +2,7 @@
  * NS16550 Serial Port
  * originally from linux source (arch/ppc/boot/ns16550.h)
  * modified slightly to
- * have addresses as offsets from CFG_ISA_BASE
+ * have addresses as offsets from CONFIG_SYS_ISA_BASE
  * added a few more definitions
  * added prototypes for ns16550.c
  * reduced no of com ports to 2
diff --git a/board/bmw/serial.c b/board/bmw/serial.c
index 712a95b..0c97f12 100644
--- a/board/bmw/serial.c
+++ b/board/bmw/serial.c
@@ -28,10 +28,10 @@
 
 #if CONFIG_CONS_INDEX == 1
 static struct NS16550 *console =
-		(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
 #elif CONFIG_CONS_INDEX == 2
 static struct NS16550 *console =
-		(struct NS16550 *) (CFG_EUMB_ADDR + 0x4500);
+		(struct NS16550 *) (CONFIG_SYS_EUMB_ADDR + 0x4500);
 #else
 #error no valid console defined
 #endif
diff --git a/board/c2mon/c2mon.c b/board/c2mon/c2mon.c
index 7d2f746..717a64b 100644
--- a/board/c2mon/c2mon.c
+++ b/board/c2mon/c2mon.c
@@ -110,7 +110,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long reg;
 	long int size8, size9;
@@ -124,17 +124,17 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 2 the SDRAM bank 2 at physical address 0.
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -154,7 +154,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -163,7 +163,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL,
 			   SDRAM_BASE2_PRELIM,
 			   SDRAM_MAX_SIZE);
 
@@ -172,7 +172,7 @@
 /*		debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {			/* back to 8 columns            */
 		size = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*		debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -185,15 +185,15 @@
 	 */
 	if (size < 0x02000000) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/*
 	 * Final mapping
 	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/*
 	 * No bank 1
@@ -204,7 +204,7 @@
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -225,7 +225,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/c2mon/flash.c b/board/c2mon/flash.c
index 7cc5ef0..d33cb6c 100644
--- a/board/c2mon/flash.c
+++ b/board/c2mon/flash.c
@@ -25,10 +25,10 @@
 #include <mpc8xx.h>
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -42,13 +42,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -79,19 +79,19 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -104,21 +104,21 @@
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V;
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -436,7 +436,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -559,7 +559,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/c2mon/pcmcia.c b/board/c2mon/pcmcia.c
index 57846b1..c833b20 100644
--- a/board/c2mon/pcmcia.c
+++ b/board/c2mon/pcmcia.c
@@ -22,8 +22,8 @@
 	volatile cpm8xx_t	*cp;
 	ushort sreg;
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	* Configure Port C for TPS2211 PC-Card Power-Interface Switch
@@ -69,10 +69,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
 	cfg_ports ();
@@ -175,8 +175,8 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* Configure PCMCIA General Control Register */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
@@ -209,9 +209,9 @@
 			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
 	* and assert RESET signal
diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c
index d3711d0..dce07bf 100644
--- a/board/canmb/canmb.c
+++ b/board/canmb/canmb.c
@@ -34,7 +34,7 @@
 #include "mt48lc16m32s2-75.h"
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -77,7 +77,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -86,7 +86,7 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -107,9 +107,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -135,10 +135,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((ulong *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -160,7 +160,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -178,7 +178,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize + dramsize2;
 }
@@ -188,7 +188,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup and enable SDRAM chip selects */
@@ -207,9 +207,9 @@
 
 	/* find RAM size */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -220,12 +220,12 @@
 	/* set SDRAM end address according to size */
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* Retrieve amount of SDRAM available */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -244,8 +244,8 @@
 {
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
 	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
 	return 0;
 }
diff --git a/board/cerf250/flash.c b/board/cerf250/flash.c
index 3ff19bc..a4b201e 100644
--- a/board/cerf250/flash.c
+++ b/board/cerf250/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -85,8 +85,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -203,10 +203,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -276,7 +276,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -410,7 +410,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/cerf250/lowlevel_init.S b/board/cerf250/lowlevel_init.S
index ad3c59f..5bfe53c 100644
--- a/board/cerf250/lowlevel_init.S
+++ b/board/cerf250/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -49,67 +49,67 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr	r0, =GPSR0
-	ldr	r1, =CFG_GPSR0_VAL
+	ldr	r1, =CONFIG_SYS_GPSR0_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPSR1
-	ldr	r1, =CFG_GPSR1_VAL
+	ldr	r1, =CONFIG_SYS_GPSR1_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPSR2
-	ldr	r1, =CFG_GPSR2_VAL
+	ldr	r1, =CONFIG_SYS_GPSR2_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPCR0
-	ldr	r1, =CFG_GPCR0_VAL
+	ldr	r1, =CONFIG_SYS_GPCR0_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPCR1
-	ldr	r1, =CFG_GPCR1_VAL
+	ldr	r1, =CONFIG_SYS_GPCR1_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPCR2
-	ldr	r1, =CFG_GPCR2_VAL
+	ldr	r1, =CONFIG_SYS_GPCR2_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPDR0
-	ldr	r1, =CFG_GPDR0_VAL
+	ldr	r1, =CONFIG_SYS_GPDR0_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPDR1
-	ldr	r1, =CFG_GPDR1_VAL
+	ldr	r1, =CONFIG_SYS_GPDR1_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GPDR2
-	ldr	r1, =CFG_GPDR2_VAL
+	ldr	r1, =CONFIG_SYS_GPDR2_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR0_L
-	ldr	r1, =CFG_GAFR0_L_VAL
+	ldr	r1, =CONFIG_SYS_GAFR0_L_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR0_U
-	ldr	r1, =CFG_GAFR0_U_VAL
+	ldr	r1, =CONFIG_SYS_GAFR0_U_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR1_L
-	ldr	r1, =CFG_GAFR1_L_VAL
+	ldr	r1, =CONFIG_SYS_GAFR1_L_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR1_U
-	ldr	r1, =CFG_GAFR1_U_VAL
+	ldr	r1, =CONFIG_SYS_GAFR1_U_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR2_L
-	ldr	r1, =CFG_GAFR2_L_VAL
+	ldr	r1, =CONFIG_SYS_GAFR2_L_VAL
 	str	r1, [r0]
 
 	ldr	r0, =GAFR2_U
-	ldr	r1, =CFG_GAFR2_U_VAL
+	ldr	r1, =CONFIG_SYS_GAFR2_U_VAL
 	str	r1, [r0]
 
 	ldr	r0, =PSSR			/* enable GPIO pins */
-	ldr	r1, =CFG_PSSR_VAL
+	ldr	r1, =CONFIG_SYS_PSSR_VAL
 	str	r1, [r0]
 
 	/* ---------------------------------------------------------------- */
@@ -147,17 +147,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr	r2, =CFG_MSC0_VAL
+	ldr	r2, =CONFIG_SYS_MSC0_VAL
 	str	r2, [r1, #MSC0_OFFSET]
 	ldr	r2, [r1, #MSC0_OFFSET]		/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr	r2, =CFG_MSC1_VAL
+	ldr	r2, =CONFIG_SYS_MSC1_VAL
 	str	r2, [r1, #MSC1_OFFSET]
 	ldr	r2, [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr	r2, =CFG_MSC2_VAL
+	ldr	r2, =CONFIG_SYS_MSC2_VAL
 	str	r2, [r1, #MSC2_OFFSET]
 	ldr	r2, [r1, #MSC2_OFFSET]
 
@@ -166,37 +166,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr	r2, =CFG_MECR_VAL
+	ldr	r2, =CONFIG_SYS_MECR_VAL
 	str	r2, [r1, #MECR_OFFSET]
 	ldr	r2, [r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr	r2, =CFG_MCMEM0_VAL
+	ldr	r2, =CONFIG_SYS_MCMEM0_VAL
 	str	r2, [r1, #MCMEM0_OFFSET]
 	ldr	r2, [r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr	r2, =CFG_MCMEM1_VAL
+	ldr	r2, =CONFIG_SYS_MCMEM1_VAL
 	str	r2, [r1, #MCMEM1_OFFSET]
 	ldr	r2, [r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr	r2, =CFG_MCATT0_VAL
+	ldr	r2, =CONFIG_SYS_MCATT0_VAL
 	str	r2, [r1, #MCATT0_OFFSET]
 	ldr	r2, [r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr	r2, =CFG_MCATT1_VAL
+	ldr	r2, =CONFIG_SYS_MCATT1_VAL
 	str	r2, [r1, #MCATT1_OFFSET]
 	ldr	r2, [r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr	r2, =CFG_MCIO0_VAL
+	ldr	r2, =CONFIG_SYS_MCIO0_VAL
 	str	r2, [r1, #MCIO0_OFFSET]
 	ldr	r2, [r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr	r2, =CFG_MCIO1_VAL
+	ldr	r2, =CONFIG_SYS_MCIO1_VAL
 	str	r2, [r1, #MCIO1_OFFSET]
 	ldr	r2, [r1, #MCIO1_OFFSET]
 
@@ -212,7 +212,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field, set SDRAM clocks free running */
 
-	ldr	r3, =CFG_MDREFR_VAL
+	ldr	r3, =CONFIG_SYS_MDREFR_VAL
 	ldr	r2, =0xFFF
 	and	r3, r3,  r2
 
@@ -243,7 +243,7 @@
 
 	/* set MDREFR according to user define with exception of a few bits */
 
-	ldr     r4, =CFG_MDREFR_VAL
+	ldr     r4, =CONFIG_SYS_MDREFR_VAL
 	ldr	r2, =(MDREFR_K0RUN|MDREFR_K0DB2|MDREFR_K1RUN|MDREFR_K1DB2|\
 					MDREFR_K2RUN |MDREFR_K2DB2)
 	and	r4, r4, r2
@@ -262,7 +262,7 @@
 
 	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired, set KXFREE  */
 
-	ldr     r4, =CFG_MDREFR_VAL
+	ldr     r4, =CONFIG_SYS_MDREFR_VAL
 	ldr	r2, =(MDREFR_E0PIN|MDREFR_E1PIN|MDREFR_K0FREE| \
 			MDREFR_K1FREE | MDREFR_K2FREE)
 	and	r4, r4, r2
@@ -274,7 +274,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4, =CFG_MDCNFG_VAL
+	ldr	r4, =CONFIG_SYS_MDCNFG_VAL
 	bic	r4, r4, #(MDCNFG_DE0|MDCNFG_DE1)
 	bic	r4, r4, #(MDCNFG_DE2|MDCNFG_DE3)
 	str     r4, [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -301,7 +301,7 @@
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr	r3, =CFG_DRAM_BASE
+	ldr	r3, =CONFIG_SYS_DRAM_BASE
 .rept 8
 	str	r2, [r3]
 .endr
@@ -315,7 +315,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2, =CFG_MDMRS_VAL
+	ldr     r2, =CONFIG_SYS_MDMRS_VAL
 	str     r2, [r1, #MDMRS_OFFSET]
 
 
diff --git a/board/cm4008/flash.c b/board/cm4008/flash.c
index 86c8e2a..2e66872 100644
--- a/board/cm4008/flash.c
+++ b/board/cm4008/flash.c
@@ -31,7 +31,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 #define mb() __asm__ __volatile__ ("" : : : "memory")
 
@@ -51,7 +51,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
@@ -71,8 +71,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
 		       &flash_info[0]);
 
 	return size;
@@ -189,10 +189,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = 0xFF;	/* restore read mode */
@@ -259,7 +259,7 @@
 
 			while (((status = *addr) & 0x80) != 0x80) {
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0xB0;	/* suspend erase */
 					*addr = 0xFF;	/* reset to read mode */
@@ -388,7 +388,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & 0x80) != 0x80) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = 0xFF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/cm41xx/flash.c b/board/cm41xx/flash.c
index 86c8e2a..2e66872 100644
--- a/board/cm41xx/flash.c
+++ b/board/cm41xx/flash.c
@@ -31,7 +31,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 #define mb() __asm__ __volatile__ ("" : : : "memory")
 
@@ -51,7 +51,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((unsigned char *) PHYS_FLASH_1, &flash_info[i]);
@@ -71,8 +71,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
 		       &flash_info[0]);
 
 	return size;
@@ -189,10 +189,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = 0xFF;	/* restore read mode */
@@ -259,7 +259,7 @@
 
 			while (((status = *addr) & 0x80) != 0x80) {
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0xB0;	/* suspend erase */
 					*addr = 0xFF;	/* reset to read mode */
@@ -388,7 +388,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & 0x80) != 0x80) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = 0xFF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/cm5200/cm5200.c b/board/cm5200/cm5200.c
index 24e8db0..9e2f1a5 100644
--- a/board/cm5200/cm5200.c
+++ b/board/cm5200/cm5200.c
@@ -57,7 +57,7 @@
 static hw_id_t hw_id;
 
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 /*
  * Helper function to initialize SDRAM controller.
  */
@@ -87,7 +87,7 @@
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = mem_conf->control | hi_addr_bit;
 }
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 
 /*
@@ -117,7 +117,7 @@
 phys_size_t initdram(int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 	mem_conf_t *mem_conf;
 
@@ -131,9 +131,9 @@
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = mem_conf->config2;
 
 	sdram_start(0, mem_conf);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1, mem_conf);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0, mem_conf);
 		dramsize = test1;
@@ -150,14 +150,14 @@
 			__builtin_ffs(dramsize >> 20) - 1;
 	} else
 		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 	if (dramsize >= 0x13)
 		dramsize = (1 << (dramsize - 0x13)) << 20;
 	else
 		dramsize = 0;
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -178,7 +178,7 @@
 {
 	int i;
 	for (i = 0; i < HW_ID_ELEM_COUNT; ++i)
-		if (i2c_read(CFG_I2C_EEPROM,
+		if (i2c_read(CONFIG_SYS_I2C_EEPROM,
 				hw_id_format[i].offset,
 				2,
 				(uchar *)&hw_id[i][0],
@@ -298,7 +298,7 @@
 	 * also use a little trick to silence I2C-related output.
 	 */
 	gd->flags |= GD_FLG_SILENT;
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	gd->flags &= ~GD_FLG_SILENT;
 
 	read_hw_id(hw_id_tmp);
@@ -363,7 +363,7 @@
 	char hostname[MODULE_NAME_MAXLEN];
 
 	/* Read ethaddr from EEPROM */
-	if (i2c_read(CFG_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM, CONFIG_MAC_OFFSET, 2, buf, 6) == 0) {
 		sprintf(str, "%02X:%02X:%02X:%02X:%02X:%02X",
 			buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
 		/* Check if MAC addr is owned by Schindler */
@@ -377,7 +377,7 @@
 		}
 	} else {
 		printf(LOG_PREFIX "Warning - Unable to read MAC from I2C"
-			" device at address %02X:%04X\n", CFG_I2C_EEPROM,
+			" device at address %02X:%04X\n", CONFIG_SYS_I2C_EEPROM,
 			CONFIG_MAC_OFFSET);
 	}
 #endif /* defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) */
diff --git a/board/cm5200/cmd_cm5200.c b/board/cm5200/cmd_cm5200.c
index 2201bdd..00f0671 100644
--- a/board/cm5200/cmd_cm5200.c
+++ b/board/cm5200/cmd_cm5200.c
@@ -39,18 +39,18 @@
 	getc();
 
 	temp = 0xf0; /* set io 0-4 as output */
-	i2c_write(CFG_I2C_IO, 3, 1, (uchar *)&temp, 1);
+	i2c_write(CONFIG_SYS_I2C_IO, 3, 1, (uchar *)&temp, 1);
 
 	printf("Press I2C4-7. LED I2C0-3 should have the same state\n\n"
 		"Press any key to stop\n\n");
 
 	while (!tstc()) {
-		i2c_read(CFG_I2C_IO, 0, 1, (uchar *)&temp, 1);
+		i2c_read(CONFIG_SYS_I2C_IO, 0, 1, (uchar *)&temp, 1);
 		temp1 = (temp >> 4) & 0x03;
 		temp1 |= (temp >> 3) & 0x08; /* S302 -> LED303 */
 		temp1 |= (temp >> 5) & 0x04; /* S303 -> LED302 */
 		temp = temp1;
-		i2c_write(CFG_I2C_IO, 1, 1, (uchar *)&temp, 1);
+		i2c_write(CONFIG_SYS_I2C_IO, 1, 1, (uchar *)&temp, 1);
 	}
 	getc();
 
@@ -392,7 +392,7 @@
 		error_status = 1;
 		break;
 	}
-	gpio->port_config |= (CFG_GPS_PORT_CONFIG & 0xFF0FF80F);
+	gpio->port_config |= (CONFIG_SYS_GPS_PORT_CONFIG & 0xFF0FF80F);
 
 	return error_status;
 }
diff --git a/board/cmc_pu2/flash.c b/board/cmc_pu2/flash.c
index 8966399..d832e62 100644
--- a/board/cmc_pu2/flash.c
+++ b/board/cmc_pu2/flash.c
@@ -30,10 +30,10 @@
 #include <common.h>
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 #define FLASH_CYCLE1	0x0555
 #define FLASH_CYCLE2	0x02AA
@@ -54,7 +54,7 @@
 unsigned long flash_init (void)
 {
 	unsigned long size = 0;
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	/* Init: no FLASHes known */
 	memset(&flash_info[0], 0, sizeof(flash_info_t));
@@ -63,12 +63,12 @@
 
 	size = flash_info[0].size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -104,14 +104,14 @@
 	flash_info_t * info;
 
 	info = NULL;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->size && info->start[0] <= base &&
 		    base <= info->start[0] + info->size - 1)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -339,7 +339,7 @@
 		last  = 0;
 		addr = (vu_short *)(info->start[l_sect]);
 		while ((addr[0] & 0x0080) != 0x0080) {
-			if ((now = get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -459,7 +459,7 @@
 
 	/* data polling for D7 */
 	while ((*dest & 0x0080) != (data & 0x0080)) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = 0x00F0;	/* reset bank */
 			return (1);
 		}
diff --git a/board/cmi/cmi.c b/board/cmi/cmi.c
index ee243db..b78183e 100644
--- a/board/cmi/cmi.c
+++ b/board/cmi/cmi.c
@@ -70,4 +70,4 @@
 /*
  * Absolute environment address for linker file.
  */
-GEN_ABS(env_start, CONFIG_ENV_OFFSET + CFG_FLASH_BASE);
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/cmi/flash.c b/board/cmi/flash.c
index 0d4582b..630c330 100644
--- a/board/cmi/flash.c
+++ b/board/cmi/flash.c
@@ -38,7 +38,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -62,7 +62,7 @@
 #define FLASH_CMD_PROTECT_CLEAR		0x00D0
 #define FLASH_STATUS_DONE		0x0080
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*
  * Local function prototypes
@@ -81,7 +81,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -102,11 +102,11 @@
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -268,10 +268,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = FLASH_CMD_RESET;		/* restore read mode */
@@ -345,7 +345,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf("Flash erase timeout at address %lx\n", info->start[sect]);
 					*addr = FLASH_CMD_SUSPEND_ERASE;
 					*addr = FLASH_CMD_RESET;
@@ -473,7 +473,7 @@
 
 	/* wait for error or finish */
 	while(!(addr[0] & FLASH_STATUS_DONE)){
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			addr[0] = FLASH_CMD_RESET;
 			return (1);
 		}
@@ -504,7 +504,7 @@
 	/* wait for error or finish */
 	start = get_timer (0);
 	while(!(addr[0] & FLASH_STATUS_DONE)){
-		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
 			addr[0] = FLASH_CMD_RESET;
 			return (1);
diff --git a/board/cobra5272/cobra5272.c b/board/cobra5272/cobra5272.c
index b928550..a62214c 100644
--- a/board/cobra5272/cobra5272.c
+++ b/board/cobra5272/cobra5272.c
@@ -42,7 +42,7 @@
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *) 0) = 0;
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 int testdram (void)
diff --git a/board/cobra5272/flash.c b/board/cobra5272/flash.c
index 82452e2..33c9361 100644
--- a/board/cobra5272/flash.c
+++ b/board/cobra5272/flash.c
@@ -23,10 +23,10 @@
 
 #include <common.h>
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -74,15 +74,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(AMD_MANUFACT & FLASH_VENDMASK) |
 			(AMD_ID_PL160CB & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -113,8 +113,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
 
 	return size;
 }
@@ -128,8 +128,8 @@
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
 
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
@@ -211,7 +211,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip1 = TMO;
 					break;
@@ -299,7 +299,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip1 = ERR | TMO;
 			break;
 		}
diff --git a/board/cobra5272/mii.c b/board/cobra5272/mii.c
index b30ba80..161c694 100644
--- a/board/cobra5272/mii.c
+++ b/board/cobra5272/mii.c
@@ -45,7 +45,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/cogent/README b/board/cogent/README
index e6eef66..31ca187 100644
--- a/board/cogent/README
+++ b/board/cogent/README
@@ -80,16 +80,16 @@
 "include/config_cogent_mpc8xx.h" and reviewing all the options and
 settings in there. In particular, check the chip select values
 installed into the memory controller's various option and base
-registers - these are set by the defines CFG_CMA_CSn_{BASE,SIZE} and
-CFG_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
-into the SCCR - via the define CFG_SCCR. Finally, decide whether you
+registers - these are set by the defines CONFIG_SYS_CMA_CSn_{BASE,SIZE} and
+CONFIG_SYS_{B,O}Rn_PRELIM. Also be careful of the clock settings installed
+into the SCCR - via the define CONFIG_SYS_SCCR. Finally, decide whether you
 want the serial console on motherboard serial port A or on one of the
 8xx SMC ports, and set CONFIG_8xx_CONS_{SMC1,SMC2,NONE} accordingly
 (NONE means use Cogent motherboard serial port A).
 
 Then edit the file "cogent/config.mk". Firstly, set TEXT_BASE to be
 the base address of the EPROM for the CPU module. This should be the
-same as the value selected for CFG_MONITOR_BASE in
+same as the value selected for CONFIG_SYS_MONITOR_BASE in
 "include/config_cogent_*.h" (in fact, I have made this automatic via
 the -DTEXT_BASE=... option in CPPFLAGS).
 
diff --git a/board/cogent/flash.c b/board/cogent/flash.c
index 942f33a..e6c85b6 100644
--- a/board/cogent/flash.c
+++ b/board/cogent/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <board/cogent/flash.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -121,7 +121,7 @@
 		fip->size += C302F_BNK_SIZE;
 		osc = fip->sector_count;
 		fip->sector_count += C302F_BNK_NBLOCKS;
-		if ((nsc = fip->sector_count) >= CFG_MAX_FLASH_SECT)
+		if ((nsc = fip->sector_count) >= CONFIG_SYS_MAX_FLASH_SECT)
 			panic("Too many sectors in flash at address 0x%08lx\n",
 				(unsigned long)base);
 
@@ -264,7 +264,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -295,7 +295,7 @@
 	flash_info_t *fip;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -303,7 +303,7 @@
 	total = 0L;
 
 #if defined(CONFIG_CMA302)
-	c302f_probe(fip, (c302f_addr_t)CFG_FLASH_BASE);
+	c302f_probe(fip, (c302f_addr_t)CONFIG_SYS_FLASH_BASE);
 	total += fip->size;
 	fip++;
 #endif
@@ -320,10 +320,10 @@
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE == CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -472,7 +472,7 @@
 			do {
 				now = get_timer(start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					break;
diff --git a/board/cogent/lcd.c b/board/cogent/lcd.c
index 814b4c8..76f5ad1 100644
--- a/board/cogent/lcd.c
+++ b/board/cogent/lcd.c
@@ -197,7 +197,7 @@
 lcd_printf(const char *fmt, ...)
 {
     va_list args;
-    char buf[CFG_PBSIZE];
+    char buf[CONFIG_SYS_PBSIZE];
 
     va_start(args, fmt);
     (void)vsprintf(buf, fmt, args);
@@ -234,7 +234,7 @@
 void board_show_activity (ulong timestamp)
 {
 #ifdef CONFIG_STATUS_LED
-	if ((timestamp % (CFG_HZ / 2) == 0)
+	if ((timestamp % (CONFIG_SYS_HZ / 2) == 0)
 		lcd_heartbeat ();
 #endif
 }
diff --git a/board/cogent/mb.h b/board/cogent/mb.h
index f6eaf0a..b3aba48 100644
--- a/board/cogent/mb.h
+++ b/board/cogent/mb.h
@@ -69,51 +69,51 @@
  * 0xA000000-0xDFFFFFF.
  */
 
-#define CMA_MB_RAM_BASE		(CFG_CMA_MB_BASE+0x0000000)
+#define CMA_MB_RAM_BASE		(CONFIG_SYS_CMA_MB_BASE+0x0000000)
 #define CMA_MB_RAM_SIZE		0x2000000	/* dip sws set actual size */
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT1)
-#define CMA_MB_SLOT1_BASE	(CFG_CMA_MB_BASE+0x2000000)
+#define CMA_MB_SLOT1_BASE	(CONFIG_SYS_CMA_MB_BASE+0x2000000)
 #define CMA_MB_SLOT1_SIZE	0x2000000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_SLOT2_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
 #define CMA_MB_SLOT2_SIZE	0x2000000
 #endif
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_STDPCI_BASE	(CFG_CMA_MB_BASE+0x4000000)
+#define CMA_MB_STDPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0x4000000)
 #define CMA_MB_STDPCI_SIZE	0x1ff0000
-#define CMA_MB_V360EPC_BASE	(CFG_CMA_MB_BASE+0x5ff0000)
+#define CMA_MB_V360EPC_BASE	(CONFIG_SYS_CMA_MB_BASE+0x5ff0000)
 #define CMA_MB_V360EPC_SIZE	0x10000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3_BASE	(CFG_CMA_MB_BASE+0x6000000)
+#define CMA_MB_SLOT3_BASE	(CONFIG_SYS_CMA_MB_BASE+0x6000000)
 #define CMA_MB_SLOT3_SIZE	0x2000000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI_EXT)
-#define CMA_MB_EXTPCI_BASE	(CFG_CMA_MB_BASE+0xa000000)
+#define CMA_MB_EXTPCI_BASE	(CONFIG_SYS_CMA_MB_BASE+0xa000000)
 #define CMA_MB_EXTPCI_SIZE	0x4000000
 #endif
 
-#define CMA_MB_ROMLOW_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_ROMLOW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
 #define CMA_MB_ROMLOW_SIZE	0x800000
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLLOW_EXEC_BASE	(CFG_CMA_MB_BASE+0xe000000)
+#define CMA_MB_FLLOW_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe000000)
 #define CMA_MB_FLLOW_EXEC_SIZE	0x100000
-#define CMA_MB_FLLOW_RDWR_BASE	(CFG_CMA_MB_BASE+0xe400000)
+#define CMA_MB_FLLOW_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe400000)
 #define CMA_MB_FLLOW_RDWR_SIZE	0x400000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_RTC)
-#define CMA_MB_RTC_BASE		(CFG_CMA_MB_BASE+0xe800000)
+#define CMA_MB_RTC_BASE		(CONFIG_SYS_CMA_MB_BASE+0xe800000)
 #define CMA_MB_RTC_SIZE		0x4000
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SERPAR)
-#define CMA_MB_SERPAR_BASE	(CFG_CMA_MB_BASE+0xe900000)
+#define CMA_MB_SERPAR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900000)
 #define   CMA_MB_SERIALB_BASE	  (CMA_MB_SERPAR_BASE+0x00)
 #define   CMA_MB_SERIALA_BASE	  (CMA_MB_SERPAR_BASE+0x40)
 #define   CMA_MB_PARALLEL_BASE	  (CMA_MB_SERPAR_BASE+0x80)
@@ -121,20 +121,20 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_KBM)
-#define CMA_MB_PKBM_BASE	(CFG_CMA_MB_BASE+0xe900100)
+#define CMA_MB_PKBM_BASE	(CONFIG_SYS_CMA_MB_BASE+0xe900100)
 #define CMA_MB_PKBM_SIZE	0x10
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_LCD)
-#define CMA_MB_LCD_BASE		(CFG_CMA_MB_BASE+0xeb00000)
+#define CMA_MB_LCD_BASE		(CONFIG_SYS_CMA_MB_BASE+0xeb00000)
 #define CMA_MB_LCD_SIZE		0x10
 #endif
 
-#define CMA_MB_DIPSW_BASE	(CFG_CMA_MB_BASE+0xec00000)
+#define CMA_MB_DIPSW_BASE	(CONFIG_SYS_CMA_MB_BASE+0xec00000)
 #define CMA_MB_DIPSW_SIZE	0x10
 
 #if (CMA_MB_CAPS & (CMA_MB_CAP_SLOT1|CMA_MB_CAP_SER2|CMA_MB_CAP_KBM))
-#define CMA_MB_SLOT1CFG_BASE	(CFG_CMA_MB_BASE+0xf100000)
+#define CMA_MB_SLOT1CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf100000)
 #if (CMA_MB_CAPS & CMA_MB_CAP_SER2)
 #define   CMA_MB_SER2_BASE	  (CMA_MB_SLOT1CFG_BASE+0x80)
 #define     CMA_MB_SER2B_BASE	    (CMA_MB_SER2_BASE+0x00)
@@ -152,7 +152,7 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT2)
-#define CMA_MB_SLOT2CFG_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#define CMA_MB_SLOT2CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
 #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT2)
 #define   CMA_MB_S2KBM_BASE	  (CMA_MB_SLOT2CFG_BASE+0x200)
 #endif
@@ -160,7 +160,7 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_PCI)
-#define CMA_MB_PCICTL_BASE	(CFG_CMA_MB_BASE+0xf200000)
+#define CMA_MB_PCICTL_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf200000)
 #define   CMA_MB_PCI_V3CTL_BASE	  (CMA_MB_PCICTL_BASE+0x100)
 #define   CMA_MB_PCI_IDSEL_BASE	  (CMA_MB_PCICTL_BASE+0x200)
 #define   CMA_MB_PCI_IMASK_BASE	  (CMA_MB_PCICTL_BASE+0x300)
@@ -171,19 +171,19 @@
 #endif
 
 #if (CMA_MB_CAPS & CMA_MB_CAP_SLOT3)
-#define CMA_MB_SLOT3CFG_BASE	(CFG_CMA_MB_BASE+0xf300000)
+#define CMA_MB_SLOT3CFG_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf300000)
 #if defined(CONFIG_CMA302) && defined(CONFIG_CMA302_SLOT3)
 #define   CMA_MB_S3KBM_BASE	  (CMA_MB_SLOT3CFG_BASE+0x200)
 #endif
 #define CMA_MB_SLOT3CFG_SIZE	0x400
 #endif
 
-#define CMA_MB_ROMHIGH_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_ROMHIGH_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
 #define CMA_MB_ROMHIGH_SIZE	0x800000
 #if (CMA_MB_CAPS & CMA_MB_CAP_FLASH)
-#define CMA_MB_FLHIGH_EXEC_BASE	(CFG_CMA_MB_BASE+0xf800000)
+#define CMA_MB_FLHIGH_EXEC_BASE	(CONFIG_SYS_CMA_MB_BASE+0xf800000)
 #define CMA_MB_FLHIGH_EXEC_SIZE	0x100000
-#define CMA_MB_FLHIGH_RDWR_BASE	(CFG_CMA_MB_BASE+0xfc00000)
+#define CMA_MB_FLHIGH_RDWR_BASE	(CONFIG_SYS_CMA_MB_BASE+0xfc00000)
 #define CMA_MB_FLHIGH_RDWR_SIZE	0x400000
 #endif
 
diff --git a/board/cpc45/cpc45.c b/board/cpc45/cpc45.c
index 16ead75..1178822 100644
--- a/board/cpc45/cpc45.c
+++ b/board/cpc45/cpc45.c
@@ -72,7 +72,7 @@
 	uint8_t mber = 0;
 	unsigned int tmp;
 
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	if (i2c_reg_read (0x50, 2) != 0x04)
 		return 0;	/* Memory type */
@@ -89,7 +89,7 @@
 	CONFIG_READ_WORD(MCCR2, mccr2);
 	mccr2 &= 0xffff0000;
 
-	start = CFG_SDRAM_BASE;
+	start = CONFIG_SYS_SDRAM_BASE;
 	end = start + (1 << (col + row + 3) ) * bank - 1;
 
 	for (i = 0; i < m; i++) {
@@ -243,8 +243,8 @@
 
 #if defined(CONFIG_CMD_PCMCIA)
 
-#ifdef CFG_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
 #endif
 
 int pcmcia_init(void)
diff --git a/board/cpc45/flash.c b/board/cpc45/flash.c
index 3826a54..8fe7584 100644
--- a/board/cpc45/flash.c
+++ b/board/cpc45/flash.c
@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -41,7 +41,7 @@
 #define MAIN_SECT_SIZE  0x40000
 #define PARAM_SECT_SIZE 0x8000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static int write_data (flash_info_t * info, ulong dest, ulong * data);
 static void write_via_fpu (vu_long * addr, ulong * data);
@@ -81,8 +81,8 @@
 
 	__asm__ volatile ("sync\n eieio");
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
 
 		addr[0] = 0x00900090;
 
@@ -124,17 +124,17 @@
 		addr[0] = 0xFFFFFFFF;
 
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		for (j = 0; j < flash_info[i].sector_count; j++) {
 			if (j > 30) {
-				flash_info[i].start[j] = CFG_FLASH_BASE +
+				flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
 					i * FLASH_BANK_SIZE +
 					(MAIN_SECT_SIZE * 31) + (j -
 								 31) *
 					PARAM_SECT_SIZE;
 			} else {
-				flash_info[i].start[j] = CFG_FLASH_BASE +
+				flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
 					i * FLASH_BANK_SIZE +
 					j * MAIN_SECT_SIZE;
 			}
@@ -162,20 +162,20 @@
 
 	/* Protect monitor and environment sectors
 	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		       &flash_info[1]);
 #else
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR,
 		       CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
@@ -309,7 +309,7 @@
 			while (((addr[0] & 0x00800080) != 0x00800080) ||
 			       ((addr[1] & 0x00800080) != 0x00800080)) {
 				if ((now = get_timer (start)) >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					addr[0] = 0x00B000B0;	/* suspend erase */
 					addr[0] = 0x00FF00FF;	/* to read mode  */
@@ -486,7 +486,7 @@
 
 	while (((addr[0] & 0x00800080) != 0x00800080) ||
 	       ((addr[1] & 0x00800080) != 0x00800080)) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			addr[0] = 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/cpc45/pd67290.c b/board/cpc45/pd67290.c
index d8f4be5..12c9c74 100644
--- a/board/cpc45/pd67290.c
+++ b/board/cpc45/pd67290.c
@@ -699,16 +699,16 @@
 	mem.map = 0;
 	mem.flags = MAP_ATTRIB | MAP_ACTIVE;
 	mem.speed = 300;
-	mem.sys_start = CFG_PCMCIA_MEM_ADDR;
-	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE - 1;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE - 1;
 	mem.card_start = 0;
 	i365_set_mem_map (&socket, &mem);
 
 	mem.map = 1;
 	mem.flags = MAP_ACTIVE;
 	mem.speed = 300;
-	mem.sys_start = CFG_PCMCIA_MEM_ADDR + CFG_PCMCIA_MEM_SIZE;
-	mem.sys_stop = CFG_PCMCIA_MEM_ADDR + (2 * CFG_PCMCIA_MEM_SIZE) - 1;
+	mem.sys_start = CONFIG_SYS_PCMCIA_MEM_ADDR + CONFIG_SYS_PCMCIA_MEM_SIZE;
+	mem.sys_stop = CONFIG_SYS_PCMCIA_MEM_ADDR + (2 * CONFIG_SYS_PCMCIA_MEM_SIZE) - 1;
 	mem.card_start = 0;
 	i365_set_mem_map (&socket, &mem);
 
@@ -794,8 +794,8 @@
 {
 	u_int tmp[2];
 	u_int *mem = (void *) socket.cb_phys;
-	u_char *cis = (void *) CFG_PCMCIA_MEM_ADDR;
-	u_char *ide = (void *) (CFG_ATA_BASE_ADDR + CFG_ATA_REG_OFFSET);
+	u_char *cis = (void *) CONFIG_SYS_PCMCIA_MEM_ADDR;
+	u_char *ide = (void *) (CONFIG_SYS_ATA_BASE_ADDR + CONFIG_SYS_ATA_REG_OFFSET);
 
 	pci_read_config_dword (dev, 0x00, tmp + 0);
 	pci_read_config_dword (dev, 0x80, tmp + 1);
diff --git a/board/cpu86/config.mk b/board/cpu86/config.mk
index 00354c4..5fe0ca0 100644
--- a/board/cpu86/config.mk
+++ b/board/cpu86/config.mk
@@ -25,7 +25,7 @@
 # CPU86 boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_CPU86.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_CPU86.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/cpu86/cpu86.c b/board/cpu86/cpu86.c
index 23ec283..bc7ebfe 100644
--- a/board/cpu86/cpu86.c
+++ b/board/cpu86/cpu86.c
@@ -225,7 +225,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -250,7 +250,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -261,7 +261,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -275,37 +275,37 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9;
 #endif
 	long psize;
 
 	psize = 32 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL) ");
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	}
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -315,6 +315,6 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
diff --git a/board/cpu86/cpu86.h b/board/cpu86/cpu86.h
index cf7852c..ca0c39f 100644
--- a/board/cpu86/cpu86.h
+++ b/board/cpu86/cpu86.h
@@ -6,19 +6,19 @@
 #define REG8(x)			(*(volatile unsigned char *)(x))
 
 /* CPU86 register definitions */
-#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
-#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
-#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
 
 /* Board Control Register bits */
 #define CPU86_BCR_FWPT		0x01
diff --git a/board/cpu86/flash.c b/board/cpu86/flash.c
index 845a3b2..8135780 100644
--- a/board/cpu86/flash.c
+++ b/board/cpu86/flash.c
@@ -28,7 +28,7 @@
 #include <mpc8xx.h>
 #include "cpu86.h"
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -177,7 +177,7 @@
 
 	/* Init: no FLASHes known
 	 */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -186,8 +186,8 @@
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
-	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
 
 	if (size_b0 > 0 || size_b1 > 0) {
 
@@ -210,22 +210,22 @@
 	/* protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
-		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
 		 * but we shouldn't protect it.
 		 */
 
 		flash_protect  (FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
 		);
 	}
 #else
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 #endif
 #endif
@@ -234,7 +234,7 @@
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
 # endif
-# if CONFIG_ENV_ADDR >= CFG_BOOTROM_BASE
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
 		flash_protect (FLAG_PROTECT_SET,
 				CONFIG_ENV_ADDR,
@@ -382,7 +382,7 @@
 		last  = start;
 		addr = (vu_char *)(info->start[l_sect]);
 		while ((addr[0] & 0x80) != 0x80) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -434,7 +434,7 @@
 				last = start;
 				while ((addr[0] & 0x00800080) != 0x00800080 ||
 				   (addr[1] & 0x00800080) != 0x00800080) {
-					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 						printf ("Timeout (erase suspended!)\n");
 						/* Suspend erase
 						 */
@@ -549,7 +549,7 @@
 
 	start = get_timer (0);
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			/* Suspend program
 			 */
 			*addr = 0x00B000B0;
@@ -604,7 +604,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/cpu87/config.mk b/board/cpu87/config.mk
index 6384c78..6a694a4 100644
--- a/board/cpu87/config.mk
+++ b/board/cpu87/config.mk
@@ -25,7 +25,7 @@
 # CPU87 board
 #
 
-# This should be equal to the CFG_FLASH_BASE define in configs/cpu87.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in configs/cpu87.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/cpu87/cpu87.c b/board/cpu87/cpu87.c
index c7a96f9..057a34c 100644
--- a/board/cpu87/cpu87.c
+++ b/board/cpu87/cpu87.c
@@ -227,7 +227,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = &memctl->memc_psdmr;
@@ -252,7 +252,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -263,7 +263,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -277,45 +277,45 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9, size10;
 #endif
 	long psize;
 
 	psize = 32 * 1024 * 1024;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
-	size10 = try_init (memctl, CFG_PSDMR_10COL, CFG_OR2_10COL,
-			  (uchar *) CFG_SDRAM_BASE);
+	size10 = try_init (memctl, CONFIG_SYS_PSDMR_10COL, CONFIG_SYS_OR2_10COL,
+			  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	psize = max(size8,max(size9,size10));
 
 	if (psize == size8) {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	} else if (psize == size9){
-		psize = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-				  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+				  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:9COL) ");
 	} else
 		printf ("(60x:10COL) ");
 
-#endif	/* CFG_RAMBOOT */
+#endif	/* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -325,7 +325,7 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/cpu87/cpu87.h b/board/cpu87/cpu87.h
index 5dbd4ae..45cb853 100644
--- a/board/cpu87/cpu87.h
+++ b/board/cpu87/cpu87.h
@@ -6,19 +6,19 @@
 #define REG8(x)			(*(volatile unsigned char *)(x))
 
 /* CPU86 register definitions */
-#define CPU86_VME_EAC		REG8(CFG_BCRS_BASE + 0x00)
-#define CPU86_VME_SAC		REG8(CFG_BCRS_BASE + 0x01)
-#define CPU86_VME_MAC		REG8(CFG_BCRS_BASE + 0x02)
-#define CPU86_BCR		REG8(CFG_BCRS_BASE + 0x03)
-#define CPU86_BSR		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_WDOG_RPORT	REG8(CFG_BCRS_BASE + 0x05)
-#define CPU86_MBOX_IRQ		REG8(CFG_BCRS_BASE + 0x04)
-#define CPU86_REV		REG8(CFG_BCRS_BASE + 0x07)
-#define CPU86_VME_IRQMASK	REG8(CFG_BCRS_BASE + 0x80)
-#define CPU86_VME_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x81)
-#define CPU86_LOCAL_IRQMASK	REG8(CFG_BCRS_BASE + 0x82)
-#define CPU86_LOCAL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x83)
-#define CPU86_PMCL_IRQSTATUS	REG8(CFG_BCRS_BASE + 0x84)
+#define CPU86_VME_EAC		REG8(CONFIG_SYS_BCRS_BASE + 0x00)
+#define CPU86_VME_SAC		REG8(CONFIG_SYS_BCRS_BASE + 0x01)
+#define CPU86_VME_MAC		REG8(CONFIG_SYS_BCRS_BASE + 0x02)
+#define CPU86_BCR		REG8(CONFIG_SYS_BCRS_BASE + 0x03)
+#define CPU86_BSR		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_WDOG_RPORT	REG8(CONFIG_SYS_BCRS_BASE + 0x05)
+#define CPU86_MBOX_IRQ		REG8(CONFIG_SYS_BCRS_BASE + 0x04)
+#define CPU86_REV		REG8(CONFIG_SYS_BCRS_BASE + 0x07)
+#define CPU86_VME_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x80)
+#define CPU86_VME_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x81)
+#define CPU86_LOCAL_IRQMASK	REG8(CONFIG_SYS_BCRS_BASE + 0x82)
+#define CPU86_LOCAL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x83)
+#define CPU86_PMCL_IRQSTATUS	REG8(CONFIG_SYS_BCRS_BASE + 0x84)
 
 /* Board Control Register bits */
 #define CPU86_BCR_FWPT		0x01
diff --git a/board/cpu87/flash.c b/board/cpu87/flash.c
index f7e121f..c35757b 100644
--- a/board/cpu87/flash.c
+++ b/board/cpu87/flash.c
@@ -28,7 +28,7 @@
 #include <mpc8xx.h>
 #include "cpu87.h"
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -183,7 +183,7 @@
 
 	/* Init: no FLASHes known
 	 */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -192,8 +192,8 @@
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_int_get_size ((ulong *) CFG_FLASH_BASE, &flash_info[0]);
-	size_b1 = flash_amd_get_size ((uchar *) CFG_BOOTROM_BASE, &flash_info[1]);
+	size_b0 = flash_int_get_size ((ulong *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	size_b1 = flash_amd_get_size ((uchar *) CONFIG_SYS_BOOTROM_BASE, &flash_info[1]);
 
 	if (size_b0 > 0 || size_b1 > 0) {
 
@@ -216,22 +216,22 @@
 	/* protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_BOOTROM_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
-		/* If U-Boot is booted from ROM the CFG_MONITOR_BASE > CFG_FLASH_BASE
+		/* If U-Boot is booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH_BASE
 		 * but we shouldn't protect it.
 		 */
 
 		flash_protect  (FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[1]
 		);
 	}
 #else
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 #endif
 #endif
@@ -240,7 +240,7 @@
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
 # endif
-# if CONFIG_ENV_ADDR >= CFG_BOOTROM_BASE
+# if CONFIG_ENV_ADDR >= CONFIG_SYS_BOOTROM_BASE
 	if (size_b1) {
 		flash_protect (FLAG_PROTECT_SET,
 				CONFIG_ENV_ADDR,
@@ -391,7 +391,7 @@
 		last  = start;
 		addr = (vu_char *)(info->start[l_sect]);
 		while ((addr[0] & 0x80) != 0x80) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -443,7 +443,7 @@
 				last = start;
 				while ((addr[0] & 0x00800080) != 0x00800080 ||
 				   (addr[1] & 0x00800080) != 0x00800080) {
-					if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+					if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 						printf ("Timeout (erase suspended!)\n");
 						/* Suspend erase
 						 */
@@ -558,7 +558,7 @@
 
 	start = get_timer (0);
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			/* Suspend program
 			 */
 			*addr = 0x00B000B0;
@@ -613,7 +613,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/cradle/flash.c b/board/cradle/flash.c
index 4783d92..b5635fb 100644
--- a/board/cradle/flash.c
+++ b/board/cradle/flash.c
@@ -30,7 +30,7 @@
 #define FLASH_BANK_SIZE 0x400000
 #define MAIN_SECT_SIZE  0x20000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -41,15 +41,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT & FLASH_VENDMASK) |
 			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		switch (i) {
 		case 0:
 			flashbase = PHYS_FLASH_1;
@@ -71,8 +71,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -88,7 +88,7 @@
 {
 	int i, j;
 
-	for (j = 0; j < CFG_MAX_FLASH_BANKS; j++) {
+	for (j = 0; j < CONFIG_SYS_MAX_FLASH_BANKS; j++) {
 		switch (info->flash_id & FLASH_VENDMASK) {
 		case (INTEL_MANUFACT & FLASH_VENDMASK):
 			printf ("Intel: ");
@@ -183,7 +183,7 @@
 
 			while ((*addr & 0x80) != 0x80) {
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0xB0;	/* suspend erase */
 					*addr = 0xFF;	/* reset to read mode */
 					rc = ERR_TIMOUT;
@@ -250,7 +250,7 @@
 
 	/* wait while polling the status register */
 	while (((val = *addr) & 0x80) != 0x80) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
 			/* suspend program command */
 			*addr = 0xB0;
diff --git a/board/cradle/lowlevel_init.S b/board/cradle/lowlevel_init.S
index 2fd307f..6b5cfb9 100644
--- a/board/cradle/lowlevel_init.S
+++ b/board/cradle/lowlevel_init.S
@@ -24,7 +24,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -51,98 +51,98 @@
     /* Set up GPIO pins first */
 
    ldr      r0,   =GPSR0
-   ldr      r1,   =CFG_GPSR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPSR1
-   ldr      r1,   =CFG_GPSR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPSR2
-   ldr      r1,   =CFG_GPSR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPCR0
-   ldr      r1,   =CFG_GPCR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPCR1
-   ldr      r1,   =CFG_GPCR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPCR2
-   ldr      r1,   =CFG_GPCR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GRER0
-   ldr      r1,   =CFG_GRER0_VAL
+   ldr      r1,   =CONFIG_SYS_GRER0_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GRER1
-   ldr      r1,   =CFG_GRER1_VAL
+   ldr      r1,   =CONFIG_SYS_GRER1_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GRER2
-   ldr      r1,   =CFG_GRER2_VAL
+   ldr      r1,   =CONFIG_SYS_GRER2_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GFER0
-   ldr      r1,   =CFG_GFER0_VAL
+   ldr      r1,   =CONFIG_SYS_GFER0_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GFER1
-   ldr      r1,   =CFG_GFER1_VAL
+   ldr      r1,   =CONFIG_SYS_GFER1_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GFER2
-   ldr      r1,   =CFG_GFER2_VAL
+   ldr      r1,   =CONFIG_SYS_GFER2_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPDR0
-   ldr      r1,   =CFG_GPDR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPDR1
-   ldr      r1,   =CFG_GPDR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GPDR2
-   ldr      r1,   =CFG_GPDR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR0_L
-   ldr      r1,   =CFG_GAFR0_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR0_U
-   ldr      r1,   =CFG_GAFR0_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR1_L
-   ldr      r1,   =CFG_GAFR1_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR1_U
-   ldr      r1,   =CFG_GAFR1_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR2_L
-   ldr      r1,   =CFG_GAFR2_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
    str      r1,   [r0]
 
    ldr      r0,   =GAFR2_U
-   ldr      r1,   =CFG_GAFR2_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
    str      r1,   [r0]
 
    /* enable GPIO pins */
    ldr      r0,   =PSSR
-   ldr      r1,   =CFG_PSSR_VAL
+   ldr      r1,   =CONFIG_SYS_PSSR_VAL
    str      r1,   [r0]
 
    SET_LED 1
 
    ldr    r3, =MSC1             /* low - bank 2 Lubbock Registers / SRAM */
-   ldr    r2, =CFG_MSC1_VAL     /* high - bank 3 Ethernet Controller */
+   ldr    r2, =CONFIG_SYS_MSC1_VAL     /* high - bank 3 Ethernet Controller */
    str    r2, [r3]              /* need to set MSC1 before trying to write to the HEX LEDs */
    ldr    r2, [r3]              /* need to read it back to make sure the value latches (see MSC section of manual) */
 
@@ -181,47 +181,47 @@
    @ Step 2a
    @ write msc0, read back to ensure data latches
    @
-   ldr     r2,   =CFG_MSC0_VAL
+   ldr     r2,   =CONFIG_SYS_MSC0_VAL
    str     r2,   [r1, #MSC0_OFFSET]
    ldr     r2,   [r1, #MSC0_OFFSET]
 
    @ write msc1
-   ldr     r2,  =CFG_MSC1_VAL
+   ldr     r2,  =CONFIG_SYS_MSC1_VAL
    str     r2,  [r1, #MSC1_OFFSET]
    ldr     r2,  [r1, #MSC1_OFFSET]
 
    @ write msc2
-   ldr     r2,  =CFG_MSC2_VAL
+   ldr     r2,  =CONFIG_SYS_MSC2_VAL
    str     r2,  [r1, #MSC2_OFFSET]
    ldr     r2,  [r1, #MSC2_OFFSET]
 
    @ Step 2b
    @ write mecr
-   ldr     r2,  =CFG_MECR_VAL
+   ldr     r2,  =CONFIG_SYS_MECR_VAL
    str     r2,  [r1, #MECR_OFFSET]
 
    @ write mcmem0
-   ldr     r2,  =CFG_MCMEM0_VAL
+   ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
    str     r2,  [r1, #MCMEM0_OFFSET]
 
    @ write mcmem1
-   ldr     r2,  =CFG_MCMEM1_VAL
+   ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
    str     r2,  [r1, #MCMEM1_OFFSET]
 
    @ write mcatt0
-   ldr     r2,  =CFG_MCATT0_VAL
+   ldr     r2,  =CONFIG_SYS_MCATT0_VAL
    str     r2,  [r1, #MCATT0_OFFSET]
 
    @ write mcatt1
-   ldr     r2,  =CFG_MCATT1_VAL
+   ldr     r2,  =CONFIG_SYS_MCATT1_VAL
    str     r2,  [r1, #MCATT1_OFFSET]
 
    @ write mcio0
-   ldr     r2,  =CFG_MCIO0_VAL
+   ldr     r2,  =CONFIG_SYS_MCIO0_VAL
    str     r2,  [r1, #MCIO0_OFFSET]
 
    @ write mcio1
-   ldr     r2,  =CFG_MCIO1_VAL
+   ldr     r2,  =CONFIG_SYS_MCIO1_VAL
    str     r2,  [r1, #MCIO1_OFFSET]
 
    /*SET_LED 3 */
@@ -229,14 +229,14 @@
    @ Step 2c
    @ fly-by-dma is defeatured on this part
    @ write flycnfg
-   @ldr     r2,  =CFG_FLYCNFG_VAL
+   @ldr     r2,  =CONFIG_SYS_FLYCNFG_VAL
    @str     r2,  [r1, #FLYCNFG_OFFSET]
 
 /* FIXME Does this sequence really make sense */
 #ifdef REDBOOT_WAY
    @ Step 2d
    @ get the mdrefr settings
-   ldr     r3,  =CFG_MDREFR_VAL
+   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
 
    @ extract DRI field (we need a valid DRI field)
    @
@@ -319,7 +319,7 @@
 #else
    @ Step 2d
    @ get the mdrefr settings
-   ldr     r3,  =CFG_MDREFR_VAL
+   ldr     r3,  =CONFIG_SYS_MDREFR_VAL
 
    @ write back mdrefr
    @
@@ -363,7 +363,7 @@
    @ Step 4d
    @ fetch platform value of mdcnfg
    @
-   ldr     r2,  =CFG_MDCNFG_VAL
+   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 
    @ disable all sdram banks
    @
@@ -400,7 +400,7 @@
    @ Access memory *not yet enabled* for CBR refresh cycles (8)
    @ - CBR is generated for all banks
 
-   ldr     r2, =CFG_DRAM_BASE
+   ldr     r2, =CONFIG_SYS_DRAM_BASE
    str     r2, [r2]
    str     r2, [r2]
    str     r2, [r2]
@@ -430,7 +430,7 @@
    @ Step 4h
    @ write mdmrs
    @
-   ldr     r2,  =CFG_MDMRS_VAL
+   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
    str     r2,  [r1, #MDMRS_OFFSET]
 
    @ Done Memory Init
@@ -449,7 +449,7 @@
 
    @ Set interrupt mask register
    @
-   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r1,  =CONFIG_SYS_ICMR_VAL
    ldr     r2,  =ICMR
    str     r1,  [r2]
 
@@ -465,7 +465,7 @@
 
    @ set core clocks
    @
-   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r2,  =CONFIG_SYS_CCCR_VAL
    ldr     r1,  =CCCR
    str     r2,  [r1]
 
@@ -488,7 +488,7 @@
 	@ Turn on needed clocks
 	@
    ldr     r1,  =CKEN
-   ldr     r2,  =CFG_CKEN_VAL
+   ldr     r2,  =CONFIG_SYS_CKEN_VAL
    str     r2,  [r1]
 
    /*SET_LED 7 */
diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c
index 49a9e5e..2babd2d 100644
--- a/board/cray/L1/L1.c
+++ b/board/cray/L1/L1.c
@@ -139,7 +139,7 @@
 	struct rtc_time tm;
 	char bootcmd[32];
 
-	hdr = (image_header_t *) (CFG_MONITOR_BASE - image_get_header_size ());
+	hdr = (image_header_t *) (CONFIG_SYS_MONITOR_BASE - image_get_header_size ());
 #if defined(CONFIG_FIT)
 	if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) {
 		puts ("Non legacy image format not supported\n");
diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c
index f313274..36d186f 100644
--- a/board/cray/L1/flash.c
+++ b/board/cray/L1/flash.c
@@ -43,7 +43,7 @@
 #define FLASH_AM320B    0x0009
 
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -65,7 +65,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -79,7 +79,7 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1)
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
 	  {
 	    /* Setup offsets */
 	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -253,7 +253,7 @@
 	start = get_timer (0);
     last  = start;
     while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return -1;
 	}
@@ -457,7 +457,7 @@
 	    start = get_timer (0);
 	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
 		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/csb226/flash.c b/board/csb226/flash.c
index 2a60909..02ded1c 100644
--- a/board/csb226/flash.c
+++ b/board/csb226/flash.c
@@ -37,7 +37,7 @@
 #define FLASH_BANK_SIZE 0x02000000
 #define MAIN_SECT_SIZE	0x40000		/* 2x16 = 256k per sector */
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /**
@@ -51,14 +51,14 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT & FLASH_VENDMASK) |
 			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
 		switch (i) {
 		case 0:
@@ -76,8 +76,8 @@
 
 	/* Protect monitor and environment sectors */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect(FLAG_PROTECT_SET,
@@ -97,7 +97,7 @@
 {
 	int i, j;
 
-	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
+	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
 
 		switch (info->flash_id & FLASH_VENDMASK) {
 		case (INTEL_MANUFACT & FLASH_VENDMASK):
@@ -189,7 +189,7 @@
 			*addr = 0x00D000D0;	/* erase confirm */
 
 			while ((*addr & 0x00800080) != 0x00800080) {
-				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0x00B000B0; /* suspend erase*/
 					*addr = 0x00FF00FF; /* read mode    */
 					rc = ERR_TIMOUT;
@@ -251,7 +251,7 @@
 
 	/* wait while polling the status register */
 	while(((val = *addr) & 0x00800080) != 0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
 			/* suspend program command */
 			*addr = 0x00B000B0;
diff --git a/board/csb226/lowlevel_init.S b/board/csb226/lowlevel_init.S
index 4c9f10f..9892430 100644
--- a/board/csb226/lowlevel_init.S
+++ b/board/csb226/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -54,71 +54,71 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 /*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
 /*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
 /*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
 /* */
@@ -168,17 +168,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CFG_MSC0_VAL
+	ldr     r2,   =CONFIG_SYS_MSC0_VAL
 	str     r2,   [r1, #MSC0_OFFSET]
 	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CFG_MSC1_VAL
+	ldr     r2,  =CONFIG_SYS_MSC1_VAL
 	str     r2,  [r1, #MSC1_OFFSET]
 	ldr     r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CFG_MSC2_VAL
+	ldr     r2,  =CONFIG_SYS_MSC2_VAL
 	str     r2,  [r1, #MSC2_OFFSET]
 	ldr     r2,  [r1, #MSC2_OFFSET]
 
@@ -187,37 +187,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CFG_MECR_VAL
+	ldr     r2,  =CONFIG_SYS_MECR_VAL
 	str     r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CFG_MCMEM0_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 	str     r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CFG_MCMEM1_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 	str     r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CFG_MCATT0_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 	str     r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CFG_MCATT1_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 	str     r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CFG_MCIO0_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 	str     r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CFG_MCIO1_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 	str     r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
@@ -239,7 +239,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr	r3,	=CFG_MDREFR_VAL
+	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
@@ -269,7 +269,7 @@
 	/* Step 4a: assert MDREFR:K?RUN and configure                       */
 	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 
-	ldr	r4,	=CFG_MDREFR_VAL
+	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
 	ldr	r4,	[r1, #MDREFR_OFFSET]
 
@@ -292,7 +292,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
 	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -325,7 +325,7 @@
 	/*          Jan 2003, Errata #116, page 30.                         */
 
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2, [r3]
 	str	r2, [r3]
 	str	r2, [r3]
@@ -345,7 +345,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,  =CFG_MDMRS_VAL
+	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 	str     r2,  [r1, #MDMRS_OFFSET]
 
 
diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c
index 5a585ae..11596d2 100644
--- a/board/csb272/csb272.c
+++ b/board/csb272/csb272.c
@@ -51,9 +51,9 @@
  */
 int pll_init(void)
 {
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-	return  i2c_write(CFG_I2C_PLL_ADDR, 0, 1,
+	return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
 		(uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
 }
 
diff --git a/board/csb272/init.S b/board/csb272/init.S
index e00ebf8..ab371f2 100644
--- a/board/csb272/init.S
+++ b/board/csb272/init.S
@@ -82,11 +82,11 @@
 	mflr	r3			/* get address of ..getAddr */
 
 	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
 	mtctr	r4
 ..ebcloop:
 	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
 	bdnz	..ebcloop		/* continue for $CTR cache lines */
 
 	/********************************************************************
diff --git a/board/csb472/init.S b/board/csb472/init.S
index aec42a1..4b6958a 100644
--- a/board/csb472/init.S
+++ b/board/csb472/init.S
@@ -82,11 +82,11 @@
 	mflr	r3			/* get address of ..getAddr */
 
 	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
 	mtctr	r4
 ..ebcloop:
 	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
 	bdnz	..ebcloop		/* continue for $CTR cache lines */
 
 	/********************************************************************
diff --git a/board/cu824/cu824.c b/board/cu824/cu824.c
index 0fd4223..720c56f 100644
--- a/board/cu824/cu824.c
+++ b/board/cu824/cu824.c
@@ -53,7 +53,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
diff --git a/board/cu824/flash.c b/board/cu824/flash.c
index 6fe2978..bd0f8d3 100644
--- a/board/cu824/flash.c
+++ b/board/cu824/flash.c
@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -43,7 +43,7 @@
 
 #define BOARD_CTRL_REG 0xFE800013
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static int write_data (flash_info_t *info, ulong dest, ulong *data);
 static void write_via_fpu(vu_long *addr, ulong *data);
@@ -75,8 +75,8 @@
     *bcr |= 0x6;	/* FWP0 = FWP1 = 1 */
     DEBUGF("Write protect is:  0x%02X\n", *bcr);
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-	vu_long *addr = (vu_long *)(CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+	vu_long *addr = (vu_long *)(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
 
 	addr[0] = 0x00900090;
 
@@ -103,15 +103,15 @@
 	addr[0] = 0xFFFFFFFF;
 
 	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 	for (j = 0; j < flash_info[i].sector_count; j++) {
 		if (j <= 7) {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
+			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
 						 i * FLASH_BANK_SIZE +
 						 j * PARAM_SECT_SIZE;
 		} else {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
+			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
 						 i * FLASH_BANK_SIZE +
 						 (j - 7)*MAIN_SECT_SIZE;
 		}
@@ -121,22 +121,22 @@
 
     /* Protect monitor and environment sectors
      */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
     flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
+	      CONFIG_SYS_MONITOR_BASE,
+	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 	      &flash_info[1]);
 #else
     flash_protect(FLAG_PROTECT_SET,
-	      CFG_MONITOR_BASE,
-	      CFG_MONITOR_BASE + monitor_flash_len - 1,
+	      CONFIG_SYS_MONITOR_BASE,
+	      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 	      &flash_info[0]);
 #endif
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
     flash_protect(FLAG_PROTECT_SET,
 	      CONFIG_ENV_ADDR,
 	      CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1,
@@ -268,7 +268,7 @@
 			while (((addr[0] & 0x00800080) != 0x00800080) ||
 			       ((addr[1] & 0x00800080) != 0x00800080) ) {
 				if ((now=get_timer(start)) >
-					   CFG_FLASH_ERASE_TOUT) {
+					   CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					addr[0] = 0x00B000B0; /* suspend erase */
 					addr[0] = 0x00FF00FF; /* to read mode  */
@@ -452,7 +452,7 @@
 
 	while (((addr[0] & 0x00800080) != 0x00800080) ||
 	       ((addr[1] & 0x00800080) != 0x00800080) ) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			addr[0] = 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/dave/B2/flash.c b/board/dave/B2/flash.c
index ad67e86..bb892e6 100644
--- a/board/dave/B2/flash.c
+++ b/board/dave/B2/flash.c
@@ -41,19 +41,19 @@
 unsigned long flash_init (void)
 {
 #ifdef __DEBUG_START_FROM_SRAM__
-	return CFG_DUMMY_FLASH_SIZE;
+	return CONFIG_SYS_DUMMY_FLASH_SIZE;
 #else
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -65,7 +65,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/dave/PPChameleonEVB/PPChameleonEVB.c b/board/dave/PPChameleonEVB/PPChameleonEVB.c
index c715ad4..a6aa655 100644
--- a/board/dave/PPChameleonEVB/PPChameleonEVB.c
+++ b/board/dave/PPChameleonEVB/PPChameleonEVB.c
@@ -38,8 +38,8 @@
 
 int board_early_init_f (void)
 {
-	out32(GPIO0_OR, CFG_NAND0_CE);                 /* set initial outputs     */
-	out32(GPIO0_OR, CFG_NAND1_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CONFIG_SYS_NAND0_CE);                 /* set initial outputs     */
+	out32(GPIO0_OR, CONFIG_SYS_NAND1_CE);                 /* set initial outputs     */
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -85,10 +85,10 @@
 {
 	/* adjust flash start and size as well as the offset */
 	gd->bd->bi_flashstart = 0 - flash_info[0].size;
-	gd->bd->bi_flashoffset= flash_info[0].size - CFG_MONITOR_LEN;
+	gd->bd->bi_flashoffset= flash_info[0].size - CONFIG_SYS_MONITOR_LEN;
 #if 0
 	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 	volatile unsigned char *duart0_mcr =
 		(unsigned char *)((ulong)DUART0_BA + 4);
 	volatile unsigned char *duart1_mcr =
@@ -103,8 +103,8 @@
 	int i;
 	unsigned long cntrl0Reg;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -168,7 +168,7 @@
 	/*
 	 * Enable power on PS/2 interface
 	 */
-	*fpga_mode |= CFG_FPGA_CTRL_PS2_RESET;
+	*fpga_mode |= CONFIG_SYS_FPGA_CTRL_PS2_RESET;
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c
index 692d275..e5a0d3d 100644
--- a/board/dave/PPChameleonEVB/flash.c
+++ b/board/dave/PPChameleonEVB/flash.c
@@ -42,7 +42,7 @@
 unsigned long flash_init (void)
 {
 #ifdef __DEBUG_START_FROM_SRAM__
-	return CFG_DUMMY_FLASH_SIZE;
+	return CONFIG_SYS_DUMMY_FLASH_SIZE;
 #else
 	unsigned long size;
 	int i;
@@ -54,7 +54,7 @@
 	debug("[%s, %d] flash_info = 0x%08X ...\n", __FUNCTION__, __LINE__, flash_info);
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -102,7 +102,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/dave/PPChameleonEVB/nand.c b/board/dave/PPChameleonEVB/nand.c
index 3ccbf65..14b61a4 100644
--- a/board/dave/PPChameleonEVB/nand.c
+++ b/board/dave/PPChameleonEVB/nand.c
@@ -67,11 +67,11 @@
 
 	/* use the base addr to find out which chip are we dealing with */
 	switch((ulong) this->IO_ADDR_W) {
-	case CFG_NAND0_BASE:
-		rb_gpio_pin = CFG_NAND0_RDY;
+	case CONFIG_SYS_NAND0_BASE:
+		rb_gpio_pin = CONFIG_SYS_NAND0_RDY;
 		break;
-	case CFG_NAND1_BASE:
-		rb_gpio_pin = CFG_NAND1_RDY;
+	case CONFIG_SYS_NAND1_BASE:
+		rb_gpio_pin = CONFIG_SYS_NAND1_RDY;
 		break;
 	default: /* this should never happen */
 		return 0;
diff --git a/board/dave/PPChameleonEVB/u-boot.lds b/board/dave/PPChameleonEVB/u-boot.lds
index e42c76f..ed02cef 100644
--- a/board/dave/PPChameleonEVB/u-boot.lds
+++ b/board/dave/PPChameleonEVB/u-boot.lds
@@ -143,7 +143,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
   . = 0xFFFF8000;
   .ppcenv :
   {
diff --git a/board/dave/common/flash.c b/board/dave/common/flash.c
index bf0f2bf..b6af63b 100644
--- a/board/dave/common/flash.c
+++ b/board/dave/common/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/processor.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -162,7 +162,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		/*
 		 * Check if whole sector is erased
 		 */
@@ -216,30 +216,30 @@
 {
 	short i;
 	short n;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
 
 	debug("[%s, %d] Entering ...\n", __FUNCTION__, __LINE__);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
 
-	value = addr2[CFG_FLASH_READ0];
+	value = addr2[CONFIG_SYS_FLASH_READ0];
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
 	default:
@@ -249,92 +249,92 @@
 		return (0);			/* no or unknown flash	*/
 	}
 
-	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_29W320DT:
 		info->flash_id += FLASH_STMW320DT;
 		info->sector_count = 67;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
 		info->flash_id += FLASH_AMDL322T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
 		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
 		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
 		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
 		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
 		info->size = 0x00800000;  break;	/* => 8 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
 		info->flash_id += FLASH_SST800A;
 		info->sector_count = 16;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
 		info->flash_id += FLASH_SST160A;
 		info->sector_count = 32;
 		info->size = 0x00200000;
@@ -432,19 +432,19 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST)
 		  info->protect[i] = 0;
 		else
-		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
 	}
 
 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 	}
 
 	return (info->size);
@@ -456,8 +456,8 @@
 
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 	int i;
@@ -498,25 +498,25 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
 		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
 			for (i=0; i<50; i++)
 			  udelay(1000);  /* wait 1 ms */
 		    } else {
 			if (sect == s_first) {
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
 			}
-			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 		    }
 		    l_sect = sect;
 		}
@@ -537,9 +537,9 @@
 
 	start = get_timer (0);
 	last  = start;
-	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -552,8 +552,8 @@
 
 DONE:
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -663,9 +663,9 @@
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
 	int i;
@@ -677,11 +677,11 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
 
-	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
 	  {
-	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
 
 	    dest2[i] = data2[i];
 
@@ -691,9 +691,9 @@
 
 	    /* data polling for D7 */
 	    start = get_timer (0);
-	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/dave/common/fpga.c b/board/dave/common/fpga.c
index 5b5b5e9..30bc196 100644
--- a/board/dave/common/fpga.c
+++ b/board/dave/common/fpga.c
@@ -36,12 +36,12 @@
 
 #define MAX_ONES               226
 
-#ifdef CFG_FPGA_PRG
-# define FPGA_PRG              CFG_FPGA_PRG /* FPGA program pin (ppc output)*/
-# define FPGA_CLK              CFG_FPGA_CLK /* FPGA clk pin (ppc output)    */
-# define FPGA_DATA             CFG_FPGA_DATA /* FPGA data pin (ppc output)  */
-# define FPGA_DONE             CFG_FPGA_DONE /* FPGA done pin (ppc input)   */
-# define FPGA_INIT             CFG_FPGA_INIT /* FPGA init pin (ppc input)   */
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG /* FPGA program pin (ppc output)*/
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK /* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA /* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE /* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT /* FPGA init pin (ppc input)   */
 #else
 # define FPGA_PRG              0x04000000  /* FPGA program pin (ppc output) */
 # define FPGA_CLK              0x02000000  /* FPGA clk pin (ppc output)     */
@@ -74,7 +74,7 @@
 	int i, index, len;
 	int count;
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	int j;
 #else
 	unsigned char b;
@@ -89,7 +89,7 @@
 		index += len + 3;
 	}
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/* search for preamble 0xFFFFFFFF */
 	while (1) {
 		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
@@ -167,7 +167,7 @@
 	DBG ("write configuration data into fpga\n");
 	/* write configuration-data into fpga... */
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/*
 	 * Load uncompressed image into fpga
 	 */
@@ -181,7 +181,7 @@
 			fpgadata[i] <<= 1;
 		}
 	}
-#else	/* ! CFG_FPGA_SPARTAN2 */
+#else	/* ! CONFIG_SYS_FPGA_SPARTAN2 */
 	/* send 0xff 0x20 */
 	FPGA_WRITE_1;
 	FPGA_WRITE_1;
@@ -228,7 +228,7 @@
 			FPGA_WRITE_1;
 		}
 	}
-#endif	/* CFG_FPGA_SPARTAN2 */
+#endif	/* CONFIG_SYS_FPGA_SPARTAN2 */
 
 	DBG ("%s, ",
 	     ((in32 (GPIO0_IR) & FPGA_DONE) == 0) ? "NOT DONE" : "DONE");
diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c
index f8f180c..ec0d761 100644
--- a/board/dave/common/pci.c
+++ b/board/dave/common/pci.c
@@ -119,24 +119,24 @@
   /*
    * Configure PLX PCI9054
    */
-  pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
   status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-  pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
 
   /* Check the latency timer for values >= 0x60.
    */
-  pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
   if (timer < 0x60)
     {
-      pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
     }
 
   /* Set I/O base register.
    */
-  pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
-  pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
 
-  pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
 
   if (pci9054_iobase == 0xffffffff)
     {
@@ -149,13 +149,13 @@
 static struct pci_config_table pci9054_config_table[] = {
 #ifndef CONFIG_PCI_PNP
   { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
-    pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
-				 CFG_ETH_IOBASE,
+    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+				 CONFIG_SYS_ETH_IOBASE,
 				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
 #ifdef CONFIG_DASA_SIM
   { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
     pci_dasa_sim_config_pci9054 },
 #endif
 #endif
diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c
index 71a3b87..be709bf 100644
--- a/board/davinci/common/misc.c
+++ b/board/davinci/common/misc.c
@@ -39,7 +39,7 @@
 
 static int dv_get_pllm_output(uint32_t pllm)
 {
-	return (pllm + 1) * (CFG_HZ_CLOCK / 1000000);
+	return (pllm + 1) * (CONFIG_SYS_HZ_CLOCK / 1000000);
 }
 
 void dv_display_clk_infos(void)
@@ -54,9 +54,9 @@
  */
 int dvevm_read_mac_address(uint8_t *buf)
 {
-#ifdef CFG_I2C_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 	/* Read MAC address. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x7F00, CFG_I2C_EEPROM_ADDR_LEN,
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0x7F00, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 		     (uint8_t *) &buf[0], 6))
 		goto i2cerr;
 
@@ -67,9 +67,9 @@
 	return 1; /* Found */
 
 i2cerr:
-	printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
+	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
 err:
-#endif /* CFG_I2C_EEPROM_ADDR */
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR */
 
 	return 0;
 }
diff --git a/board/davinci/common/psc.c b/board/davinci/common/psc.c
index 00dc07c..d538d51 100644
--- a/board/davinci/common/psc.c
+++ b/board/davinci/common/psc.c
@@ -81,7 +81,7 @@
 }
 
 /* If DSPLINK is used, we don't want U-Boot to power on the DSP. */
-#if !defined(CFG_USE_DSPLINK)
+#if !defined(CONFIG_SYS_USE_DSPLINK)
 void dsp_on(void)
 {
 	int i;
@@ -114,4 +114,4 @@
 
 	REG(PSC_GBLCTL) &= ~0x1f;
 }
-#endif /* CFG_USE_DSPLINK */
+#endif /* CONFIG_SYS_USE_DSPLINK */
diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c
index 151f8a9..abf60b3 100644
--- a/board/davinci/dvevm/dvevm.c
+++ b/board/davinci/dvevm/dvevm.c
@@ -53,10 +53,10 @@
 	lpsc_on(DAVINCI_LPSC_TIMER1);
 	lpsc_on(DAVINCI_LPSC_GPIO);
 
-#if !defined(CFG_USE_DSPLINK)
+#if !defined(CONFIG_SYS_USE_DSPLINK)
 	/* Powerup the DSP */
 	dsp_on();
-#endif /* CFG_USE_DSPLINK */
+#endif /* CONFIG_SYS_USE_DSPLINK */
 
 	/* Bringup UART0 out of reset */
 	REG(UART0_PWREMU_MGMT) = 0x0000e003;
diff --git a/board/davinci/schmoogie/schmoogie.c b/board/davinci/schmoogie/schmoogie.c
index 99fd326..3504a2e 100644
--- a/board/davinci/schmoogie/schmoogie.c
+++ b/board/davinci/schmoogie/schmoogie.c
@@ -53,10 +53,10 @@
 	lpsc_on(DAVINCI_LPSC_TIMER1);
 	lpsc_on(DAVINCI_LPSC_GPIO);
 
-#if !defined(CFG_USE_DSPLINK)
+#if !defined(CONFIG_SYS_USE_DSPLINK)
 	/* Powerup the DSP */
 	dsp_on();
-#endif /* CFG_USE_DSPLINK */
+#endif /* CONFIG_SYS_USE_DSPLINK */
 
 	/* Bringup UART0 out of reset */
 	REG(UART0_PWREMU_MGMT) = 0x0000e003;
@@ -125,13 +125,13 @@
 	dv_display_clk_infos();
 
 	/* Set serial number from UID chip */
-	if (i2c_read(CFG_UID_ADDR, 0, 1, buf, 8)) {
-		printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+	if (i2c_read(CONFIG_SYS_UID_ADDR, 0, 1, buf, 8)) {
+		printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
 		forceenv("serial#", "FAILED");
 	} else {
 		if (buf[0] != 0x70) {
 			/* Device Family Code */
-			printf("\nUID @ 0x%02x read FAILED!!!\n", CFG_UID_ADDR);
+			printf("\nUID @ 0x%02x read FAILED!!!\n", CONFIG_SYS_UID_ADDR);
 			forceenv("serial#", "FAILED");
 		}
 	}
@@ -141,7 +141,7 @@
 		tmp[0] = crc_tbl[tmp[0] ^ buf[i]];
 
 	if (tmp[0] != 0) {
-		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CFG_UID_ADDR);
+		printf("\nUID @ 0x%02x - BAD CRC!!!\n", CONFIG_SYS_UID_ADDR);
 		forceenv("serial#", "FAILED");
 	} else {
 		/* CRC OK, set "serial" env variable */
diff --git a/board/davinci/sffsdr/sffsdr.c b/board/davinci/sffsdr/sffsdr.c
index 6e878eb..9296d7b 100644
--- a/board/davinci/sffsdr/sffsdr.c
+++ b/board/davinci/sffsdr/sffsdr.c
@@ -63,10 +63,10 @@
 	lpsc_on(DAVINCI_LPSC_TIMER1);
 	lpsc_on(DAVINCI_LPSC_GPIO);
 
-#if !defined(CFG_USE_DSPLINK)
+#if !defined(CONFIG_SYS_USE_DSPLINK)
 	/* Powerup the DSP */
 	dsp_on();
-#endif /* CFG_USE_DSPLINK */
+#endif /* CONFIG_SYS_USE_DSPLINK */
 
 	/* Bringup UART0 out of reset */
 	REG(UART0_PWREMU_MGMT) = 0x0000e003;
@@ -99,35 +99,35 @@
 	u_int32_t value, mac[2], address;
 
 	/* Read Integrity data structure checkword. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
-		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_CHECKWORD_OFFSET,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 		goto err;
 	if (value != INTEGRITY_CHECKWORD_VALUE)
 		return 0;
 
 	/* Read SYSCFG structure offset. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
-		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, INTEGRITY_SYSCFG_OFFSET,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 		goto err;
 	address = 0x800 + (int) value; /* Address of SYSCFG structure. */
 
 	/* Read NET CONFIG structure offset. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
-		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 		goto err;
 	address = 0x800 + (int) value; /* Address of NET CONFIG structure. */
 	address += 12; /* Address of NET INTERFACE CONFIG structure. */
 
 	/* Read NET INTERFACE CONFIG 2 structure offset. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
-		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &value, 4))
 		goto err;
 	address = 0x800 + 16 + (int) value;	/* Address of NET INTERFACE
 						 * CONFIG 2 structure. */
 
 	/* Read MAC address. */
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, address,
-		     CFG_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, address,
+		     CONFIG_SYS_I2C_EEPROM_ADDR_LEN, (uint8_t *) &mac[0], 8))
 		goto err;
 
 	buf[0] = mac[0] >> 24;
@@ -140,7 +140,7 @@
 	return 1; /* Found */
 
 err:
-	printf("Read from EEPROM @ 0x%02x failed\n", CFG_I2C_EEPROM_ADDR);
+	printf("Read from EEPROM @ 0x%02x failed\n", CONFIG_SYS_I2C_EEPROM_ADDR);
 	return 0;
 }
 
@@ -156,10 +156,10 @@
 	dv_display_clk_infos();
 
 	/* Configure I2C switch (PCA9543) to enable channel 0. */
-	i2cbuf = CFG_I2C_PCA9543_ENABLE_CH0;
-	if (i2c_write(CFG_I2C_PCA9543_ADDR, 0,
-		      CFG_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
-		printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR);
+	i2cbuf = CONFIG_SYS_I2C_PCA9543_ENABLE_CH0;
+	if (i2c_write(CONFIG_SYS_I2C_PCA9543_ADDR, 0,
+		      CONFIG_SYS_I2C_PCA9543_ADDR_LEN, &i2cbuf, 1)) {
+		printf("Write to MUX @ 0x%02x failed\n", CONFIG_SYS_I2C_PCA9543_ADDR);
 		return 1;
 	}
 
diff --git a/board/davinci/sonata/sonata.c b/board/davinci/sonata/sonata.c
index a6fe825..6de9356 100644
--- a/board/davinci/sonata/sonata.c
+++ b/board/davinci/sonata/sonata.c
@@ -52,10 +52,10 @@
 	lpsc_on(DAVINCI_LPSC_TIMER1);
 	lpsc_on(DAVINCI_LPSC_GPIO);
 
-#if !defined(CFG_USE_DSPLINK)
+#if !defined(CONFIG_SYS_USE_DSPLINK)
 	/* Powerup the DSP */
 	dsp_on();
-#endif /* CFG_USE_DSPLINK */
+#endif /* CONFIG_SYS_USE_DSPLINK */
 
 	/* Bringup UART0 out of reset */
 	REG(UART0_PWREMU_MGMT) = 0x0000e003;
diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c
index 629dc31..42756f5 100644
--- a/board/dbau1x00/dbau1x00.c
+++ b/board/dbau1x00/dbau1x00.c
@@ -106,19 +106,19 @@
 	/* We dont need theese unless we run whole pcmcia package */
 	write_one_tlb(20,                 /* index */
 		      0x01ffe000,         /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
 		      0x3C000017,         /* Lo0 */
 		      0x3C200017);        /* Lo1 */
 
 	write_one_tlb(21,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
 #endif	/* 0 */
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
 #endif	/* CONFIG_IDE_PCMCIA */
diff --git a/board/dbau1x00/flash.c b/board/dbau1x00/flash.c
index 3cf29e8..a2fed1d 100644
--- a/board/dbau1x00/flash.c
+++ b/board/dbau1x00/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * flash_init()
diff --git a/board/dbau1x00/lowlevel_init.S b/board/dbau1x00/lowlevel_init.S
index 13e6bfc..842fb76 100644
--- a/board/dbau1x00/lowlevel_init.S
+++ b/board/dbau1x00/lowlevel_init.S
@@ -8,8 +8,8 @@
 #define AU1500_SYS_ADDR		0xB1900000
 #define sys_endian		0x0038
 #define CP0_Config0		$16
-#define CPU_SCALE		((CFG_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
-#define MEM_1MS			((CFG_MHZ) * 1000)
+#define CPU_SCALE		((CONFIG_SYS_MHZ) / 12) /* CPU clock is a multiple of 12 MHz */
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
 
 	.text
 	.set noreorder
diff --git a/board/delta/delta.c b/board/delta/delta.c
index 6e22774..878416f 100644
--- a/board/delta/delta.c
+++ b/board/delta/delta.c
@@ -304,8 +304,8 @@
 	GPCR0 = (1<<17);	/* drive GPIO17 low */
 	GPSR0 = (1<<17);	/* drive GPIO17 high */
 
-#if CFG_DA9030_EXTON_DELAY
-	udelay((unsigned long) CFG_DA9030_EXTON_DELAY);	/* wait for DA9030 */
+#if CONFIG_SYS_DA9030_EXTON_DELAY
+	udelay((unsigned long) CONFIG_SYS_DA9030_EXTON_DELAY);	/* wait for DA9030 */
 #endif
 	GPCR0 = (1<<17);	/* drive GPIO17 low */
 
diff --git a/board/delta/lowlevel_init.S b/board/delta/lowlevel_init.S
index f059db5..eef6318 100644
--- a/board/delta/lowlevel_init.S
+++ b/board/delta/lowlevel_init.S
@@ -24,7 +24,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 .macro wait time
 	ldr		r2, =OSCR
@@ -108,10 +108,10 @@
 	orr		r1, r1, #MDCNFG_DMCEN
 	str		r1, [r0]
 
-#ifndef CFG_SKIP_DRAM_SCRUB
+#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
 	/* scrub/init SDRAM if enabled/present */
-	ldr	r8, =CFG_DRAM_BASE	/* base address of SDRAM (CFG_DRAM_BASE) */
-	ldr	r9, =CFG_DRAM_SIZE	/* size of memory to scrub (CFG_DRAM_SIZE) */
+	ldr	r8, =CONFIG_SYS_DRAM_BASE	/* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
+	ldr	r9, =CONFIG_SYS_DRAM_SIZE	/* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
 	mov	r0, #0			/* scrub with 0x0000:0000 */
 	mov	r1, #0
 	mov	r2, #0
@@ -125,7 +125,7 @@
 	stmia	r8!, {r0-r7}
 	beq	15f
 	b	10b
-#endif /* CFG_SKIP_DRAM_SCRUB */
+#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
 
 15:
 	/* Mask all interrupts */
diff --git a/board/delta/nand.c b/board/delta/nand.c
index ceb798b..14382f5 100644
--- a/board/delta/nand.c
+++ b/board/delta/nand.c
@@ -28,19 +28,19 @@
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
 
-#ifdef CFG_DFC_DEBUG1
+#ifdef CONFIG_SYS_DFC_DEBUG1
 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG1(fmt, args...)
 #endif
 
-#ifdef CFG_DFC_DEBUG2
+#ifdef CONFIG_SYS_DFC_DEBUG2
 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG2(fmt, args...)
 #endif
 
-#ifdef CFG_DFC_DEBUG3
+#ifdef CONFIG_SYS_DFC_DEBUG3
 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG3(fmt, args...)
@@ -206,7 +206,7 @@
 static void dfc_clear_nddb(void)
 {
 	NDCR &= ~NDCR_ND_RUN;
-	wait_us(CFG_NAND_OTHER_TO);
+	wait_us(CONFIG_SYS_NAND_OTHER_TO);
 }
 
 /* wait_event with timeout */
@@ -217,9 +217,9 @@
 	if(!event)
 		return 0xff000000;
 	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+		timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
 	else
-		timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+		timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
 
 	while(1) {
 		ndsr = NDSR;
@@ -242,7 +242,7 @@
 	int retry = 0;
 	unsigned long status;
 
-	while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
 		/* Clear NDSR */
 		NDSR = 0xFFF;
 
@@ -433,8 +433,8 @@
 	/* turn on the NAND Controller Clock (104 MHz @ D0) */
 	CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
 
-#undef CFG_TIMING_TIGHT
-#ifndef CFG_TIMING_TIGHT
+#undef CONFIG_SYS_TIMING_TIGHT
+#ifndef CONFIG_SYS_TIMING_TIGHT
 	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
 		  DFC_MAX_tCH);
 	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
@@ -473,7 +473,7 @@
 		   DFC_MAX_tWHR);
 	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
 		  DFC_MAX_tAR);
-#endif /* CFG_TIMING_TIGHT */
+#endif /* CONFIG_SYS_TIMING_TIGHT */
 
 
 	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);
diff --git a/board/dnp1110/flash.c b/board/dnp1110/flash.c
index 84b820a..c81abc5 100644
--- a/board/dnp1110/flash.c
+++ b/board/dnp1110/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@
    int i;
     ulong size = 0;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	switch (i)
 	{
@@ -83,8 +83,8 @@
     /* Protect monitor and environment sectors
      */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + monitor_flash_len  - 1,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len  - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,
@@ -194,10 +194,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
     }
 
 	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
@@ -267,7 +267,7 @@
 			*addr = (FPW)0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW)0x00B000B0; /* suspend erase	  */
 					*addr = (FPW)0x00FF00FF; /* reset to read mode */
@@ -402,7 +402,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW)0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/eXalion/eXalion.c b/board/eXalion/eXalion.c
index c5dff24..34538c4 100644
--- a/board/eXalion/eXalion.c
+++ b/board/eXalion/eXalion.c
@@ -56,12 +56,12 @@
 phys_size_t initdram (int board_type)
 {
 	int i, cnt;
-	volatile uchar *base = CFG_SDRAM_BASE;
+	volatile uchar *base = CONFIG_SYS_SDRAM_BASE;
 	volatile ulong *addr;
 	ulong save[32];
 	ulong val, ret = 0;
 
-	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+	for (i = 0, cnt = (CONFIG_SYS_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
 	     cnt >>= 1) {
 		addr = (volatile ulong *) base + cnt;
 		save[i++] = *addr;
@@ -77,7 +77,7 @@
 		goto Done;
 	}
 
-	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+	for (cnt = 1; cnt <= CONFIG_SYS_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
 		addr = (volatile ulong *) base + cnt;
 		val = *addr;
 		*addr = save[--i];
@@ -100,7 +100,7 @@
 		}
 	}
 
-	ret = CFG_MAX_RAM_SIZE;
+	ret = CONFIG_SYS_MAX_RAM_SIZE;
       Done:
 	return ret;
 }
diff --git a/board/earthlcd/favr-32-ezkit/flash.c b/board/earthlcd/favr-32-ezkit/flash.c
index 2aa9415..5f73ff0 100644
--- a/board/earthlcd/favr-32-ezkit/flash.c
+++ b/board/earthlcd/favr-32-ezkit/flash.c
@@ -53,17 +53,17 @@
 	unsigned long addr;
 	unsigned int i;
 
-	flash_info[0].size = CFG_FLASH_SIZE;
+	flash_info[0].size = CONFIG_SYS_FLASH_SIZE;
 	flash_info[0].sector_count = 135;
 
-	flash_identify(uncached((void *)CFG_FLASH_BASE), &flash_info[0]);
+	flash_identify(uncached((void *)CONFIG_SYS_FLASH_BASE), &flash_info[0]);
 
 	for (i = 0, addr = 0; i < 8; i++, addr += 0x2000)
 		flash_info[0].start[i] = addr;
 	for (; i < flash_info[0].sector_count; i++, addr += 0x10000)
 		flash_info[0].start[i] = addr;
 
-	return CFG_FLASH_SIZE;
+	return CONFIG_SYS_FLASH_SIZE;
 }
 
 void flash_print_info(flash_info_t *info)
diff --git a/board/eltec/bab7xx/asm_init.S b/board/eltec/bab7xx/asm_init.S
index 2a9b33e..a85fb8b 100644
--- a/board/eltec/bab7xx/asm_init.S
+++ b/board/eltec/bab7xx/asm_init.S
@@ -125,7 +125,7 @@
     lis     r2, 0xfee0
     ori     r2, r2, 0xcfc
 
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
 /*
  * Switch to address map A if necessary.
  */
@@ -835,17 +835,17 @@
 /*
  * Get base addr of ISA I/O space
  */
-    lis     r6, CFG_ISA_IO@h
-    ori     r6, r6, CFG_ISA_IO@l
+    lis     r6, CONFIG_SYS_ISA_IO@h
+    ori     r6, r6, CONFIG_SYS_ISA_IO@l
 
 /*
  * Set offset to base address for config registers.
  */
-#if defined(CFG_NS87308_BADDR_0x)
+#if defined(CONFIG_SYS_NS87308_BADDR_0x)
     addi    r4, r0, 0x0279
-#elif defined(CFG_NS87308_BADDR_10)
+#elif defined(CONFIG_SYS_NS87308_BADDR_10)
     addi    r4, r0, 0x015C
-#elif defined(CFG_NS87308_BADDR_11)
+#elif defined(CONFIG_SYS_NS87308_BADDR_11)
     addi    r4, r0, 0x002E
 #endif
     add     r6, r6, r4          /* add offset to base */
@@ -867,7 +867,7 @@
     addi    r5, r0, SIO_LUNENABLE
     bl      .sio_bw
 
-    lis     r8, CFG_ISA_IO@h
+    lis     r8, CONFIG_SYS_ISA_IO@h
     ori     r8, r8, 0x0460
     li      r9, 0x03
     stb     r9, 0(r8)               /* select PMC2 register */
@@ -898,7 +898,7 @@
 /*
  * Init COM1 for polled output
  */
-    lis     r8, CFG_ISA_IO@h
+    lis     r8, CONFIG_SYS_ISA_IO@h
     ori     r8, r8, 0x03f8
     li      r9, 0x00
     stb     r9, 1(r8)           /* int disabled */
@@ -972,8 +972,8 @@
 /*
  * Get base addr of ISA I/O space
  */
-    lis     r3, CFG_ISA_IO@h
-    ori     r3, r3, CFG_ISA_IO@l
+    lis     r3, CONFIG_SYS_ISA_IO@h
+    ori     r3, r3, CONFIG_SYS_ISA_IO@l
 
     addi    r3, r3, 0x015C      /* adjust to superI/O 87308 base */
     or      r6, r3, r3          /* make a copy */
@@ -1076,7 +1076,7 @@
  */
 .globl Printf
 Printf:
-    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
     ori     r10, r10, 0x03f8
 
 WaitChr:
@@ -1107,7 +1107,7 @@
 OutHex:
     li      r9, 28              /* shift reg for 8 digits */
 OHstart:
-    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
     ori     r10, r10, 0x03f8
 OutDig:
     lbz     r0, 5(r10)          /* read link status */
@@ -1149,7 +1149,7 @@
     mullw   r10, r0, r6
     subf    r7, r10, r3
 
-    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
     ori     r10, r10, 0x03f8
 
     or.     r7, r7, r7
@@ -1198,7 +1198,7 @@
  */
 .globl    OutChr
 OutChr:
-    lis     r10, CFG_ISA_IO@h   /* COM1 port */
+    lis     r10, CONFIG_SYS_ISA_IO@h   /* COM1 port */
     ori     r10, r10, 0x03f8
 
 OutChr1:
@@ -1216,7 +1216,7 @@
 spdRead:
     mfspr   r26, 8              /* save link register */
 
-    lis     r30, CFG_ISA_IO@h
+    lis     r30, CONFIG_SYS_ISA_IO@h
     ori     r30, r30, 0x220     /* GPIO Port 1 */
     li      r7, 0x00
     li      r8, 0x100
diff --git a/board/eltec/bab7xx/bab7xx.c b/board/eltec/bab7xx/bab7xx.c
index 8c56116..1f78f8d 100644
--- a/board/eltec/bab7xx/bab7xx.c
+++ b/board/eltec/bab7xx/bab7xx.c
@@ -44,7 +44,7 @@
 	 * The GPIO Port 1 on BAB7xx reflects the bus speed.
 	 */
 	volatile struct GPIO *gpio =
-		(struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
+		(struct GPIO *) (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_GPIO_BASE);
 
 	unsigned char data = gpio->dta1;
 
@@ -87,7 +87,7 @@
 
 int checkboard (void)
 {
-#ifdef CFG_ADDRESS_MAP_A
+#ifdef CONFIG_SYS_ADDRESS_MAP_A
 	puts ("Board: ELTEC BAB7xx PReP\n");
 #else
 	puts ("Board: ELTEC BAB7xx CHRP\n");
@@ -126,16 +126,16 @@
 
 	register unsigned long i, msar1, mear1, memSize;
 
-#if defined(CFG_MEMTEST)
+#if defined(CONFIG_SYS_MEMTEST)
 	register unsigned long reg;
 
 	printf ("Testing DRAM\n");
 
 	/* write each mem addr with it's address */
-	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
 		*reg = reg;
 
-	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
 		if (*reg != reg)
 			return -1;
 	}
diff --git a/board/eltec/bab7xx/flash.c b/board/eltec/bab7xx/flash.c
index 442dd00..21ae098 100644
--- a/board/eltec/bab7xx/flash.c
+++ b/board/eltec/bab7xx/flash.c
@@ -34,7 +34,7 @@
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size (vu_long *addr, flash_info_t *info);
 static int write_word (flash_info_t *info, ulong dest, ulong data);
@@ -55,7 +55,7 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
@@ -96,8 +96,8 @@
     if (size2 == 4*1024*1024)
     {
 	(void)flash_protect(FLAG_PROTECT_SET,
-		CFG_FLASH_BASE,
-		CFG_FLASH_BASE+monitor_flash_len-1,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
 		&flash_info[1]);
     }
 
@@ -370,7 +370,7 @@
     last  = start;
     addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
     while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -500,7 +500,7 @@
 	    start = get_timer (0);
 	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
 		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/eltec/bab7xx/l2cache.c b/board/eltec/bab7xx/l2cache.c
index 1e75377..787704f 100644
--- a/board/eltec/bab7xx/l2cache.c
+++ b/board/eltec/bab7xx/l2cache.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#if defined(CFG_L2_BAB7xx)
+#if defined(CONFIG_SYS_L2_BAB7xx)
 
 #include <pci.h>
 #include <mpc106.h>
@@ -77,7 +77,7 @@
 	pci_write_config_dword (devbusfn, PCI_PICR2, reg32);
 
 	/* cache size */
-	if (*(volatile unsigned char *) (CFG_ISA_IO + 0x220) & 0x04)
+	if (*(volatile unsigned char *) (CONFIG_SYS_ISA_IO + 0x220) & 0x04)
 	{
 	    /* cache size is 512 KB */
 	    picr2CacheSize = PICR2_L2_SIZE_512K;
@@ -156,4 +156,4 @@
 
 /*----------------------------------------------------------------------------*/
 
-#endif /* (CFG_L2_BAB7xx) */
+#endif /* (CONFIG_SYS_L2_BAB7xx) */
diff --git a/board/eltec/bab7xx/misc.c b/board/eltec/bab7xx/misc.c
index 6a24807..1c94a76 100644
--- a/board/eltec/bab7xx/misc.c
+++ b/board/eltec/bab7xx/misc.c
@@ -31,7 +31,7 @@
 #include "srom.h"
 
 /* imports  */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
 extern int l2_cache_enable (int l2control);
 extern void *nvram_read (void *dest, const short src, size_t count);
 extern void nvram_write (short dest, const void *src, size_t count);
@@ -134,7 +134,7 @@
 		SECOND_DEVICE, FIRST_BLOCK);
 
     /* read out current nvram shadow image */
-    nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+    nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
 
     if (strcmp (eerev.magic, "ELTEC") != 0)
     {
@@ -162,8 +162,8 @@
 	copyNv   = 1;  /* copy to nvram */
     }
 
-    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CFG_SROM_SIZE) !=
-		el_srom_checksum((u_char*)buf, CFG_SROM_SIZE)))
+    if ((copyNv == 0) &&   (el_srom_checksum((u_char*)&eerev, CONFIG_SYS_SROM_SIZE) !=
+		el_srom_checksum((u_char*)buf, CONFIG_SYS_SROM_SIZE)))
     {
 	printf ("Invalid revision info copy in nvram !\n");
 	printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
@@ -304,13 +304,13 @@
 	    printf("OK\n\n");
 
 	/* write new values as shadow image to nvram */
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+	nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
 
     } /*if (initSrom) */
 
     /* copy current values as shadow image to nvram */
     if (initSrom == 0 && copyNv == 1)
-	nvram_write (CFG_NV_SROM_COPY_ADDR, (void *)&eerev, CFG_SROM_SIZE);
+	nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *)&eerev, CONFIG_SYS_SROM_SIZE);
 
     /* update environment */
     sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
@@ -333,7 +333,7 @@
    /*
     * L2 cache configuration
     */
-#if defined(CFG_L2_BAB7xx)
+#if defined(CONFIG_SYS_L2_BAB7xx)
     ptr = getenv("l2cache");
     if (*ptr == '0')
     {
diff --git a/board/eltec/bab7xx/pci.c b/board/eltec/bab7xx/pci.c
index edbd3dd..46e5a8b 100644
--- a/board/eltec/bab7xx/pci.c
+++ b/board/eltec/bab7xx/pci.c
@@ -43,41 +43,41 @@
     hose->last_busno = 0xff;
 
     pci_set_region(hose->regions + 0,
-	CFG_PCI_MEMORY_BUS,
-	CFG_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
     /*
     * Attention: pci_hose_phys_to_bus() failes in address compare,
-    * so we need (CFG_PCI_MEMORY_SIZE-1)
+    * so we need (CONFIG_SYS_PCI_MEMORY_SIZE-1)
     */
-	CFG_PCI_MEMORY_SIZE-1,
+	CONFIG_SYS_PCI_MEMORY_SIZE-1,
 	PCI_REGION_MEM | PCI_REGION_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
-	CFG_PCI_MEM_BUS,
-	CFG_PCI_MEM_PHYS,
-	CFG_PCI_MEM_SIZE,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* ISA/PCI memory space */
     pci_set_region(hose->regions + 2,
-	CFG_ISA_MEM_BUS,
-	CFG_ISA_MEM_PHYS,
-	CFG_ISA_MEM_SIZE,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* PCI I/O space */
     pci_set_region(hose->regions + 3,
-	CFG_PCI_IO_BUS,
-	CFG_PCI_IO_PHYS,
-	CFG_PCI_IO_SIZE,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
 	PCI_REGION_IO);
 
     /* ISA/PCI I/O space */
     pci_set_region(hose->regions + 4,
-	CFG_ISA_IO_BUS,
-	CFG_ISA_IO_PHYS,
-	CFG_ISA_IO_SIZE,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
 	PCI_REGION_IO);
 
     hose->region_count = 5;
diff --git a/board/eltec/bab7xx/srom.h b/board/eltec/bab7xx/srom.h
index c18ab91..504b742 100644
--- a/board/eltec/bab7xx/srom.h
+++ b/board/eltec/bab7xx/srom.h
@@ -40,8 +40,8 @@
 #define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
 
 /* bab7xx ELTEC srom */
-#define I2C_BUS_DAT             (CFG_ISA_IO + 0x220)
-#define I2C_BUS_DIR             (CFG_ISA_IO + 0x221)
+#define I2C_BUS_DAT             (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CONFIG_SYS_ISA_IO + 0x221)
 
 /* srom at mpc107 */
 #define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
diff --git a/board/eltec/elppc/asm_init.S b/board/eltec/elppc/asm_init.S
index 1b8d399..8cbe9d8 100644
--- a/board/eltec/elppc/asm_init.S
+++ b/board/eltec/elppc/asm_init.S
@@ -272,15 +272,15 @@
  * set LEDs first time
  */
     li      r3, 0x1
-    lis     r30, CFG_USR_LED_BASE@h
+    lis     r30, CONFIG_SYS_USR_LED_BASE@h
     stb     r3, 2(r30)
     sync
 
 /*
  * init COM1 for polled output
  */
-    lis     r8, CFG_NS16550_COM1@h  /* COM1 base address*/
-    ori     r8, r8, CFG_NS16550_COM1@l
+    lis     r8, CONFIG_SYS_NS16550_COM1@h  /* COM1 base address*/
+    ori     r8, r8, CONFIG_SYS_NS16550_COM1@l
     li      r9, 0x00
     stb     r9, 1(r8)           /* int disabled */
     eieio
@@ -290,10 +290,10 @@
     li      r9, 0x80
     stb     r9, 3(r8)           /* link ctrl */
     eieio
-    li      r9, (CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE)
+    li      r9, (CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE)
     stb     r9, 0(r8)           /* baud rate (LSB)*/
     eieio
-    li      r9, ((CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
+    li      r9, ((CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE) >> 8)
     stb     r9, 1(r8)           /* baud rate (MSB) */
     eieio
     li      r9, 0x07
@@ -589,7 +589,7 @@
  * set LEDs end
  */
     li      r3, 0xf
-    lis     r30, CFG_USR_LED_BASE@h
+    lis     r30, CONFIG_SYS_USR_LED_BASE@h
     stb     r3, 2(r30)
     sync
 
@@ -602,8 +602,8 @@
  */
 
 Printf:
-    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
-    ori     r10, r10, CFG_NS16550_COM1@l
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
 WaitChr:
     lbz     r0, 5(r10)          /* read link status */
     eieio
@@ -622,8 +622,8 @@
  * print a char to COM1 in polling mode (r10=COM1 port, r3=char)
  */
 OutChr:
-    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
-    ori     r10, r10, CFG_NS16550_COM1@l
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
 OutChr1:
     lbz     r0, 5(r10)          /* read link status */
     eieio
@@ -645,8 +645,8 @@
 OutHex:
     li      r9, 28              /* shift reg for 8 digits */
 OHstart:
-    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
-    ori     r10, r10, CFG_NS16550_COM1@l
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
 OutDig:
     lbz     r0, 0(r29)          /* slow down dummy read */
     lbz     r0, 5(r10)          /* read link status */
@@ -685,8 +685,8 @@
     divwu   r0, r3, r6          /* r0 = r3 / 10, r7 = r3 mod 10 */
     mullw   r10, r0, r6
     subf    r7, r10, r3
-    lis     r10, CFG_NS16550_COM1@h /* COM1 base address*/
-    ori     r10, r10, CFG_NS16550_COM1@l
+    lis     r10, CONFIG_SYS_NS16550_COM1@h /* COM1 base address*/
+    ori     r10, r10, CONFIG_SYS_NS16550_COM1@l
     or.     r7, r7, r7
     bne     noblank1
     li      r3, 0x20
diff --git a/board/eltec/elppc/elppc.c b/board/eltec/elppc/elppc.c
index d3ac278..e73c712 100644
--- a/board/eltec/elppc/elppc.c
+++ b/board/eltec/elppc/elppc.c
@@ -68,16 +68,16 @@
 
 	register unsigned long i, msar1, mear1, memSize;
 
-#if defined(CFG_MEMTEST)
+#if defined(CONFIG_SYS_MEMTEST)
 	register unsigned long reg;
 
 	printf ("Testing DRAM\n");
 
 	/* write each mem addr with it's address */
-	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4)
 		*reg = reg;
 
-	for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
+	for (reg = CONFIG_SYS_MEMTEST_START; reg < CONFIG_SYS_MEMTEST_END; reg += 4) {
 		if (*reg != reg)
 			return -1;
 	}
diff --git a/board/eltec/elppc/flash.c b/board/eltec/elppc/flash.c
index 442dd00..21ae098 100644
--- a/board/eltec/elppc/flash.c
+++ b/board/eltec/elppc/flash.c
@@ -34,7 +34,7 @@
 #include <asm/processor.h>
 #include <asm/pci_io.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size (vu_long *addr, flash_info_t *info);
 static int write_word (flash_info_t *info, ulong dest, ulong data);
@@ -55,7 +55,7 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i)
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i)
     {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
@@ -96,8 +96,8 @@
     if (size2 == 4*1024*1024)
     {
 	(void)flash_protect(FLAG_PROTECT_SET,
-		CFG_FLASH_BASE,
-		CFG_FLASH_BASE+monitor_flash_len-1,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
 		&flash_info[1]);
     }
 
@@ -370,7 +370,7 @@
     last  = start;
     addr = (FLASH_WORD_SIZE *)(info->start[l_sect]);
     while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -500,7 +500,7 @@
 	    start = get_timer (0);
 	    while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
 		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/eltec/elppc/misc.c b/board/eltec/elppc/misc.c
index 5e3a81c..cbaf10b 100644
--- a/board/eltec/elppc/misc.c
+++ b/board/eltec/elppc/misc.c
@@ -29,7 +29,7 @@
 #include "srom.h"
 
 /* imports  */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
 extern int l2_cache_enable (int l2control);
 extern int eepro100_write_eeprom (struct eth_device *dev, int location,
 				  int addr_len, unsigned short data);
@@ -95,7 +95,7 @@
 			  SECOND_DEVICE, FIRST_BLOCK);
 
 	/* read out current nvram shadow image */
-	nvram_read (buf, CFG_NV_SROM_COPY_ADDR, CFG_SROM_SIZE);
+	nvram_read (buf, CONFIG_SYS_NV_SROM_COPY_ADDR, CONFIG_SYS_SROM_SIZE);
 
 	if (strcmp (eerev.magic, "ELTEC") != 0) {
 		/* srom is not initialized -> create a default revision info */
@@ -124,8 +124,8 @@
 	}
 
 	if ((copyNv == 0)
-	    && (el_srom_checksum ((u_char *) & eerev, CFG_SROM_SIZE) !=
-		el_srom_checksum ((u_char *) buf, CFG_SROM_SIZE))) {
+	    && (el_srom_checksum ((u_char *) & eerev, CONFIG_SYS_SROM_SIZE) !=
+		el_srom_checksum ((u_char *) buf, CONFIG_SYS_SROM_SIZE))) {
 		printf ("Invalid revision info copy in nvram !\n");
 		printf ("Press key:\n  <c> to copy current revision info to nvram.\n");
 		printf ("  <r> to reenter revision info.\n");
@@ -232,16 +232,16 @@
 			printf ("OK\n\n");
 
 		/* write new values as shadow image to nvram */
-		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
-			     CFG_SROM_SIZE);
+		nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CONFIG_SYS_SROM_SIZE);
 
 	}
 
 	/*if (initSrom) */
 	/* copy current values as shadow image to nvram */
 	if (initSrom == 0 && copyNv == 1)
-		nvram_write (CFG_NV_SROM_COPY_ADDR, (void *) &eerev,
-			     CFG_SROM_SIZE);
+		nvram_write (CONFIG_SYS_NV_SROM_COPY_ADDR, (void *) &eerev,
+			     CONFIG_SYS_SROM_SIZE);
 
 	/* update environment */
 	sprintf (buf, "%02x:%02x:%02x:%02x:%02x:%02x",
diff --git a/board/eltec/elppc/pci.c b/board/eltec/elppc/pci.c
index 5b115ea..bf133b7 100644
--- a/board/eltec/elppc/pci.c
+++ b/board/eltec/elppc/pci.c
@@ -42,37 +42,37 @@
     hose->last_busno = 0xff;
 
     pci_set_region(hose->regions + 0,
-	CFG_PCI_MEMORY_BUS,
-	CFG_PCI_MEMORY_PHYS,
-	CFG_PCI_MEMORY_SIZE,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_SIZE,
 	PCI_REGION_MEM | PCI_REGION_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
-	CFG_PCI_MEM_BUS,
-	CFG_PCI_MEM_PHYS,
-	CFG_PCI_MEM_SIZE,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* ISA/PCI memory space */
     pci_set_region(hose->regions + 2,
-	CFG_ISA_MEM_BUS,
-	CFG_ISA_MEM_PHYS,
-	CFG_ISA_MEM_SIZE,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* PCI I/O space */
     pci_set_region(hose->regions + 3,
-	CFG_PCI_IO_BUS,
-	CFG_PCI_IO_PHYS,
-	CFG_PCI_IO_SIZE,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
 	PCI_REGION_IO);
 
     /* ISA/PCI I/O space */
     pci_set_region(hose->regions + 4,
-	CFG_ISA_IO_BUS,
-	CFG_ISA_IO_PHYS,
-	CFG_ISA_IO_SIZE,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
 	PCI_REGION_IO);
 
     hose->region_count = 5;
diff --git a/board/eltec/elppc/srom.h b/board/eltec/elppc/srom.h
index c18ab91..504b742 100644
--- a/board/eltec/elppc/srom.h
+++ b/board/eltec/elppc/srom.h
@@ -40,8 +40,8 @@
 #define SROM_SHORT(pX)          (*(u8 *)(pX) | *((u8 *)(pX)+1) << 8)
 
 /* bab7xx ELTEC srom */
-#define I2C_BUS_DAT             (CFG_ISA_IO + 0x220)
-#define I2C_BUS_DIR             (CFG_ISA_IO + 0x221)
+#define I2C_BUS_DAT             (CONFIG_SYS_ISA_IO + 0x220)
+#define I2C_BUS_DIR             (CONFIG_SYS_ISA_IO + 0x221)
 
 /* srom at mpc107 */
 #define MPC107_I2CADDR          (mpc107_eumb_addr + 0x3000)     /* address      */
diff --git a/board/eltec/mhpc/flash.c b/board/eltec/mhpc/flash.c
index 4cc66a9..2fbdb27 100644
--- a/board/eltec/mhpc/flash.c
+++ b/board/eltec/mhpc/flash.c
@@ -25,7 +25,7 @@
 #include <mpc8xx.h>
 #include <linux/byteorder/swab.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Protection Flags:
@@ -62,13 +62,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -81,18 +81,18 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    CFG_FLASH_BASE,
-			    CFG_FLASH_BASE+monitor_flash_len-1,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 
 	flash_info[0].size = size_b0;
@@ -203,10 +203,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW)0xFF00FF00;      /* restore read mode */
@@ -277,7 +277,7 @@
 			udelay (1000);
 
 			while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW)0xB000B000; /* suspend erase */
 					*addr = (FPW)0xFF00FF00; /* reset to read mode */
@@ -419,7 +419,7 @@
 	start = get_timer (0);
 
 	while (((status = SWAP(*addr)) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW)0xFF00FF00;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/eltec/mhpc/mhpc.c b/board/eltec/mhpc/mhpc.c
index 3666791..7cca6b2 100644
--- a/board/eltec/mhpc/mhpc.c
+++ b/board/eltec/mhpc/mhpc.c
@@ -36,7 +36,7 @@
 #include <video_fb.h>
 
 /* imports from common/main.c */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
 
 extern void eeprom_init (void);
 extern int eeprom_read (unsigned dev_addr, unsigned offset,
@@ -105,7 +105,7 @@
 
 int board_early_init_f (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile cpm8xx_t *cp = &(im->im_cpm);
 	volatile iop8xx_t *ip = (iop8xx_t *) & (im->im_ioport);
 
@@ -160,7 +160,7 @@
 	int i;
 
 	/* check revision data */
-	eeprom_read (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
+	eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo, 32);
 
 	if (strncmp ((char *) &mhpcRevInfo.board[2], "MHPC", 4) != 0) {
 		printf ("Enter revision number (0-9): %c  ",
@@ -228,7 +228,7 @@
 		}
 
 		/* setup new revision data */
-		eeprom_write (CFG_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
+		eeprom_write (CONFIG_SYS_I2C_EEPROM_ADDR, 480, (uchar *) &mhpcRevInfo,
 			      32);
 	}
 
@@ -253,13 +253,13 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
 
-	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* should this be mamr? - NTL */
 	memctl->memc_mptpr = MPTPR_PTP_DIV64;
 	memctl->memc_mar = 0x00008800;
@@ -267,15 +267,15 @@
 	/*
 	 * Map controller SDRAM bank 0
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 	udelay (200);
 
 	/*
 	 * Map controller SDRAM bank 1
 	 */
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 
 	/*
 	 * Perform SDRAM initializsation sequence
@@ -419,7 +419,7 @@
 {
 	unsigned int clut = 0;
 	unsigned char *penv;
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* enable video only on CLUT value */
 	if ((penv = (uchar *)getenv ("clut")) != NULL)
@@ -470,7 +470,7 @@
 		    unsigned char r, unsigned char g, unsigned char b)
 {
 	unsigned int lum;
-	unsigned short *pLut = (unsigned short *) (CFG_IMMR + 0x0e00);
+	unsigned short *pLut = (unsigned short *) (CONFIG_SYS_IMMR + 0x0e00);
 
 	/* 16 bit lut values, 12 bit used, xxxx BBGG RRii iiii */
 	/* y = 0.299*R + 0.587*G + 0.114*B */
diff --git a/board/emk/common/flash.c b/board/emk/common/flash.c
index 04c35bc..330978b 100644
--- a/board/emk/common/flash.c
+++ b/board/emk/common/flash.c
@@ -26,7 +26,7 @@
 
 #include <common.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 #if defined (CONFIG_TOP860)
   typedef unsigned short FLASH_PORT_WIDTH;
@@ -95,7 +95,7 @@
 	int i = 0;
 	extern void flash_preinit(void);
 	extern void flash_afterinit(uint, ulong, ulong);
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	flash_preinit();
 
@@ -105,12 +105,12 @@
 			flash_get_size((FPW *)flashbase, &flash_info[i]);
 	size += flash_info[i].size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -147,14 +147,14 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->size &&
 			info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -459,7 +459,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -473,14 +473,14 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
 		}
 
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
 			putc ('.');
 			last = get_timer(0);
 		}
@@ -581,7 +581,7 @@
 
 	/* data polling for D7 */
 	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW)0x00F000F0;	/* reset bank */
 			res = 1;
 		}
diff --git a/board/emk/common/vpd.c b/board/emk/common/vpd.c
index 8a3a12b..c2af219 100644
--- a/board/emk/common/vpd.c
+++ b/board/emk/common/vpd.c
@@ -36,8 +36,8 @@
 	uint len;
 
 	/* get length first */
-	addr = CFG_FACT_OFFSET;
-	if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, 2)) {
+	addr = CONFIG_SYS_FACT_OFFSET;
+	if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, 2)) {
 	  bailout:
 		printf ("cannot read factory configuration\n");
 		printf ("be sure to set ethaddr	yourself!\n");
@@ -47,14 +47,14 @@
 	addr += 2;
 
 	/* sanity check */
-	if (length < 20 || length > CFG_FACT_SIZE - 2)
+	if (length < 20 || length > CONFIG_SYS_FACT_SIZE - 2)
 		goto bailout;
 
 	/* read lines */
 	while (length > 0) {
 		/* read one line */
 		len = length > 80 ? 80 : length;
-		if (eeprom_read (CFG_I2C_FACT_ADDR, addr, buf, len))
+		if (eeprom_read (CONFIG_SYS_I2C_FACT_ADDR, addr, buf, len))
 			goto bailout;
 		/* mark end of buffer */
 		buf[len] = 0;
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
index 2788626..7efbcb0 100644
--- a/board/emk/top5200/top5200.c
+++ b/board/emk/top5200/top5200.c
@@ -35,7 +35,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 #if 0
 	ulong	t;
 	ulong	tap_del;
@@ -46,33 +46,33 @@
 	#define	SOFT_REF	4
 
 	/* configure SDRAM start/end */
-	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CFG_SDRAM_BASE & 0xFFF00000) | CFG_DRAM_RAM_SIZE;
+	*(vu_long *)MPC5XXX_SDRAM_CS0CFG = (CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | CONFIG_SYS_DRAM_RAM_SIZE;
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x80000000;	/* disabled */
 
 	/* setup config registers */
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CFG_DRAM_CONFIG1;
-	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CFG_DRAM_CONFIG2;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = CONFIG_SYS_DRAM_CONFIG1;
+	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = CONFIG_SYS_DRAM_CONFIG2;
 
 	/* unlock mode register */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN;
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
-#ifdef CFG_DRAM_DDR
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+#ifdef CONFIG_SYS_DRAM_DDR
 	/* set extended mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_EMODE;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_EMODE;
 #endif
 	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE | 0x0400;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE | 0x0400;
 	/* precharge all banks */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_PRE;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_PRE;
 	/* auto refresh */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL | MODE_EN | SOFT_REF;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL | MODE_EN | SOFT_REF;
 	/* set mode register */
-	*(vu_short *)MPC5XXX_SDRAM_MODE = CFG_DRAM_MODE;
+	*(vu_short *)MPC5XXX_SDRAM_MODE = CONFIG_SYS_DRAM_MODE;
 	/* normal operation */
-	*(vu_long *)MPC5XXX_SDRAM_CTRL = CFG_DRAM_CONTROL;
+	*(vu_long *)MPC5XXX_SDRAM_CTRL = CONFIG_SYS_DRAM_CONTROL;
 	/* write default TAP delay */
-	*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
+	*(vu_long *)MPC5XXX_CDM_PORCFG = CONFIG_SYS_DRAM_TAP_DEL << 24;
 
 #if 0
 	for (tap_del = 0; tap_del < 32; tap_del++)
@@ -97,7 +97,7 @@
 		}
 	}
 #endif
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	dramsize = ((1 << (*(vu_long *)MPC5XXX_SDRAM_CS0CFG - 0x13)) << 20);
 
diff --git a/board/emk/top860/top860.c b/board/emk/top860/top860.c
index aca4991..76f7a0c 100644
--- a/board/emk/top860/top860.c
+++ b/board/emk/top860/top860.c
@@ -78,7 +78,7 @@
  *****************************************************************************/
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/*
@@ -93,8 +93,8 @@
 			   sizeof (edo_60ns_25MHz_tbl) / sizeof (uint));
 		memctl->memc_mptpr = 0x0200;
 		memctl->memc_mamr = 0x0ca20330;
-		memctl->memc_or2 = -CFG_DRAM_MAX | OR_CSNT_SAM;
-		memctl->memc_br2 = CFG_DRAM_BASE | BR_MS_UPMA | BR_V;
+		memctl->memc_or2 = -CONFIG_SYS_DRAM_MAX | OR_CSNT_SAM;
+		memctl->memc_br2 = CONFIG_SYS_DRAM_BASE | BR_MS_UPMA | BR_V;
 		/*
 		 * Do 8 read accesses to DRAM
 		 */
@@ -112,7 +112,7 @@
 		addr2[1] = 0x47110815;
 		if (addr1[0] == 0xfeedc0de && addr1[1] == 0x47110815) {
 			/* only 4MB populated */
-			memctl->memc_or2 = -(CFG_DRAM_MAX / 4) | OR_CSNT_SAM;
+			memctl->memc_or2 = -(CONFIG_SYS_DRAM_MAX / 4) | OR_CSNT_SAM;
 		}
 	}
 
diff --git a/board/ep7312/flash.c b/board/ep7312/flash.c
index 1ef06f8..0c2b3ae 100644
--- a/board/ep7312/flash.c
+++ b/board/ep7312/flash.c
@@ -27,7 +27,7 @@
 #define FLASH_BANK_SIZE 0x1000000
 #define MAIN_SECT_SIZE  0x20000
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -38,15 +38,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 				(INTEL_MANUFACT & FLASH_VENDMASK) |
 				(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -60,8 +60,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -165,7 +165,7 @@
 			*addr = 0xD0;		/* erase confirm */
 
 			while ((*addr & 0x80) != 0x80) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0xB0;	/* suspend erase */
 					*addr = 0xFF;	/* reset to read mode */
 					rc = ERR_TIMOUT;
@@ -232,7 +232,7 @@
 
 	/* wait while polling the status register */
 	while (((val = *addr) & 0x80) != 0x80) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
 			/* suspend program command */
 			*addr = 0xB0;
diff --git a/board/ep8248/ep8248.c b/board/ep8248/ep8248.c
index 4cfb2ac..bc20ba7 100644
--- a/board/ep8248/ep8248.c
+++ b/board/ep8248/ep8248.c
@@ -35,31 +35,31 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A */
     {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
-	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
-	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
-	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
-	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
-	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
 	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
 	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
 	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
 	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22            */
-	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
 	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
 	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
 	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
@@ -78,20 +78,20 @@
 
     /* Port B */
     {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
 	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
@@ -123,11 +123,11 @@
 	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
 	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
 	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
-	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK11) */
 	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
-	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
-	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK13) */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
 	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17            */
 	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
 	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
@@ -187,7 +187,7 @@
 
 int board_early_init_f (void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	bcsr[4] |= 0x30; /* Turn the LEDs off */
 
@@ -198,39 +198,39 @@
 	bcsr[7] |= 0x10;
 #endif
 
-#if CFG_FCC1
+#if CONFIG_SYS_FCC1
 	bcsr[8] |= 0xC0;
-#endif /* CFG_FCC1 */
-#if CFG_FCC2
+#endif /* CONFIG_SYS_FCC1 */
+#if CONFIG_SYS_FCC2
 	bcsr[8] |= 0x30;
-#endif /* CFG_FCC2 */
+#endif /* CONFIG_SYS_FCC2 */
 
 	return 0;
 }
 
 phys_size_t initdram(int board_type)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 	long int msize = 16L << (bcsr[2] & 3);
 
-#ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
 	uchar c = 0xFF;
-	uint psdmr = CFG_PSDMR;
+	uint psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	immap->im_siu_conf.sc_ppc_acr  = 0x02;
 	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or1  = CFG_SDRAM_OR;
-	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
@@ -240,7 +240,7 @@
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
 	*ramaddr = c;
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 	/* Return total 60x bus SDRAM size */
 	return msize * 1024 * 1024;
@@ -248,7 +248,7 @@
 
 int checkboard(void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	puts("Board: ");
 	switch (bcsr[0]) {
diff --git a/board/ep8260/config.mk b/board/ep8260/config.mk
index eaf1560..1225830 100644
--- a/board/ep8260/config.mk
+++ b/board/ep8260/config.mk
@@ -25,7 +25,7 @@
 # EP8260 boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_ep8260.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_ep8260.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/ep8260/ep8260.c b/board/ep8260/ep8260.c
index 0e43c6d..90ab047 100644
--- a/board/ep8260/ep8260.c
+++ b/board/ep8260/ep8260.c
@@ -190,12 +190,12 @@
 */
 int board_early_init_f (void)
 {
-	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-	memctl->memc_br4 = CFG_BR4_PRELIM;
-	memctl->memc_or4 = CFG_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
 	regs->bcsr1 = 0x62;	/* to enable terminal on SMC1 */
 	regs->bcsr2 = 0x30;	/* enable NVRAM and writing FLASH */
 	return 0;
@@ -203,7 +203,7 @@
 
 void reset_phy (void)
 {
-	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
 
 	regs->bcsr4 = 0xC0;
 }
@@ -216,7 +216,7 @@
 
 int checkboard (void)
 {
-	volatile t_ep_regs *regs = (t_ep_regs *) CFG_REGS_BASE;
+	volatile t_ep_regs *regs = (t_ep_regs *) CONFIG_SYS_REGS_BASE;
 	uint major = 0, minor = 0;
 
 	switch (regs->bcsr0) {
@@ -245,18 +245,18 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar c = 0;
-	volatile uchar *ramaddr = (uchar *) (CFG_SDRAM_BASE) + 0x110;
+	volatile uchar *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE) + 0x110;
 
 /*
-	ulong psdmr = CFG_PSDMR;
-#ifdef CFG_LSDRAM
-	ulong lsdmr = CFG_LSDMR;
+	ulong psdmr = CONFIG_SYS_PSDMR;
+#ifdef CONFIG_SYS_LSDRAM
+	ulong lsdmr = CONFIG_SYS_LSDMR;
 #endif
 */
-	long size = CFG_SDRAM0_SIZE;
+	long size = CONFIG_SYS_SDRAM0_SIZE;
 	int i;
 
 
@@ -277,44 +277,44 @@
 *  accessing the SDRAM with a single-byte transaction."
 *
 * The appropriate BRx/ORx registers have already been set when we
-* get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+* get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 */
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_PREA;
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_PREA;
 	*ramaddr = c;
 
-	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_CBRR;
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_CBRR;
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
 
-	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_MRW;
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_MRW;
 	*ramaddr = c;
 
-	memctl->memc_psdmr = (ulong) CFG_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	memctl->memc_psdmr = (ulong) CONFIG_SYS_PSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
 	*ramaddr = c;
 
-#ifndef CFG_RAMBOOT
-#ifdef CFG_LSDRAM
-	size += CFG_SDRAM1_SIZE;
-	ramaddr = (uchar *) (CFG_SDRAM1_BASE) + 0x8c;
-	memctl->memc_lsrt = CFG_LSRT;
+#ifndef CONFIG_SYS_RAMBOOT
+#ifdef CONFIG_SYS_LSDRAM
+	size += CONFIG_SYS_SDRAM1_SIZE;
+	ramaddr = (uchar *) (CONFIG_SYS_SDRAM1_BASE) + 0x8c;
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
 
-	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_PREA;
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
 	*ramaddr = c;
 
-	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_CBRR;
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
 
-	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_MRW;
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
 	*ramaddr = c;
 
-	memctl->memc_lsdmr = (ulong) CFG_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
+	memctl->memc_lsdmr = (ulong) CONFIG_SYS_LSDMR | PSDMR_OP_NORM | PSDMR_RFEN;
 	*ramaddr = c;
-#endif /* CFG_LSDRAM */
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_LSDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
 	return (size * 1024 * 1024);
 }
diff --git a/board/ep8260/flash.c b/board/ep8260/flash.c
index d32486d..2a81de5 100644
--- a/board/ep8260/flash.c
+++ b/board/ep8260/flash.c
@@ -35,7 +35,7 @@
 #define V_BYTE(a)	(*(volatile unsigned char *)( a ))
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -134,13 +134,13 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_get_size(CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size(CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 			size_b0, size_b0>>20);
@@ -150,10 +150,10 @@
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -284,7 +284,7 @@
 	while ((V_ULONG( info->start[l_sect] ) & 0x00800080) != 0x00800080 ||
 	       (V_ULONG( info->start[l_sect] + 4 ) & 0x00800080) != 0x00800080)
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -403,7 +403,7 @@
 	start = get_timer (0);
 	while (((V_ULONG( dest ) & 0x00800080) != (ch & 0x00800080)) ||
 	       ((V_ULONG( dest + 4 ) & 0x00800080) != (cl & 0x00800080))) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/ep8260/mii_phy.c b/board/ep8260/mii_phy.c
index 813f020..c7aa275 100644
--- a/board/ep8260/mii_phy.c
+++ b/board/ep8260/mii_phy.c
@@ -54,7 +54,7 @@
 {
     int i;
     unsigned short tmp, val = 0, adr = 0;
-    t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
 
     tmp = 0x6002 | (adr << 7) | (reg << 2);
     regs->bcsr4 = 0xC3;
@@ -83,7 +83,7 @@
 {
     int i;
     unsigned short tmp, adr = 0;
-    t_ep_regs *regs = (t_ep_regs*)CFG_REGS_BASE;
+    t_ep_regs *regs = (t_ep_regs*)CONFIG_SYS_REGS_BASE;
 
     tmp = 0x5002 | (adr << 7) | (reg << 2);
     regs->bcsr4 = 0xC3;
diff --git a/board/ep82xxm/ep82xxm.c b/board/ep82xxm/ep82xxm.c
index 03baf0b..c1d6e91 100644
--- a/board/ep82xxm/ep82xxm.c
+++ b/board/ep82xxm/ep82xxm.c
@@ -39,8 +39,8 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
-#define CFG_FCC2 1
-#define CFG_FCC3 1
+#define CONFIG_SYS_FCC2 1
+#define CONFIG_SYS_FCC3 1
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
@@ -82,34 +82,34 @@
 
     /* Port B */
     {	/*	     conf	ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CFG_FCC2,	 1,   1,   1,	0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_DIV     */
-	/* PB16 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_ERR     */
-	/* PB15 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_ERR     */
-	/* PB14 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_EN      */
-	/* PB13 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:COL	     */
-	/* PB12 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:CRS	     */
-	/* PB11 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
-	/* PB10 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
-	/* PB9	*/ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
-	/* PB8	*/ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB31 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,	 1,   1,   1,	0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,	 1,   0,   1,	0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_DIV     */
+	/* PB16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RX_ERR     */
+	/* PB15 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_ERR     */
+	/* PB14 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TX_EN      */
+	/* PB13 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:COL	     */
+	/* PB12 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:CRS	     */
+	/* PB11 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB10 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB9	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
+	/* PB8	*/ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* FCC3:RXD	     */
 	/* PB7	*/ { 0,		 0,   0,   0,	0,   0 }, /* PB7	     */
-	/* PB6	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
-	/* PB5	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
-	/* PB4	*/ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB6	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB5	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
+	/* PB4	*/ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3:TXD	     */
 	/* PB3	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
 	/* PB2	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
 	/* PB1	*/ { 0,		 0,   0,   0,	0,   0 }, /* non-existent    */
@@ -122,7 +122,7 @@
 	/* PC30 */ { 0,		 0,   0,   0,	0,   0 }, /* PC30	     */
 	/* PC29 */ { 1,		 1,   1,   0,	0,   0 }, /* SCC1 CTS#	     */
 	/* PC28 */ { 0,		 0,   0,   0,	0,   0 }, /* PC28	     */
-	/* PC27 */ { CFG_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3: TXD[0]    */
+	/* PC27 */ { CONFIG_SYS_FCC3,	 1,   0,   1,	0,   0 }, /* FCC3: TXD[0]    */
 	/* PC26 */ { 0,		 0,   0,   0,	0,   0 }, /* PC26	     */
 	/* PC25 */ { 0,		 0,   0,   0,	0,   0 }, /* PC25	     */
 	/* PC24 */ { 0,		 0,   0,   0,	0,   0 }, /* PC24	     */
@@ -130,10 +130,10 @@
 	/* PC22 */ { 0,		 0,   0,   0,	0,   0 }, /* PC22	     */
 	/* PC21 */ { 0,		 0,   0,   0,	0,   0 }, /* PC21	     */
 	/* PC20 */ { 0,		 0,   0,   0,	0,   0 }, /* PC20	     */
-	/* PC19 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* RxClk (CLK13)   */
-	/* PC18 */ { CFG_FCC2,	 1,   0,   0,	0,   0 }, /* TxClk (CLK14)   */
-	/* PC17 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* RxClk (CLK15)   */
-	/* PC16 */ { CFG_FCC3,	 1,   0,   0,	0,   0 }, /* TxClk (CLK16)   */
+	/* PC19 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* RxClk (CLK13)   */
+	/* PC18 */ { CONFIG_SYS_FCC2,	 1,   0,   0,	0,   0 }, /* TxClk (CLK14)   */
+	/* PC17 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* RxClk (CLK15)   */
+	/* PC16 */ { CONFIG_SYS_FCC3,	 1,   0,   0,	0,   0 }, /* TxClk (CLK16)   */
 	/* PC15 */ { 0,		 0,   0,   0,	0,   0 }, /* PC15	     */
 	/* PC14 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC1 CD#	     */
 	/* PC13 */ { 1,		 1,   0,   0,	0,   0 }, /* SCC2 CTS#	     */
@@ -198,7 +198,7 @@
 
 int board_early_init_f (void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	bcsr[4] |= 0x30; /* Turn the LEDs off */
 
@@ -209,12 +209,12 @@
 	bcsr[7] |= 0x10;
 #endif
 
-#if CFG_FCC3
+#if CONFIG_SYS_FCC3
 	bcsr[8] |= 0xC0;
-#endif /* CFG_FCC3 */
-#if CFG_FCC2
+#endif /* CONFIG_SYS_FCC3 */
+#if CONFIG_SYS_FCC2
 	bcsr[8] |= 0x30;
-#endif /* CFG_FCC2 */
+#endif /* CONFIG_SYS_FCC2 */
 
 	return 0;
 }
@@ -224,23 +224,23 @@
 	/* Size in MB of SDRAM populated on board*/
 	long int msize = 256;
 
-#ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	uint psdmr = CFG_PSDMR;
+	uint psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	unsigned char	ramtmp;
 	unsigned char	*ramptr1 = (unsigned char *)0x00000110;
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 udelay(400);
 
 	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or1  = CFG_SDRAM_OR;
-	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
 	memctl->memc_psdmr = psdmr;
 
 udelay(400);
@@ -255,7 +255,7 @@
 	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;  /* Mode Register write */
 	*ramptr1  = 0xFF;
 	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 	/* Return total 60x bus SDRAM size */
 	return msize * 1024 * 1024;
@@ -263,7 +263,7 @@
 
 int checkboard(void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	puts("Board: ");
 	switch (bcsr[0]) {
diff --git a/board/ep88x/ep88x.c b/board/ep88x/ep88x.c
index 92e5f0c..7e95007 100644
--- a/board/ep88x/ep88x.c
+++ b/board/ep88x/ep88x.c
@@ -63,7 +63,7 @@
 
 int board_early_init_f (void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	bcsr[0] |= 0x0C; /* Turn the LEDs off */
 	bcsr[2] |= 0x08; /* Enable flash WE# line - necessary for
@@ -89,7 +89,7 @@
 phys_size_t initdram (int board_type)
 {
 	long int msize;
-	volatile immap_t     *immap  = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMA, sdram_table, sizeof(sdram_table) / sizeof(uint));
@@ -97,7 +97,7 @@
 	/* Configure SDRAM refresh */
 	memctl->memc_mptpr = MPTPR_PTP_DIV2; /* BRGCLK/2 */
 
-	memctl->memc_mamr = (65 << 24) | CFG_MAMR; /* No refresh */
+	memctl->memc_mamr = (65 << 24) | CONFIG_SYS_MAMR; /* No refresh */
 	udelay(100);
 
 	/* Run MRS pattern from location 0x36 */
@@ -106,10 +106,10 @@
 	udelay(100);
 
 	memctl->memc_mamr |=  MAMR_PTAE; /* Enable refresh */
-	memctl->memc_or1   = ~(CFG_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
-	memctl->memc_br1   =  CFG_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
+	memctl->memc_or1   = ~(CONFIG_SYS_SDRAM_MAX_SIZE - 1) | OR_CSNT_SAM;
+	memctl->memc_br1   =  CONFIG_SYS_SDRAM_BASE | BR_PS_32 | BR_MS_UPMA | BR_V;
 
-	msize = get_ram_size(CFG_SDRAM_BASE, CFG_SDRAM_MAX_SIZE);
+	msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_SDRAM_MAX_SIZE);
 	memctl->memc_or1  |= ~(msize - 1);
 
 	return msize;
@@ -117,7 +117,7 @@
 
 int checkboard( void )
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	puts("Board: ");
 	switch (bcsr[15]) {
diff --git a/board/eric/eric.c b/board/eric/eric.c
index 972d485..600b9d7 100644
--- a/board/eric/eric.c
+++ b/board/eric/eric.c
@@ -142,7 +142,7 @@
 	 * so let init.S do the init job for SDRAM
 	 * and simply return 32MByte here
 	 */
-	return (CFG_SDRAM_SIZE * 1024 * 1024);
+	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
 #else
 
 	/* Read Serial Presence Detect Information */
diff --git a/board/eric/flash.c b/board/eric/flash.c
index 2c7d2a0..7e57513 100644
--- a/board/eric/flash.c
+++ b/board/eric/flash.c
@@ -25,10 +25,10 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 
-#ifdef CFG_FLASH_16BIT
+#ifdef CONFIG_SYS_FLASH_16BIT
 #define FLASH_WORD_SIZE	unsigned short
 #define	FLASH_ID_MASK	0xFFFF
 #else
@@ -42,7 +42,7 @@
 /* stolen from esteem192e/flash.c */
 ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t *info, ulong dest, ulong data);
 #else
 static int write_short (flash_info_t *info, ulong dest, ushort data);
@@ -61,7 +61,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -75,7 +75,7 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1)
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1)
 	  {
 	    /* Setup offsets */
 	    flash_get_offsets (FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -88,8 +88,8 @@
 				&flash_info[0]);
 #else
 	    (void)flash_protect(FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE+monitor_flash_len-1,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 				&flash_info[0]);
 #endif
 	    size_b1 = 0 ;
@@ -137,8 +137,8 @@
 				&flash_info[0]);
 #else
 	    (void)flash_protect(FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE+monitor_flash_len-1,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 				&flash_info[0]);
 #endif
 
@@ -187,7 +187,7 @@
 	} else if (info->flash_id & FLASH_BTYPE) {
 	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 		/* set sector offsets for bottom boot block type	*/
 		info->start[0] = base + 0x00000000;
 		info->start[1] = base + 0x00004000;
@@ -241,7 +241,7 @@
 		i = info->sector_count - 1;
 	     if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 		info->start[i--] = base + info->size - 0x00004000;
 		info->start[i--] = base + info->size - 0x00008000;
 		info->start[i--] = base + info->size - 0x0000C000;
@@ -403,7 +403,7 @@
 	/* Write auto select command: read Manufacturer ID */
 
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 	/*
 	 * Note: if it is an AMD flash and the word at addr[0000]
@@ -654,7 +654,7 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
     if(info->flash_id < FLASH_AMD_COMP) {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 	addr[0x0555] = 0x00AA00AA;
 	addr[0x02AA] = 0x00550055;
 	addr[0x0555] = 0x00800080;
@@ -695,7 +695,7 @@
 	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
 			  (0x00800080&FLASH_ID_MASK)  )
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -716,7 +716,7 @@
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
 			barf = 0;
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			addr = (vu_long*)(info->start[sect]);
 			addr[0] = 0x00200020;
 			addr[0] = 0x00D000D0;
@@ -767,7 +767,7 @@
 	flash_info_t *info;
 	int i;
 
-	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
 		if ((addr >= info->start[0]) &&
 		    (addr < (info->start[0] + info->size)) ) {
 			return (info);
@@ -844,7 +844,7 @@
 
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 	ulong cp, wp, data;
 	int l;
 #else
@@ -853,7 +853,7 @@
 #endif
 	int i, rc;
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 
 	wp = (addr & ~3);	/* get lower word aligned address */
@@ -980,7 +980,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long *) (info->start[0]);
@@ -1018,7 +1018,7 @@
 
 		while ((*((vu_long *) dest) & 0x00800080) !=
 		       (data & 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1026,7 +1026,7 @@
 	} else {
 
 		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 
@@ -1093,7 +1093,7 @@
 	if (info->flash_id < FLASH_AMD_COMP) {
 		/* AMD stuff */
 		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1101,7 +1101,7 @@
 	} else {
 		/* intel stuff */
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 
@@ -1120,7 +1120,7 @@
 		*addr = 0x00B0;
 		*addr = 0x0070;
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 		*addr = 0x00FF;
diff --git a/board/eric/init.S b/board/eric/init.S
index 9d4e7ff..2304cc7 100644
--- a/board/eric/init.S
+++ b/board/eric/init.S
@@ -219,7 +219,7 @@
 
 	mflr	r31
 
-#ifdef CFG_SDRAM_MANUALLY
+#ifdef CONFIG_SYS_SDRAM_MANUALLY
 	/*------------------------------------------------------------------- */
 	/* Set MB0CF for bank 0. (0-32MB) Address Mode 4 since 12x8(2) */
 	/*------------------------------------------------------------------- */
diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c
index d9eccba..dd578c8 100644
--- a/board/esd/adciop/flash.c
+++ b/board/esd/adciop/flash.c
@@ -45,7 +45,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c
index e629fd9..ac9bbb3 100644
--- a/board/esd/apc405/apc405.c
+++ b/board/esd/apc405/apc405.c
@@ -41,7 +41,7 @@
 extern void lxt971_no_sleep(void);
 extern ulong flash_get_size (ulong base, int banknum);
 
-int flash_banks = CFG_MAX_FLASH_BANKS_DETECT;
+int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT;
 
 /* fpga configuration data - gzip compressed and generated by bin2c */
 const unsigned char fpgadata[] =
@@ -140,7 +140,7 @@
 	 * First pull fpga-prg pin low, to disable fpga logic
 	 */
 	out_be32((void*)GPIO0_ODR, 0x00000000);        /* no open drain pins */
-	out_be32((void*)GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output   */
+	out_be32((void*)GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output   */
 	out_be32((void*)GPIO0_OR, 0);                  /* pull prg low       */
 
 	/*
@@ -178,8 +178,8 @@
 		mtebc(pb1cr, 0);
 
 		/* resize CS0 to 32MB */
-		mtebc(pb0ap, CFG_EBC_PB0AP_HWREV8);
-		mtebc(pb0cr, CFG_EBC_PB0CR_HWREV8);
+		mtebc(pb0ap, CONFIG_SYS_EBC_PB0AP_HWREV8);
+		mtebc(pb0cr, CONFIG_SYS_EBC_PB0CR_HWREV8);
 	}
 
 	return 0;
@@ -200,8 +200,8 @@
 
 int misc_init_r(void)
 {
-	u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
-	u16 *fpga_ctrl2 =(u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL2);
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
+	u16 *fpga_ctrl2 =(u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL2);
 	u8 *duart0_mcr = (u8 *)(DUART0_BA + 4);
 	u8 *duart1_mcr = (u8 *)(DUART1_BA + 4);
 	unsigned char *dst;
@@ -222,8 +222,8 @@
 	cntrl0Reg = mfdcr(cntrl0);
 	mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset(NULL, 0, 0, NULL);
 	}
@@ -297,11 +297,11 @@
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
-	out_be16(fpga_mode, in_be16(fpga_mode) | CFG_FPGA_CTRL_PS2_RESET);
+	out_be16(fpga_mode, in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 	for (i=0;i<100;i++)
 		udelay(1000);
 	udelay(1000);
-	out_be16(fpga_mode, in_be16(fpga_mode) & ~CFG_FPGA_CTRL_PS2_RESET);
+	out_be16(fpga_mode, in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_PS2_RESET);
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -315,15 +315,15 @@
 	str = getenv("splashimage");
 	if (str) {
 		logo_addr = (uchar *)simple_strtoul(str, NULL, 16);
-		logo_size = CFG_VIDEO_LOGO_MAX_SIZE;
+		logo_size = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
 	} else {
 		logo_addr = logo_bmp;
 		logo_size = sizeof(logo_bmp);
 	}
 
 	if (gd->board_type >= 6) {
-		result = lcd_init((uchar *)CFG_LCD_BIG_REG,
-				  (uchar *)CFG_LCD_BIG_MEM,
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				  regs_13505_640_480_16bpp,
 				  sizeof(regs_13505_640_480_16bpp) /
 				  sizeof(regs_13505_640_480_16bpp[0]),
@@ -332,16 +332,16 @@
 			/* retry with internal image */
 			logo_addr = logo_bmp;
 			logo_size = sizeof(logo_bmp);
-			lcd_init((uchar *)CFG_LCD_BIG_REG,
-				 (uchar *)CFG_LCD_BIG_MEM,
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				 regs_13505_640_480_16bpp,
 				 sizeof(regs_13505_640_480_16bpp) /
 				 sizeof(regs_13505_640_480_16bpp[0]),
 				 logo_addr, logo_size);
 		}
 	} else {
-		result = lcd_init((uchar *)CFG_LCD_BIG_REG,
-				  (uchar *)CFG_LCD_BIG_MEM,
+		result = lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				  (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				  regs_13806_640_480_16bpp,
 				  sizeof(regs_13806_640_480_16bpp) /
 				  sizeof(regs_13806_640_480_16bpp[0]),
@@ -350,8 +350,8 @@
 			/* retry with internal image */
 			logo_addr = logo_bmp;
 			logo_size = sizeof(logo_bmp);
-			lcd_init((uchar *)CFG_LCD_BIG_REG,
-				 (uchar *)CFG_LCD_BIG_MEM,
+			lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG,
+				 (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 				 regs_13806_640_480_16bpp,
 				 sizeof(regs_13806_640_480_16bpp) /
 				 sizeof(regs_13806_640_480_16bpp[0]),
@@ -389,12 +389,12 @@
 	 * fix environment for field updated units
 	 */
 	if (getenv("altbootcmd") == NULL) {
-		setenv("usb_load", CFG_USB_LOAD_COMMAND);
-		setenv("usbargs", CFG_USB_ARGS);
+		setenv("usb_load", CONFIG_SYS_USB_LOAD_COMMAND);
+		setenv("usbargs", CONFIG_SYS_USB_ARGS);
 		setenv("bootcmd", CONFIG_BOOTCOMMAND);
-		setenv("usb_self", CFG_USB_SELF_COMMAND);
-		setenv("bootlimit", CFG_BOOTLIMIT);
-		setenv("altbootcmd", CFG_ALT_BOOTCOMMAND);
+		setenv("usb_self", CONFIG_SYS_USB_SELF_COMMAND);
+		setenv("bootlimit", CONFIG_SYS_BOOTLIMIT);
+		setenv("altbootcmd", CONFIG_SYS_ALT_BOOTCOMMAND);
 		saveenv();
 	}
 
@@ -426,17 +426,17 @@
 #ifdef CONFIG_IDE_RESET
 void ide_set_reset(int on)
 {
-	u16 *fpga_mode = (u16 *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+	u16 *fpga_mode = (u16 *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
 	if (on) {
 		out_be16(fpga_mode,
-			 in_be16(fpga_mode) & ~CFG_FPGA_CTRL_CF_RESET);
+			 in_be16(fpga_mode) & ~CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	} else {
 		out_be16(fpga_mode,
-			 in_be16(fpga_mode) | CFG_FPGA_CTRL_CF_RESET);
+			 in_be16(fpga_mode) | CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	}
 }
 #endif /* CONFIG_IDE_RESET */
@@ -449,7 +449,7 @@
 	lxt971_no_sleep();
 }
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 int usb_board_init(void)
 {
 	return 0;
@@ -480,4 +480,4 @@
 	usb_board_stop();
 	return 0;
 }
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/ar405/flash.c
+++ b/board/esd/ar405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/ash405/ash405.c b/board/esd/ash405/ash405.c
index c3710ab..dd1e2ec 100644
--- a/board/esd/ash405/ash405.c
+++ b/board/esd/ash405/ash405.c
@@ -94,8 +94,8 @@
 	int index;
 	int i;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -157,9 +157,9 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_DUART_RST);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 	udelay(10); /* wait 10us */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_DUART_RST);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 	udelay(1000); /* wait 1ms */
 
 	/*
diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/ash405/flash.c
+++ b/board/esd/ash405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c
index de847f9..56c822e 100644
--- a/board/esd/canbt/flash.c
+++ b/board/esd/canbt/flash.c
@@ -47,7 +47,7 @@
 	unsigned long base_b0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/cms700/cms700.c b/board/esd/cms700/cms700.c
index 806c755..5709d45 100644
--- a/board/esd/cms700/cms700.c
+++ b/board/esd/cms700/cms700.c
@@ -69,9 +69,9 @@
 	/*
 	 * Reset CPLD via GPIO12 (CS3) pin
 	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_PLD_RESET);
 	udelay(1000); /* wait 1ms */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_PLD_RESET);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_PLD_RESET);
 	udelay(1000); /* wait 1ms */
 
 	return 0;
@@ -86,7 +86,7 @@
 	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 
 	return (0);
 }
@@ -101,8 +101,8 @@
 	char str[64];
 	int flashcnt;
 	int delay;
-	volatile unsigned char *led_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1000);
-	volatile unsigned char *ver_reg = (unsigned char *)((ulong)CFG_PLD_BASE + 0x1001);
+	volatile unsigned char *led_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1000);
+	volatile unsigned char *ver_reg = (unsigned char *)((ulong)CONFIG_SYS_PLD_BASE + 0x1001);
 
 	puts ("Board: ");
 
@@ -132,7 +132,7 @@
 
 /* ------------------------------------------------------------------------- */
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
  *	               0: disable write
@@ -143,23 +143,23 @@
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
 	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in_be32((void *)GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void *)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 			break;
 		}
 	}
@@ -173,21 +173,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
 		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts ("Setup of write access state failed.\n");
@@ -200,7 +200,7 @@
 U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
 /* ------------------------------------------------------------------------- */
 
diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c
index 89af119..274ada9 100644
--- a/board/esd/cms700/flash.c
+++ b/board/esd/cms700/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index a1e0ce5..633f641 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -72,7 +72,7 @@
 			     size_t len, int clean);
 #endif
 
-extern block_dev_desc_t ide_dev_desc[CFG_IDE_MAXDEVICE];
+extern block_dev_desc_t ide_dev_desc[CONFIG_SYS_IDE_MAXDEVICE];
 
 int au_check_cksum_valid(int i, long nbytes)
 {
@@ -335,7 +335,7 @@
 	char c, prev;
 	const char *varname_start = NULL;
 	int inputcnt  = strlen (input);
-	int outputcnt = CFG_CBSIZE;
+	int outputcnt = CONFIG_SYS_CBSIZE;
 	int state = 0;	/* 0 = waiting for '$'	*/
 			/* 1 = waiting for '(' or '{' */
 			/* 2 = waiting for ')' or '}' */
@@ -394,7 +394,7 @@
 	    case 2:			/* Waiting for )	*/
 		if (c == ')' || c == '}') {
 			int i;
-			char envname[CFG_CBSIZE], *envval;
+			char envname[CONFIG_SYS_CBSIZE], *envval;
 			/* Varname # of chars */
 			int envcnt = input - varname_start - 1;
 
diff --git a/board/esd/common/esd405ep_nand.c b/board/esd/common/esd405ep_nand.c
index 40d1efb..736176f 100644
--- a/board/esd/common/esd405ep_nand.c
+++ b/board/esd/common/esd405ep_nand.c
@@ -35,17 +35,17 @@
 	struct nand_chip *this = mtd->priv;
 	if (ctrl & NAND_CTRL_CHANGE) {
 		if ( ctrl & NAND_CLE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CLE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CLE);
 		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CLE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CLE);
 		if ( ctrl & NAND_ALE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_ALE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_ALE);
 		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_ALE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_ALE);
 		if ( ctrl & NAND_NCE )
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CFG_NAND_CE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~CONFIG_SYS_NAND_CE);
 		else
-			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+			out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 	}
 
 	if (cmd != NAND_CMD_NONE)
@@ -58,7 +58,7 @@
  */
 static int esd405ep_nand_device_ready(struct mtd_info *mtdinfo)
 {
-	if (in_be32((void *)GPIO0_IR) & CFG_NAND_RDY)
+	if (in_be32((void *)GPIO0_IR) & CONFIG_SYS_NAND_RDY)
 		return 1;
 	return 0;
 }
@@ -69,8 +69,8 @@
 	/*
 	 * Set NAND-FLASH GPIO signals to defaults
 	 */
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void *)GPIO0_OR, in_be32((void *)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 
 	/*
 	 * Initialize nand_chip structure
diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c
index bda361e..3ea053b 100644
--- a/board/esd/common/flash.c
+++ b/board/esd/common/flash.c
@@ -27,7 +27,7 @@
 #endif
 #include <asm/processor.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -167,7 +167,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		/*
 		 * Check if whole sector is erased
 		 */
@@ -221,28 +221,28 @@
 {
 	short i;
 	short n;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
 
-	value = addr2[CFG_FLASH_READ0];
+	value = addr2[CONFIG_SYS_FLASH_READ0];
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
 		info->flash_id = FLASH_MAN_EXCEL;
 		break;
 	default:
@@ -252,104 +252,104 @@
 		return (0);			/* no or unknown flash	*/
 	}
 
-	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
 		info->flash_id += FLASH_AMDL322T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
 		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
 		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
 		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV640U:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV640U:
 		info->flash_id += FLASH_AM640U;
 		info->sector_count = 128;
 		info->size = 0x00800000;  break;	/* => 8 MB	*/
 
 #if !(defined(CONFIG_ADCIOP) || defined(CONFIG_DASA_SIM))
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF800A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF800A:
 		info->flash_id += FLASH_SST800A;
 		info->sector_count = 16;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF160A:
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1601:
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF1602:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF160A:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1601:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF1602:
 		info->flash_id += FLASH_SST160A;
 		info->sector_count = 32;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3201:
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF3202:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3201:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF3202:
 		info->flash_id += FLASH_SST320;
 		info->sector_count = 64;
 		info->size = 0x00400000;
 		break;				/* => 4 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6401:
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF6402:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6401:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF6402:
 		info->flash_id += FLASH_SST640;
 		info->sector_count = 128;
 		info->size = 0x00800000;
@@ -424,19 +424,19 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
 		  info->protect[i] = 0;
 		else
-		  info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+		  info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
 	}
 
 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 	}
 
 	return (info->size);
@@ -448,8 +448,8 @@
 
 int	flash_erase (flash_info_t *info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 	int i;
@@ -490,25 +490,25 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-		    addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+		    addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
 		    if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00500050;  /* block erase */
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00500050;  /* block erase */
 			for (i=0; i<50; i++)
 			  udelay(1000);  /* wait 1 ms */
 		    } else {
 			if (sect == s_first) {
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-			    addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-			    addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+			    addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+			    addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
 			}
-			addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 		    }
 		    l_sect = sect;
 		}
@@ -529,9 +529,9 @@
 
 	start = get_timer (0);
 	last  = start;
-	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -544,8 +544,8 @@
 
 DONE:
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -630,9 +630,9 @@
  */
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
 	int i;
@@ -645,11 +645,11 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
 
-	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++)
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++)
 	  {
-	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	    addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	    addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	    addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	    addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
 
 	    dest2[i] = data2[i];
 
@@ -659,9 +659,9 @@
 
 	    /* data polling for D7 */
 	    start = get_timer (0);
-	    while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-		   (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	    while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		   (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/esd/common/fpga.c b/board/esd/common/fpga.c
index 9e2be7e..5232ddd 100644
--- a/board/esd/common/fpga.c
+++ b/board/esd/common/fpga.c
@@ -36,12 +36,12 @@
 
 #define MAX_ONES               226
 
-#ifdef CFG_FPGA_PRG
-# define FPGA_PRG              CFG_FPGA_PRG	/* FPGA program pin (ppc output) */
-# define FPGA_CLK              CFG_FPGA_CLK	/* FPGA clk pin (ppc output)    */
-# define FPGA_DATA             CFG_FPGA_DATA	/* FPGA data pin (ppc output)  */
-# define FPGA_DONE             CFG_FPGA_DONE	/* FPGA done pin (ppc input)   */
-# define FPGA_INIT             CFG_FPGA_INIT	/* FPGA init pin (ppc input)   */
+#ifdef CONFIG_SYS_FPGA_PRG
+# define FPGA_PRG              CONFIG_SYS_FPGA_PRG	/* FPGA program pin (ppc output) */
+# define FPGA_CLK              CONFIG_SYS_FPGA_CLK	/* FPGA clk pin (ppc output)    */
+# define FPGA_DATA             CONFIG_SYS_FPGA_DATA	/* FPGA data pin (ppc output)  */
+# define FPGA_DONE             CONFIG_SYS_FPGA_DONE	/* FPGA done pin (ppc input)   */
+# define FPGA_INIT             CONFIG_SYS_FPGA_INIT	/* FPGA init pin (ppc input)   */
 #else
 # define FPGA_PRG              0x04000000	/* FPGA program pin (ppc output) */
 # define FPGA_CLK              0x02000000	/* FPGA clk pin (ppc output)     */
@@ -98,7 +98,7 @@
 	int count;
 	unsigned char b;
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	int j;
 #else
 	int bit;
@@ -112,7 +112,7 @@
 		index += len + 3;
 	}
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/* search for preamble 0xFFFFFFFF */
 	while (1) {
 		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
@@ -186,7 +186,7 @@
 	DBG ("write configuration data into fpga\n");
 	/* write configuration-data into fpga... */
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/*
 	 * Load uncompressed image into fpga
 	 */
diff --git a/board/esd/common/lcd.c b/board/esd/common/lcd.c
index c23dc81..1eea59e 100644
--- a/board/esd/common/lcd.c
+++ b/board/esd/common/lcd.c
@@ -37,7 +37,7 @@
 unsigned char *glob_lcd_reg;
 unsigned char *glob_lcd_mem;
 
-#if defined(CFG_LCD_ENDIAN)
+#if defined(CONFIG_SYS_LCD_ENDIAN)
 void lcd_setup(int lcd, int config)
 {
 	if (lcd == 0) {
@@ -47,21 +47,21 @@
 
 		/* set reset to low */
 		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) & ~CFG_LCD0_RST);
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD0_RST);
 		udelay(10); /* wait 10us */
 		if (config == 1) {
 			/* big-endian */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
 		} else {
 			/* little-endian */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
 		}
 		udelay(10); /* wait 10us */
 		/* set reset to high */
 		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) | CFG_LCD0_RST);
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD0_RST);
 	} else {
 		/*
 		 * Set endianess and reset lcd controller 1 (big)
@@ -69,29 +69,29 @@
 
 		/* set reset to low */
 		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) & ~CFG_LCD1_RST);
+			 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD1_RST);
 		udelay(10); /* wait 10us */
 		if (config == 1) {
 			/* big-endian */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
 		} else {
 			/* little-endian */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CFG_LCD_ENDIAN);
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_LCD_ENDIAN);
 		}
 		udelay(10); /* wait 10us */
 		/* set reset to high */
 		out_be32((void*)GPIO0_OR,
-			 in_be32((void*)GPIO0_OR) | CFG_LCD1_RST);
+			 in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD1_RST);
 	}
 
 	/*
-	 * CFG_LCD_ENDIAN may also be FPGA_RESET, so set inactive
+	 * CONFIG_SYS_LCD_ENDIAN may also be FPGA_RESET, so set inactive
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_LCD_ENDIAN);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_LCD_ENDIAN);
 }
-#endif /* CFG_LCD_ENDIAN */
+#endif /* CONFIG_SYS_LCD_ENDIAN */
 
 
 int lcd_bmp(uchar *logo_bmp)
@@ -116,20 +116,20 @@
 		/*
 		 * Decompress bmp image
 		 */
-		len = CFG_VIDEO_LOGO_MAX_SIZE;
-		dst = malloc(CFG_VIDEO_LOGO_MAX_SIZE);
+		len = CONFIG_SYS_VIDEO_LOGO_MAX_SIZE;
+		dst = malloc(CONFIG_SYS_VIDEO_LOGO_MAX_SIZE);
 		if (dst == NULL) {
 			printf("Error: malloc for gunzip failed!\n");
 			return 1;
 		}
-		if (gunzip(dst, CFG_VIDEO_LOGO_MAX_SIZE,
+		if (gunzip(dst, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE,
 			   (uchar *)logo_bmp, &len) != 0) {
 			free(dst);
 			return 1;
 		}
-		if (len == CFG_VIDEO_LOGO_MAX_SIZE) {
+		if (len == CONFIG_SYS_VIDEO_LOGO_MAX_SIZE) {
 			printf("Image could be truncated"
-			       " (increase CFG_VIDEO_LOGO_MAX_SIZE)!\n");
+			       " (increase CONFIG_SYS_VIDEO_LOGO_MAX_SIZE)!\n");
 		}
 
 		/*
diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c
index f711205..dcb764c 100644
--- a/board/esd/common/pci.c
+++ b/board/esd/common/pci.c
@@ -119,24 +119,24 @@
   /*
    * Configure PLX PCI9054
    */
-  pci_read_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, &status);
+  pci_read_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, &status);
   status |= PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY;
-  pci_write_config_word(CFG_PCI9054_DEV_FN, PCI_COMMAND, status);
+  pci_write_config_word(CONFIG_SYS_PCI9054_DEV_FN, PCI_COMMAND, status);
 
   /* Check the latency timer for values >= 0x60.
    */
-  pci_read_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
+  pci_read_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, &timer);
   if (timer < 0x60)
     {
-      pci_write_config_byte(CFG_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
+      pci_write_config_byte(CONFIG_SYS_PCI9054_DEV_FN, PCI_LATENCY_TIMER, 0x60);
     }
 
   /* Set I/O base register.
    */
-  pci_write_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CFG_PCI9054_IOBASE);
-  pci_read_config_dword(CFG_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
+  pci_write_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, CONFIG_SYS_PCI9054_IOBASE);
+  pci_read_config_dword(CONFIG_SYS_PCI9054_DEV_FN, PCI_BASE_ADDRESS_0, &iobase);
 
-  pci9054_iobase = pci_mem_to_phys(CFG_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
+  pci9054_iobase = pci_mem_to_phys(CONFIG_SYS_PCI9054_DEV_FN, iobase & PCI_BASE_ADDRESS_MEM_MASK);
 
   if (pci9054_iobase == 0xffffffff)
     {
@@ -149,13 +149,13 @@
 static struct pci_config_table pci9054_config_table[] = {
 #ifndef CONFIG_PCI_PNP
   { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CFG_ETH_DEV_FN), PCI_DEV(CFG_ETH_DEV_FN), PCI_FUNC(CFG_ETH_DEV_FN),
-    pci_cfgfunc_config_device, { CFG_ETH_IOBASE,
-				 CFG_ETH_IOBASE,
+    PCI_BUS(CONFIG_SYS_ETH_DEV_FN), PCI_DEV(CONFIG_SYS_ETH_DEV_FN), PCI_FUNC(CONFIG_SYS_ETH_DEV_FN),
+    pci_cfgfunc_config_device, { CONFIG_SYS_ETH_IOBASE,
+				 CONFIG_SYS_ETH_IOBASE,
 				 PCI_COMMAND_IO | PCI_COMMAND_MASTER }},
 #ifdef CONFIG_DASA_SIM
   { PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
-    PCI_BUS(CFG_PCI9054_DEV_FN), PCI_DEV(CFG_PCI9054_DEV_FN), PCI_FUNC(CFG_PCI9054_DEV_FN),
+    PCI_BUS(CONFIG_SYS_PCI9054_DEV_FN), PCI_DEV(CONFIG_SYS_PCI9054_DEV_FN), PCI_FUNC(CONFIG_SYS_PCI9054_DEV_FN),
     pci_dasa_sim_config_pci9054 },
 #endif
 #endif
diff --git a/board/esd/common/xilinx_jtag/ports.h b/board/esd/common/xilinx_jtag/ports.h
index 0e38990..b702fdd 100644
--- a/board/esd/common/xilinx_jtag/ports.h
+++ b/board/esd/common/xilinx_jtag/ports.h
@@ -38,12 +38,12 @@
 #define TDI (short) 2
 
 /*
- * Use CFG_FPGA_xxx defines from board include file.
+ * Use CONFIG_SYS_FPGA_xxx defines from board include file.
  */
-#define JTAG_TMS   CFG_FPGA_PRG     /* output */
-#define JTAG_TCK   CFG_FPGA_CLK     /* output */
-#define JTAG_TDI   CFG_FPGA_DATA    /* output */
-#define JTAG_TDO   CFG_FPGA_DONE    /* input */
+#define JTAG_TMS   CONFIG_SYS_FPGA_PRG     /* output */
+#define JTAG_TCK   CONFIG_SYS_FPGA_CLK     /* output */
+#define JTAG_TDI   CONFIG_SYS_FPGA_DATA    /* output */
+#define JTAG_TDO   CONFIG_SYS_FPGA_DONE    /* input */
 
 /* set the port "p" (TCK, TMS, or TDI) to val (0 or 1) */
 void setPort(short p, short val);
diff --git a/board/esd/cpci2dp/cpci2dp.c b/board/esd/cpci2dp/cpci2dp.c
index 8bc40d5..dcab906 100644
--- a/board/esd/cpci2dp/cpci2dp.c
+++ b/board/esd/cpci2dp/cpci2dp.c
@@ -36,12 +36,12 @@
 	 * Setup GPIO pins
 	 */
 	cntrl0Reg = mfdcr(cntrl0);
-	mtdcr(cntrl0, cntrl0Reg | ((CFG_EEPROM_WP | CFG_PB_LED | CFG_SELF_RST | CFG_INTA_FAKE) << 5));
+	mtdcr(cntrl0, cntrl0Reg | ((CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED | CONFIG_SYS_SELF_RST | CONFIG_SYS_INTA_FAKE) << 5));
 
 	/* set output pins to high */
-	out32(GPIO0_OR,  CFG_EEPROM_WP);
+	out32(GPIO0_OR,  CONFIG_SYS_EEPROM_WP);
 	/* setup for output (LED=off) */
-	out32(GPIO0_TCR, CFG_EEPROM_WP | CFG_PB_LED);
+	out32(GPIO0_TCR, CONFIG_SYS_EEPROM_WP | CONFIG_SYS_PB_LED);
 
 	/*
 	 * IRQ 0-15  405GP internally generated; active high; level sensitive
@@ -108,7 +108,7 @@
 	return 0;
 }
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *	   <state>     -1: deliver current state
  *		       0: disable write
@@ -118,23 +118,23 @@
  *		     0/1: current state if <state> was -1.
  */
 int eeprom_write_enable (unsigned dev_addr, int state) {
-	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
 	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 			break;
 		}
 	}
@@ -142,7 +142,7 @@
 }
 #endif
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 int do_eep_wren (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int query = argc == 1;
@@ -150,21 +150,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
 		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts ("Setup of write access state failed.\n");
@@ -179,4 +179,4 @@
 	"eepwren - Enable / disable / query EEPROM write access\n",
 	NULL
 	);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c
index de847f9..56c822e 100644
--- a/board/esd/cpci2dp/flash.c
+++ b/board/esd/cpci2dp/flash.c
@@ -47,7 +47,7 @@
 	unsigned long base_b0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/cpci405/cpci405.c b/board/esd/cpci405/cpci405.c
index fb34957..c5ccb34 100644
--- a/board/esd/cpci405/cpci405.c
+++ b/board/esd/cpci405/cpci405.c
@@ -110,8 +110,8 @@
 	 * First pull fpga-prg pin low, to disable fpga logic (on version 2 board)
 	 */
 	out32(GPIO0_ODR, 0x00000000);	     /* no open drain pins	*/
-	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output	*/
-	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output	*/
+	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
 	out32(GPIO0_OR, 0);		     /* pull prg low		*/
 
 	/*
@@ -282,8 +282,8 @@
 		cntrl0Reg = mfdcr(cntrl0);
 		mtdcr(cntrl0, cntrl0Reg | 0x00300000);
 
-		dst = malloc(CFG_FPGA_MAX_SIZE);
-		if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+		dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+		if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 			printf ("GUNZIP ERROR - must RESET board to recover\n");
 			do_reset (NULL, 0, 0, NULL);
 		}
@@ -347,13 +347,13 @@
 
 #ifdef CONFIG_CPCI405_6U
 		if (cpci405_version() == 3) {
-			volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
-			volatile unsigned char *leds = (unsigned char *)CFG_LED_ADDR;
+			volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
+			volatile unsigned char *leds = (unsigned char *)CONFIG_SYS_LED_ADDR;
 
 			/*
 			 * Enable outputs in fpga on version 3 board
 			 */
-			*fpga_mode |= CFG_FPGA_MODE_ENABLE_OUTPUT;
+			*fpga_mode |= CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT;
 
 			/*
 			 * Set outputs to 0
@@ -363,9 +363,9 @@
 			/*
 			 * Reset external DUART
 			 */
-			*fpga_mode |= CFG_FPGA_MODE_DUART_RESET;
+			*fpga_mode |= CONFIG_SYS_FPGA_MODE_DUART_RESET;
 			udelay(100);
-			*fpga_mode &= ~(CFG_FPGA_MODE_DUART_RESET);
+			*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_DUART_RESET);
 		}
 #endif
 	}
@@ -445,9 +445,9 @@
 
 #if 0 /* test-only */
 	if (ver >= 2) {
-		volatile u16 *fpga_status = (u16 *)CFG_FPGA_BASE_ADDR + 1;
+		volatile u16 *fpga_status = (u16 *)CONFIG_SYS_FPGA_BASE_ADDR + 1;
 
-		if (*fpga_status & CFG_FPGA_STATUS_FLASH) {
+		if (*fpga_status & CONFIG_SYS_FPGA_STATUS_FLASH) {
 			puts ("FLASH Bank B, ");
 		} else {
 			puts ("FLASH Bank A, ");
@@ -504,15 +504,15 @@
 
 void ide_set_reset(int on)
 {
-	volatile unsigned short *fpga_mode = (unsigned short *)CFG_FPGA_BASE_ADDR;
+	volatile unsigned short *fpga_mode = (unsigned short *)CONFIG_SYS_FPGA_BASE_ADDR;
 
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		*fpga_mode &= ~(CFG_FPGA_MODE_CF_RESET);
+		*fpga_mode &= ~(CONFIG_SYS_FPGA_MODE_CF_RESET);
 	} else {		/* release RESET */
-		*fpga_mode |= CFG_FPGA_MODE_CF_RESET;
+		*fpga_mode |= CONFIG_SYS_FPGA_MODE_CF_RESET;
 	}
 }
 
@@ -555,12 +555,12 @@
 
 #ifdef CONFIG_CPCI405AB
 
-#define ONE_WIRE_CLEAR	 (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
-			  |= CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_SET	 (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_MODE) \
-			  &= ~CFG_FPGA_MODE_1WIRE_DIR)
-#define ONE_WIRE_GET	 (*(volatile unsigned short *)(CFG_FPGA_BASE_ADDR + CFG_FPGA_STATUS) \
-			  & CFG_FPGA_MODE_1WIRE)
+#define ONE_WIRE_CLEAR	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+			  |= CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_SET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_MODE) \
+			  &= ~CONFIG_SYS_FPGA_MODE_1WIRE_DIR)
+#define ONE_WIRE_GET	 (*(volatile unsigned short *)(CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_STATUS) \
+			  & CONFIG_SYS_FPGA_MODE_1WIRE)
 
 /*
  * Generate a 1-wire reset, return 1 if no presence detect was found,
@@ -690,7 +690,7 @@
 	NULL
 	);
 
-#define CFG_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
+#define CONFIG_SYS_I2C_EEPROM_ADDR_2	0x51	/* EEPROM CAT28WC32		*/
 #define CONFIG_ENV_SIZE_2	0x800	/* 2048 bytes may be used for env vars*/
 
 /*
@@ -706,7 +706,7 @@
 	IPaddr_t ipaddr;
 
 	buf = malloc(CONFIG_ENV_SIZE_2);
-	if (eeprom_read(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
 		puts("\nError reading backplane EEPROM!\n");
 	} else {
 		crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
@@ -771,7 +771,7 @@
 	crc = crc32(0, (uchar *)(buf+4), CONFIG_ENV_SIZE_2-4);
 	*(ulong *)buf = crc;
 
-	if (eeprom_write(CFG_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
+	if (eeprom_write(CONFIG_SYS_I2C_EEPROM_ADDR_2, 0, (uchar *)buf, CONFIG_ENV_SIZE_2)) {
 		puts("\nError writing backplane EEPROM!\n");
 	}
 
diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c
index e766895..d535924 100644
--- a/board/esd/cpci405/flash.c
+++ b/board/esd/cpci405/flash.c
@@ -66,7 +66,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/cpci5200/cpci5200.c b/board/esd/cpci5200/cpci5200.c
index 2a42e65..6eedb83 100644
--- a/board/esd/cpci5200/cpci5200.c
+++ b/board/esd/cpci5200/cpci5200.c
@@ -81,7 +81,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -106,9 +106,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
 
 	if (test1 > test2) {
 		sdram_start(0);
@@ -144,9 +144,9 @@
 #if 0
 	/* find RAM size using SDRAM CS1 only */
 	sdram_start(0);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(1);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(0);
 #endif
 	/* set SDRAM CS1 size according to the amount of RAM found */
@@ -180,10 +180,10 @@
 		/* adjust mapping */
 		*(vu_long *) MPC5XXX_BOOTCS_START =
 		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CFG_BOOTCS_START | size);
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
 		*(vu_long *) MPC5XXX_BOOTCS_STOP =
 		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CFG_BOOTCS_START | size, size);
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 }
 
diff --git a/board/esd/cpci5200/strataflash.c b/board/esd/cpci5200/strataflash.c
index d76af02..9b578b5 100644
--- a/board/esd/cpci5200/strataflash.c
+++ b/board/esd/cpci5200/strataflash.c
@@ -102,7 +102,7 @@
 
 #define NUM_ERASE_REGIONS 4
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -121,7 +121,7 @@
 			       cfiword_t cword);
 static int flash_full_status_check(flash_info_t * info, ulong sector,
 				   ulong tout, char *prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp,
 				 int len);
 #endif
@@ -185,14 +185,14 @@
 	 *
 	 */
 
-	address = CFG_FLASH_BASE;
+	address = CONFIG_SYS_FLASH_BASE;
 	size = 0;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		size += flash_info[i].size = flash_get_size(address, i);
-		address += CFG_FLASH_INCREMENT;
+		address += CONFIG_SYS_FLASH_INCREMENT;
 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 			printf
 			    ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",
@@ -202,9 +202,9 @@
 
 #if 0				/* test-only */
 	/* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
 	for (i = 0;
-	     flash_info[0].start[i] < CFG_MONITOR_BASE + monitor_flash_len - 1;
+	     flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1;
 	     i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
@@ -326,7 +326,7 @@
 			return rc;
 		wp = cp;
 	}
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while (cnt >= info->portwidth) {
 		i = info->buffer_size > cnt ? cnt : info->buffer_size;
 		if ((rc = flash_write_cfibuffer(info, wp, src, i)) != ERR_OK)
@@ -347,7 +347,7 @@
 		wp += info->portwidth;
 		cnt -= info->portwidth;
 	}
-#endif				/* CFG_FLASH_USE_BUFFER_WRITE */
+#endif				/* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 	if (cnt == 0) {
 		return (0);
 	}
@@ -727,7 +727,7 @@
 	return flash_full_status_check(info, 0, info->write_tout, "write");
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* loop through the sectors from the highest address
  * when the passed address is greater or equal to the sector address
@@ -801,4 +801,4 @@
 	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 	return retcode;
 }
-#endif				/* CFG_USE_FLASH_BUFFER_WRITE */
+#endif				/* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/esd/cpci750/cpci750.c b/board/esd/cpci750/cpci750.c
index 5ab76c6..70bae60 100644
--- a/board/esd/cpci750/cpci750.c
+++ b/board/esd/cpci750/cpci750.c
@@ -125,7 +125,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -134,7 +134,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 
 /* ------------------------------------------------------------------------- */
@@ -197,7 +197,7 @@
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/*if  PCI-X */
@@ -206,7 +206,7 @@
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -224,21 +224,21 @@
 	/* ronen- add write to pci remap registers for 64460.
 	   in 64360 when writing to pci base go and overide remap automaticaly,
 	   in 64460 it doesn't */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -254,7 +254,7 @@
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -270,7 +270,7 @@
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 
 	/* set the SINGLE_CPU bit  see MV64360 P.399 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 
@@ -320,7 +320,7 @@
 	 * it last time. (huber)
 	 */
 
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	/* No PCI in first release of Port To_do: enable it. */
 #ifdef CONFIG_PCI
@@ -364,45 +364,45 @@
 	 * registers to boot from the sram. (device0)
 	 */
 
-	memoryMapDeviceSpace (DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-	memoryMapDeviceSpace (DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace (DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace (DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace (DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+	memoryMapDeviceSpace (DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace (DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace (DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 
 	/* configure device timing */
-	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
-	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
-	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
-	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_DEV3_PAR);
+	GT_REG_WRITE (DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
+	GT_REG_WRITE (DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
+	GT_REG_WRITE (DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
+	GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_DEV3_PAR);
 
-#ifdef CFG_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR	/* set port parameters for Flash device module access */
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD (DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS,
-			      CFG_32BIT_BOOT_PAR);
+			      CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE (DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);*/
+/*	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);*/
 #endif
 
 
 	gt_cpu_config ();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 	DEBUG_LED0_ON ();
 	DEBUG_LED1_ON ();
 	DEBUG_LED2_ON ();
@@ -415,7 +415,7 @@
 int misc_init_r ()
 {
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -428,19 +428,19 @@
 	/* disable the dcache and MMU */
 	dcache_lock ();
 #endif
-	if (flash_info[3].size < CFG_FLASH_INCREMENT) {
+	if (flash_info[3].size < CONFIG_SYS_FLASH_INCREMENT) {
 		unsigned int flash_offset;
 		unsigned int l;
 
-		flash_offset =  CFG_FLASH_INCREMENT - flash_info[3].size;
-		for (l = 0; l < CFG_MAX_FLASH_SECT; l++) {
+		flash_offset =  CONFIG_SYS_FLASH_INCREMENT - flash_info[3].size;
+		for (l = 0; l < CONFIG_SYS_MAX_FLASH_SECT; l++) {
 			if (flash_info[3].start[l] != 0) {
 			      flash_info[3].start[l] += flash_offset;
 			}
 		}
 		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len  - 1,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len  - 1,
 			       &flash_info[3]);
 	}
 	return 0;
@@ -449,7 +449,7 @@
 void after_reloc (ulong dest_addr, gd_t * gd)
 {
 
-  memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+  memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
 
   display_mem_map ();
   /* now, jump to the main ppcboot board init code */
@@ -469,7 +469,7 @@
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
@@ -540,7 +540,7 @@
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -571,7 +571,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaLL,
@@ -634,7 +634,7 @@
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -661,9 +661,9 @@
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -688,8 +688,8 @@
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -706,9 +706,9 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -766,7 +766,7 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -798,8 +798,8 @@
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -865,23 +865,23 @@
 	int runaddress = 0;
 	int runwalk    = 0;
 
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	s = getenv ("testdramdata");
 	rundata = (s && (*s == 'y')) ? 1 : 0;
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	s = getenv ("testdramaddress");
 	runaddress = (s && (*s == 'y')) ? 1 : 0;
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	s = getenv ("testdramwalk");
 	runwalk = (s && (*s == 'y')) ? 1 : 0;
 #endif
 
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
-		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CFG_MEMTEST_START, CFG_MEMTEST_END);
+		printf ("Testing RAM from 0x%08x to 0x%08x ...  (don't panic... that will take a moment !!!!)\n", CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -891,7 +891,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -901,7 +901,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -917,7 +917,7 @@
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function		*/
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
@@ -956,7 +956,7 @@
 /*      GV_REG_WRITE (MV64360_ETH_RECEIVE_QUEUE_COMMAND_REG (2), 0x0000ff00); */
 
 /* Relocate MV64360 internal regs */
-	my_remap_gt_regs_bootm (CFG_GT_REGS, CFG_DFL_GT_REGS);
+	my_remap_gt_regs_bootm (CONFIG_SYS_GT_REGS, CONFIG_SYS_DFL_GT_REGS);
 
 	icache_disable ();
 	dcache_disable ();
diff --git a/board/esd/cpci750/i2c.c b/board/esd/cpci750/i2c.c
index 5b1bc01..d95567f 100644
--- a/board/esd/cpci750/i2c.c
+++ b/board/esd/cpci750/i2c.c
@@ -46,7 +46,7 @@
 	unsigned int n, m, freq, margin, power;
 	unsigned int actualN = 0, actualM = 0;
 	unsigned int minMargin = 0xffffffff;
-	unsigned int tclk = CFG_TCLK;
+	unsigned int tclk = CONFIG_SYS_TCLK;
 	unsigned int i2cFreq = speed;	/* 100000 max. Fast mode not supported */
 
 	DP (puts ("i2c_init\n"));
@@ -380,7 +380,7 @@
 	  int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_read\n"));
 
@@ -428,7 +428,7 @@
 	   int len)
 {
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_write\n"));
 
@@ -464,7 +464,7 @@
 	unsigned int i2c_status;
 #endif
 	uchar status = 0;
-	unsigned int i2cFreq = CFG_I2C_SPEED;
+	unsigned int i2cFreq = CONFIG_SYS_I2C_SPEED;
 
 	DP (puts ("i2c_probe\n"));
 
diff --git a/board/esd/cpci750/ide.c b/board/esd/cpci750/ide.c
index 0adafe2..9bdc523 100644
--- a/board/esd/cpci750/ide.c
+++ b/board/esd/cpci750/ide.c
@@ -30,7 +30,7 @@
 #include <ide.h>
 #include <pci.h>
 
-extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 
 int ide_preinit (void)
 {
@@ -39,7 +39,7 @@
 	int l;
 
 	status = 1;
-	for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
 	devbusfn = pci_find_device (0x1103, 0x0004, 0);
@@ -51,11 +51,11 @@
 		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_0,
 				       (u32 *) & ide_bus_offset[0]);
 		ide_bus_offset[0] &= 0xfffffffe;
-		ide_bus_offset[0] += CFG_PCI0_IO_SPACE;
+		ide_bus_offset[0] += CONFIG_SYS_PCI0_IO_SPACE;
 		pci_read_config_dword (devbusfn, PCI_BASE_ADDRESS_2,
 				       (u32 *) & ide_bus_offset[1]);
 		ide_bus_offset[1] &= 0xfffffffe;
-		ide_bus_offset[1] += CFG_PCI0_IO_SPACE;
+		ide_bus_offset[1] += CONFIG_SYS_PCI0_IO_SPACE;
 	}
 	return (status);
 }
diff --git a/board/esd/cpci750/local.h b/board/esd/cpci750/local.h
index bca0e1f..de3758a 100644
--- a/board/esd/cpci750/local.h
+++ b/board/esd/cpci750/local.h
@@ -48,7 +48,7 @@
 /* #define CONFIG_BOOTCOMMAND */
 /* #define CONFIG_RAMBOOTCOMMAND */
 /* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CFG_AUTOLOAD */
+/* #define CONFIG_SYS_AUTOLOAD */
 /* #define CONFIG_PREBOOT */
 
 /* These don't */
diff --git a/board/esd/cpci750/misc.S b/board/esd/cpci750/misc.S
index 160b1d3..233fd83 100644
--- a/board/esd/cpci750/misc.S
+++ b/board/esd/cpci750/misc.S
@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */
@@ -153,11 +153,11 @@
 	cmp	cr0, r7, r6
 	bne	1b
 
-	lis	r3, CFG_INT_SRAM_BASE@h
-	ori	r3, r3, CFG_INT_SRAM_BASE@l
+	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
+	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
 	rlwinm  r3, r3, 16, 16, 31
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTEGRATED_SRAM_BASE_ADDR
 	stwbrx  r3, r5, r4
 
diff --git a/board/esd/cpci750/mpsc.c b/board/esd/cpci750/mpsc.c
index fa8d3bd..c89426d 100644
--- a/board/esd/cpci750/mpsc.c
+++ b/board/esd/cpci750/mpsc.c
@@ -427,7 +427,7 @@
 			  (MV64360_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 /* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 /* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -517,9 +517,9 @@
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
diff --git a/board/esd/cpci750/pci.c b/board/esd/cpci750/pci.c
index c335ebf..cbe766f 100644
--- a/board/esd/cpci750/pci.c
+++ b/board/esd/cpci750/pci.c
@@ -932,14 +932,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -981,14 +981,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
diff --git a/board/esd/cpci750/sdram_init.c b/board/esd/cpci750/sdram_init.c
index 0291937..4c03630 100644
--- a/board/esd/cpci750/sdram_init.c
+++ b/board/esd/cpci750/sdram_init.c
@@ -350,7 +350,7 @@
 	} else
 		dimmInfo->slot = slot;	/* start to fill up dimminfo for this "slot" */
 
-#ifdef CFG_DISPLAY_DIMM_SPD_CONTENT
+#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 
 	for (i = 0; i <= 127; i++) {
 		printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
@@ -1656,13 +1656,13 @@
 	if (dimmInfo2.numOfModuleBanks > 2)
 		printf("Error, SPD claims DIMM2 has >2 banks\n");
 
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (! checkbank[bank_no])
 			continue;
 
-		if ((total + check) > CFG_GT_REGS)
-			check = CFG_GT_REGS - total;
+		if ((total + check) > CONFIG_SYS_GT_REGS)
+			check = CONFIG_SYS_GT_REGS - total;
 
 		memory_map_bank(bank_no, total, check);
 		realsize = dram_size((long int *)total, check);
diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c
index de847f9..56c822e 100644
--- a/board/esd/cpciiser4/flash.c
+++ b/board/esd/cpciiser4/flash.c
@@ -47,7 +47,7 @@
 	unsigned long base_b0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/dasa_sim/cmd_dasa_sim.c b/board/esd/dasa_sim/cmd_dasa_sim.c
index 89a4aaf..36dd58c 100644
--- a/board/esd/dasa_sim/cmd_dasa_sim.c
+++ b/board/esd/dasa_sim/cmd_dasa_sim.c
@@ -48,13 +48,13 @@
 	unsigned int ret;
 	int count;
 
-	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
 				(offs << 16) | 0x0003);
 	count = 0;
 
 	for (;;) {
 		udelay (10 * 1000);
-		pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+		pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
 		if ((ret & 0x80000000) != 0) {
 			break;
 		} else {
@@ -66,7 +66,7 @@
 		}
 	}
 
-	pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x50, &value);
+	pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, &value);
 
 	return value;
 }
@@ -77,14 +77,14 @@
 	unsigned int ret;
 	int count;
 
-	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x50, value);
-	pci_write_config_dword (CFG_PCI9054_DEV_FN, 0x4c,
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x50, value);
+	pci_write_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c,
 				(offs << 16) | 0x80000003);
 	count = 0;
 
 	for (;;) {
 		udelay (10 * 1000);
-		pci_read_config_dword (CFG_PCI9054_DEV_FN, 0x4c, &ret);
+		pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN, 0x4c, &ret);
 		if ((ret & 0x80000000) == 0) {
 			break;
 		} else {
@@ -109,7 +109,7 @@
 	for (l = 0; l < 6; l++) {
 		printf ("%02x: ", l * 0x10);
 		for (i = 0; i < 4; i++) {
-			pci_read_config_dword (CFG_PCI9054_DEV_FN,
+			pci_read_config_dword (CONFIG_SYS_PCI9054_DEV_FN,
 						l * 16 + i * 4,
 						(unsigned int *)&val);
 			printf ("%08x ", val);
diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c
index d2ac13f..9c71b04 100644
--- a/board/esd/dasa_sim/flash.c
+++ b/board/esd/dasa_sim/flash.c
@@ -47,7 +47,7 @@
 	unsigned long base_b0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/dp405/flash.c
+++ b/board/esd/dp405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c
index 14549c0..240aa09 100644
--- a/board/esd/du405/flash.c
+++ b/board/esd/du405/flash.c
@@ -47,7 +47,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/du440/config.mk b/board/esd/du440/config.mk
index 5164334..91e65ec 100644
--- a/board/esd/du440/config.mk
+++ b/board/esd/du440/config.mk
@@ -33,5 +33,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c
index 6dca35d..2f97a12 100644
--- a/board/esd/du440/du440.c
+++ b/board/esd/du440/du440.c
@@ -29,7 +29,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 extern ulong flash_get_size (ulong base, int banknum);
 
 int usbhub_init(void);
@@ -51,8 +51,8 @@
 	/*
 	 * Setup the GPIO pins
 	 */
-	out_be32((void*)GPIO0_OR, 0x00000000 | CFG_GPIO0_EP_EEP);
-	out_be32((void*)GPIO0_TCR, 0x0000001f | CFG_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_OR, 0x00000000 | CONFIG_SYS_GPIO0_EP_EEP);
+	out_be32((void*)GPIO0_TCR, 0x0000001f | CONFIG_SYS_GPIO0_EP_EEP);
 	out_be32((void*)GPIO0_OSRL, 0x50055400);
 	out_be32((void*)GPIO0_OSRH, 0x55005000);
 	out_be32((void*)GPIO0_TSRL, 0x50055400);
@@ -66,13 +66,13 @@
 
 	out_be32((void*)GPIO1_OR, 0x00000000);
 	out_be32((void*)GPIO1_TCR, 0xc2000000 |
-		 CFG_GPIO1_IORSTN |
-		 CFG_GPIO1_IORST2N |
-		 CFG_GPIO1_LEDUSR1 |
-		 CFG_GPIO1_LEDUSR2 |
-		 CFG_GPIO1_LEDPOST |
-		 CFG_GPIO1_LEDDU);
-	out_be32((void*)GPIO1_ODR, CFG_GPIO1_LEDDU);
+		 CONFIG_SYS_GPIO1_IORSTN |
+		 CONFIG_SYS_GPIO1_IORST2N |
+		 CONFIG_SYS_GPIO1_LEDUSR1 |
+		 CONFIG_SYS_GPIO1_LEDUSR2 |
+		 CONFIG_SYS_GPIO1_LEDPOST |
+		 CONFIG_SYS_GPIO1_LEDDU);
+	out_be32((void*)GPIO1_ODR, CONFIG_SYS_GPIO1_LEDDU);
 	out_be32((void*)GPIO1_OSRL, 0x0c280000);
 	out_be32((void*)GPIO1_OSRH, 0x00000000);
 	out_be32((void*)GPIO1_TSRL, 0xcc000000);
@@ -154,8 +154,8 @@
 		SDR0_CUST0_NDFC_ENABLE		|
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
-		(0x80000000 >> (28 + CFG_NAND0_CS)) |
-		(0x80000000 >> (28 + CFG_NAND1_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND0_CS)) |
+		(0x80000000 >> (28 + CONFIG_SYS_NAND1_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	return 0;
@@ -273,7 +273,7 @@
 	 * We have to wait at least 560ms until we may call usbhub_init
 	 */
 	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) |
-		 CFG_GPIO1_IORSTN | CFG_GPIO1_IORST2N);
+		 CONFIG_SYS_GPIO1_IORSTN | CONFIG_SYS_GPIO1_IORST2N);
 
 	/*
 	 * flash USR1/2 LEDs (600ms)
@@ -282,22 +282,22 @@
 	 */
 	for (j = 0; j < 3; j++) {
 		out_be32((void*)GPIO1_OR,
-			 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR2) |
-			 CFG_GPIO1_LEDUSR1);
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR2) |
+			 CONFIG_SYS_GPIO1_LEDUSR1);
 
 		for (i = 0; i < 100; i++)
 			udelay(1000);
 
 		out_be32((void*)GPIO1_OR,
-			 (in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDUSR1) |
-			 CFG_GPIO1_LEDUSR2);
+			 (in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDUSR1) |
+			 CONFIG_SYS_GPIO1_LEDUSR2);
 
 		for (i = 0; i < 100; i++)
 			udelay(1000);
 	}
 
 	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) &
-		 ~(CFG_GPIO1_LEDUSR1 | CFG_GPIO1_LEDUSR2));
+		 ~(CONFIG_SYS_GPIO1_LEDUSR1 | CONFIG_SYS_GPIO1_LEDUSR2));
 
 	if (usbhub_init())
 		du440_post_errors++;
@@ -310,14 +310,14 @@
 
 int pld_revision(void)
 {
-	out8(CFG_CPLD_BASE, 0x00);
-	return (int)(in8(CFG_CPLD_BASE) & CPLD_VERSION_MASK);
+	out8(CONFIG_SYS_CPLD_BASE, 0x00);
+	return (int)(in8(CONFIG_SYS_CPLD_BASE) & CPLD_VERSION_MASK);
 }
 
 int board_revision(void)
 {
-	int rpins = (int)((in_be32((void*)GPIO1_IR) & CFG_GPIO1_HWVER_MASK)
-			  >> CFG_GPIO1_HWVER_SHIFT);
+	int rpins = (int)((in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_HWVER_MASK)
+			  >> CONFIG_SYS_GPIO1_HWVER_SHIFT);
 
 	return ((rpins & 1) << 3) | ((rpins & 2) << 1) |
 		((rpins & 4) >> 1) | ((rpins & 8) >> 3);
@@ -328,7 +328,7 @@
 {
 	if ((timestamp % 100) == 0)
 		out_be32((void*)GPIO1_OR,
-			 in_be32((void*)GPIO1_OR) ^ CFG_GPIO1_LEDUSR1);
+			 in_be32((void*)GPIO1_OR) ^ CONFIG_SYS_GPIO1_LEDUSR1);
 }
 
 void show_activity(int arg)
@@ -421,7 +421,7 @@
  * inbound map (PIM). But the bootstrap config choices are limited and
  * may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*
@@ -437,16 +437,16 @@
 	 */
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
@@ -479,9 +479,9 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -496,7 +496,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*
  * is_pci_host
@@ -524,18 +524,18 @@
 	int e, i;
 
 	/* everyting is ok: turn on POST-LED */
-	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+	out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
 
 	/* slowly blink on errors and finally keep LED off */
 	for (e = 0; e < du440_post_errors; e++) {
 		out_be32((void*)GPIO1_OR,
-			 in_be32((void*)GPIO1_OR) | CFG_GPIO1_LEDPOST);
+			 in_be32((void*)GPIO1_OR) | CONFIG_SYS_GPIO1_LEDPOST);
 
 		for (i = 0; i < 500; i++)
 			udelay(1000);
 
 		out_be32((void*)GPIO1_OR,
-			 in_be32((void*)GPIO1_OR) & ~CFG_GPIO1_LEDPOST);
+			 in_be32((void*)GPIO1_OR) & ~CONFIG_SYS_GPIO1_LEDPOST);
 
 		for (i = 0; i < 500; i++)
 			udelay(1000);
@@ -583,9 +583,9 @@
 		printf("ERROR - no signal\n");
 
 	t1 = t2 = 0;
-	pinold = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+	pinold = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
 	while (!ctrlc()) {
-		pin = in_be32((void*)GPIO1_IR) & CFG_GPIO1_DCF77;
+		pin = in_be32((void*)GPIO1_IR) & CONFIG_SYS_GPIO1_DCF77;
 		if (pin && !pinold) { /* bit start */
 			t1 = get_ticks();
 			if (t2 && ((unsigned int)(t1 - t2) /
@@ -661,7 +661,7 @@
 	);
 #endif /* CONFIG_I2C_MULTI_BUS */
 
-#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
 int boot_eeprom_write (unsigned dev_addr,
 		       unsigned offset,
 		       uchar *buffer,
@@ -671,7 +671,7 @@
 	unsigned blk_off;
 	int rcode = 0;
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 	eeprom_write_enable(dev_addr, 1);
 #endif
 	/*
@@ -700,9 +700,9 @@
 		 * bytes that can be ccessed with the single read or write
 		 * operation.
 		 */
-#if defined(CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#if defined(CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 
-#define	BOOT_EEPROM_PAGE_SIZE (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define	BOOT_EEPROM_PAGE_SIZE (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 #define BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 
 		maxlen = BOOT_EEPROM_PAGE_SIZE -
@@ -722,11 +722,11 @@
 		buffer += len;
 		offset += len;
 
-#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
-		udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 	}
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 	eeprom_write_enable(dev_addr, 0);
 #endif
 	return rcode;
@@ -779,7 +779,7 @@
 	}
 
 	printf("Writing boot EEPROM ...\n");
-	if (boot_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+	if (boot_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
 			      0, (uchar*)sdsdp, 16) != 0)
 		printf("boot_eeprom_write failed\n");
 	else
@@ -793,7 +793,7 @@
 	NULL
 	);
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /*
  * Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
@@ -805,27 +805,27 @@
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-	if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
-	    (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr))
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr))
 		return -1;
 	else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CFG_GPIO0_EP_EEP);
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_GPIO0_EP_EEP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CFG_GPIO0_EP_EEP);
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_GPIO0_EP_EEP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
 			state = (0 == (in_be32((void*)GPIO0_OR) &
-				       CFG_GPIO0_EP_EEP));
+				       CONFIG_SYS_GPIO0_EP_EEP));
 			break;
 		}
 	}
@@ -839,21 +839,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0)
 			puts ("Query of write access state failed.\n");
 		else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0)
 			puts ("Setup of write access state failed.\n");
@@ -865,19 +865,19 @@
 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
 static int got_pldirq;
 
 static int pld_interrupt(u32 arg)
 {
 	int rc = -1; /* not for us */
-	u8 status = in8(CFG_CPLD_BASE);
+	u8 status = in8(CONFIG_SYS_CPLD_BASE);
 
 	/* check for PLD interrupt */
 	if (status & PWR_INT_FLAG) {
 		/* reset this int */
-		out8(CFG_CPLD_BASE, 0);
+		out8(CONFIG_SYS_CPLD_BASE, 0);
 		rc = 0;
 		got_pldirq = 1; /* trigger backend */
 	}
@@ -890,7 +890,7 @@
 	got_pldirq = 0;
 
 	/* clear any pending interrupt */
-	out8(CFG_CPLD_BASE, 0);
+	out8(CONFIG_SYS_CPLD_BASE, 0);
 
 	irq_install_handler(CPLD_IRQ,
 			    (interrupt_handler_t *)pld_interrupt, 0);
@@ -906,7 +906,7 @@
 	if (got_pldirq) {
 		printf("Got interrupt!\n");
 		printf("Power %sready!\n",
-		       in8(CFG_CPLD_BASE) & PWR_RDY ? "":"NOT ");
+		       in8(CONFIG_SYS_CPLD_BASE) & PWR_RDY ? "":"NOT ");
 	}
 
 	irq_free_handler(CPLD_IRQ);
@@ -970,7 +970,7 @@
 int do_time(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	unsigned long long start, end;
-	char c, cmd[CFG_CBSIZE];
+	char c, cmd[CONFIG_SYS_CBSIZE];
 	char *p, *d = cmd;
 	int ret, i;
 	ulong us;
@@ -998,7 +998,7 @@
 	return ret;
 }
 U_BOOT_CMD(
-	time,	CFG_MAXARGS,	1,	do_time,
+	time,	CONFIG_SYS_MAXARGS,	1,	do_time,
 	"time    - run command and output execution time\n",
 	NULL
 	);
@@ -1048,7 +1048,7 @@
 	return 0;
 }
 U_BOOT_CMD(
-	gfxdemo,	CFG_MAXARGS,	1,	do_gfxdemo,
+	gfxdemo,	CONFIG_SYS_MAXARGS,	1,	do_gfxdemo,
 	"gfxdemo - demo\n",
 	NULL
 	);
diff --git a/board/esd/du440/du440.h b/board/esd/du440/du440.h
index 83fdac7..a124a7e 100644
--- a/board/esd/du440/du440.h
+++ b/board/esd/du440/du440.h
@@ -20,18 +20,18 @@
 
 #define SDR0_USB0		0x0320     /* USB Control Register */
 
-#define CFG_GPIO0_EP_EEP	(0x80000000 >> 23)       /* GPIO0_23 */
-#define CFG_GPIO1_DCF77		(0x80000000 >> (42-32))  /* GPIO1_42 */
+#define CONFIG_SYS_GPIO0_EP_EEP	(0x80000000 >> 23)       /* GPIO0_23 */
+#define CONFIG_SYS_GPIO1_DCF77		(0x80000000 >> (42-32))  /* GPIO1_42 */
 
-#define CFG_GPIO1_IORSTN	(0x80000000 >> (55-32))  /* GPIO1_55 */
-#define CFG_GPIO1_IORST2N	(0x80000000 >> (47-32))  /* GPIO1_47 */
+#define CONFIG_SYS_GPIO1_IORSTN	(0x80000000 >> (55-32))  /* GPIO1_55 */
+#define CONFIG_SYS_GPIO1_IORST2N	(0x80000000 >> (47-32))  /* GPIO1_47 */
 
-#define CFG_GPIO1_HWVER_MASK	0x000000f0 /* GPIO1_56-59 */
-#define CFG_GPIO1_HWVER_SHIFT	4
-#define CFG_GPIO1_LEDUSR1	0x00000008 /* GPIO1_60 */
-#define CFG_GPIO1_LEDUSR2	0x00000004 /* GPIO1_61 */
-#define CFG_GPIO1_LEDPOST	0x00000002 /* GPIO1_62 */
-#define CFG_GPIO1_LEDDU		0x00000001 /* GPIO1_63 */
+#define CONFIG_SYS_GPIO1_HWVER_MASK	0x000000f0 /* GPIO1_56-59 */
+#define CONFIG_SYS_GPIO1_HWVER_SHIFT	4
+#define CONFIG_SYS_GPIO1_LEDUSR1	0x00000008 /* GPIO1_60 */
+#define CONFIG_SYS_GPIO1_LEDUSR2	0x00000004 /* GPIO1_61 */
+#define CONFIG_SYS_GPIO1_LEDPOST	0x00000002 /* GPIO1_62 */
+#define CONFIG_SYS_GPIO1_LEDDU		0x00000001 /* GPIO1_63 */
 
 #define CPLD_VERSION_MASK	0x0f
 #define PWR_INT_FLAG		0x80
diff --git a/board/esd/du440/init.S b/board/esd/du440/init.S
index 4390b50..3cac6b1 100644
--- a/board/esd/du440/init.S
+++ b/board/esd/du440/init.S
@@ -44,30 +44,30 @@
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M,  CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M,  CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for PCI IO */
-	tlbentry( CFG_PCI_IOBASE, SZ_64K, CFG_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_IOBASE, SZ_64K, CONFIG_SYS_PCI_IOBASE, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entries for EBC:	 CPLD, DUMEM, DUIO */
-	tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_DUMEM_BASE, SZ_1M, CFG_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_DUIO_BASE, SZ_64K, CFG_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_DUMEM_BASE, SZ_1M, CONFIG_SYS_DUMEM_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_DUIO_BASE, SZ_64K, CONFIG_SYS_DUIO_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for NAND */
-	tlbentry( CFG_NAND0_ADDR, SZ_1K, CFG_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_NAND1_ADDR, SZ_1K, CFG_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_NAND0_ADDR, SZ_1K, CONFIG_SYS_NAND0_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_NAND1_ADDR, SZ_1K, CONFIG_SYS_NAND1_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
 	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
diff --git a/board/esd/du440/u-boot.lds b/board/esd/du440/u-boot.lds
index b20fb1c..3cfec83 100644
--- a/board/esd/du440/u-boot.lds
+++ b/board/esd/du440/u-boot.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/hh405/flash.c
+++ b/board/esd/hh405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/hh405/hh405.c b/board/esd/hh405/hh405.c
index 9fc41c8..efadf16 100644
--- a/board/esd/hh405/hh405.c
+++ b/board/esd/hh405/hh405.c
@@ -345,7 +345,7 @@
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
 	mtdcr(uicer, 0x00000000);       /* disable all ints */
 	mtdcr(uiccr, 0x00000000);       /* set all to be non-critical*/
-	mtdcr(uicpr, CFG_UIC0_POLARITY);/* set int polarities */
+	mtdcr(uicpr, CONFIG_SYS_UIC0_POLARITY);/* set int polarities */
 	mtdcr(uictr, 0x10000000);       /* set int trigger levels */
 	mtdcr(uicvcr, 0x00000001);      /* set vect base=0,INT0 highest priority*/
 	mtdcr(uicsr, 0xFFFFFFFF);       /* clear all ints */
@@ -363,26 +363,26 @@
 	int i;
 
 	volatile unsigned short *fpga_ctrl =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 	volatile unsigned short *fpga_status =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
 
 	if (gd->board_type >= 2) {
-		if (*fpga_status & CFG_FPGA_STATUS_CF_DETECT) {
-			if (!(*fpga_ctrl & CFG_FPGA_CTRL_CF_BUS_EN)) {
-				*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_PWRN;
+		if (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT) {
+			if (!(*fpga_ctrl & CONFIG_SYS_FPGA_CTRL_CF_BUS_EN)) {
+				*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_PWRN;
 
 				for (i=0; i<300; i++)
 					udelay(1000);
 
-				*fpga_ctrl |= CFG_FPGA_CTRL_CF_BUS_EN;
+				*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
 
 				for (i=0; i<20; i++)
 					udelay(1000);
 			}
 		} else {
-			*fpga_ctrl &= ~CFG_FPGA_CTRL_CF_BUS_EN;
-			*fpga_ctrl |= CFG_FPGA_CTRL_CF_PWRN;
+			*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_CF_BUS_EN;
+			*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_CF_PWRN;
 		}
 	}
 
@@ -392,11 +392,11 @@
 int misc_init_r (void)
 {
 	volatile unsigned short *fpga_ctrl =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 	volatile unsigned short *lcd_contrast =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
 	volatile unsigned short *lcd_backlight =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
 	int status;
@@ -405,8 +405,8 @@
 	char *str;
 	unsigned long contrast0 = 0xffffffff;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -474,22 +474,22 @@
 	/*
 	 * Setup and enable EEPROM write protection
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 
 	/*
 	 * Reset touch-screen controller
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_TOUCH_RST);
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_TOUCH_RST);
 	udelay(1000);
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_TOUCH_RST);
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_TOUCH_RST);
 
 	/*
 	 * Enable power on PS/2 interface (with reset)
 	 */
-	*fpga_ctrl &= ~(CFG_FPGA_CTRL_PS2_PWR);
+	*fpga_ctrl &= ~(CONFIG_SYS_FPGA_CTRL_PS2_PWR);
 	for (i=0;i<500;i++)
 		udelay(1000);
-	*fpga_ctrl |= (CFG_FPGA_CTRL_PS2_PWR);
+	*fpga_ctrl |= (CONFIG_SYS_FPGA_CTRL_PS2_PWR);
 
 	/*
 	 * Get contrast value from environment variable
@@ -512,11 +512,11 @@
 		/*
 		 * Switch backlight on
 		 */
-		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL;
+		*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL;
 		*lcd_backlight = 0x0000;
 
 		lcd_setup(1, 0);
-		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 			 regs_13806_1024_768_8bpp,
 			 sizeof(regs_13806_1024_768_8bpp)/sizeof(regs_13806_1024_768_8bpp[0]),
 			 logo_bmp_1024, sizeof(logo_bmp_1024));
@@ -524,11 +524,11 @@
 		/*
 		 * Switch backlight on
 		 */
-		*fpga_ctrl &= ~CFG_FPGA_CTRL_VGA0_BL;
+		*fpga_ctrl &= ~CONFIG_SYS_FPGA_CTRL_VGA0_BL;
 		*lcd_backlight = 0x0000;
 
 		lcd_setup(1, 0);
-		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 			 regs_13806_640_480_16bpp,
 			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 			 logo_bmp_640, sizeof(logo_bmp_640));
@@ -545,7 +545,7 @@
 		/*
 		 * Switch backlight on
 		 */
-		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+		*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
 		/*
 		 * Set lcd clock (small epson)
 		 */
@@ -553,7 +553,7 @@
 		udelay(100);               /* wait for 100 us */
 
 		lcd_setup(0, 1);
-		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 			 regs_13705_320_240_8bpp,
 			 sizeof(regs_13705_320_240_8bpp)/sizeof(regs_13705_320_240_8bpp[0]),
 			 logo_bmp_320_8bpp, sizeof(logo_bmp_320_8bpp));
@@ -570,14 +570,14 @@
 		/*
 		 * Switch backlight on
 		 */
-		*fpga_ctrl |= CFG_FPGA_CTRL_VGA0_BL | CFG_FPGA_CTRL_VGA0_BL_MODE;
+		*fpga_ctrl |= CONFIG_SYS_FPGA_CTRL_VGA0_BL | CONFIG_SYS_FPGA_CTRL_VGA0_BL_MODE;
 		/*
 		 * Set lcd clock (small epson), enable 1-wire interface
 		 */
-		*fpga_ctrl |= LCD_CLK_08330 | CFG_FPGA_CTRL_OW_ENABLE;
+		*fpga_ctrl |= LCD_CLK_08330 | CONFIG_SYS_FPGA_CTRL_OW_ENABLE;
 
 		lcd_setup(0, 1);
-		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 			 regs_13704_320_240_4bpp,
 			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 			 logo_bmp_320, sizeof(logo_bmp_320));
@@ -647,27 +647,27 @@
 void ide_set_reset(int on)
 {
 	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 	volatile unsigned short *fpga_status =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 2);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 2);
 
-	if (((gd->board_type >= 2) && (*fpga_status & CFG_FPGA_STATUS_CF_DETECT)) ||
+	if (((gd->board_type >= 2) && (*fpga_status & CONFIG_SYS_FPGA_STATUS_CF_DETECT)) ||
 	    (gd->board_type < 2)) {
 		/*
 		 * Assert or deassert CompactFlash Reset Pin
 		 */
 		if (on) {		/* assert RESET */
 			cf_enable();
-			*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+			*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
 		} else {		/* release RESET */
-			*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+			*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
 		}
 	}
 }
 #endif /* CONFIG_IDE_RESET */
 
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
  *	               0: disable write
@@ -678,23 +678,23 @@
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
 	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_EEPROM_WP);
+			out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO_SINT2. */
-			out32(GPIO0_OR, in32(GPIO0_OR) | CFG_EEPROM_WP);
+			out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in32(GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in32(GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 			break;
 		}
 	}
@@ -708,21 +708,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
 		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts ("Setup of write access state failed.\n");
@@ -735,7 +735,7 @@
 U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
 
 #ifdef CONFIG_VIDEO_SM501
diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/hub405/flash.c
+++ b/board/esd/hub405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/hub405/hub405.c b/board/esd/hub405/hub405.c
index 38a6f7a..8785e6c 100644
--- a/board/esd/hub405/hub405.c
+++ b/board/esd/hub405/hub405.c
@@ -125,23 +125,23 @@
 	 * Set RS232/RS422 control (RS232 = high on GPIO)
 	 */
 	val = in32(GPIO0_OR);
-	val &= ~(CFG_UART2_RS232 | CFG_UART3_RS232 | CFG_UART4_RS232 | CFG_UART5_RS232);
+	val &= ~(CONFIG_SYS_UART2_RS232 | CONFIG_SYS_UART3_RS232 | CONFIG_SYS_UART4_RS232 | CONFIG_SYS_UART5_RS232);
 
 	str = getenv("phys0");
 	if (!str || (str && (str[0] == '0')))
-		val |= CFG_UART2_RS232;
+		val |= CONFIG_SYS_UART2_RS232;
 
 	str = getenv("phys1");
 	if (!str || (str && (str[0] == '0')))
-		val |= CFG_UART3_RS232;
+		val |= CONFIG_SYS_UART3_RS232;
 
 	str = getenv("phys2");
 	if (!str || (str && (str[0] == '0')))
-		val |= CFG_UART4_RS232;
+		val |= CONFIG_SYS_UART4_RS232;
 
 	str = getenv("phys3");
 	if (!str || (str && (str[0] == '0')))
-		val |= CFG_UART5_RS232;
+		val |= CONFIG_SYS_UART5_RS232;
 
 	out32(GPIO0_OR, val);
 
@@ -174,9 +174,9 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
 	/*
diff --git a/board/esd/mecp5200/mecp5200.c b/board/esd/mecp5200/mecp5200.c
index ff44abd..3192450 100644
--- a/board/esd/mecp5200/mecp5200.c
+++ b/board/esd/mecp5200/mecp5200.c
@@ -81,7 +81,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -106,9 +106,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size(CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x80000000);
 
 	if (test1 > test2) {
 		sdram_start(0);
@@ -143,9 +143,9 @@
 #if 0
 	/* find RAM size using SDRAM CS1 only */
 	sdram_start(0);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(1);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(0);
 #endif
 	/* set SDRAM CS1 size according to the amount of RAM found */
@@ -175,14 +175,14 @@
 
 void flash_afterinit(ulong size)
 {
-	if (size == CFG_FLASH_SIZE) {
+	if (size == CONFIG_SYS_FLASH_SIZE) {
 		/* adjust mapping */
 		*(vu_long *) MPC5XXX_BOOTCS_START =
 		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CFG_BOOTCS_START | size);
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
 		*(vu_long *) MPC5XXX_BOOTCS_STOP =
 		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CFG_BOOTCS_START | size, size);
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 }
 
diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c
index c3d8bec..e763a89 100644
--- a/board/esd/ocrtc/flash.c
+++ b/board/esd/ocrtc/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c
index 3b21781..9058483 100644
--- a/board/esd/pci405/flash.c
+++ b/board/esd/pci405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c
index f8d7c28..4db7052 100644
--- a/board/esd/pci405/pci405.c
+++ b/board/esd/pci405/pci405.c
@@ -57,11 +57,11 @@
  */
 #include "../common/fpga.c"
 
-#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_DONE)
-#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_DONE_V12)
+#define FPGA_DONE_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_DONE_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_DONE_V12)
 
-#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CFG_FPGA_INIT)
-#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CFG_FPGA_INIT_V12)
+#define FPGA_INIT_STATE_V11 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT)
+#define FPGA_INIT_STATE_V12 (in32(GPIO0_IR) & CONFIG_SYS_FPGA_INIT_V12)
 
 
 int board_revision(void)
@@ -138,8 +138,8 @@
 	 * First pull fpga-prg pin low, to disable fpga logic (on version 1.2 board)
 	 */
 	out32(GPIO0_ODR, 0x00000000);        /* no open drain pins      */
-	out32(GPIO0_TCR, CFG_FPGA_PRG);      /* setup for output        */
-	out32(GPIO0_OR,  CFG_FPGA_PRG);      /* set output pins to high */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG);      /* setup for output        */
+	out32(GPIO0_OR,  CONFIG_SYS_FPGA_PRG);      /* set output pins to high */
 	out32(GPIO0_OR, 0);                  /* pull prg low            */
 
 	/*
@@ -205,8 +205,8 @@
 	 * FPGA can be gzip compressed (malloc) and booted this late.
 	 */
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
diff --git a/board/esd/pf5200/flash.c b/board/esd/pf5200/flash.c
index 8178b56..9850445 100644
--- a/board/esd/pf5200/flash.c
+++ b/board/esd/pf5200/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 typedef unsigned short FLASH_PORT_WIDTH;
 typedef volatile unsigned short FLASH_PORT_WIDTHV;
@@ -60,7 +60,7 @@
 	extern void flash_preinit(void);
 	extern void flash_afterinit(uint, ulong, ulong);
 
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	flash_preinit();
 
@@ -69,11 +69,11 @@
 	flash_info[i].size = flash_get_size((FPW *) flashbase, &flash_info[i]);
 	size += flash_info[i].size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
-	flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE + monitor_flash_len - 1,
-		      flash_get_info(CFG_MONITOR_BASE));
+	flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef  CONFIG_ENV_IS_IN_FLASH
@@ -107,14 +107,14 @@
 	int i;
 	flash_info_t *info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		info = &flash_info[i];
 		if ((info->size) && (info->start[0] <= base)
 		    && (base <= info->start[0] + info->size - 1)) {
 			break;
 		}
 	}
-	return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
 }
 
 /*-----------------------------------------------------------------------
@@ -336,7 +336,7 @@
 		udelay(1000);
 
 		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf("Timeout\n");
 				if (intel) {
 					/* suspend erase        */
@@ -347,14 +347,14 @@
 				break;
 			}
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {
 				/* every second */
 				putc('.');
 				last = get_timer(0);
 			}
 		}
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {
 			/* every second */
 			putc('.');
 			last = get_timer(0);
@@ -452,7 +452,7 @@
 	/* data polling for D7 */
 	while (res == 0
 	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00F000F0;	/* reset bank */
 			res = 1;
 		}
diff --git a/board/esd/pf5200/pf5200.c b/board/esd/pf5200/pf5200.c
index c4c0221..f7962af 100644
--- a/board/esd/pf5200/pf5200.c
+++ b/board/esd/pf5200/pf5200.c
@@ -81,7 +81,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -106,9 +106,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *) CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *) CONFIG_SYS_SDRAM_BASE, 0x80000000);
 
 	if (test1 > test2) {
 		sdram_start(0);
@@ -144,9 +144,9 @@
 #if 0
 	/* find RAM size using SDRAM CS1 only */
 	sdram_start(0);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(1);
-	get_ram_size((ulong *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	get_ram_size((ulong *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	sdram_start(0);
 #endif
 	/* set SDRAM CS1 size according to the amount of RAM found */
@@ -180,10 +180,10 @@
 		/* adjust mapping */
 		*(vu_long *) MPC5XXX_BOOTCS_START =
 		    *(vu_long *) MPC5XXX_CS0_START =
-		    START_REG(CFG_BOOTCS_START | size);
+		    START_REG(CONFIG_SYS_BOOTCS_START | size);
 		*(vu_long *) MPC5XXX_BOOTCS_STOP =
 		    *(vu_long *) MPC5XXX_CS0_STOP =
-		    STOP_REG(CFG_BOOTCS_START | size, size);
+		    STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 }
 
@@ -258,10 +258,10 @@
 		*(vu_long *) MPC5XXX_SIMPLEIO_GPIO_DATA_OUTPUT |= GPIO_USB0;
 		__asm__ volatile ("sync");
 	}
-	*(vu_char *) CFG_CS1_START = 0x02;	/* Red Power LED on */
+	*(vu_char *) CONFIG_SYS_CS1_START = 0x02;	/* Red Power LED on */
 	__asm__ volatile ("sync");
 
-	*(vu_char *) (CFG_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
+	*(vu_char *) (CONFIG_SYS_CS1_START + 1) = 0x02;	/* Disable driver for KB11 */
 	__asm__ volatile ("sync");
 }
 
diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/plu405/flash.c
+++ b/board/esd/plu405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/plu405/plu405.c b/board/esd/plu405/plu405.c
index 3db9c0a..61186a8 100644
--- a/board/esd/plu405/plu405.c
+++ b/board/esd/plu405/plu405.c
@@ -113,8 +113,8 @@
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -179,23 +179,23 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST);
 	udelay(10);
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST);
 	udelay(1000);
 
 	/*
 	 * Set NAND-FLASH GPIO signals to default
 	 */
 	out_be32((void*)GPIO0_OR,
-		 in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+		 in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 
 	/*
 	 * Setup EEPROM write protection
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
-	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -230,15 +230,15 @@
 void ide_set_reset(int on)
 {
 	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+		*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	} else {		/* release RESET */
-		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+		*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
 	}
 }
 #endif /* CONFIG_IDE_RESET */
@@ -254,7 +254,7 @@
 #endif
 }
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
  *	               0: disable write
@@ -265,26 +265,26 @@
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
 	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO0. */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+				 in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO0. */
 			out_be32((void*)GPIO0_OR,
-				 in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+				 in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
 			state = (0 == (in_be32((void*)GPIO0_OR) &
-				       CFG_EEPROM_WP));
+				       CONFIG_SYS_EEPROM_WP));
 			break;
 		}
 	}
@@ -298,21 +298,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
 		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts ("Setup of write access state failed.\n");
@@ -325,4 +325,4 @@
 U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/pmc405/pmc405.c b/board/esd/pmc405/pmc405.c
index 90a212b..c0781dc 100644
--- a/board/esd/pmc405/pmc405.c
+++ b/board/esd/pmc405/pmc405.c
@@ -72,23 +72,23 @@
 	 * Setup GPIO pins
 	 */
 
-	mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_FPGA_INIT | \
-					CFG_FPGA_DONE | \
-					CFG_XEREADY | \
-					CFG_NONMONARCH | \
-					CFG_REV1_2) << 5));
+	mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_FPGA_INIT | \
+					CONFIG_SYS_FPGA_DONE | \
+					CONFIG_SYS_XEREADY | \
+					CONFIG_SYS_NONMONARCH | \
+					CONFIG_SYS_REV1_2) << 5));
 
-	if (!(in32(GPIO0_IR) & CFG_REV1_2)) {
+	if (!(in32(GPIO0_IR) & CONFIG_SYS_REV1_2)) {
 		/* rev 1.2 boards */
-		mtdcr(cntrl0, mfdcr(cntrl0) | ((CFG_INTA_FAKE | \
-						CFG_SELF_RST) << 5));
+		mtdcr(cntrl0, mfdcr(cntrl0) | ((CONFIG_SYS_INTA_FAKE | \
+						CONFIG_SYS_SELF_RST) << 5));
 	}
 
 	out32(GPIO0_OR, 0);
-	out32(GPIO0_TCR, CFG_FPGA_PRG | CFG_FPGA_CLK | CFG_FPGA_DATA | CFG_XEREADY); /* setup for output */
+	out32(GPIO0_TCR, CONFIG_SYS_FPGA_PRG | CONFIG_SYS_FPGA_CLK | CONFIG_SYS_FPGA_DATA | CONFIG_SYS_XEREADY); /* setup for output */
 
 	/* - check if rev1_2 is low, then:
-	 * - set/reset CFG_INTA_FAKE/CFG_SELF_RST in TCR to assert INTA# or SELFRST#
+	 * - set/reset CONFIG_SYS_INTA_FAKE/CONFIG_SYS_SELF_RST in TCR to assert INTA# or SELFRST#
 	 */
 
 	return 0;
@@ -104,7 +104,7 @@
 	gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 	gd->bd->bi_flashoffset = 0;
 
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_XEREADY); /* deassert EREADY# */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_XEREADY); /* deassert EREADY# */
 	return (0);
 }
 
@@ -112,13 +112,13 @@
 {
 	ulong val;
 	val = in32(GPIO0_IR);
-	if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
-		if (val & CFG_NONMONARCH) { /* monarch# signal */
-			return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
+		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
+			return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
 		}
-		return CFG_PCI_SUBSYS_DEVICEID_MONARCH;
+		return CONFIG_SYS_PCI_SUBSYS_DEVICEID_MONARCH;
 	}
-	return CFG_PCI_SUBSYS_DEVICEID_NONMONARCH;
+	return CONFIG_SYS_PCI_SUBSYS_DEVICEID_NONMONARCH;
 }
 
 /*
@@ -140,9 +140,9 @@
 	}
 
 	val = in32(GPIO0_IR);
-	if (!(val & CFG_REV1_2)) { /* low=rev1.2 */
+	if (!(val & CONFIG_SYS_REV1_2)) { /* low=rev1.2 */
 		puts(" rev1.2 (");
-		if (val & CFG_NONMONARCH) { /* monarch# signal */
+		if (val & CONFIG_SYS_NONMONARCH) { /* monarch# signal */
 			puts("non-");
 		}
 		puts("monarch)");
diff --git a/board/esd/pmc440/cmd_pmc440.c b/board/esd/pmc440/cmd_pmc440.c
index 74cf4c3..38ee74e 100644
--- a/board/esd/pmc440/cmd_pmc440.c
+++ b/board/esd/pmc440/cmd_pmc440.c
@@ -323,7 +323,7 @@
 	}
 
 	printf("Writing boot EEPROM ...\n");
-	if (bootstrap_eeprom_write(CFG_I2C_BOOT_EEPROM_ADDR,
+	if (bootstrap_eeprom_write(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
 				   0, (uchar*)sdsdp, count) != 0)
 		printf("bootstrap_eeprom_write failed\n");
 	else
@@ -513,7 +513,7 @@
 	"<pciaddr> (pciaddr will be aligned to 256MB)\n"
 	);
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 int do_eep_wren(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int query = argc == 1;
@@ -521,21 +521,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts("Query of write access state failed.\n");
 		} else {
 			printf("Write access for device 0x%0x is %sabled.\n",
-			       CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+			       CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable(CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable(CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts("Setup of write access state failed.\n");
@@ -547,6 +547,6 @@
 U_BOOT_CMD(eepwren, 2, 0, do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
 #endif /* CONFIG_CMD_BSP */
diff --git a/board/esd/pmc440/config.mk b/board/esd/pmc440/config.mk
index e62b8d3..0c4d582 100644
--- a/board/esd/pmc440/config.mk
+++ b/board/esd/pmc440/config.mk
@@ -37,5 +37,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/esd/pmc440/init.S b/board/esd/pmc440/init.S
index 148af71..26a8282 100644
--- a/board/esd/pmc440/init.S
+++ b/board/esd/pmc440/init.S
@@ -44,28 +44,28 @@
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
 #ifndef CONFIG_NAND_SPL
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G )
 #else
-	tlbentry( CFG_NAND_BOOT_SPL_SRC, SZ_4K, CFG_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_NAND_BOOT_SPL_SRC, SZ_4K, CONFIG_SYS_NAND_BOOT_SPL_SRC, 1, AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for DDR SDRAM (Up to 2GB) */
 #ifdef CONFIG_4xx_DCACHE
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G)
 #else
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entries for EBC */
 	/* PMC440 maps EBC to 0xef000000 which is handled by the peripheral
@@ -76,7 +76,7 @@
 	tlbentry( 0xc0000000, SZ_256M, 0xc0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for NAND */
-	tlbentry( CFG_NAND_ADDR, SZ_1K, CFG_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_NAND_ADDR, SZ_1K, CONFIG_SYS_NAND_ADDR, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
 	tlbentry( 0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I )
@@ -98,8 +98,8 @@
 	 * For NAND booting the first TLB has to be reconfigured to full size
 	 * and with caching disabled after running from RAM!
 	 */
-#define TLB00	TLB0(CFG_BOOT_BASE_ADDR, SZ_256M)
-#define TLB01	TLB1(CFG_BOOT_BASE_ADDR, 1)
+#define TLB00	TLB0(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M)
+#define TLB01	TLB1(CONFIG_SYS_BOOT_BASE_ADDR, 1)
 #define TLB02	TLB2(AC_R|AC_W|AC_X|SA_G|SA_I)
 
 	.globl	reconfig_tlb0
diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c
index 85ef26f..013815e 100644
--- a/board/esd/pmc440/pmc440.c
+++ b/board/esd/pmc440/pmc440.c
@@ -44,7 +44,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size(ulong base, int banknum);
 int pci_is_66mhz(void);
@@ -71,7 +71,7 @@
 		/* mark scratchreg valid */
 		scratchreg = (scratchreg & 0xffffff00) | 0x80;
 
-		i = bootstrap_eeprom_read(CFG_I2C_BOOT_EEPROM_ADDR,
+		i = bootstrap_eeprom_read(CONFIG_SYS_I2C_BOOT_EEPROM_ADDR,
 					  0x10, buf, 4);
 		if ((i != -1) && (buf[0] == 0x19) && (buf[1] == 0x75)) {
 			scratchreg |= buf[2];
@@ -103,7 +103,7 @@
 
 	/*
 	 * Setup the GPIO pins
-	 * TODO: setup GPIOs via CFG_4xx_GPIO_TABLE in board's config file
+	 * TODO: setup GPIOs via CONFIG_SYS_4xx_GPIO_TABLE in board's config file
 	 */
 	out32(GPIO0_OR,    0x40000002);
 	out32(GPIO0_TCR,   0x4c90011f);
@@ -190,7 +190,7 @@
 		SDR0_CUST0_NDFC_ENABLE		|
 		SDR0_CUST0_NDFC_BW_8_BIT	|
 		SDR0_CUST0_NDFC_ARE_MASK	|
-		(0x80000000 >> (28 + CFG_NAND_CS));
+		(0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 	mtsdr(SDR0_CUST0, sdr0_cust0);
 
 	return 0;
@@ -242,7 +242,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -498,7 +498,7 @@
  * inbound map (PIM). But the bootstrap config choices are limited and
  * may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	char *ptmla_str, *ptmms_str;
@@ -516,8 +516,8 @@
 	 */
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE); /* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE); /* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xc0000001);	/* 1G + No prefetching, */
 						/* and enable region */
@@ -563,7 +563,7 @@
 
 	/* Program the board's vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
 
 	/* disabled for PMC405 backward compatibility */
 	/* Configure command register as bus master */
@@ -581,9 +581,9 @@
 	if (!is_monarch()) {
 		/* Program the board's subsystem id/classcode */
 		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
-				      CFG_PCI_SUBSYS_ID_NONMONARCH);
+				      CONFIG_SYS_PCI_SUBSYS_ID_NONMONARCH);
 		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
-				      CFG_PCI_CLASSCODE_NONMONARCH);
+				      CONFIG_SYS_PCI_CLASSCODE_NONMONARCH);
 
 		/* PCI configuration done: release ERREADY */
 		out_be32((void*)GPIO1_OR,
@@ -593,17 +593,17 @@
 	} else {
 		/* Program the board's subsystem id/classcode */
 		pci_write_config_word(0, PCI_SUBSYSTEM_ID,
-				      CFG_PCI_SUBSYS_ID_MONARCH);
+				      CONFIG_SYS_PCI_SUBSYS_ID_MONARCH);
 		pci_write_config_word(0, PCI_CLASS_SUB_CODE,
-				      CFG_PCI_CLASSCODE_MONARCH);
+				      CONFIG_SYS_PCI_CLASSCODE_MONARCH);
 	}
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*
  * pci_master_init
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -620,7 +620,7 @@
 				      PCI_COMMAND_MEMORY);
 	}
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 static void wait_for_pci_ready(void)
 {
@@ -708,7 +708,7 @@
 }
 #endif
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /*
  *  Input: <dev_addr> I2C address of EEPROM device to enable.
  *         <state>    -1: deliver current state
@@ -720,8 +720,8 @@
  */
 int eeprom_write_enable(unsigned dev_addr, int state)
 {
-	if ((CFG_I2C_EEPROM_ADDR != dev_addr) &&
-	    (CFG_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
+	if ((CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) &&
+	    (CONFIG_SYS_I2C_BOOT_EEPROM_ADDR != dev_addr)) {
 		return -1;
 	} else {
 		switch (state) {
@@ -743,9 +743,9 @@
 	}
 	return state;
 }
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
 
-#define CFG_BOOT_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS 3
 int bootstrap_eeprom_write(unsigned dev_addr, unsigned offset,
 			   uchar *buffer, unsigned cnt)
 {
@@ -753,7 +753,7 @@
 	unsigned blk_off;
 	int rcode = 0;
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 	eeprom_write_enable(dev_addr, 1);
 #endif
 	/*
@@ -776,7 +776,7 @@
 
 		len = end - offset;
 
-#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CFG_BOOT_EEPROM_PAGE_WRITE_BITS)
+#define	BOOT_EEPROM_PAGE_SIZE	   (1 << CONFIG_SYS_BOOT_EEPROM_PAGE_WRITE_BITS)
 #define	BOOT_EEPROM_PAGE_OFFSET(x) ((x) & (BOOT_EEPROM_PAGE_SIZE - 1))
 
 		maxlen = BOOT_EEPROM_PAGE_SIZE -
@@ -793,11 +793,11 @@
 		buffer += len;
 		offset += len;
 
-#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
-		udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+		udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 	}
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 	eeprom_write_enable(dev_addr, 0);
 #endif
 	return rcode;
@@ -845,7 +845,7 @@
 	return rcode;
 }
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_BOARD_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT)
 int usb_board_init(void)
 {
 	char *act = getenv("usbact");
@@ -875,4 +875,4 @@
 	usb_board_stop();
 	return 0;
 }
-#endif /* defined(CONFIG_USB_OHCI) && defined(CFG_USB_OHCI_BOARD_INIT) */
+#endif /* defined(CONFIG_USB_OHCI) && defined(CONFIG_SYS_USB_OHCI_BOARD_INIT) */
diff --git a/board/esd/pmc440/pmc440.h b/board/esd/pmc440/pmc440.h
index 7e70fd1..d834f25 100644
--- a/board/esd/pmc440/pmc440.h
+++ b/board/esd/pmc440/pmc440.h
@@ -54,7 +54,7 @@
 /*-----------------------------------------------------------------------
  * FPGA interface
  */
-#define FPGA_BA CFG_FPGA_BASE0
+#define FPGA_BA CONFIG_SYS_FPGA_BASE0
 #define FPGA_OUT32(p,v) out_be32(((void*)(p)), (v))
 #define FPGA_IN32(p) in_be32((void*)(p))
 #define FPGA_SETBITS(p,v) out_be32(((void*)(p)), in_be32((void*)(p)) | (v))
@@ -134,7 +134,7 @@
 #define HOSTCTRL_HCINT_GATE  (1 <<  1)
 #define HOSTCTRL_HCINT_FLAG  (1 <<  0)
 
-#define NGCC_CTRL_BASE         (CFG_FPGA_BASE0 + 0x80000)
+#define NGCC_CTRL_BASE         (CONFIG_SYS_FPGA_BASE0 + 0x80000)
 #define NGCC_CTRL_FPGARST_N    (1 <<  2)
 
 /*-----------------------------------------------------------------------
diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c
index c7294c9..197857a 100644
--- a/board/esd/pmc440/sdram.c
+++ b/board/esd/pmc440/sdram.c
@@ -111,5 +111,5 @@
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
diff --git a/board/esd/pmc440/u-boot.lds b/board/esd/pmc440/u-boot.lds
index b20fb1c..3cfec83 100644
--- a/board/esd/pmc440/u-boot.lds
+++ b/board/esd/pmc440/u-boot.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c
index 13c07d2..ce905e9 100644
--- a/board/esd/tasreg/flash.c
+++ b/board/esd/tasreg/flash.c
@@ -45,13 +45,13 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -65,8 +65,8 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    CFG_FLASH_BASE,
-			    CFG_FLASH_BASE+CFG_MONITOR_LEN-1,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+CONFIG_SYS_MONITOR_LEN-1,
 			    &flash_info[0]);
 
 	flash_info[0].size = size_b0;
diff --git a/board/esd/tasreg/tasreg.c b/board/esd/tasreg/tasreg.c
index fabb746..64e6d63 100644
--- a/board/esd/tasreg/tasreg.c
+++ b/board/esd/tasreg/tasreg.c
@@ -40,8 +40,8 @@
 
 /* predefine these here for FPGA programming (before including fpga.c) */
 #define SET_FPGA(data)  mbar2_writeLong(MCFSIM_GPIO1_OUT, data)
-#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (mbar2_readLong(MCFSIM_GPIO1_READ) & CONFIG_SYS_FPGA_INIT)
 #define FPGA_PROG_ACTIVE_HIGH          /* on this platform is PROG active high!   */
 #define out32(a,b)                     /* nothing to do (gpio already configured) */
 
@@ -70,7 +70,7 @@
 	/*
 	 * Set LED on
 	 */
-	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
 	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
 
 	return 0;
@@ -85,13 +85,13 @@
 	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
 	 */
 
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
 	/*
 	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
 	 */
 	mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
 	/*
 	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -129,7 +129,7 @@
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 
@@ -150,8 +150,8 @@
 	int i;
 	uchar buf[8];
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/voh405/flash.c
+++ b/board/esd/voh405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/voh405/voh405.c b/board/esd/voh405/voh405.c
index 115f8b4..ec65ffd 100644
--- a/board/esd/voh405/voh405.c
+++ b/board/esd/voh405/voh405.c
@@ -109,9 +109,9 @@
 	unsigned char *duart0_mcr = (unsigned char *)((ulong)DUART0_BA + 4);
 	unsigned char *duart1_mcr = (unsigned char *)((ulong)DUART1_BA + 4);
 	unsigned short *lcd_contrast =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 4);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 4);
 	unsigned short *lcd_backlight =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL + 6);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL + 6);
 	unsigned char *dst;
 	ulong len = sizeof(fpgadata);
 	int status;
@@ -119,8 +119,8 @@
 	int i;
 	char *str;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -183,22 +183,22 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 	udelay(10); /* wait 10us */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
 	/*
 	 * Set NAND-FLASH GPIO signals to default
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_NAND_CE);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_NAND_CE);
 
 	/*
 	 * Setup EEPROM write protection
 	 */
-	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
-	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_EEPROM_WP);
+	out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_EEPROM_WP);
 
 	/*
 	 * Enable interrupts in exar duart mcr[3]
@@ -212,29 +212,29 @@
 	str = getenv("bd_type");
 	if (strcmp(str, "voh405_bw") == 0) {
 		lcd_setup(0, 1);
-		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 			 regs_13704_320_240_4bpp,
 			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 			 logo_bmp_320, sizeof(logo_bmp_320));
 	} else if (strcmp(str, "voh405_bwbw") == 0) {
 		lcd_setup(0, 1);
-		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 			 regs_13704_320_240_4bpp,
 			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 			 logo_bmp_320, sizeof(logo_bmp_320));
 		lcd_setup(1, 1);
-		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 			 regs_13806_320_240_4bpp,
 			 sizeof(regs_13806_320_240_4bpp)/sizeof(regs_13806_320_240_4bpp[0]),
 			 logo_bmp_320, sizeof(logo_bmp_320));
 	} else if (strcmp(str, "voh405_bwc") == 0) {
 		lcd_setup(0, 1);
-		lcd_init((uchar *)CFG_LCD_SMALL_REG, (uchar *)CFG_LCD_SMALL_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_SMALL_REG, (uchar *)CONFIG_SYS_LCD_SMALL_MEM,
 			 regs_13704_320_240_4bpp,
 			 sizeof(regs_13704_320_240_4bpp)/sizeof(regs_13704_320_240_4bpp[0]),
 			 logo_bmp_320, sizeof(logo_bmp_320));
 		lcd_setup(1, 0);
-		lcd_init((uchar *)CFG_LCD_BIG_REG, (uchar *)CFG_LCD_BIG_MEM,
+		lcd_init((uchar *)CONFIG_SYS_LCD_BIG_REG, (uchar *)CONFIG_SYS_LCD_BIG_MEM,
 			 regs_13806_640_480_16bpp,
 			 sizeof(regs_13806_640_480_16bpp)/sizeof(regs_13806_640_480_16bpp[0]),
 			 logo_bmp_640, sizeof(logo_bmp_640));
@@ -246,8 +246,8 @@
 	/*
 	 * Set invert bit in small lcd controller
 	 */
-	out_8((unsigned char *)(CFG_LCD_SMALL_REG + 2),
-	      in_8((unsigned char *)(CFG_LCD_SMALL_REG + 2)) | 0x01);
+	out_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2),
+	      in_8((unsigned char *)(CONFIG_SYS_LCD_SMALL_REG + 2)) | 0x01);
 
 	/*
 	 * Set default contrast voltage on epson vga controller
@@ -262,7 +262,7 @@
 	/*
 	 * Enable external I2C bus
 	 */
-	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CFG_IIC_ON);
+	out_be32((void*)GPIO0_TCR, in_be32((void*)GPIO0_TCR) | CONFIG_SYS_IIC_ON);
 
 	return (0);
 }
@@ -300,15 +300,15 @@
 void ide_set_reset(int on)
 {
 	volatile unsigned short *fpga_mode =
-		(unsigned short *)((ulong)CFG_FPGA_BASE_ADDR + CFG_FPGA_CTRL);
+		(unsigned short *)((ulong)CONFIG_SYS_FPGA_BASE_ADDR + CONFIG_SYS_FPGA_CTRL);
 
 	/*
 	 * Assert or deassert CompactFlash Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		*fpga_mode &= ~(CFG_FPGA_CTRL_CF_RESET);
+		*fpga_mode &= ~(CONFIG_SYS_FPGA_CTRL_CF_RESET);
 	} else {		/* release RESET */
-		*fpga_mode |= CFG_FPGA_CTRL_CF_RESET;
+		*fpga_mode |= CONFIG_SYS_FPGA_CTRL_CF_RESET;
 	}
 }
 #endif /* CONFIG_IDE_RESET */
@@ -326,7 +326,7 @@
 }
 #endif
 
-#if defined(CFG_EEPROM_WREN)
+#if defined(CONFIG_SYS_EEPROM_WREN)
 /* Input: <dev_addr>  I2C address of EEPROM device to enable.
  *         <state>     -1: deliver current state
  *	               0: disable write
@@ -337,23 +337,23 @@
  */
 int eeprom_write_enable (unsigned dev_addr, int state)
 {
-	if (CFG_I2C_EEPROM_ADDR != dev_addr) {
+	if (CONFIG_SYS_I2C_EEPROM_ADDR != dev_addr) {
 		return -1;
 	} else {
 		switch (state) {
 		case 1:
 			/* Enable write access, clear bit GPIO0. */
-			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CFG_EEPROM_WP);
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) & ~CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		case 0:
 			/* Disable write access, set bit GPIO0. */
-			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CFG_EEPROM_WP);
+			out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | CONFIG_SYS_EEPROM_WP);
 			state = 0;
 			break;
 		default:
 			/* Read current status back. */
-			state = (0 == (in_be32((void*)GPIO0_OR) & CFG_EEPROM_WP));
+			state = (0 == (in_be32((void*)GPIO0_OR) & CONFIG_SYS_EEPROM_WP));
 			break;
 		}
 	}
@@ -367,21 +367,21 @@
 
 	if (query) {
 		/* Query write access state. */
-		state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, -1);
+		state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, -1);
 		if (state < 0) {
 			puts ("Query of write access state failed.\n");
 		} else {
 			printf ("Write access for device 0x%0x is %sabled.\n",
-				CFG_I2C_EEPROM_ADDR, state ? "en" : "dis");
+				CONFIG_SYS_I2C_EEPROM_ADDR, state ? "en" : "dis");
 			state = 0;
 		}
 	} else {
 		if ('0' == argv[1][0]) {
 			/* Disable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 0);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 0);
 		} else {
 			/* Enable write access. */
-			state = eeprom_write_enable (CFG_I2C_EEPROM_ADDR, 1);
+			state = eeprom_write_enable (CONFIG_SYS_I2C_EEPROM_ADDR, 1);
 		}
 		if (state < 0) {
 			puts ("Setup of write access state failed.\n");
@@ -394,4 +394,4 @@
 U_BOOT_CMD(eepwren,	2,	0,	do_eep_wren,
 	   "eepwren - Enable / disable / query EEPROM write access\n",
 	   NULL);
-#endif /* #if defined(CFG_EEPROM_WREN) */
+#endif /* #if defined(CONFIG_SYS_EEPROM_WREN) */
diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/vom405/flash.c
+++ b/board/esd/vom405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c
index 89af119..274ada9 100644
--- a/board/esd/wuh405/flash.c
+++ b/board/esd/wuh405/flash.c
@@ -48,7 +48,7 @@
 	int size_val = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,7 +91,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
diff --git a/board/esd/wuh405/wuh405.c b/board/esd/wuh405/wuh405.c
index 3a94fd8..5eca3bd 100644
--- a/board/esd/wuh405/wuh405.c
+++ b/board/esd/wuh405/wuh405.c
@@ -92,8 +92,8 @@
 	int index;
 	int i;
 
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip (dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip (dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf ("GUNZIP ERROR - must RESET board to recover\n");
 		do_reset (NULL, 0, 0, NULL);
 	}
@@ -155,9 +155,9 @@
 	/*
 	 * Reset external DUARTs
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_DUART_RST); /* set reset to high */
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_DUART_RST); /* set reset to high */
 	udelay(10); /* wait 10us */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~CFG_DUART_RST); /* set reset to low */
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~CONFIG_SYS_DUART_RST); /* set reset to low */
 	udelay(1000); /* wait 1ms */
 
 	/*
diff --git a/board/esteem192e/esteem192e.c b/board/esteem192e/esteem192e.c
index f3c8662..b784cbb 100644
--- a/board/esteem192e/esteem192e.c
+++ b/board/esteem192e/esteem192e.c
@@ -103,7 +103,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0, size_b1;
 
@@ -113,7 +113,7 @@
 
 	memctl->memc_mptpr = 0x0200;	/* divide by 32 */
 
-	memctl->memc_mamr = 0x18003112;	/*CFG_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
+	memctl->memc_mamr = 0x18003112;	/*CONFIG_SYS_MAMR_8COL; */ /* 0x18005112 TODO: explain here */
 
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
@@ -124,11 +124,11 @@
 	 * SDRAM size has been determined.
 	 */
 
-	memctl->memc_or2 = CFG_OR2_PRELIM;	/* not defined yet */
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	/* not defined yet */
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
 
 	/* perform SDRAM initializsation sequence */
@@ -139,7 +139,7 @@
 	memctl->memc_mcr = 0x80006830;	/* SDRAM bank 1 execute 8 refresh */
 	memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
 
-	memctl->memc_mamr = CFG_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* 0x18803112  start refresh timer TODO: explain here */
 
 /* printf ("banks 0 and 1 are programed\n"); */
 
diff --git a/board/esteem192e/flash.c b/board/esteem192e/flash.c
index d5eb201..cce73fa 100644
--- a/board/esteem192e/flash.c
+++ b/board/esteem192e/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 #ifdef CONFIG_FLASH_16BIT
 #define FLASH_WORD_SIZE	unsigned short
@@ -54,13 +54,13 @@
  */
 unsigned long flash_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -91,44 +91,44 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = CFG_FLASH_BASE | 0x00000801;	/*  (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = CONFIG_SYS_FLASH_BASE | 0x00000801;	/*  (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V; */
 
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
+	size_b0 = flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
 				  &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	(void) flash_protect (FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 
 	if (size_b1) {
 		memctl->memc_or1 =
-			CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+			CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
 		memctl->memc_br1 =
-			(CFG_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
-		/*((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+			(CONFIG_SYS_FLASH_BASE | 0x00000801) + (size_b0 & BR_BA_MSK);
+		/*((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 		   BR_MS_GPCM | BR_V; */
 
 		/* Re-do sizing to get full correct info */
 		size_b1 =
 			flash_get_size ((volatile FLASH_WORD_SIZE
-					 *) (CFG_FLASH_BASE + size_b0),
+					 *) (CONFIG_SYS_FLASH_BASE + size_b0),
 					&flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		(void) flash_protect (FLAG_PROTECT_SET,
-				      CFG_MONITOR_BASE,
-				      CFG_MONITOR_BASE + monitor_flash_len -
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
 				      1, &flash_info[1]);
 #endif
 	} else {
@@ -769,7 +769,7 @@
 		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
 		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
 		       (0x00800080 & FLASH_ID_MASK)) {
-			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -1022,7 +1022,7 @@
 
 		while ((*((vu_long *) dest) & 0x00800080) !=
 		       (data & 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1030,7 +1030,7 @@
 	} else {
 
 		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 
@@ -1096,7 +1096,7 @@
 	if (info->flash_id < FLASH_AMD_COMP) {
 		/* AMD stuff */
 		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1104,7 +1104,7 @@
 	} else {
 		/* intel stuff */
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 
@@ -1123,7 +1123,7 @@
 		*addr = 0x00B0;
 		*addr = 0x0070;
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 		*addr = 0x00FF;
diff --git a/board/etin/debris/debris.c b/board/etin/debris/debris.c
index a5d394c..227c49a 100644
--- a/board/etin/debris/debris.c
+++ b/board/etin/debris/debris.c
@@ -63,7 +63,7 @@
 	uint32_t mear2 = 0, emear2 = 0, msar2 = 0, emsar2 = 0;
 	uint8_t mber = 0;
 
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	if (i2c_reg_read (0x50, 2) != 0x04) return 0;	/* Memory type */
 	m = i2c_reg_read (0x50, 5);	/* # of physical banks */
@@ -74,7 +74,7 @@
 	CONFIG_READ_WORD(MCCR1, mccr1);
 	mccr1 &= 0xffff0000;
 
-	start = CFG_SDRAM_BASE;
+	start = CONFIG_SYS_SDRAM_BASE;
 	end = start + (1 << (col + row + 3) ) * bank - 1;
 
 	for (i = 0; i < m; i++) {
@@ -174,7 +174,7 @@
 int misc_init_r(void)
 {
 	/* Write ethernet addr in NVRAM for VxWorks */
-	nvram_write(CONFIG_ENV_ADDR + CFG_NVRAM_VXWORKS_OFFS,
+	nvram_write(CONFIG_ENV_ADDR + CONFIG_SYS_NVRAM_VXWORKS_OFFS,
 			(char*)&gd->bd->bi_enetaddr[0], 6);
 	return 0;
 }
diff --git a/board/etin/debris/flash.c b/board/etin/debris/flash.c
index a4100e5..a3c8138 100644
--- a/board/etin/debris/flash.c
+++ b/board/etin/debris/flash.c
@@ -71,7 +71,7 @@
 	return (uint16_t)read32(base + addr);
 }
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 static void move64(uint64_t *src, uint64_t *dest)
 {
@@ -99,7 +99,7 @@
 		status &= CMD(0x80);
 		if(status == CMD(0x80))
 			break;
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			cfi_cmd(flash, 0xff, 0);
 			return 1;
 		}
@@ -128,7 +128,7 @@
 	start = get_timer (0);
 	status = ~data;
 	while(status != data) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 			return 1;
 		status = cfi_read(flash, dest);
 		udelay(1);
@@ -230,7 +230,7 @@
 		status &= CMD(0x80);
 		if (status == CMD(0x80))
 			break;
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			cfi_cmd(flash, 0xff, 0);
 			printf ("Timeout\n");
 			return ERR_TIMOUT;
@@ -296,7 +296,7 @@
 		if (status == CMD(0xffff))
 			break;
 
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return ERR_TIMOUT;
 		}
@@ -581,7 +581,7 @@
 	mtdbat1u(0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP);
 	set_msr(msr);
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	size = cfi_init(FLASH_BASE0_PRELIM, &flash_info[0]);
 	if (!size)
diff --git a/board/etin/debris/phantom.c b/board/etin/debris/phantom.c
index 48b81f7..fcb4c40 100644
--- a/board/etin/debris/phantom.c
+++ b/board/etin/debris/phantom.c
@@ -20,7 +20,7 @@
 
 #if defined(CONFIG_CMD_DATE)
 
-#define RTC_BASE (CFG_NVRAM_BASE_ADDR + 0x7fff8)
+#define RTC_BASE (CONFIG_SYS_NVRAM_BASE_ADDR + 0x7fff8)
 
 #define RTC_YEAR                ( RTC_BASE + 7 )
 #define RTC_MONTH               ( RTC_BASE + 6 )
diff --git a/board/etin/kvme080/kvme080.c b/board/etin/kvme080/kvme080.c
index be6924d..8c6afc9 100644
--- a/board/etin/kvme080/kvme080.c
+++ b/board/etin/kvme080/kvme080.c
@@ -46,7 +46,7 @@
 	CONFIG_READ_WORD(MCCR1, mccr1);
 	mccr1 &= 0xffff0000;
 
-	start = CFG_SDRAM_BASE;
+	start = CONFIG_SYS_SDRAM_BASE;
 	end = start + (1 << (col + row + 3) ) * bank - 1;
 
 	for (i = 0; i < m; i++) {
@@ -101,31 +101,31 @@
 
 	msr = mfmsr();
 	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CFG_IBAT0L + 0x10000000);
-	mtspr(IBAT2U, CFG_IBAT0U + 0x10000000);
-	mtspr(DBAT2L, CFG_DBAT0L + 0x10000000);
-	mtspr(DBAT2U, CFG_DBAT0U + 0x10000000);
+	mtspr(IBAT2L, CONFIG_SYS_IBAT0L + 0x10000000);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT0U + 0x10000000);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT0L + 0x10000000);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT0U + 0x10000000);
 	mtmsr(msr);
 
-	if (setdram(2,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x20000000))
+	if (setdram(2,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x20000000))
 		size = 0x20000000;	/* 512MB */
-	else if (setdram(1,13,10,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+	else if (setdram(1,13,10,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
 		size = 0x10000000;	/* 256MB */
-	else if (setdram(2,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x10000000))
+	else if (setdram(2,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x10000000))
 		size = 0x10000000;	/* 256MB */
-	else if (setdram(1,13,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+	else if (setdram(1,13,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
 		size = 0x08000000;	/* 128MB */
-	else if (setdram(2,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x08000000))
+	else if (setdram(2,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x08000000))
 		size = 0x08000000;	/* 128MB */
-	else if (setdram(1,12,9,4) == get_ram_size(CFG_SDRAM_BASE, 0x04000000))
+	else if (setdram(1,12,9,4) == get_ram_size(CONFIG_SYS_SDRAM_BASE, 0x04000000))
 		size = 0x04000000;	/* 64MB */
 
 	msr = mfmsr();
 	mtmsr(msr & ~(MSR_IR | MSR_DR));
-	mtspr(IBAT2L, CFG_IBAT2L);
-	mtspr(IBAT2U, CFG_IBAT2U);
-	mtspr(DBAT2L, CFG_DBAT2L);
-	mtspr(DBAT2U, CFG_DBAT2U);
+	mtspr(IBAT2L, CONFIG_SYS_IBAT2L);
+	mtspr(IBAT2U, CONFIG_SYS_IBAT2U);
+	mtspr(DBAT2L, CONFIG_SYS_DBAT2L);
+	mtspr(DBAT2U, CONFIG_SYS_DBAT2U);
 	mtmsr(msr);
 
 	return size;
diff --git a/board/etx094/etx094.c b/board/etx094/etx094.c
index 7806519..d6f638a 100644
--- a/board/etx094/etx094.c
+++ b/board/etx094/etx094.c
@@ -127,7 +127,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0, size_b1, size8, size9;
 
@@ -140,7 +140,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;	/* MPTPR_PTP_DIV32 0x0200 */
 
 	/* A3(SDRAM)=0      => Bursttype = Sequential
 	 * A2-A0(SDRAM)=010 => Burst length = 4
@@ -153,15 +153,15 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
 	if (board_type == 0) {	/* "L" type boards have only one bank SDRAM */
-		memctl->memc_or3 = CFG_OR3_PRELIM;
-		memctl->memc_br3 = CFG_BR3_PRELIM;
+		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 	}
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -186,7 +186,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -194,7 +194,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
@@ -202,7 +202,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {					/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -230,7 +230,7 @@
 	 */
 	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/*DIV16 */
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/*DIV16 */
 		udelay (1000);
 	}
 
@@ -239,18 +239,18 @@
 	 */
 	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
 
-		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br3 =
-			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b0 > 0) {
 			/*
 			 * Position Bank 0 immediately above Bank 1
 			 */
 			memctl->memc_or2 =
-				((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+				((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 			memctl->memc_br2 =
-				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 				+ size_b1;
 		} else {
 			unsigned long reg;
@@ -264,24 +264,24 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 
 	} else {			/* SDRAM Bank 0 is bigger - map first   */
 
-		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br2 =
-				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b1 > 0) {
 			/*
 			 * Position Bank 1 immediately above Bank 0
 			 */
 			memctl->memc_or3 =
-					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 			memctl->memc_br3 =
-					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 					+ size_b0;
 		} else {
 			unsigned long reg;
@@ -295,7 +295,7 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 	}
@@ -318,7 +318,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -343,7 +343,7 @@
 	unsigned short rd_msk = 0x02A0;
 
 	/* HW-ID pin-definition */
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	immr->im_ioport.iop_pddir &= ~(rd_msk);
 	immr->im_ioport.iop_pdpar &= ~(rd_msk);
diff --git a/board/etx094/flash.c b/board/etx094/flash.c
index 98a7c0c..fa51c90 100644
--- a/board/etx094/flash.c
+++ b/board/etx094/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -75,47 +75,47 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
 #ifdef CONFIG_FLASH_16BIT
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16; /* 16 Bit data port */
 #else
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 #endif
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
 #ifdef CONFIG_FLASH_16BIT
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V | BR_PS_16;
 #else
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V;
 #endif
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 	} else {
@@ -388,10 +388,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
@@ -548,7 +548,7 @@
 #else
 			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
 #endif
-				if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					return 1;
 				}
@@ -693,7 +693,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
@@ -733,7 +733,7 @@
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
 #endif
 
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/evb4510/flash.c b/board/evb4510/flash.c
index bcefafc..c9c6e02 100644
--- a/board/evb4510/flash.c
+++ b/board/evb4510/flash.c
@@ -26,7 +26,7 @@
 #include <asm/hardware.h>
 #include <flash.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 typedef enum {
 	FLASH_DEV_U9_512KB = 0,
@@ -327,7 +327,7 @@
 	s16 amd160 = -1;
 	u32 amd160base = 0;
 
-#if CFG_MAX_FLASH_BANKS == 2
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
 	s16 amd040 = -1;
 	u32 amd040base = 0;
 #endif
@@ -336,7 +336,7 @@
 	if (_detectFlash (FLASH_DEV_U7_2MB, PHYS_FLASH_1, 0x1, 0x49)) {
 		amd160 = 0;
 		amd160base = PHYS_FLASH_1;
-#if CFG_MAX_FLASH_BANKS == 1
+#if CONFIG_SYS_MAX_FLASH_BANKS == 1
 	}
 #else
 		if (_detectFlash
@@ -401,7 +401,7 @@
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR, CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, info);
 
-#if CFG_MAX_FLASH_BANKS == 2
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
 	/* Configure AMD Am29LV040B (512KB) */
 	info = &flash_info[amd040];
 	info->flash_id = FLASH_DEV_U9_512KB;
@@ -421,7 +421,7 @@
 #endif
 
 	return flash_info[0].size
-#if CFG_MAX_FLASH_BANKS == 2
+#if CONFIG_SYS_MAX_FLASH_BANKS == 2
 		+ flash_info[1].size
 #endif
 		;
@@ -478,7 +478,7 @@
 			error = _flash_poll (info->flash_id,
 					     info->
 					     start[i] | CACHE_DISABLE_MASK,
-					     0xFF, CFG_FLASH_ERASE_TOUT);
+					     0xFF, CONFIG_SYS_FLASH_ERASE_TOUT);
 			FLASH_CMD_RESET (info->flash_id,
 					 (info->
 					  start[0] | CACHE_DISABLE_MASK));
@@ -524,7 +524,7 @@
 		/*  Check if the write is done */
 		for (i = 0; i < 0xff; i++);
 		error = _flash_poll (info->flash_id, (u32) bp, *bps,
-				     CFG_FLASH_WRITE_TOUT);
+				     CONFIG_SYS_FLASH_WRITE_TOUT);
 		if (error) {
 			return error;
 		}
diff --git a/board/evb64260/evb64260.c b/board/evb64260/evb64260.c
index bc108d0..80756a5 100644
--- a/board/evb64260/evb64260.c
+++ b/board/evb64260/evb64260.c
@@ -57,7 +57,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -65,7 +65,7 @@
  * See also my_remap_gt_regs below. (NTL)
  */
 
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 
 /* ------------------------------------------------------------------------- */
 
@@ -100,26 +100,26 @@
 {
 	/* move PCI stuff out of the way - NTL */
 	/* map PCI Host 0 */
-	pciMapSpace(PCI_HOST0, PCI_REGION0, CFG_PCI0_0_MEM_SPACE,
-		CFG_PCI0_0_MEM_SPACE, CFG_PCI0_MEM_SIZE);
+	pciMapSpace(PCI_HOST0, PCI_REGION0, CONFIG_SYS_PCI0_0_MEM_SPACE,
+		CONFIG_SYS_PCI0_0_MEM_SPACE, CONFIG_SYS_PCI0_MEM_SIZE);
 
 	pciMapSpace(PCI_HOST0, PCI_REGION1, 0, 0, 0);
 	pciMapSpace(PCI_HOST0, PCI_REGION2, 0, 0, 0);
 	pciMapSpace(PCI_HOST0, PCI_REGION3, 0, 0, 0);
 
-	pciMapSpace(PCI_HOST0, PCI_IO, CFG_PCI0_IO_SPACE_PCI,
-		CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE);
+	pciMapSpace(PCI_HOST0, PCI_IO, CONFIG_SYS_PCI0_IO_SPACE_PCI,
+		CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE);
 
 	/* map PCI Host 1 */
-	pciMapSpace(PCI_HOST1, PCI_REGION0, CFG_PCI1_0_MEM_SPACE,
-		CFG_PCI1_0_MEM_SPACE, CFG_PCI1_MEM_SIZE);
+	pciMapSpace(PCI_HOST1, PCI_REGION0, CONFIG_SYS_PCI1_0_MEM_SPACE,
+		CONFIG_SYS_PCI1_0_MEM_SPACE, CONFIG_SYS_PCI1_MEM_SIZE);
 
 	pciMapSpace(PCI_HOST1, PCI_REGION1, 0, 0, 0);
 	pciMapSpace(PCI_HOST1, PCI_REGION2, 0, 0, 0);
 	pciMapSpace(PCI_HOST1, PCI_REGION3, 0, 0, 0);
 
-	pciMapSpace(PCI_HOST1, PCI_IO, CFG_PCI1_IO_SPACE_PCI,
-		CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE);
+	pciMapSpace(PCI_HOST1, PCI_IO, CONFIG_SYS_PCI1_IO_SPACE_PCI,
+		CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE);
 
 	/* PCI interface settings */
 	GT_REG_WRITE(PCI_0TIMEOUT_RETRY, 0xffff);
@@ -201,7 +201,7 @@
 	 * that if it's not at the power-on location, it's where we put
 	 * it last time. (huber)
 	 */
-	my_remap_gt_regs(CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs(CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 	gt_pci_config();
 
@@ -218,7 +218,7 @@
 	GT_REG_WRITE(CPU_INT_3_MASK, 0);
 
 	/* now, onto the configuration */
-	GT_REG_WRITE(SDRAM_CONFIGURATION, CFG_SDRAM_CONFIG);
+	GT_REG_WRITE(SDRAM_CONFIGURATION, CONFIG_SYS_SDRAM_CONFIG);
 
 	/* ----- DEVICE BUS SETTINGS ------ */
 
@@ -245,61 +245,61 @@
 	/* Zuma has no SRAM */
 	sram_boot = 0;
 #else
-	if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CFG_MONITOR_BASE)
+	if (memoryGetDeviceBaseAddress(DEVICE0) && 0xfff00000 == CONFIG_SYS_MONITOR_BASE)
 		sram_boot = 1;
 #endif
 
-		memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
+		memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
 
-	memoryMapDeviceSpace(DEVICE1, CFG_DEV1_SPACE, CFG_DEV1_SIZE);
-	memoryMapDeviceSpace(DEVICE2, CFG_DEV2_SPACE, CFG_DEV2_SIZE);
-	memoryMapDeviceSpace(DEVICE3, CFG_DEV3_SPACE, CFG_DEV3_SIZE);
+	memoryMapDeviceSpace(DEVICE1, CONFIG_SYS_DEV1_SPACE, CONFIG_SYS_DEV1_SIZE);
+	memoryMapDeviceSpace(DEVICE2, CONFIG_SYS_DEV2_SPACE, CONFIG_SYS_DEV2_SIZE);
+	memoryMapDeviceSpace(DEVICE3, CONFIG_SYS_DEV3_SPACE, CONFIG_SYS_DEV3_SIZE);
 
 	/* configure device timing */
-#ifdef CFG_DEV0_PAR
+#ifdef CONFIG_SYS_DEV0_PAR
 	if (!sram_boot)
-		GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CFG_DEV0_PAR);
+		GT_REG_WRITE(DEVICE_BANK0PARAMETERS, CONFIG_SYS_DEV0_PAR);
 #endif
 
-#ifdef CFG_DEV1_PAR
-	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CFG_DEV1_PAR);
+#ifdef CONFIG_SYS_DEV1_PAR
+	GT_REG_WRITE(DEVICE_BANK1PARAMETERS, CONFIG_SYS_DEV1_PAR);
 #endif
-#ifdef CFG_DEV2_PAR
-	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CFG_DEV2_PAR);
+#ifdef CONFIG_SYS_DEV2_PAR
+	GT_REG_WRITE(DEVICE_BANK2PARAMETERS, CONFIG_SYS_DEV2_PAR);
 #endif
 
 #ifdef CONFIG_EVB64260
-#ifdef CFG_32BIT_BOOT_PAR
+#ifdef CONFIG_SYS_32BIT_BOOT_PAR
 	/* detect if we are booting from the 32 bit flash */
 	if (GTREGREAD(DEVICE_BOOT_BANK_PARAMETERS) & (0x3 << 20)) {
 		/* 32 bit boot flash */
-		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_8BIT_BOOT_PAR);
-		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_32BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
 	} else {
 		/* 8 bit boot flash */
-		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CFG_32BIT_BOOT_PAR);
-		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BANK3PARAMETERS, CONFIG_SYS_32BIT_BOOT_PAR);
+		GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 	}
 #else
 	/* 8 bit boot flash only */
-	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_8BIT_BOOT_PAR);
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_8BIT_BOOT_PAR);
 #endif
 #else /* CONFIG_EVB64260 not defined */
 		/* We are booting from 16-bit flash.
 		 */
-	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_16BIT_BOOT_PAR);
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_16BIT_BOOT_PAR);
 #endif
 
 	gt_cpu_config();
 
 	/* MPP setup */
-	GT_REG_WRITE(MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE(MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE(MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE(MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE(MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE(MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE(MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE(MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE(GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
-	GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CFG_SERIAL_PORT_MUX);
+	GT_REG_WRITE(GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE(SERIAL_PORT_MULTIPLEX, CONFIG_SYS_SERIAL_PORT_MUX);
 
 	return 0;
 }
@@ -309,7 +309,7 @@
 int misc_init_r (void)
 {
 	icache_enable();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable();
 #endif
 
@@ -330,9 +330,9 @@
 	 * back to the way they should be. (we're running from main
 	 * memory at this point now */
 
-	if (memoryGetDeviceBaseAddress(DEVICE0) == CFG_MONITOR_BASE) {
-		memoryMapDeviceSpace(DEVICE0, CFG_DEV0_SPACE, CFG_DEV0_SIZE);
-		memoryMapDeviceSpace(BOOT_DEVICE, CFG_FLASH_BASE, _1M);
+	if (memoryGetDeviceBaseAddress(DEVICE0) == CONFIG_SYS_MONITOR_BASE) {
+		memoryMapDeviceSpace(DEVICE0, CONFIG_SYS_DEV0_SPACE, CONFIG_SYS_DEV0_SIZE);
+		memoryMapDeviceSpace(BOOT_DEVICE, CONFIG_SYS_FLASH_BASE, _1M);
 	}
 
 	/* now, jump to the main U-Boot board init code */
@@ -350,7 +350,7 @@
 int
 checkboard (void)
 {
-	puts ("Board: " CFG_BOARD_NAME "\n");
+	puts ("Board: " CONFIG_SYS_BOARD_NAME "\n");
 	return (0);
 }
 
@@ -365,29 +365,29 @@
 	if (mode == 1) {
 		switch (led) {
 		case 0:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x08000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x08000);
 			break;
 
 		case 1:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x0c000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x0c000);
 			break;
 
 		case 2:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x10000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x10000);
 			break;
 		}
 	} else if (mode == 0) {
 		switch (led) {
 		case 0:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x14000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x14000);
 			break;
 
 		case 1:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x18000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x18000);
 			break;
 
 		case 2:
-			addr = (int *)((unsigned int)CFG_DEV1_SPACE | 0x1c000);
+			addr = (int *)((unsigned int)CONFIG_SYS_DEV1_SPACE | 0x1c000);
 			break;
 		}
 	}
diff --git a/board/evb64260/flash.c b/board/evb64260/flash.c
index f2d5390..115e8cd 100644
--- a/board/evb64260/flash.c
+++ b/board/evb64260/flash.c
@@ -46,7 +46,7 @@
 int flash_erase_intel(flash_info_t *info, int s_first, int s_last);
 int write_word_intel(bank_addr_t addr, bank_word_t value);
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -67,16 +67,16 @@
 	unsigned long base, flash_size;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* the boot flash */
-	base = CFG_FLASH_BASE;
-#ifndef CFG_BOOT_FLASH_WIDTH
-#define CFG_BOOT_FLASH_WIDTH	1
+	base = CONFIG_SYS_FLASH_BASE;
+#ifndef CONFIG_SYS_BOOT_FLASH_WIDTH
+#define CONFIG_SYS_BOOT_FLASH_WIDTH	1
 #endif
-	size_b0 = flash_get_size(CFG_BOOT_FLASH_WIDTH, (vu_long *)base,
+	size_b0 = flash_get_size(CONFIG_SYS_BOOT_FLASH_WIDTH, (vu_long *)base,
 	                         &flash_info[0]);
 
 #ifndef CONFIG_P3G4
@@ -90,9 +90,9 @@
 			base, size_b0, size_b0<<20);
 	}
 
-	base = memoryGetDeviceBaseAddress(CFG_EXTRA_FLASH_DEVICE);
-	for(i=1;i<CFG_MAX_FLASH_BANKS;i++) {
-	    unsigned long size = flash_get_size(CFG_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
+	base = memoryGetDeviceBaseAddress(CONFIG_SYS_EXTRA_FLASH_DEVICE);
+	for(i=1;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
+	    unsigned long size = flash_get_size(CONFIG_SYS_EXTRA_FLASH_WIDTH, (vu_long *)base, &flash_info[i]);
 
 #ifndef CONFIG_P3G4
 	    printf("[");
@@ -111,12 +111,12 @@
 	    base+=size;
 	}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-	              CFG_MONITOR_BASE,
-	              CFG_MONITOR_BASE + monitor_flash_len - 1,
-	              flash_get_info(CFG_MONITOR_BASE));
+	              CONFIG_SYS_MONITOR_BASE,
+	              CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+	              flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef  CONFIG_ENV_IS_IN_FLASH
@@ -183,13 +183,13 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -682,7 +682,7 @@
 	addr = (volatile unsigned char *)(info->start[l_sect]);
 	/* broken for 2x16: TODO */
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -846,7 +846,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/evb64260/intel_flash.c b/board/evb64260/intel_flash.c
index ed6a2a0..994264a 100644
--- a/board/evb64260/intel_flash.c
+++ b/board/evb64260/intel_flash.c
@@ -157,7 +157,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -234,7 +234,7 @@
 			do {
 				now = get_timer(start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					break;
diff --git a/board/evb64260/intel_flash.h b/board/evb64260/intel_flash.h
index dc2aa00..cc3a339 100644
--- a/board/evb64260/intel_flash.h
+++ b/board/evb64260/intel_flash.h
@@ -42,7 +42,7 @@
 /* ID and Lock Configuration */
 #define CHIP_RD_ID_LOCK		0x01		/* Bit 0 of each byte */
 #define CHIP_RD_ID_MAN		0x89		/* Manufacturer code = 0x89 */
-#define CHIP_RD_ID_DEV		CFG_FLASH_ID
+#define CHIP_RD_ID_DEV		CONFIG_SYS_FLASH_ID
 
 /* dimensions */
 #define CHIP_WIDTH		2		/* chips are in 16 bit mode */
diff --git a/board/evb64260/local.h b/board/evb64260/local.h
index 3d9b443..8a3f4b2 100644
--- a/board/evb64260/local.h
+++ b/board/evb64260/local.h
@@ -26,7 +26,7 @@
 /* #define CONFIG_BOOTCOMMAND */
 /* #define CONFIG_RAMBOOTCOMMAND */
 /* #define CONFIG_NFSBOOTCOMMAND */
-/* #define CFG_AUTOLOAD */
+/* #define CONFIG_SYS_AUTOLOAD */
 /* #define CONFIG_PREBOOT */
 
 /* These don't */
diff --git a/board/evb64260/misc.S b/board/evb64260/misc.S
index 438dea6..f09528d 100644
--- a/board/evb64260/misc.S
+++ b/board/evb64260/misc.S
@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */
diff --git a/board/evb64260/mpsc.c b/board/evb64260/mpsc.c
index 3b338c7..8c4a4c8 100644
--- a/board/evb64260/mpsc.c
+++ b/board/evb64260/mpsc.c
@@ -390,7 +390,7 @@
 
 #if defined(CONFIG_ZUMA_V2) || defined(CONFIG_P3G4)
 	/* from tclk */
-	clock = (CFG_BUS_HZ/(16*rate)) - 1;
+	clock = (CONFIG_SYS_BUS_HZ/(16*rate)) - 1;
 #else
 	clock = (3686400/(16*rate)) - 1;
 #endif
diff --git a/board/evb64260/pci.c b/board/evb64260/pci.c
index 59b9acb..582f24c 100644
--- a/board/evb64260/pci.c
+++ b/board/evb64260/pci.c
@@ -675,14 +675,14 @@
 	local_buses[0] = pci0_hose.first_busno;
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -720,14 +720,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
diff --git a/board/evb64260/sdram_init.c b/board/evb64260/sdram_init.c
index 9ae4465..e2f0769 100644
--- a/board/evb64260/sdram_init.c
+++ b/board/evb64260/sdram_init.c
@@ -300,7 +300,7 @@
 
 	DP (printf ("tpar set to: %d\n", info->tpar));
 
-#ifdef CFG_BROKEN_CL2
+#ifdef CONFIG_SYS_BROKEN_CL2
 	if (info->tpar == 2) {
 		info->tpar = 3;
 		DP (printf ("tpar fixed-up to: %d\n", info->tpar));
@@ -598,7 +598,7 @@
 	 *         limitation: we only support 256M per bank due to
 	 *         us only having 1 BAT for all DRAM
 	 */
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		/* skip over banks that are not populated */
 		if (!checkbank[bank_no])
 			continue;
@@ -617,7 +617,7 @@
 	 *         space.
 	 */
 	dimm_info[0].banks = dimm_info[1].banks = 0;
-	for (bank_no = 0; bank_no < CFG_DRAM_BANKS; bank_no++) {
+	for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
 		if (!checkbank[bank_no])
 			continue;
 
diff --git a/board/evb64260/serial.c b/board/evb64260/serial.c
index f1bcab3..9d71115 100644
--- a/board/evb64260/serial.c
+++ b/board/evb64260/serial.c
@@ -31,7 +31,7 @@
 #include <command.h>
 #include <galileo/memory.h>
 
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
 #include <ns16550.h>
 #endif
 
@@ -41,26 +41,26 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
-const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
-				(NS16550_t) CFG_NS16550_COM2 };
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
+				(NS16550_t) CONFIG_SYS_NS16550_COM2 };
 #endif
 
 #ifdef CONFIG_MPSC
 
 int serial_init (void)
 {
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 #endif
 
 	mpsc_init(gd->baudrate);
 
 	/* init the DUART chans so that KGDB in the kernel can use them */
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit(COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit(COM_PORTS[1], clock_divisor);
 #endif
 	return (0);
@@ -97,12 +97,12 @@
 
 int serial_init (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	(void)NS16550_init(COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	(void)NS16550_init(COM_PORTS[1], clock_divisor);
 #endif
 
@@ -113,32 +113,32 @@
 serial_putc(const char c)
 {
 	if (c == '\n')
-		NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int
 serial_getc(void)
 {
-	return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int
 serial_tstc(void)
 {
-	return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void
 serial_setbrg (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit(COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit(COM_PORTS[1], clock_divisor);
 #endif
 }
diff --git a/board/exbitgen/flash.c b/board/exbitgen/flash.c
index 745fba2..cd45cb6 100644
--- a/board/exbitgen/flash.c
+++ b/board/exbitgen/flash.c
@@ -33,7 +33,7 @@
 #include <asm/processor.h>
 #include <ppc4xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -68,7 +68,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].size = 0;
 	}
@@ -76,7 +76,7 @@
 	tot_size = 0;
 
 	/* Detect Boot Flash */
-	bank_addr = CFG_FLASH0_BASE;
+	bank_addr = CONFIG_SYS_FLASH0_BASE;
 	bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[0]);
 	if (bank_size > 0) {
 		(void)flash_protect(FLAG_PROTECT_CLEAR,
@@ -91,8 +91,8 @@
 	tot_size += bank_size;
 
 	/* Detect Application Flash */
-	bank_addr = CFG_FLASH1_BASE;
-	for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
+	bank_addr = CONFIG_SYS_FLASH1_BASE;
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		bank_size = flash_get_size((vu_long *)bank_addr, &flash_info[i]);
 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
 			break;
@@ -112,13 +112,13 @@
 	}
 
 	/* Protect monitor and environment sectors */
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect(FLAG_PROTECT_SET,
-		CFG_MONITOR_BASE,
-		CFG_MONITOR_BASE + monitor_flash_len - 1,
+		CONFIG_SYS_MONITOR_BASE,
+		CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		&flash_info[0]);
-#if 0xfffffffc >= CFG_FLASH0_BASE
-#if 0xfffffffc <= CFG_FLASH0_BASE + CFG_FLASH0_SIZE - 1
+#if 0xfffffffc >= CONFIG_SYS_FLASH0_BASE
+#if 0xfffffffc <= CONFIG_SYS_FLASH0_BASE + CONFIG_SYS_FLASH0_SIZE - 1
 	flash_protect(FLAG_PROTECT_SET,
 		0xfffffffc, 0xffffffff,
 		&flash_info[0]);
@@ -450,7 +450,7 @@
 			while ((addr2[0] & 0x00800080) !=
 				(FLASH_WORD_SIZE) 0x00800080) {
 				if ((now=get_timer(start)) >
-					   CFG_FLASH_ERASE_TOUT) {
+					   CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					addr[0] = (FLASH_WORD_SIZE)0x00F000F0;
 					return 1;
@@ -581,7 +581,7 @@
 		/* data polling for D7 */
 		start = get_timer (0);
 		while ((dest2[i] & 0x00800080) != (data2[i] & 0x00800080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				addr2[0] = (FLASH_WORD_SIZE)0x00F000F0;
 				return (1);
 			}
diff --git a/board/exbitgen/init.S b/board/exbitgen/init.S
index 71aefb9..760835a 100644
--- a/board/exbitgen/init.S
+++ b/board/exbitgen/init.S
@@ -265,7 +265,7 @@
 	.globl  sdram_init
 
 sdram_init:
-#if CFG_MONITOR_BASE < CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE
 	blr
 #else
 	mflr	r31
@@ -402,7 +402,7 @@
 	addi	r9, 0, 13	/* bit offset of addressing mode in configuration register  */
 	slw	r29, r29, r9	/*  */
 	or	r3, r29, r3	/* merge size code and addressing mode */
-	ori	r6, r3, CFG_SDRAM_BASE + 1 /* insert base address and enable bank */
+	ori	r6, r3, CONFIG_SYS_SDRAM_BASE + 1 /* insert base address and enable bank */
 
 	/* Calculate banksize r15 = (density << 22) / 2 */
 	/*--------------------------------------------- */
diff --git a/board/fads/fads.c b/board/fads/fads.c
index 9e601df..278fa2a 100644
--- a/board/fads/fads.c
+++ b/board/fads/fads.c
@@ -190,7 +190,7 @@
 /* ------------------------------------------------------------------------- */
 static int _draminit (uint base, uint noMbytes, uint edo, uint delay)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/* init upm */
@@ -283,7 +283,7 @@
 
 static void _dramdisable(void)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_br2 = 0x00000000;
@@ -423,7 +423,7 @@
 
 static int _initsdram(uint base, uint noMbytes)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
@@ -501,7 +501,7 @@
 
 static int _initsdram(uint base, uint noMbytes)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig(UPMB, (uint *)sdram_table,sizeof(sdram_table)/sizeof(uint));
@@ -564,7 +564,7 @@
 
 static void _sdramdisable(void)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_br4 = 0x00000000;
@@ -576,7 +576,7 @@
 
 static int initsdram(uint base, uint *noMbytes)
 {
-	uint m = CFG_SDRAM_SIZE>>20;
+	uint m = CONFIG_SYS_SDRAM_SIZE>>20;
 
 	/* _initsdram needs access to sdram */
 	*((uint *)BCSR1) |= BCSR1_SDRAM_EN; /* enable sdram */
@@ -688,7 +688,7 @@
  * Check Board Identity:
  */
 
-#if defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD)
+#if defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD)
 static void checkdboard(void)
 {
 	/* get db type from BCSR 3 */
@@ -722,7 +722,7 @@
 	default : printf("0x%x", k);
 	}
 }
-#endif	/* defined(CONFIG_FADS) && defined(CFG_DAUGHTERBOARD) */
+#endif	/* defined(CONFIG_FADS) && defined(CONFIG_SYS_DAUGHTERBOARD) */
 
 int checkboard (void)
 {
@@ -780,8 +780,8 @@
 
 #if defined(CONFIG_CMD_PCMCIA)
 
-#ifdef CFG_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char*)CFG_PCMCIA_MEM_ADDR;
+#ifdef CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char*)CONFIG_SYS_PCMCIA_MEM_ADDR;
 #endif
 
 int pcmcia_init(void)
@@ -792,10 +792,10 @@
 	/*
 	** Enable the PCMCIA for a Flash card.
 	*/
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 #if 0
-	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
 	pcmp->pcmc_por0 = 0xc00ff05d;
 #endif
 
@@ -925,25 +925,25 @@
 
 /* ========================================================================= */
 
-#ifdef CFG_PC_IDE_RESET
+#ifdef CONFIG_SYS_PC_IDE_RESET
 
 void ide_set_reset(int on)
 {
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 
 	/*
 	 * Configure PC for IDE Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 	} else {		/* release RESET */
-		immr->im_ioport.iop_pcdat |=   CFG_PC_IDE_RESET;
+		immr->im_ioport.iop_pcdat |=   CONFIG_SYS_PC_IDE_RESET;
 	}
 
 	/* program port pin as GPIO output */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcso  &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcdir |=   CFG_PC_IDE_RESET;
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |=   CONFIG_SYS_PC_IDE_RESET;
 }
 
-#endif	/* CFG_PC_IDE_RESET */
+#endif	/* CONFIG_SYS_PC_IDE_RESET */
diff --git a/board/fads/fads.h b/board/fads/fads.h
index 23310a4..24e43ea 100644
--- a/board/fads/fads.h
+++ b/board/fads/fads.h
@@ -95,7 +95,7 @@
 #endif
 
 #ifdef CONFIG_FEC_ENET
-#define CFG_DISCOVER_PHY
+#define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_MII_INIT		1
 #endif
 
@@ -130,24 +130,24 @@
 /*
  * Miscellaneous configurable options
  */
-#define	CFG_PROMPT		"=>"		/* Monitor Command Prompt	*/
-#define CFG_HUSH_PARSER
-#define CFG_PROMPT_HUSH_PS2	"> "
-#define	CFG_LONGHELP				/* #undef to save memory	*/
+#define	CONFIG_SYS_PROMPT		"=>"		/* Monitor Command Prompt	*/
+#define CONFIG_SYS_HUSH_PARSER
+#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
+#define	CONFIG_SYS_LONGHELP				/* #undef to save memory	*/
 #if defined(CONFIG_CMD_KGDB)
-#define	CFG_CBSIZE		1024		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
 #else
-#define	CFG_CBSIZE		256		/* Console I/O Buffer Size	*/
+#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
 #endif
-#define	CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) /* Print Buffer Size	*/
-#define	CFG_MAXARGS		16		/* max number of command args	*/
-#define CFG_BARGSIZE		CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size	*/
+#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
+#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
 
-#define CFG_LOAD_ADDR		0x00100000
+#define CONFIG_SYS_LOAD_ADDR		0x00100000
 
-#define	CFG_HZ		        1000	/* decrementer freq: 1 ms ticks */
+#define	CONFIG_SYS_HZ		        1000	/* decrementer freq: 1 ms ticks */
 
-#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
 
 /*
  * Low Level Configuration Settings
@@ -158,25 +158,25 @@
 /*-----------------------------------------------------------------------
  * Internal Memory Mapped Register
  */
-#define CFG_IMMR		0xFF000000
+#define CONFIG_SYS_IMMR		0xFF000000
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)
  */
-#define CFG_INIT_RAM_ADDR	CFG_IMMR
-#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
-#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
-#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
-#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
+#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*-----------------------------------------------------------------------
  * Start addresses for the final memory configuration
  * (Set up by the startup code)
- * Please note that CFG_SDRAM_BASE _must_ start at 0
+ * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  */
-#define	CFG_SDRAM_BASE		0x00000000
+#define	CONFIG_SYS_SDRAM_BASE		0x00000000
 #if defined(CONFIG_MPC86xADS) || defined(CONFIG_MPC885ADS) /* New ADS or Duet */
-#define	CFG_SDRAM_SIZE		0x00800000	/* 8 Mbyte */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00800000	/* 8 Mbyte */
 /*
  * 2048	SDRAM rows
  * 1000	factor s -> ms
@@ -184,55 +184,55 @@
  * 4	Number of refresh cycles per period
  * 64	Refresh cycle in ms per number of rows
  */
-#define CFG_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
+#define CONFIG_SYS_PTA_PER_CLK		((2048 * 64 * 1000) / (4 * 64))
 #elif defined(CONFIG_FADS)				/* Old/new FADS */
-#define	CFG_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00400000		/* 4 Mbyte */
 #else							/* Old ADS */
-#define	CFG_SDRAM_SIZE		0x00000000		/* No SDRAM */
+#define	CONFIG_SYS_SDRAM_SIZE		0x00000000		/* No SDRAM */
 #endif
 
-#define CFG_MEMTEST_START	0x0100000	/* memtest works on	*/
-#if (CFG_SDRAM_SIZE)
-#define CFG_MEMTEST_END		CFG_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
+#define CONFIG_SYS_MEMTEST_START	0x0100000	/* memtest works on	*/
+#if (CONFIG_SYS_SDRAM_SIZE)
+#define CONFIG_SYS_MEMTEST_END		CONFIG_SYS_SDRAM_SIZE	/* 1 ... SDRAM_SIZE	*/
 #else
-#define CFG_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
-#endif /* CFG_SDRAM_SIZE */
+#define CONFIG_SYS_MEMTEST_END		0x0400000	/* 1 ... 4 MB in DRAM	*/
+#endif /* CONFIG_SYS_SDRAM_SIZE */
 
 /*
  * For booting Linux, the board info and command line data
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
 
-#define CFG_MONITOR_BASE	TEXT_BASE
-#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
+#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE
+#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/
 
 #ifdef CONFIG_BZIP2
-#define	CFG_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
+#define	CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
 #else
-#define	CFG_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
+#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
 #endif /* CONFIG_BZIP2 */
 
 /*-----------------------------------------------------------------------
  * Flash organization
  */
-#define CFG_FLASH_BASE		CFG_MONITOR_BASE
-#define CFG_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/
+#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_MONITOR_BASE
+#define CONFIG_SYS_FLASH_SIZE		((uint)(8 * 1024 * 1024))	/* max 8Mbyte	*/
 
-#define CFG_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
-#define CFG_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
+#define CONFIG_SYS_MAX_FLASH_BANKS	4	/* max number of memory banks		*/
+#define CONFIG_SYS_MAX_FLASH_SECT	8	/* max number of sectors on one chip	*/
 
-#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
-#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
 
 #define	CONFIG_ENV_IS_IN_FLASH	1
 #define CONFIG_ENV_SECT_SIZE	0x40000	/* see README - env sector total size	*/
 #define CONFIG_ENV_OFFSET		CONFIG_ENV_SECT_SIZE
 #define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment		*/
-#define	CFG_USE_PPCENV			/* Environment embedded in sect .ppcenv */
+#define	CONFIG_SYS_USE_PPCENV			/* Environment embedded in sect .ppcenv */
 
-#define	CFG_DIRECT_FLASH_TFTP
+#define	CONFIG_SYS_DIRECT_FLASH_TFTP
 
 #if defined(CONFIG_CMD_JFFS2)
 
@@ -254,22 +254,22 @@
 #define MTDPARTS_DEFAULT	"mtdparts=fads-0:-@1m(user1),fads-1:-(user2),fads-2:-(user3),fads-3:-(user4)"
 */
 
-#define CFG_JFFS2_SORT_FRAGMENTS
+#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS
 #endif
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 
 /*-----------------------------------------------------------------------
  * I2C configuration
  */
 #if defined(CONFIG_CMD_I2C)
 #define CONFIG_HARD_I2C		1	/* I2C with hardware support */
-#define CFG_I2C_SPEED		400000	/* I2C speed and slave address defaults */
-#define CFG_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address defaults */
+#define CONFIG_SYS_I2C_SLAVE		0x7F
 #endif
 
 /*-----------------------------------------------------------------------
@@ -279,10 +279,10 @@
  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  */
 #if defined(CONFIG_WATCHDOG)
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 #else
-#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 #endif
 
 /*-----------------------------------------------------------------------
@@ -290,21 +290,21 @@
  *-----------------------------------------------------------------------
  * PCMCIA config., multi-function pin tri-state
  */
-#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 
 /*-----------------------------------------------------------------------
  * TBSCR - Time Base Status and Control				11-26
  *-----------------------------------------------------------------------
  * Clear Reference Interrupt Status, Timebase freezing enabled
  */
-#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
+#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
 
 /*-----------------------------------------------------------------------
  * PISCR - Periodic Interrupt Status and Control		11-31
  *-----------------------------------------------------------------------
  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  */
-#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)
 
 /*-----------------------------------------------------------------------
  * SCCR - System Clock and reset Control Register		15-27
@@ -313,14 +313,14 @@
  * power management and some other internal clocks
  */
 #define SCCR_MASK	SCCR_EBDF11
-#define CFG_SCCR	SCCR_TBS
+#define CONFIG_SYS_SCCR	SCCR_TBS
 
 /*-----------------------------------------------------------------------
  * DER - Debug Enable Register
  *-----------------------------------------------------------------------
  * Set to zero to prevent the processor from entering debug mode
  */
-#define CFG_DER		 0
+#define CONFIG_SYS_DER		 0
 
 /* Because of the way the 860 starts up and assigns CS0 the entire
  * address space, we have to set the memory controller differently.
@@ -339,17 +339,17 @@
 
 #define BCSR_ADDR		((uint) 0xFF080000)
 
-#define CFG_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
+#define CONFIG_SYS_PRELIM_OR_AM	0xFF800000	/* OR addr mask */
 
 /* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
-#define CFG_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
+#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
 
-#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
-#define CFG_BR0_PRELIM	((CFG_FLASH_BASE & BR_BA_MSK) | BR_V )
+#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)   /* 8 Mbyte until detected */
+#define CONFIG_SYS_BR0_PRELIM	((CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_V )
 
 /* BCSRx - Board Control and Status Registers */
-#define CFG_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
-#define CFG_BR1_PRELIM	((BCSR_ADDR) | BR_V)
+#define CONFIG_SYS_OR1_PRELIM	0xFFFF8110		/* 64Kbyte address space */
+#define CONFIG_SYS_BR1_PRELIM	((BCSR_ADDR) | BR_V)
 
 /*
  * Internal Definitions
@@ -442,9 +442,9 @@
 
 /* BSCR5 exists on MPC86xADS and MPC885ADS only */
 
-#define CFG_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
+#define CONFIG_SYS_PHYDEV_ADDR		(BCSR_ADDR + 0x20000)
 
-#define BCSR5			(CFG_PHYDEV_ADDR + 0x300)
+#define BCSR5			(CONFIG_SYS_PHYDEV_ADDR + 0x300)
 
 #define BCSR5_MII2_EN		0x40
 #define BCSR5_MII2_RST		0x20
@@ -462,14 +462,14 @@
  * PCMCIA stuff
  *-----------------------------------------------------------------------
  */
-#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
-#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
-#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
-#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
-#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
-#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
+#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )
 
 /*-----------------------------------------------------------------------
  * IDE/ATA stuff
@@ -487,18 +487,18 @@
 #undef	CONFIG_IDE_LED			/* LED	 for ide not supported	*/
 #undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
 
-#define CFG_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
-#define CFG_IDE_MAXDEVICE	(CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
+#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 2 IDE busses	*/
+#define CONFIG_SYS_IDE_MAXDEVICE	(CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
 
-#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
-#define CFG_ATA_IDE0_OFFSET	0x0000
+#define CONFIG_SYS_ATA_BASE_ADDR	CONFIG_SYS_PCMCIA_MEM_ADDR
+#define CONFIG_SYS_ATA_IDE0_OFFSET	0x0000
 
 /* Offset for data I/O			*/
-#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_DATA_OFFSET	(CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for normal register accesses	*/
-#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+#define CONFIG_SYS_ATA_REG_OFFSET	(2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 /* Offset for alternate registers	*/
-#define CFG_ATA_ALT_OFFSET	0x0000
+#define CONFIG_SYS_ATA_ALT_OFFSET	0x0000
 
 #define CONFIG_DISK_SPINUP_TIME 1000000
 /* #undef CONFIG_DISK_SPINUP_TIME */	/* usin  Compact Flash */
diff --git a/board/fads/flash.c b/board/fads/flash.c
index cd0e4d5..b9afb75 100644
--- a/board/fads/flash.c
+++ b/board/fads/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -54,14 +54,14 @@
  */
 unsigned long flash_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	vu_long *bcsr = (vu_long *)BCSR_ADDR;
 	unsigned long pd_size, total_size, bsize, or_am;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].size = 0;
 		flash_info[i].sector_count = 0;
@@ -94,8 +94,8 @@
 	}
 
 	total_size = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
-		bsize = flash_get_size((vu_long *)(CFG_FLASH_BASE + total_size),
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && total_size < pd_size; ++i) {
+		bsize = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + total_size),
 				       &flash_info[i]);
 
 		if (flash_info[i].flash_id == FLASH_UNKNOWN) {
@@ -112,15 +112,15 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = or_am | CFG_OR_TIMING_FLASH;
+	memctl->memc_or0 = or_am | CONFIG_SYS_OR_TIMING_FLASH;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS && flash_info[i].size != 0; ++i) {
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
-		if (CFG_MONITOR_BASE >= flash_info[i].start[0])
+		if (CONFIG_SYS_MONITOR_BASE >= flash_info[i].start[0])
 			flash_protect (FLAG_PROTECT_SET,
-				       CFG_MONITOR_BASE,
-				       CFG_MONITOR_BASE + monitor_flash_len - 1,
+				       CONFIG_SYS_MONITOR_BASE,
+				       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 				       &flash_info[i]);
 #endif
 
@@ -428,7 +428,7 @@
 	addr = (vu_long *) (info->start[l_sect]);
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
 	{
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return ERR_TIMOUT;
 		}
@@ -552,7 +552,7 @@
 	start = get_timer (0);
 	while ((*((vu_long *) dest) & 0x80808080) != (data & 0x80808080))
 	{
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return ERR_TIMOUT;
 		}
 	}
diff --git a/board/flagadm/flagadm.c b/board/flagadm/flagadm.c
index 7caedc9..dc9e2dc 100644
--- a/board/flagadm/flagadm.c
+++ b/board/flagadm/flagadm.c
@@ -98,18 +98,18 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0;
 
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 
 	udelay(100);
 	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
 	memctl->memc_mptpr = MPTPR_PTP_DIV16;
-	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_1X;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_1X;
 
 	/*Do the initialization of the SDRAM*/
 	/*Start with the precharge cycle*/
@@ -117,7 +117,7 @@
 				MCR_MLCF(1) | MCR_MAD(0x5));
 
 	/*Then we need two refresh cycles*/
-	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_2X;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_2X;
 	memctl->memc_mcr = (MCR_OP_RUN | MCR_UPM_A | MCR_MB_CS2 | \
 				MCR_MLCF(2) | MCR_MAD(0x30));
 
@@ -127,7 +127,7 @@
 				MCR_MLCF(1) | MCR_MAD(0x1C));
 
 	/* That should do it, just enable the periodic refresh in burst of 4*/
-	memctl->memc_mamr = CFG_MAMR_48_SDR | MAMR_TLFA_4X;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_48_SDR | MAMR_TLFA_4X;
 	memctl->memc_mamr |= (MAMR_PTAE | MAMR_GPL_A4DIS);
 
 	size_b0 = 16*1024*1024;
@@ -143,8 +143,8 @@
 
 	memctl->memc_mbmr = MBMR_GPL_B4DIS;
 
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 
 	return (size_b0);
 }
diff --git a/board/flagadm/flash.c b/board/flagadm/flash.c
index aa8b0f9..bbefbac 100644
--- a/board/flagadm/flash.c
+++ b/board/flagadm/flash.c
@@ -25,7 +25,7 @@
 #include <mpc8xx.h>
 #include <flash.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -39,45 +39,45 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t	*memctl = &immap->im_memctl;
 	int i;
 	int rec;
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	*((vu_short*)CFG_FLASH_BASE) = 0xffff;
+	*((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
 
-	flash_get_geometry ((vu_long*)CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_geometry ((vu_long*)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
 		(memctl->memc_br0 & ~(BR_BA_MSK));
 
-	rec = flash_recognize((vu_long*)CFG_FLASH_BASE);
+	rec = flash_recognize((vu_long*)CONFIG_SYS_FLASH_BASE);
 
 	if (rec == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				flash_info[0].size, flash_info[0].size<<20);
 	}
 
-#if CFG_FLASH_PROTECTION
+#if CONFIG_SYS_FLASH_PROTECTION
 	/*Unprotect all the flash memory*/
 	flash_unprotect(&flash_info[0]);
 #endif
 
-	*((vu_short*)CFG_FLASH_BASE) = 0xffff;
+	*((vu_short*)CONFIG_SYS_FLASH_BASE) = 0xffff;
 
 	return (flash_info[0].size);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -400,7 +400,7 @@
 			*addr = 0x70; /*Read status register command*/
 			tmp = (short)*addr & 0x00FF; /* Read the status */
 			while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0x0050; /* Reset the status register */
 					*addr = 0xffff;
 					printf ("Timeout\n");
@@ -440,7 +440,7 @@
 	for(i = 0; i < info->sector_count; i++)
 		info->protect[i] = 0;
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 		_flash_real_protect(info, 0, 0);
 #endif
 }
@@ -555,7 +555,7 @@
 		flag  = 0;
 		*addr = 0x0070; /*Read statusregister command */
 		while (((csr = *addr) & INTEL_FLASH_STATUS_WSMS)!=INTEL_FLASH_STATUS_WSMS) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flag = 1;
 				break;
 			}
@@ -642,7 +642,7 @@
 	while(!(tmp & INTEL_FLASH_STATUS_WSMS)) {
 		/*Write State Machine Busy*/
 		/*Wait untill done or timeout.*/
-		if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = 0x0050; /* Reset the status register */
 			*addr = 0xffff; /* Reset the chip */
 			printf ("TTimeout\n");
@@ -670,7 +670,7 @@
 	tmp = ((ushort)(*addr)) & 0x00FF; /* Read the status */
 	while (!(tmp & INTEL_FLASH_STATUS_WSMS)) {
 		/* Write State Machine Busy */
-		if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = 0x0050; /* Reset the status register */
 			*addr = 0xffff;
 			printf ("Timeout\n");
diff --git a/board/freescale/common/cadmus.c b/board/freescale/common/cadmus.c
index 5f86de5..db54bc4 100644
--- a/board/freescale/common/cadmus.c
+++ b/board/freescale/common/cadmus.c
@@ -27,8 +27,8 @@
 /*
  * CADMUS Board System Registers
  */
-#ifndef CFG_CADMUS_BASE_REG
-#define CFG_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
+#ifndef CONFIG_SYS_CADMUS_BASE_REG
+#define CONFIG_SYS_CADMUS_BASE_REG	(CADMUS_BASE_ADDR + 0x4000)
 #endif
 
 typedef struct cadmus_reg {
@@ -47,7 +47,7 @@
 unsigned int
 get_board_version(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
 
 	return cadmus->cm_ver;
 }
@@ -56,7 +56,7 @@
 unsigned long
 get_clock_freq(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
 
 	uint pci1_speed = (cadmus->cm_pci >> 2) & 0x3; /* PSPEED in [4:5] */
 
@@ -74,7 +74,7 @@
 unsigned int
 get_pci_slot(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI slot in USER bits CSR[6:7] by convention.
@@ -86,7 +86,7 @@
 unsigned int
 get_pci_dual(void)
 {
-	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CFG_CADMUS_BASE_REG;
+	volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
 
 	/*
 	 * PCI DUAL in CM_PCI[3]
diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c
index 4d4b0a1..2fc878b 100644
--- a/board/freescale/common/fsl_diu_fb.c
+++ b/board/freescale/common/fsl_diu_fb.c
@@ -205,7 +205,7 @@
 	unsigned int i, j;
 
 	debug("Enter fsl_diu_init\n");
-	dr.diu_reg = (struct diu *) (CFG_DIU_ADDR);
+	dr.diu_reg = (struct diu *) (CONFIG_SYS_DIU_ADDR);
 	hw = (struct diu *) dr.diu_reg;
 
 	disable_lcdc();
diff --git a/board/freescale/common/pixis.c b/board/freescale/common/pixis.c
index b5a0e84..348696e 100644
--- a/board/freescale/common/pixis.c
+++ b/board/freescale/common/pixis.c
@@ -207,8 +207,8 @@
 	out8(PIXIS_BASE + PIXIS_VCFGEN1, tmp);
 }
 
-#ifndef CFG_PIXIS_VBOOT_MASK
-#define CFG_PIXIS_VBOOT_MASK	(0x40)
+#ifndef CONFIG_SYS_PIXIS_VBOOT_MASK
+#define CONFIG_SYS_PIXIS_VBOOT_MASK	(0x40)
 #endif
 
 void clear_altbank(void)
@@ -216,7 +216,7 @@
 	u8 tmp;
 
 	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
-	tmp &= ~CFG_PIXIS_VBOOT_MASK;
+	tmp &= ~CONFIG_SYS_PIXIS_VBOOT_MASK;
 
 	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
 }
@@ -227,7 +227,7 @@
 	u8 tmp;
 
 	tmp = in8(PIXIS_BASE + PIXIS_VBOOT);
-	tmp |= CFG_PIXIS_VBOOT_MASK;
+	tmp |= CONFIG_SYS_PIXIS_VBOOT_MASK;
 
 	out8(PIXIS_BASE + PIXIS_VBOOT, tmp);
 }
@@ -327,7 +327,7 @@
 }
 
 U_BOOT_CMD(
-		pixis_set_sgmii, CFG_MAXARGS, 1, pixis_set_sgmii,
+		pixis_set_sgmii, CONFIG_SYS_MAXARGS, 1, pixis_set_sgmii,
 		"pixis_set_sgmii"
 		" - Enable or disable SGMII mode for a given TSEC \n",
 		"\npixis_set_sgmii [TSEC num] <on|off|switch>\n"
@@ -518,7 +518,7 @@
 
 
 U_BOOT_CMD(
-	pixis_reset, CFG_MAXARGS, 1, pixis_reset_cmd,
+	pixis_reset, CONFIG_SYS_MAXARGS, 1, pixis_reset_cmd,
 	"pixis_reset - Reset the board using the FPGA sequencer\n",
 	"    pixis_reset\n"
 	"    pixis_reset [altbank]\n"
diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c
index 9bef92e..eb58c7f 100644
--- a/board/freescale/common/sys_eeprom.c
+++ b/board/freescale/common/sys_eeprom.c
@@ -30,8 +30,8 @@
 
 #include "../common/eeprom.h"
 
-#if !defined(CFG_I2C_EEPROM_CCID) && !defined(CFG_I2C_EEPROM_NXID)
-#error "Please define either CFG_I2C_EEPROM_CCID or CFG_I2C_EEPROM_NXID"
+#if !defined(CONFIG_SYS_I2C_EEPROM_CCID) && !defined(CONFIG_SYS_I2C_EEPROM_NXID)
+#error "Please define either CONFIG_SYS_I2C_EEPROM_CCID or CONFIG_SYS_I2C_EEPROM_NXID"
 #endif
 
 /**
@@ -40,7 +40,7 @@
  * See application note AN3638 for details.
  */
 static struct __attribute__ ((__packed__)) eeprom {
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
 	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'CCID' */
 	u8 major;         /* 0x04        Board revision, major */
 	u8 minor;         /* 0x05        Board revision, minor */
@@ -53,7 +53,7 @@
 	u8 mac[8][6];     /* 0x42 - 0x71 MAC addresses */
 	u32 crc;          /* 0x72        CRC32 checksum */
 #endif
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	u8 id[4];         /* 0x00 - 0x03 EEPROM Tag 'NXID' */
 	u8 sn[12];        /* 0x04 - 0x0F Serial Number */
 	u8 errata[5];     /* 0x10 - 0x14 Errata Level */
@@ -74,12 +74,12 @@
 /* Set to 1 if we've read EEPROM into memory */
 static int has_been_read = 0;
 
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 /* Is this a valid NXID EEPROM? */
 #define is_valid (*((u32 *)e.id) == (('N' << 24) | ('X' << 16) | ('I' << 8) | 'D'))
 #endif
 
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
 /* Is this a valid CCID EEPROM? */
 #define is_valid (*((u32 *)e.id) == (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
 #endif
@@ -93,7 +93,7 @@
 	unsigned int crc;
 
 	/* EEPROM tag ID, either CCID or NXID */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("ID: %c%c%c%c v%u\n", e.id[0], e.id[1], e.id[2], e.id[3],
 		be32_to_cpu(e.version));
 #else
@@ -104,7 +104,7 @@
 	printf("SN: %s\n", e.sn);
 
 	/* Errata level. */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	printf("Errata: %s\n", e.errata);
 #else
 	printf("Errata: %c%c\n",
@@ -152,22 +152,22 @@
 static int read_eeprom(void)
 {
 	int ret;
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	unsigned int bus;
 #endif
 
 	if (has_been_read)
 		return 0;
 
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
 #endif
 
-	ret = i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+	ret = i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 		(void *)&e, sizeof(e));
 
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	i2c_set_bus_num(bus);
 #endif
 
@@ -188,12 +188,12 @@
 	int ret, i, length;
 	unsigned int crc;
 	void *p;
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	unsigned int bus;
 #endif
 
 	/* Set the reserved values to 0xFF   */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 	e.res_0 = 0xFF;
 	memset(e.res_1, 0xFF, sizeof(e.res_1));
 #else
@@ -204,20 +204,20 @@
 	crc = crc32(0, (void *)&e, length - 4);
 	e.crc = cpu_to_be32(crc);
 
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	bus = i2c_get_bus_num();
-	i2c_set_bus_num(CFG_EEPROM_BUS_NUM);
+	i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM);
 #endif
 
 	for (i = 0, p = &e; i < length; i += 8, p += 8) {
-		ret = i2c_write(CFG_I2C_EEPROM_ADDR, i, CFG_I2C_EEPROM_ADDR_LEN,
+		ret = i2c_write(CONFIG_SYS_I2C_EEPROM_ADDR, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 			p, min((length - i), 8));
 		if (ret)
 			break;
 		udelay(5000);	/* 5ms write cycle timing */
 	}
 
-#ifdef CFG_EEPROM_BUS_NUM
+#ifdef CONFIG_SYS_EEPROM_BUS_NUM
 	i2c_set_bus_num(bus);
 #endif
 
@@ -343,7 +343,7 @@
 		strncpy((char *)e.sn, argv[2], sizeof(e.sn) - 1);
 		break;
 	case 'e':	/* errata */
-#ifdef CFG_I2C_EEPROM_NXID
+#ifdef CONFIG_SYS_I2C_EEPROM_NXID
 		memset(e.errata, 0, 5);
 		strncpy((char *)e.errata, argv[2], 4);
 #else
@@ -429,7 +429,7 @@
 	return 0;
 }
 
-#ifdef CFG_I2C_EEPROM_CCID
+#ifdef CONFIG_SYS_I2C_EEPROM_CCID
 
 /**
  * get_cpu_board_revision - get the CPU board revision on 85xx boards
@@ -439,11 +439,11 @@
  * This function is called before relocation, so we need to read a private
  * copy of the EEPROM into a local variable on the stack.
  *
- * Also, we assume that CFG_EEPROM_BUS_NUM == CFG_SPD_BUS_NUM.  The global
- * variable i2c_bus_num must be compile-time initialized to CFG_SPD_BUS_NUM,
+ * Also, we assume that CONFIG_SYS_EEPROM_BUS_NUM == CONFIG_SYS_SPD_BUS_NUM.  The global
+ * variable i2c_bus_num must be compile-time initialized to CONFIG_SYS_SPD_BUS_NUM,
  * so that the SPD code will work.  This means that all pre-relocation I2C
- * operations can only occur on the CFG_SPD_BUS_NUM bus.  So if
- * CFG_EEPROM_BUS_NUM != CFG_SPD_BUS_NUM, then we can't read the EEPROM when
+ * operations can only occur on the CONFIG_SYS_SPD_BUS_NUM bus.  So if
+ * CONFIG_SYS_EEPROM_BUS_NUM != CONFIG_SYS_SPD_BUS_NUM, then we can't read the EEPROM when
  * this function is called.  Oh well.
  */
 unsigned int get_cpu_board_revision(void)
@@ -454,7 +454,7 @@
 		u8 minor;         /* 0x05        Board revision, minor */
 	} be;
 
-	i2c_read(CFG_I2C_EEPROM_ADDR, 0, CFG_I2C_EEPROM_ADDR_LEN,
+	i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, CONFIG_SYS_I2C_EEPROM_ADDR_LEN,
 		(void *)&be, sizeof(be));
 
 	if (be.id != (('C' << 24) | ('C' << 16) | ('I' << 8) | 'D'))
diff --git a/board/freescale/m52277evb/m52277evb.c b/board/freescale/m52277evb/m52277evb.c
index e5f47d2..838a6de 100644
--- a/board/freescale/m52277evb/m52277evb.c
+++ b/board/freescale/m52277evb/m52277evb.c
@@ -41,7 +41,7 @@
 	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -49,28 +49,28 @@
 	}
 	i--;
 
-	sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CFG_SDRAM_CFG1;
-	sdram->sdcfg2 = CFG_SDRAM_CFG2;
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	/*sdram->sdmr = CFG_SDRAM_EMOD; */
-	sdram->sdmr = CFG_SDRAM_MODE;
+	/*sdram->sdmr = CONFIG_SYS_SDRAM_EMOD; */
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
 
 	udelay(1000);
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
 
 	udelay(100);
 
diff --git a/board/freescale/m5235evb/m5235evb.c b/board/freescale/m5235evb/m5235evb.c
index bd8a4e5..b9e6126 100644
--- a/board/freescale/m5235evb/m5235evb.c
+++ b/board/freescale/m5235evb/m5235evb.c
@@ -57,7 +57,7 @@
 	    GPIO_PAR_SDRAM_SDWE | GPIO_PAR_SDRAM_SCAS | GPIO_PAR_SDRAM_SRAS |
 	    GPIO_PAR_SDRAM_SCKE | GPIO_PAR_SDRAM_SDCS(3);
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
@@ -65,7 +65,7 @@
 	i--;
 
 	if (!(sdram->dacr0 & SDRAMC_DARCn_RE)) {
-		dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
 
 		/* Initialize DRAM Control Register: DCR */
 		sdram->dcr = SDRAMC_DCR_RTIM_9CLKS |
@@ -73,7 +73,7 @@
 
 		/* Initialize DACR0 */
 		sdram->dacr0 =
-		    SDRAMC_DARCn_BA(CFG_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
+		    SDRAMC_DARCn_BA(CONFIG_SYS_SDRAM_BASE) | SDRAMC_DARCn_CASL_C1 |
 		    SDRAMC_DARCn_CBM_CMD20 | SDRAMC_DARCn_PS_32;
 		asm("nop");
 
@@ -90,7 +90,7 @@
 		}
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CFG_SDRAM_BASE) = 0xA5A59696;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
 
 		/*  Set RE (bit 15) in DACR */
 		sdram->dacr0 |= SDRAMC_DARCn_RE;
@@ -105,7 +105,7 @@
 		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
-		*(u32 *) (CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 
 	return dramsize;
diff --git a/board/freescale/m5235evb/mii.c b/board/freescale/m5235evb/mii.c
index 1fd4d99..5fbbd66 100644
--- a/board/freescale/m5235evb/mii.c
+++ b/board/freescale/m5235evb/mii.c
@@ -49,7 +49,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5249evb/m5249evb.c b/board/freescale/m5249evb/m5249evb.c
index c9ed341..b1ccbeb 100644
--- a/board/freescale/m5249evb/m5249evb.c
+++ b/board/freescale/m5249evb/m5249evb.c
@@ -42,7 +42,7 @@
 	/*
 	 * Set LED on
 	 */
-	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CFG_GPIO1_LED;
+	val = mbar2_readLong(MCFSIM_GPIO1_OUT) & ~CONFIG_SYS_GPIO1_LED;
 	mbar2_writeLong(MCFSIM_GPIO1_OUT, val);   /* Set LED on */
 
 	return 0;
@@ -57,13 +57,13 @@
 	 *	RC = ([(RefreshTime/#rows) / (1/BusClk)] / 16) - 1
 	 */
 
-#ifdef CFG_FAST_CLK
+#ifdef CONFIG_SYS_FAST_CLK
 	/*
 	 * Busclk=70MHz, RefreshTime=64ms, #rows=4096 (4K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=39
 	 */
 	mbar_writeShort(MCFSIM_DCR, 0x8239);
-#elif CFG_PLL_BYPASS
+#elif CONFIG_SYS_PLL_BYPASS
 	/*
 	 * Busclk=5.6448MHz, RefreshTime=64ms, #rows=8192 (8K)
 	 * SO=1, NAM=0, COC=0, RTIM=01 (6clk refresh), RC=02
@@ -101,7 +101,7 @@
 	mbar_writeLong(MCFSIM_DACR0, 0x0000b364);  /* Enable DACR0[IMRS] (bit 6); RE remains enabled */
 	*((volatile unsigned long *) 0x800) = junk; /* Access RAM to initialize the mode register */
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 
diff --git a/board/freescale/m5253demo/flash.c b/board/freescale/m5253demo/flash.c
index 1bf1e97..08f767d 100644
--- a/board/freescale/m5253demo/flash.c
+++ b/board/freescale/m5253demo/flash.c
@@ -28,7 +28,7 @@
 
 #include <asm/immap.h>
 
-#ifndef CFG_FLASH_CFI
+#ifndef CONFIG_SYS_FLASH_CFI
 typedef unsigned short FLASH_PORT_WIDTH;
 typedef volatile unsigned short FLASH_PORT_WIDTHV;
 
@@ -49,14 +49,14 @@
 int write_word(flash_info_t * info, FPWV * dest, u16 data);
 void inline spin_wheel(void);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 ulong flash_init(void)
 {
 	ulong size = 0;
 	ulong fbase = 0;
 
-	fbase = (ulong) CFG_FLASH_BASE;
+	fbase = (ulong) CONFIG_SYS_FLASH_BASE;
 	flash_get_size((FPWV *) fbase, &flash_info[0]);
 	flash_get_offsets((ulong) fbase, &flash_info[0]);
 	fbase += flash_info[0].size;
@@ -64,8 +64,8 @@
 
 	/* Protect monitor and environment sectors */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	return size;
 }
@@ -77,8 +77,8 @@
 	if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
 
 		info->start[0] = base;
-		for (k = 0, j = 0; j < CFG_SST_SECT; j++, k++) {
-			info->start[k + 1] = info->start[k] + CFG_SST_SECTSZ;
+		for (k = 0, j = 0; j < CONFIG_SYS_SST_SECT; j++, k++) {
+			info->start[k + 1] = info->start[k] + CONFIG_SYS_SST_SECTSZ;
 			info->protect[k] = 0;
 		}
 	}
@@ -174,16 +174,16 @@
 
 	info->sector_count = 0;
 	info->size = 0;
-	info->sector_count = CFG_SST_SECT;
-	info->size = CFG_SST_SECT * CFG_SST_SECTSZ;
+	info->sector_count = CONFIG_SYS_SST_SECT;
+	info->size = CONFIG_SYS_SST_SECT * CONFIG_SYS_SST_SECTSZ;
 
 	/* reset ID mode */
 	*addr = (FPWV) 0x00F000F0;
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf("** ERROR: sector count %d > max (%d) **\n",
-		       info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+		       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	return (info->size);
@@ -235,7 +235,7 @@
 	start = get_timer(0);
 	last = start;
 
-	if ((s_last - s_first) == (CFG_SST_SECT - 1)) {
+	if ((s_last - s_first) == (CONFIG_SYS_SST_SECT - 1)) {
 		if (prot == 0) {
 			addr = (FPWV *) info->start[0];
 
@@ -255,7 +255,7 @@
 					count = 0;
 				}
 
-				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf("Timeout\n");
 					*addr = 0x00F0;	/* reset to read mode */
 
@@ -271,7 +271,7 @@
 				enable_interrupts();
 
 			return 0;
-		} else if (prot == CFG_SST_SECT) {
+		} else if (prot == CONFIG_SYS_SST_SECT) {
 			return 1;
 		}
 	}
@@ -294,7 +294,7 @@
 
 					flag = disable_interrupts();
 
-					base = (FPWV *) (CFG_FLASH_BASE);	/* First sector */
+					base = (FPWV *) (CONFIG_SYS_FLASH_BASE);	/* First sector */
 
 					base[FLASH_CYCLE1] = 0x00AA;	/* unlock */
 					base[FLASH_CYCLE2] = 0x0055;	/* unlock */
@@ -308,7 +308,7 @@
 
 					while ((*addr & 0x0080) != 0x0080) {
 						if (get_timer(start) >
-						    CFG_FLASH_ERASE_TOUT) {
+						    CONFIG_SYS_FLASH_ERASE_TOUT) {
 							printf("Timeout\n");
 							*addr = 0x00F0;	/* reset to read mode */
 
@@ -424,7 +424,7 @@
 		return (2);
 	}
 
-	base = (FPWV *) (CFG_FLASH_BASE);
+	base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
 
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
@@ -444,7 +444,7 @@
 	/* data polling for D7 */
 	while (res == 0
 	       && (*dest & (u8) 0x00800080) != (data & (u8) 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (u8) 0x00F000F0;	/* reset bank */
 			res = 1;
 		}
diff --git a/board/freescale/m5253demo/m5253demo.c b/board/freescale/m5253demo/m5253demo.c
index 2eb6a04..b39cd4d 100644
--- a/board/freescale/m5253demo/m5253demo.c
+++ b/board/freescale/m5253demo/m5253demo.c
@@ -45,7 +45,7 @@
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, temp;
 
-		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 
 		/* Initialize DRAM Control Register: DCR */
@@ -56,7 +56,7 @@
 		__asm__("nop");
 
 		/* Initialize DMR0 */
-		dramsize = (CFG_SDRAM_SIZE << 20);
+		dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
 		temp = (dramsize - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, temp | 1);
 		__asm__("nop");
@@ -65,7 +65,7 @@
 		__asm__("nop");
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		__asm__("nop");
 
 		/* Set RE bit in DACR */
@@ -81,7 +81,7 @@
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		__asm__("nop");
 
-		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
 	return dramsize;
@@ -104,7 +104,7 @@
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -121,7 +121,7 @@
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 
 #define CALC_TIMING(t) (t + period - 1) / period
-		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
 		ata->t1 = CALC_TIMING(piotms[2][0]);
diff --git a/board/freescale/m5253evbe/m5253evbe.c b/board/freescale/m5253evbe/m5253evbe.c
index f3b1efd..ae69f67 100644
--- a/board/freescale/m5253evbe/m5253evbe.c
+++ b/board/freescale/m5253evbe/m5253evbe.c
@@ -43,7 +43,7 @@
 	if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
 		u32 RC, dramsize;
 
-		RC = (CFG_CLK / 1000000) >> 1;
+		RC = (CONFIG_SYS_CLK / 1000000) >> 1;
 		RC = (RC * 15) >> 4;
 
 		/* Initialize DRAM Control Register: DCR */
@@ -54,7 +54,7 @@
 		asm("nop");
 
 		/* Initialize DMR0 */
-		dramsize = ((CFG_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
+		dramsize = ((CONFIG_SYS_SDRAM_SIZE << 20) - 1) & 0xFFFC0000;
 		mbar_writeLong(MCFSIM_DMR0, dramsize | 1);
 		asm("nop");
 
@@ -62,7 +62,7 @@
 		asm("nop");
 
 		/* Write to this block to initiate precharge */
-		*(u32 *) (CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 		asm("nop");
 
 		/* Set RE bit in DACR */
@@ -78,10 +78,10 @@
 			       mbar_readLong(MCFSIM_DACR0) | 0x0040);
 		asm("nop");
 
-		*(u32 *) (CFG_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
+		*(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
 	}
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 
 int testdram(void)
@@ -101,7 +101,7 @@
 
 void ide_set_reset(int idereset)
 {
-	volatile atac_t *ata = (atac_t *) CFG_ATA_BASE_ADDR;
+	volatile atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
 	long period;
 	/*  t1,  t2,  t3,  t4,  t5,  t6,  t9, tRD,  tA */
 	int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35},	/* PIO 0 */
@@ -118,7 +118,7 @@
 		mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
 
 #define CALC_TIMING(t) (t + period - 1) / period
-		period = 1000000000 / (CFG_CLK / 2);	/* period in ns */
+		period = 1000000000 / (CONFIG_SYS_CLK / 2);	/* period in ns */
 
 		/*ata->ton = CALC_TIMING (180); */
 		ata->t1 = CALC_TIMING(piotms[2][0]);
diff --git a/board/freescale/m5271evb/m5271evb.c b/board/freescale/m5271evb/m5271evb.c
index e089d5f..5505cc4 100644
--- a/board/freescale/m5271evb/m5271evb.c
+++ b/board/freescale/m5271evb/m5271evb.c
@@ -66,7 +66,7 @@
 		 * PS: 32bit port size
 		 */
 		mbar_writeLong(MCF_SDRAMC_DACR0,
-				MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18)
+				MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18)
 				| MCF_SDRAMC_DACRn_CASL(1)
 				| MCF_SDRAMC_DACRn_CBM(3)
 				| MCF_SDRAMC_DACRn_PS(0));
@@ -85,7 +85,7 @@
 			asm(" nop");
 
 		/* Write to this block to initiate precharge */
-		*(u32 *)(CFG_SDRAM_BASE) = 0xa5a5a5a5;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
 
 		/* Set RE bit in DACR */
 		mbar_writeLong(MCF_SDRAMC_DACR0, mbar_readLong(MCF_SDRAMC_DACR0)
@@ -108,10 +108,10 @@
 		 * Burst Type = Sequential
 		 * Burst Length = 1
 		 */
-		*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xa5a5a5a5;
 	}
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 int testdram (void) {
diff --git a/board/freescale/m5271evb/mii.c b/board/freescale/m5271evb/mii.c
index 78a7028..e79fa19 100644
--- a/board/freescale/m5271evb/mii.c
+++ b/board/freescale/m5271evb/mii.c
@@ -38,14 +38,14 @@
 {
 	if (setclear) {
 		/* Enable Ethernet pins */
-		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
 	} else {
 	}
 
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5272c3/flash.c b/board/freescale/m5272c3/flash.c
index ea0b1fd..586a2cf 100644
--- a/board/freescale/m5272c3/flash.c
+++ b/board/freescale/m5272c3/flash.c
@@ -23,10 +23,10 @@
 
 #include <common.h>
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x200000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -74,15 +74,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(AMD_MANUFACT & FLASH_VENDMASK) |
 			(AMD_ID_PL160CB & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -113,8 +113,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0x3ffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0x3ffff, &flash_info[0]);
 
 	return size;
 }
@@ -128,8 +128,8 @@
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
 
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
@@ -211,7 +211,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip1 = TMO;
 					break;
@@ -299,7 +299,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip1 = ERR | TMO;
 			break;
 		}
diff --git a/board/freescale/m5272c3/m5272c3.c b/board/freescale/m5272c3/m5272c3.c
index d17cb2e..902ca3a 100644
--- a/board/freescale/m5272c3/m5272c3.c
+++ b/board/freescale/m5272c3/m5272c3.c
@@ -40,7 +40,7 @@
 	/* Dummy write to start SDRAM */
 	*((volatile unsigned long *)0) = 0;
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 	};
 
 int testdram (void) {
diff --git a/board/freescale/m5272c3/mii.c b/board/freescale/m5272c3/mii.c
index b30ba80..161c694 100644
--- a/board/freescale/m5272c3/mii.c
+++ b/board/freescale/m5272c3/mii.c
@@ -45,7 +45,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5275evb/m5275evb.c b/board/freescale/m5275evb/m5275evb.c
index be19e02..35c9b20 100644
--- a/board/freescale/m5275evb/m5275evb.c
+++ b/board/freescale/m5275evb/m5275evb.c
@@ -44,7 +44,7 @@
 	gpio_reg->par_sdram = 0x3FF; /* Enable SDRAM */
 
 	/* Set up chip select */
-	sdp->sdbar0 = CFG_SDRAM_BASE;
+	sdp->sdbar0 = CONFIG_SYS_SDRAM_BASE;
 	sdp->sdbmr0 = MCF_SDRAMC_SDMRn_BAM_32M | MCF_SDRAMC_SDMRn_V;
 
 	/* Set up timing */
@@ -58,34 +58,34 @@
 	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
 
 	/* Dummy write to start SDRAM */
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LEMR */
 	sdp->sdmr = MCF_SDRAMC_SDMR_BNKAD_LEMR
 			| MCF_SDRAMC_SDMR_AD(0x0)
 			| MCF_SDRAMC_SDMR_CMD;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Send LMR */
 	sdp->sdmr = 0x058d0000;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
 	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
 
 	/* Set precharge */
 	sdp->sdcr |= MCF_SDRAMC_SDCR_IPALL;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop manual precharge, send 2 IREF */
 	sdp->sdcr &= ~(MCF_SDRAMC_SDCR_IPALL);
 	sdp->sdcr |= MCF_SDRAMC_SDCR_IREF;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Write mode register, clear reset DLL */
 	sdp->sdmr = 0x018d0000;
-	*((volatile unsigned long *)CFG_SDRAM_BASE) = 0xa5a59696;
+	*((volatile unsigned long *)CONFIG_SYS_SDRAM_BASE) = 0xa5a59696;
 
 	/* Stop sending commands */
 	sdp->sdmr &= ~(MCF_SDRAMC_SDMR_CMD);
@@ -100,7 +100,7 @@
 		| MCF_SDRAMC_SDCR_RCNT((SDRAM_TREFI/(PERIOD*64)) - 1 + 1)
 		| MCF_SDRAMC_SDCR_DQS_OE(0x3);
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 int testdram(void)
diff --git a/board/freescale/m5275evb/mii.c b/board/freescale/m5275evb/mii.c
index 6c7ace9..706d8d6 100644
--- a/board/freescale/m5275evb/mii.c
+++ b/board/freescale/m5275evb/mii.c
@@ -41,7 +41,7 @@
 
 	if (setclear) {
 		/* Enable Ethernet pins */
-		if (info->iobase == CFG_FEC0_IOBASE) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 			gpio->par_feci2c |= 0x0F00;
 			gpio->par_fec0hl |= 0xC0;
 		} else {
@@ -49,7 +49,7 @@
 			gpio->par_fec1hl |= 0xC0;
 		}
 	} else {
-		if (info->iobase == CFG_FEC0_IOBASE) {
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE) {
 			gpio->par_feci2c &= ~0x0F00;
 			gpio->par_fec0hl &= ~0xC0;
 		} else {
@@ -61,7 +61,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -147,9 +147,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif	/* CFG_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
+#endif	/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_COMMANDS & CONFIG_CMD_MII) */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -214,7 +214,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5282evb/m5282evb.c b/board/freescale/m5282evb/m5282evb.c
index 31d6923..b0c9fc8 100644
--- a/board/freescale/m5282evb/m5282evb.c
+++ b/board/freescale/m5282evb/m5282evb.c
@@ -36,7 +36,7 @@
 {
 	u32 dramsize, i, dramclk;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
@@ -45,7 +45,7 @@
 
 	if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
 	{
-		dramclk = gd->bus_clk / (CFG_HZ * CFG_HZ);
+		dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
 
 		/* Initialize DRAM Control Register: DCR */
 		MCFSDRAMC_DCR = (0
@@ -55,7 +55,7 @@
 
 		/* Initialize DACR0 */
 		MCFSDRAMC_DACR0 = (0
-			| MCFSDRAMC_DACR_BASE(CFG_SDRAM_BASE)
+			| MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
 			| MCFSDRAMC_DACR_CASL(1)
 			| MCFSDRAMC_DACR_CBM(3)
 			| MCFSDRAMC_DACR_PS_32);
@@ -77,7 +77,7 @@
 		}
 
 		/* Write to this block to initiate precharge */
-		*(u32 *)(CFG_SDRAM_BASE) = 0xA5A59696;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
 		asm("nop");
 
 		/* Set RE (bit 15) in DACR */
@@ -94,7 +94,7 @@
 		asm("nop");
 
 		/* Write to the SDRAM Mode Register */
-		*(u32 *)(CFG_SDRAM_BASE + 0x400) = 0xA5A59696;
+		*(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
 	}
 	return dramsize;
 }
diff --git a/board/freescale/m5282evb/mii.c b/board/freescale/m5282evb/mii.c
index 8ae2ec6..7f92514 100644
--- a/board/freescale/m5282evb/mii.c
+++ b/board/freescale/m5282evb/mii.c
@@ -38,15 +38,15 @@
 {
 	if (setclear) {
 		MCFGPIO_PASPAR |= 0x0F00;
-		MCFGPIO_PEHLPAR = CFG_PEHLPAR;
+		MCFGPIO_PEHLPAR = CONFIG_SYS_PEHLPAR;
 	} else {
 		MCFGPIO_PASPAR &= 0xF0FF;
-		MCFGPIO_PEHLPAR &= ~CFG_PEHLPAR;
+		MCFGPIO_PEHLPAR &= ~CONFIG_SYS_PEHLPAR;
 	}
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -132,9 +132,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -199,7 +199,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5329evb/m5329evb.c b/board/freescale/m5329evb/m5329evb.c
index f9fa9fb..b4df22f 100644
--- a/board/freescale/m5329evb/m5329evb.c
+++ b/board/freescale/m5329evb/m5329evb.c
@@ -42,7 +42,7 @@
 	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -50,29 +50,29 @@
 	}
 	i--;
 
-	sdram->cs0 = (CFG_SDRAM_BASE | i);
-	sdram->cfg1 = CFG_SDRAM_CFG1;
-	sdram->cfg2 = CFG_SDRAM_CFG2;
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->mode = CFG_SDRAM_EMOD;
-	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->mode = CFG_SDRAM_MODE;
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
 
-	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
 
 	udelay(100);
 
diff --git a/board/freescale/m5329evb/mii.c b/board/freescale/m5329evb/mii.c
index 8f6abf3..c0f5817 100644
--- a/board/freescale/m5329evb/mii.c
+++ b/board/freescale/m5329evb/mii.c
@@ -50,7 +50,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -134,9 +134,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -201,7 +201,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5329evb/nand.c b/board/freescale/m5329evb/nand.c
index f84912e..82492f6 100644
--- a/board/freescale/m5329evb/nand.c
+++ b/board/freescale/m5329evb/nand.c
@@ -83,7 +83,7 @@
 {
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 
-	*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+	*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
 
 	/* set up pin configuration */
 	gpio->par_timer &= ~GPIO_PAR_TIN3_TIN3;
diff --git a/board/freescale/m5373evb/m5373evb.c b/board/freescale/m5373evb/m5373evb.c
index a269ee6..376de4b 100644
--- a/board/freescale/m5373evb/m5373evb.c
+++ b/board/freescale/m5373evb/m5373evb.c
@@ -42,7 +42,7 @@
 	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -50,29 +50,29 @@
 	}
 	i--;
 
-	sdram->cs0 = (CFG_SDRAM_BASE | i);
-	sdram->cfg1 = CFG_SDRAM_CFG1;
-	sdram->cfg2 = CFG_SDRAM_CFG2;
+	sdram->cs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->mode = CFG_SDRAM_EMOD;
-	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->mode = CFG_SDRAM_MODE;
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
 
-	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
 
 	udelay(100);
 
diff --git a/board/freescale/m5373evb/mii.c b/board/freescale/m5373evb/mii.c
index 8f6abf3..c0f5817 100644
--- a/board/freescale/m5373evb/mii.c
+++ b/board/freescale/m5373evb/mii.c
@@ -50,7 +50,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -134,9 +134,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -201,7 +201,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m5373evb/nand.c b/board/freescale/m5373evb/nand.c
index 404a9c3..d01b819 100644
--- a/board/freescale/m5373evb/nand.c
+++ b/board/freescale/m5373evb/nand.c
@@ -67,7 +67,7 @@
 	volatile gpio_t *gpio = (gpio_t *) MMAP_GPIO;
 	volatile fbcs_t *fbcs = (fbcs_t *) MMAP_FBCS;
 
-	*((volatile u16 *)CFG_LATCH_ADDR) |= 0x0004;
+	*((volatile u16 *)CONFIG_SYS_LATCH_ADDR) |= 0x0004;
 	fbcs->csmr2 &= ~FBCS_CSMR_WP;
 
 	/* set up pin configuration */
diff --git a/board/freescale/m54451evb/m54451evb.c b/board/freescale/m54451evb/m54451evb.c
index 768f40b..088c8c4 100644
--- a/board/freescale/m54451evb/m54451evb.c
+++ b/board/freescale/m54451evb/m54451evb.c
@@ -49,16 +49,16 @@
 	 * Serial Boot: The dram is already initialized in start.S
 	 * only require to return DRAM size
 	 */
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 #else
 	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
 	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
 	u32 i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
 
-	if ((sdram->sdcfg1 == CFG_SDRAM_CFG1) &&
-	    (sdram->sdcfg2 == CFG_SDRAM_CFG2))
+	if ((sdram->sdcfg1 == CONFIG_SYS_SDRAM_CFG1) &&
+	    (sdram->sdcfg2 == CONFIG_SYS_SDRAM_CFG2))
 		return dramsize;
 
 	for (i = 0x13; i < 0x20; i++) {
@@ -67,32 +67,32 @@
 	}
 	i--;
 
-	gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
 
-	sdram->sdcs0 = (CFG_SDRAM_BASE | i);
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
 
-	sdram->sdcfg1 = CFG_SDRAM_CFG1;
-	sdram->sdcfg2 = CFG_SDRAM_CFG2;
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	udelay(200);
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 	__asm__("nop");
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 	__asm__("nop");
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 	__asm__("nop");
 
 	/* Issue LEMR */
-	sdram->sdmr = CFG_SDRAM_MODE;
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE;
 	__asm__("nop");
-	sdram->sdmr = CFG_SDRAM_EMOD;
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD;
 	__asm__("nop");
 
-	sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000000;
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000000;
 
 	udelay(100);
 #endif
diff --git a/board/freescale/m54451evb/mii.c b/board/freescale/m54451evb/mii.c
index 5a4330c..6e24736 100644
--- a/board/freescale/m54451evb/mii.c
+++ b/board/freescale/m54451evb/mii.c
@@ -43,7 +43,7 @@
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
 		else
 			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
@@ -51,7 +51,7 @@
 		gpio->par_feci2c &=
 		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
 		else
 			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
@@ -59,7 +59,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -135,9 +135,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -202,7 +202,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
 
diff --git a/board/freescale/m54455evb/m54455evb.c b/board/freescale/m54455evb/m54455evb.c
index 100682a..293b5b0 100644
--- a/board/freescale/m54455evb/m54455evb.c
+++ b/board/freescale/m54455evb/m54455evb.c
@@ -45,13 +45,13 @@
 	 * Serial Boot: The dram is already initialized in start.S
 	 * only require to return DRAM size
 	 */
-	dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
 #else
 	volatile sdramc_t *sdram = (volatile sdramc_t *)(MMAP_SDRAM);
 	volatile gpio_t *gpio = (volatile gpio_t *)(MMAP_GPIO);
 	u32 i;
 
-	dramsize = CFG_SDRAM_SIZE * 0x100000 >> 1;
+	dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000 >> 1;
 
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
@@ -59,33 +59,33 @@
 	}
 	i--;
 
-	gpio->mscr_sdram = CFG_SDRAM_DRV_STRENGTH;
+	gpio->mscr_sdram = CONFIG_SYS_SDRAM_DRV_STRENGTH;
 
-	sdram->sdcs0 = (CFG_SDRAM_BASE | i);
-	sdram->sdcs1 = (CFG_SDRAM_BASE1 | i);
+	sdram->sdcs0 = (CONFIG_SYS_SDRAM_BASE | i);
+	sdram->sdcs1 = (CONFIG_SYS_SDRAM_BASE1 | i);
 
-	sdram->sdcfg1 = CFG_SDRAM_CFG1;
-	sdram->sdcfg2 = CFG_SDRAM_CFG2;
+	sdram->sdcfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->sdcfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->sdmr = CFG_SDRAM_EMOD | 0x408;
-	sdram->sdmr = CFG_SDRAM_MODE | 0x300;
+	sdram->sdmr = CONFIG_SYS_SDRAM_EMOD | 0x408;
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x300;
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->sdcr = CFG_SDRAM_CTRL | 2;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Perform two refresh cycles */
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
-	sdram->sdcr = CFG_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->sdcr = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->sdmr = CFG_SDRAM_MODE | 0x200;
+	sdram->sdmr = CONFIG_SYS_SDRAM_MODE | 0x200;
 
-	sdram->sdcr = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
+	sdram->sdcr = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000c00;
 
 	udelay(100);
 #endif
@@ -175,11 +175,11 @@
 #include <flash.h>
 ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info)
 {
-	int sect[] = CFG_ATMEL_SECT;
-	int sectsz[] = CFG_ATMEL_SECTSZ;
+	int sect[] = CONFIG_SYS_ATMEL_SECT;
+	int sectsz[] = CONFIG_SYS_ATMEL_SECTSZ;
 	int i, j, k;
 
-	if (base != CFG_ATMEL_BASE)
+	if (base != CONFIG_SYS_ATMEL_BASE)
 		return 0;
 
 	info->flash_id          = 0x01000000;
@@ -205,9 +205,9 @@
 	info->name              = "CFI conformant";
 
 	info->size              = 0;
-	info->sector_count      = CFG_ATMEL_TOTALSECT;
+	info->sector_count      = CONFIG_SYS_ATMEL_TOTALSECT;
 	info->start[0] = base;
-	for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
+	for (k = 0, i = 0; i < CONFIG_SYS_ATMEL_REGION; i++) {
 		info->size += sect[i] * sectsz[i];
 
 		for (j = 0; j < sect[i]; j++, k++) {
@@ -218,4 +218,4 @@
 
 	return 1;
 }
-#endif				/* CFG_FLASH_CFI */
+#endif				/* CONFIG_SYS_FLASH_CFI */
diff --git a/board/freescale/m54455evb/mii.c b/board/freescale/m54455evb/mii.c
index 0be5439..c195191 100644
--- a/board/freescale/m54455evb/mii.c
+++ b/board/freescale/m54455evb/mii.c
@@ -43,7 +43,7 @@
 		gpio->par_feci2c |=
 		    (GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec |= GPIO_PAR_FEC_FEC0_RMII_GPIO;
 		else
 			gpio->par_fec |= GPIO_PAR_FEC_FEC1_RMII_ATA;
@@ -51,7 +51,7 @@
 		gpio->par_feci2c &=
 		    ~(GPIO_PAR_FECI2C_MDC0_MDC0 | GPIO_PAR_FECI2C_MDIO0_MDIO0);
 
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_fec &= GPIO_PAR_FEC_FEC0_MASK;
 		else
 			gpio->par_fec &= GPIO_PAR_FEC_FEC1_MASK;
@@ -59,7 +59,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -152,9 +152,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || (CONFIG_MII) */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -219,7 +219,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/freescale/m547xevb/m547xevb.c b/board/freescale/m547xevb/m547xevb.c
index 6d7d270..9f1ec38 100644
--- a/board/freescale/m547xevb/m547xevb.c
+++ b/board/freescale/m547xevb/m547xevb.c
@@ -43,53 +43,53 @@
 	volatile siu_t *siu = (siu_t *) (MMAP_SIU);
 	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
-#ifdef CFG_DRAMSZ1
+#ifdef CONFIG_SYS_DRAMSZ1
 	u32 temp;
 #endif
 
-	siu->drv = CFG_SDRAM_DRVSTRENGTH;
+	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
 
-	dramsize = CFG_DRAMSZ * 0x100000;
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
 	}
 	i--;
-	siu->cs0cfg = (CFG_SDRAM_BASE | i);
+	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
 
-#ifdef CFG_DRAMSZ1
-	temp = CFG_DRAMSZ1 * 0x100000;
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (temp == (1 << i))
 			break;
 	}
 	i--;
 	dramsize += temp;
-	siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
 #endif
 
-	sdram->cfg1 = CFG_SDRAM_CFG1;
-	sdram->cfg2 = CFG_SDRAM_CFG2;
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->mode = CFG_SDRAM_EMOD;
-	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->mode = CFG_SDRAM_MODE;
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
 
-	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
 
 	udelay(100);
 
diff --git a/board/freescale/m547xevb/mii.c b/board/freescale/m547xevb/mii.c
index 5b2683b..4d11506 100644
--- a/board/freescale/m547xevb/mii.c
+++ b/board/freescale/m547xevb/mii.c
@@ -41,12 +41,12 @@
 	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
 
 	if (setclear) {
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_feci2cirq |= 0xF000;
 		else
 			gpio->par_feci2cirq |= 0x0FC0;
 	} else {
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_feci2cirq &= 0x0FFF;
 		else
 			gpio->par_feci2cirq &= 0xF03F;
@@ -54,7 +54,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -140,9 +140,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -217,7 +217,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
 
diff --git a/board/freescale/m548xevb/m548xevb.c b/board/freescale/m548xevb/m548xevb.c
index e6510c9..4a2a5c7 100644
--- a/board/freescale/m548xevb/m548xevb.c
+++ b/board/freescale/m548xevb/m548xevb.c
@@ -44,49 +44,49 @@
 	volatile sdram_t *sdram = (volatile sdram_t *)(MMAP_SDRAM);
 	u32 dramsize, i;
 
-	siu->drv = CFG_SDRAM_DRVSTRENGTH;
+	siu->drv = CONFIG_SYS_SDRAM_DRVSTRENGTH;
 
-	dramsize = CFG_DRAMSZ * 0x100000;
+	dramsize = CONFIG_SYS_DRAMSZ * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (dramsize == (1 << i))
 			break;
 	}
 	i--;
-	siu->cs0cfg = (CFG_SDRAM_BASE | i);
+	siu->cs0cfg = (CONFIG_SYS_SDRAM_BASE | i);
 
-#ifdef CFG_DRAMSZ1
-	temp = CFG_DRAMSZ1 * 0x100000;
+#ifdef CONFIG_SYS_DRAMSZ1
+	temp = CONFIG_SYS_DRAMSZ1 * 0x100000;
 	for (i = 0x13; i < 0x20; i++) {
 		if (temp == (1 << i))
 			break;
 	}
 	i--;
 	dramsize += temp;
-	siu->cs1cfg = ((CFG_SDRAM_BASE + temp) | i);
+	siu->cs1cfg = ((CONFIG_SYS_SDRAM_BASE + temp) | i);
 #endif
 
-	sdram->cfg1 = CFG_SDRAM_CFG1;
-	sdram->cfg2 = CFG_SDRAM_CFG2;
+	sdram->cfg1 = CONFIG_SYS_SDRAM_CFG1;
+	sdram->cfg2 = CONFIG_SYS_SDRAM_CFG2;
 
 	/* Issue PALL */
-	sdram->ctrl = CFG_SDRAM_CTRL | 2;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 2;
 
 	/* Issue LEMR */
-	sdram->mode = CFG_SDRAM_EMOD;
-	sdram->mode = (CFG_SDRAM_MODE | 0x04000000);
+	sdram->mode = CONFIG_SYS_SDRAM_EMOD;
+	sdram->mode = (CONFIG_SYS_SDRAM_MODE | 0x04000000);
 
 	udelay(500);
 
 	/* Issue PALL */
-	sdram->ctrl = (CFG_SDRAM_CTRL | 2);
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL | 2);
 
 	/* Perform two refresh cycles */
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
-	sdram->ctrl = CFG_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
+	sdram->ctrl = CONFIG_SYS_SDRAM_CTRL | 4;
 
-	sdram->mode = CFG_SDRAM_MODE;
+	sdram->mode = CONFIG_SYS_SDRAM_MODE;
 
-	sdram->ctrl = (CFG_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
+	sdram->ctrl = (CONFIG_SYS_SDRAM_CTRL & ~0x80000000) | 0x10000F00;
 
 	udelay(100);
 
diff --git a/board/freescale/m548xevb/mii.c b/board/freescale/m548xevb/mii.c
index 5b2683b..4d11506 100644
--- a/board/freescale/m548xevb/mii.c
+++ b/board/freescale/m548xevb/mii.c
@@ -41,12 +41,12 @@
 	struct fec_info_dma *info = (struct fec_info_dma *)dev->priv;
 
 	if (setclear) {
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_feci2cirq |= 0xF000;
 		else
 			gpio->par_feci2cirq |= 0x0FC0;
 	} else {
-		if (info->iobase == CFG_FEC0_IOBASE)
+		if (info->iobase == CONFIG_SYS_FEC0_IOBASE)
 			gpio->par_feci2cirq &= 0x0FFF;
 		else
 			gpio->par_feci2cirq &= 0xF03F;
@@ -54,7 +54,7 @@
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -140,9 +140,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -217,7 +217,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__ ((weak, alias("__mii_init")));
 
diff --git a/board/freescale/mpc7448hpc2/asm_init.S b/board/freescale/mpc7448hpc2/asm_init.S
index 521301f..b9495fd 100644
--- a/board/freescale/mpc7448hpc2/asm_init.S
+++ b/board/freescale/mpc7448hpc2/asm_init.S
@@ -123,7 +123,7 @@
 
 /* Initialize pointer to Tsi108 register space */
 
-	LOAD_PTR(r29,CFG_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
+	LOAD_PTR(r29,CONFIG_SYS_TSI108_CSR_RST_BASE)/* r29 - pointer to tsi108 CSR space */
 	ori r4,r29,TSI108_PB_REG_OFFSET
 
 /* Check Processor Version Number */
@@ -214,12 +214,12 @@
 
 	ori r4,r29,TSI108_PB_REG_OFFSET
 
-#if (CFG_TSI108_CSR_BASE != CFG_TSI108_CSR_RST_BASE)
+#if (CONFIG_SYS_TSI108_CSR_BASE != CONFIG_SYS_TSI108_CSR_RST_BASE)
 	/* Relocate (if required) Tsi108 registers. Set new value for
 	 * PB_REG_BAR:
 	 * Note we are in the 32-bit address mode.
 	 */
-	LOAD_U32(r5,(CFG_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
+	LOAD_U32(r5,(CONFIG_SYS_TSI108_CSR_BASE | 0x01)) /* PB_REG_BAR: BA + EN */
 	stw	r5,PB_REG_BAR(r4)
 	andis.	r29,r5,0xFFFF
 	sync
diff --git a/board/freescale/mpc7448hpc2/mpc7448hpc2.c b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
index cfdbed5..117b951 100644
--- a/board/freescale/mpc7448hpc2/mpc7448hpc2.c
+++ b/board/freescale/mpc7448hpc2/mpc7448hpc2.c
@@ -60,7 +60,7 @@
 {
 	int l_type = 0;
 
-	printf ("BOARD: %s\n", CFG_BOARD_NAME);
+	printf ("BOARD: %s\n", CONFIG_SYS_BOARD_NAME);
 	return (l_type);
 }
 
diff --git a/board/freescale/mpc7448hpc2/tsi108_init.c b/board/freescale/mpc7448hpc2/tsi108_init.c
index 9c40b72..74bb564 100644
--- a/board/freescale/mpc7448hpc2/tsi108_init.c
+++ b/board/freescale/mpc7448hpc2/tsi108_init.c
@@ -88,7 +88,7 @@
 	{0x00000000, 0x00000240}  /* PBA=0xFF00_0000 -> HLP : (Translation Enabled + Byte-Swap)*/
 };
 
-#ifdef CFG_CLK_SPREAD
+#ifdef CONFIG_SYS_CLK_SPREAD
 typedef struct {
 	ulong ctrl0;
 	ulong ctrl1;
@@ -111,7 +111,7 @@
 	{0x005c0044, 0x00000039},	/* 6: CG_PB_CLKO = 200 MHz */
 	{0x004f0044, 0x0000003e}	/* 7: CG_PB_CLKO = 233 MHz */
 };
-#endif	/* CFG_CLK_SPREAD */
+#endif	/* CONFIG_SYS_CLK_SPREAD */
 
 /*
  * Prosessor Bus Clock (in MHz) defined by CG_PB_SELECT
@@ -129,7 +129,7 @@
 	ulong i;
 
 	/* Detect PB clock freq. */
-	i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
 	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
 
 	return pb_clk_sel[i] * 1000000;
@@ -146,7 +146,7 @@
 	ulong i;
 
 	gd->mem_clk = 0;
-	i = in32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
+	i = in32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET +
 			CG_PWRUP_STATUS);
 	i = (i >> 20) & 0x07;	/* Get GD PLL multiplier */
 	switch (i) {
@@ -182,7 +182,7 @@
 	volatile ulong *reg_ptr;
 
 	reg_ptr =
-		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x900);
 
 	for (i = 0; i < 32; i++) {
 		*reg_ptr++ = 0x00000201;	/* SWAP ENABLED */
@@ -194,7 +194,7 @@
 
 	/* Setup PB_OCN_BAR2: size 256B + ENable @ 0x0_80000000 */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2,
 		0x80000001);
 	__asm__ __volatile__ ("sync");
 
@@ -202,7 +202,7 @@
 	 * read from SDRAM)
 	 */
 
-	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
+	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR2);
 	__asm__ __volatile__ ("sync");
 
 	/*
@@ -221,7 +221,7 @@
 	 * initialize pointer to LUT associated with PB_OCN_BAR1
 	 */
 	reg_ptr =
-		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + 0x800);
 
 	for (i = 0; i < 32; i++) {
 		*reg_ptr++ = pb2ocn_lut1[i].lower;
@@ -232,73 +232,73 @@
 
 	/* Base addresses for CS0, CS1, CS2, CS3 */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_ADDR,
 		0x00000000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_ADDR,
 		0x00100000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_ADDR,
 		0x00200000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_ADDR,
 		0x00300000);
 	__asm__ __volatile__ ("sync");
 
 	/* Masks for HLP banks */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_MASK,
 		0xFFF00000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_MASK,
 		0xFFF00000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_MASK,
 		0xFFF00000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_MASK,
 		0xFFF00000);
 	__asm__ __volatile__ ("sync");
 
 	/* Set CTRL0 values for banks */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL0,
 		0x7FFC44C2);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL0,
 		0x7FFC44C0);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL0,
 		0x7FFC44C0);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL0,
 		0x7FFC44C2);
 	__asm__ __volatile__ ("sync");
 
 	/* Set banks to latched mode, enabled, and other default settings */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B0_CTRL1,
 		0x7C0F2000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B1_CTRL1,
 		0x7C0F2000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B2_CTRL1,
 		0x7C0F2000);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_HLP_REG_OFFSET + HLP_B3_CTRL1,
 		0x7C0F2000);
 	__asm__ __volatile__ ("sync");
 
@@ -306,7 +306,7 @@
 	 * Set new value for PB_OCN_BAR1: switch from BOOT to LUT mode.
 	 * value for PB_OCN_BAR1: (BA-0xE000_0000 + size 512MB + ENable)
 	 */
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1,
 		0xE0000011);
 	__asm__ __volatile__ ("sync");
 
@@ -314,7 +314,7 @@
 	 * immediate read from SDRAM)
 	 */
 
-	temp = in32(CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
+	temp = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_OCN_BAR1);
 	__asm__ __volatile__ ("sync");
 
 	/*
@@ -341,7 +341,7 @@
 	temp = get_cpu_type ();
 
 	if ((CPU_750FX == temp) || (CPU_750GX == temp))
-		out32 (CFG_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
+		out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PB_REG_OFFSET + PB_MCMD,
 			0x00009955);
 #endif	/* DISABLE_PBM */
 
@@ -351,27 +351,27 @@
 	 */
 
 	/* Map PCI/X Configuration Space (16MB @ 0x0_FE000000) */
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
 		PCI_PFAB_BAR0_UPPER, 0);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_BAR0,
 		0xFB000001);
 	__asm__ __volatile__ ("sync");
 
 	/* Set Bus Number for the attached PCI/X bus (we will use 0 for NB) */
 
-	temp =	in32(CFG_TSI108_CSR_BASE +
+	temp =	in32(CONFIG_SYS_TSI108_CSR_BASE +
 		TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT);
 
 	temp &= ~0xFF00;	/* Clear the BUS_NUM field */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PCIX_STAT,
 		temp);
 
 	/* Map PCI/X IO Space (64KB @ 0x0_FD000000) takes one 16MB LUT entry */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO_UPPER,
 		0);
 	__asm__ __volatile__ ("sync");
 
@@ -379,7 +379,7 @@
 	 * and maps it as a IO address.
 	 */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_PFAB_IO,
 		0x00000001);
 	__asm__ __volatile__ ("sync");
 
@@ -405,7 +405,7 @@
 	 */
 
 	reg_ptr =
-		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x500);
 
 #ifdef DISABLE_PBM
 
@@ -442,7 +442,7 @@
 	__asm__ __volatile__ ("eieio");
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
 		reg_val);
 	__asm__ __volatile__ ("sync");
 
@@ -450,9 +450,9 @@
 	 * ( 0 is the best choice for easy mapping)
 	 */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2,
 		0x00000000);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR2_UPPER,
 		0x00000000);
 	__asm__ __volatile__ ("sync");
 
@@ -470,7 +470,7 @@
 	 *  set pointer to LUT associated with PCI P2O_BAR3
 	 */
 	reg_ptr =
-		(ulong *) (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
+		(ulong *) (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + 0x600);
 
 	reg_val = 0x00000004;	/* Destination port = SDC */
 
@@ -490,19 +490,19 @@
 	/* Configure PCI P2O_BAR3 (size = 512MB, Enabled) */
 
 	reg_val =
-		in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
+		in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET +
 		 PCI_P2O_PAGE_SIZES);
 	reg_val &= ~0x00FF;
 	reg_val |= 0x0071;
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_PAGE_SIZES,
 		reg_val);
 	__asm__ __volatile__ ("sync");
 
 	/* Set 64-bit base PCI bus address for window (0x20000000) */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3_UPPER,
 		0x00000000);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR3,
 		0x20000000);
 	__asm__ __volatile__ ("sync");
 
@@ -511,17 +511,17 @@
 #ifdef ENABLE_PCI_CSR_BAR
 	/* open if required access to Tsi108 CSRs from the PCI/X bus */
 	/* enable BAR0 on the PCI/X bus */
-	reg_val = in32(CFG_TSI108_CSR_BASE +
+	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE +
 		TSI108_PCI_REG_OFFSET + PCI_MISC_CSR);
 	reg_val |= 0x02;
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_MISC_CSR,
 		reg_val);
 	__asm__ __volatile__ ("sync");
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0_UPPER,
 		0x00000000);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
-		CFG_TSI108_CSR_BASE);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_P2O_BAR0,
+		CONFIG_SYS_TSI108_CSR_BASE);
 	__asm__ __volatile__ ("sync");
 
 #endif
@@ -530,9 +530,9 @@
 	 * Finally enable PCI/X Bus Master and Memory Space access
 	 */
 
-	reg_val = in32(CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
+	reg_val = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR);
 	reg_val |= 0x06;
-	out32 (CFG_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_PCI_REG_OFFSET + PCI_CSR, reg_val);
 	__asm__ __volatile__ ("sync");
 
 #endif	/* CONFIG_PCI */
@@ -546,10 +546,10 @@
 	 * PB_INT[3] -> MCP (CPU1)
 	 * Set interrupt controller outputs as Level_Sensitive/Active_Low
 	 */
-	out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(0), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(1), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(2), 0x02);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_MPIC_REG_OFFSET + MPIC_CSR(3), 0x02);
 	__asm__ __volatile__ ("sync");
 
 	/*
@@ -584,42 +584,42 @@
 
 int misc_init_r (void)
 {
-#ifdef CFG_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
+#ifdef CONFIG_SYS_CLK_SPREAD	/* Initialize Spread-Spectrum Clock generation */
 	ulong i;
 
 	/* Ensure that Spread-Spectrum is disabled */
-	out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, 0);
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0, 0);
 
 	/* Initialize PLL1: CG_PCI_CLK , internal OCN_CLK
 	 * Uses pre-calculated value for Fout = 800 MHz, Fs = 30 kHz, D = 0.5%
 	 */
 
-	out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
 		0x002e0044);	/* D = 0.25% */
-	out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL1,
 		0x00000039);	/* BWADJ */
 
 	/* Initialize PLL0: CG_PB_CLKO  */
 	/* Detect PB clock freq. */
-	i = in32(CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
+	i = in32(CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PWRUP_STATUS);
 	i = (i >> 16) & 0x07;	/* Get PB PLL multiplier */
 
-	out32 (CFG_TSI108_CSR_BASE +
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
 		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0, pll0_config[i].ctrl0);
-	out32 (CFG_TSI108_CSR_BASE +
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
 		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL1, pll0_config[i].ctrl1);
 
 	/* Wait and set SSEN for both PLL0 and 1 */
 	udelay (1000);
-	out32 (CFG_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
+	out32 (CONFIG_SYS_TSI108_CSR_BASE + TSI108_CLK_REG_OFFSET + CG_PLL1_CTRL0,
 		0x802e0044);	/* D=0.25% */
-	out32 (CFG_TSI108_CSR_BASE +
+	out32 (CONFIG_SYS_TSI108_CSR_BASE +
 		TSI108_CLK_REG_OFFSET + CG_PLL0_CTRL0,
 		0x80000000 | pll0_config[i].ctrl0);
-#endif	/* CFG_CLK_SPREAD */
+#endif	/* CONFIG_SYS_CLK_SPREAD */
 
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 	printf ("BUS:   %lu MHz\n", gd->bus_clk / 1000000);
diff --git a/board/freescale/mpc8260ads/flash.c b/board/freescale/mpc8260ads/flash.c
index 7fcc874..e03852f 100644
--- a/board/freescale/mpc8260ads/flash.c
+++ b/board/freescale/mpc8260ads/flash.c
@@ -52,7 +52,7 @@
 #define INTEL_FINISHED 0x80808080
 #define INTEL_OK       0x80808080
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * This board supports 32-bit wide flash SIMMs (4x8-bit configuration.)
@@ -66,8 +66,8 @@
 	ulong size = 0, sect_start, sect_size = 0, bank_size;
 	ushort sect_count = 0;
 	int i, j, nbanks;
-	vu_long *addr = (vu_long *)CFG_FLASH_BASE;
-	vu_long *bcsr = (vu_long *)CFG_BCSR;
+	vu_long *addr = (vu_long *)CONFIG_SYS_FLASH_BASE;
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
 
 	switch (bcsr[2] & 0xF) {
 	case 0:
@@ -80,11 +80,11 @@
 		nbanks = 1;
 		break;
 	default:		/* Unsupported configurations */
-		nbanks = CFG_MAX_FLASH_BANKS;
+		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
 	}
 
-	if (nbanks > CFG_MAX_FLASH_BANKS)
-		nbanks = CFG_MAX_FLASH_BANKS;
+	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
+		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
 
 	for (i = 0; i < nbanks; i++) {
 		*addr = INTEL_READID;	/* Read Intelligent Identifier */
@@ -98,9 +98,9 @@
 				break;
 			default:
 				flash_info[i].flash_id = FLASH_UNKNOWN;
-				sect_count = CFG_MAX_FLASH_SECT;
+				sect_count = CONFIG_SYS_MAX_FLASH_SECT;
 				sect_size =
-				   CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS / CFG_MAX_FLASH_SECT;
+				   CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS / CONFIG_SYS_MAX_FLASH_SECT;
 			}
 		}
 		else
@@ -127,10 +127,10 @@
 	}
 
 	if (size == 0) {	/* Unknown flash, fill with hard-coded values */
-		sect_start = CFG_FLASH_BASE;
-		for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+		sect_start = CONFIG_SYS_FLASH_BASE;
+		for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 			flash_info[i].flash_id = FLASH_UNKNOWN;
-			flash_info[i].size = CFG_FLASH_SIZE / CFG_MAX_FLASH_BANKS;
+			flash_info[i].size = CONFIG_SYS_FLASH_SIZE / CONFIG_SYS_MAX_FLASH_BANKS;
 			flash_info[i].sector_count = sect_count;
 			for (j = 0; j < sect_count; j++) {
 				flash_info[i].start[j]   = sect_start;
@@ -138,20 +138,20 @@
 				sect_start += sect_size;
 			}
 		}
-		size = CFG_FLASH_SIZE;
+		size = CONFIG_SYS_FLASH_SIZE;
 	}
 	else
-		for (i = nbanks; i < CFG_MAX_FLASH_BANKS; i++) {
+		for (i = nbanks; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 			flash_info[i].flash_id = FLASH_UNKNOWN;
 			flash_info[i].size = 0;
 			flash_info[i].sector_count = 0;
 		}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -274,7 +274,7 @@
 				enable_interrupts();
 
 			while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = INTEL_RESET;	/* reset bank */
 					return 1;
@@ -338,7 +338,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			printf("Write timed out\n");
 			rc = 1;
 			break;
@@ -454,7 +454,7 @@
 
 	start = get_timer(0);
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -480,7 +480,7 @@
 				addr = (vu_long *)(info->start[i]);
 				*addr = INTEL_LOCKBIT;	/* Sector lock bit */
 				*addr = INTEL_PROTECT;	/* set */
-				udelay(CFG_FLASH_LOCK_TOUT * 1000);
+				udelay(CONFIG_SYS_FLASH_LOCK_TOUT * 1000);
 			}
 
 	if (flag)
diff --git a/board/freescale/mpc8260ads/mpc8260ads.c b/board/freescale/mpc8260ads/mpc8260ads.c
index 8ab7d35..49a88bb 100644
--- a/board/freescale/mpc8260ads/mpc8260ads.c
+++ b/board/freescale/mpc8260ads/mpc8260ads.c
@@ -58,32 +58,32 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A configuration */
     {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
 	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
 	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
 	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
 	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
 	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
 	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
 	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
@@ -102,34 +102,34 @@
 
     /* Port B configuration */
     {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
-	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
-	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
-	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
-	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
-	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
-	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
-	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
-	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
-	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
-	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
-	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
-	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
-	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
-	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_DIV */
+	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RX_ERR */
+	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_ERR */
+	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TX_EN */
+	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:COL */
+	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:CRS */
+	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3:RXD */
+	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
+	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3:TXD */
 	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
 	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
 	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
@@ -147,32 +147,32 @@
 	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25 */
 	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24 */
 	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23 */
-	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
-	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Tx Clock (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII Rx Clock (CLK11) */
 	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 	/* PC19 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
 	/* PC18 */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
-	/* PC16 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
+	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK15) */
+	/* PC16 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK16) */
 #else
-	/* PC19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
-	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
+	/* PC19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Rx Clock (CLK13) */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII Tx Clock (CLK14) */
 	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
 	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16 */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
 	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
 	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
 	/* PC12 */ { 0,          0,   0,   0,   0,   0 }, /* PC12 */
 	/* PC11 */ { 0,          0,   0,   0,   0,   0 }, /* PC11 */
-#if CONFIG_ADSTYPE == CFG_8272ADS
+#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 	/* PC10 */ { 0,          0,   0,   0,   0,   0 }, /* PC10 */
 	/* PC9  */ { 0,          0,   0,   0,   0,   0 }, /* PC9  */
 #else
 	/* PC10 */ { 1,          0,   0,   1,   0,   0 }, /* FETHMDC  */
 	/* PC9  */ { 1,          0,   0,   0,   0,   0 }, /* FETHMDIO */
-#endif /* CONFIG_ADSTYPE == CFG_8272ADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */
 	/* PC8  */ { 0,          0,   0,   0,   0,   0 }, /* PC8 */
 	/* PC7  */ { 0,          0,   0,   0,   0,   0 }, /* PC7 */
 	/* PC6  */ { 0,          0,   0,   0,   0,   0 }, /* PC6 */
@@ -223,10 +223,10 @@
 
 void reset_phy (void)
 {
-	vu_long *bcsr = (vu_long *)CFG_BCSR;
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
 
 	/* Reset the PHY */
-#if CFG_PHY_ADDR == 0
+#if CONFIG_SYS_PHY_ADDR == 0
 	bcsr[1] &= ~(FETHIEN1 | FETH1_RST);
 	udelay(2);
 	bcsr[1] |=  FETH1_RST;
@@ -234,16 +234,16 @@
 	bcsr[3] &= ~(FETHIEN2 | FETH2_RST);
 	udelay(2);
 	bcsr[3] |=  FETH2_RST;
-#endif /* CFG_PHY_ADDR == 0 */
+#endif /* CONFIG_SYS_PHY_ADDR == 0 */
 	udelay(1000);
 #ifdef CONFIG_MII
-#if CONFIG_ADSTYPE >= CFG_PQ2FADS
+#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS
 	/*
 	 * Do not bypass Rx/Tx (de)scrambler (fix configuration error)
 	 * Enable autonegotiation.
 	 */
-	bb_miiphy_write(NULL, CFG_PHY_ADDR, 16, 0x610);
-	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, 16, 0x610);
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
 			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
 #else
 	/*
@@ -254,14 +254,14 @@
 	 */
 
 	/* Advertise all capabilities */
-	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E1);
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_ANAR, 0x01E1);
 
 	/* Do not bypass Rx/Tx (de)scrambler */
-	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_DCR,  0x0000);
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_DCR,  0x0000);
 
-	bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR,
+	bb_miiphy_write(NULL, CONFIG_SYS_PHY_ADDR, PHY_BMCR,
 			PHY_BMCR_AUTON | PHY_BMCR_RST_NEG);
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 #endif /* CONFIG_MII */
 }
 
@@ -274,10 +274,10 @@
 
 int board_early_init_f (void)
 {
-	vu_long *bcsr = (vu_long *)CFG_BCSR;
+	vu_long *bcsr = (vu_long *)CONFIG_SYS_BCSR;
 
 #ifdef CONFIG_PCI
-	volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT;
+	volatile pci_ic_t* pci_ic = (pci_ic_t *) CONFIG_SYS_PCI_INT;
 
 	/* mask alll the PCI interrupts */
 	pci_ic->pci_int_mask |= 0xfff00000;
@@ -289,19 +289,19 @@
 	bcsr[1] &= ~RS232EN_2;
 #endif
 
-#if CONFIG_ADSTYPE != CFG_8260ADS /* PCI mode can be selected */
-#if CONFIG_ADSTYPE == CFG_PQ2FADS
+#if CONFIG_ADSTYPE != CONFIG_SYS_8260ADS /* PCI mode can be selected */
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 	if ((bcsr[3] & BCSR_PCI_MODE) == 0) /* PCI mode selected by JP9 */
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
 	{
-		volatile immap_t *immap = (immap_t *) CFG_IMMR;
+		volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 		immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
 		immap->im_siu_conf.sc_siumcr =
 			(immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11)
 			| SIUMCR_LBPC01;
 	}
-#endif /* CONFIG_ADSTYPE != CFG_8260ADS */
+#endif /* CONFIG_ADSTYPE != CONFIG_SYS_8260ADS */
 
 	return 0;
 }
@@ -310,16 +310,16 @@
 
 phys_size_t initdram (int board_type)
 {
-#if   CONFIG_ADSTYPE == CFG_PQ2FADS
+#if   CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 	long int msize = 32;
-#elif CONFIG_ADSTYPE == CFG_8272ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 	long int msize = 64;
 #else
 	long int msize = 16;
 #endif
 
-#ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *ramaddr, c = 0xff;
 	uint or;
@@ -332,33 +332,33 @@
 	immap->im_siu_conf.sc_ppc_alrh = 0x01267893;
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-#ifdef CFG_LSDRAM_BASE
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+#ifdef CONFIG_SYS_LSDRAM_BASE
 	/*
 	  Initialise local bus SDRAM only if the pins
 	  are configured as local bus pins and not as PCI.
 	  The configuration is determined by the HRCW.
 	*/
 	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CFG_LSRT;
-#if CONFIG_ADSTYPE == CFG_PQ2FADS /* CS3 */
+		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+#if CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS /* CS3 */
 		memctl->memc_or3   = 0xFF803280;
-		memctl->memc_br3   = CFG_LSDRAM_BASE | 0x00001861;
+		memctl->memc_br3   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
 #else				  /* CS4 */
 		memctl->memc_or4   = 0xFFC01480;
-		memctl->memc_br4   = CFG_LSDRAM_BASE | 0x00001861;
-#endif /* CONFIG_ADSTYPE == CFG_PQ2FADS */
-		memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
-		ramaddr = (uchar *) CFG_LSDRAM_BASE;
+		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BASE | 0x00001861;
+#endif /* CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS */
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
+		ramaddr = (uchar *) CONFIG_SYS_LSDRAM_BASE;
 		*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
 		for (i = 0; i < 8; i++)
 			*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
 		*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
 	}
-#endif /* CFG_LSDRAM_BASE */
+#endif /* CONFIG_SYS_LSDRAM_BASE */
 
 	/* Init 60x bus SDRAM */
 #ifdef CONFIG_SPD_EEPROM
@@ -498,14 +498,14 @@
 #endif /* SPD_DEBUG */
 	}
 #else  /* !CONFIG_SPD_EEPROM */
-	or    = CFG_OR2;
-	psdmr = CFG_PSDMR;
-	psrt  = CFG_PSRT;
+	or    = CONFIG_SYS_OR2;
+	psdmr = CONFIG_SYS_PSDMR;
+	psrt  = CONFIG_SYS_PSRT;
 #endif /* CONFIG_SPD_EEPROM */
 	memctl->memc_psrt = psrt;
 	memctl->memc_or2 = or;
-	memctl->memc_br2 = CFG_SDRAM_BASE | 0x00000041;
-	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x00000041;
+	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
 	memctl->memc_psdmr = psdmr | 0x28000000;	/* Precharge all banks */
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | 0x08000000;	/* CBR refresh */
@@ -516,7 +516,7 @@
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | 0x40000000;	/* Refresh enable */
 	*ramaddr = c;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/* return total 60x bus SDRAM size */
 	return (msize * 1024 * 1024);
@@ -524,13 +524,13 @@
 
 int checkboard (void)
 {
-#if   CONFIG_ADSTYPE == CFG_8260ADS
+#if   CONFIG_ADSTYPE == CONFIG_SYS_8260ADS
 	puts ("Board: Motorola MPC8260ADS\n");
-#elif CONFIG_ADSTYPE == CFG_8266ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8266ADS
 	puts ("Board: Motorola MPC8266ADS\n");
-#elif CONFIG_ADSTYPE == CFG_PQ2FADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS
 	puts ("Board: Motorola PQ2FADS-ZU\n");
-#elif CONFIG_ADSTYPE == CFG_8272ADS
+#elif CONFIG_ADSTYPE == CONFIG_SYS_8272ADS
 	puts ("Board: Motorola MPC8272ADS\n");
 #else
 	puts ("Board: unknown\n");
diff --git a/board/freescale/mpc8266ads/flash.c b/board/freescale/mpc8266ads/flash.c
index b4cdcd9..06dde36 100644
--- a/board/freescale/mpc8266ads/flash.c
+++ b/board/freescale/mpc8266ads/flash.c
@@ -29,11 +29,11 @@
 #include <common.h>
 
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -56,7 +56,7 @@
 unsigned long flash_init (void)
 {
 #ifndef CONFIG_MPC8266ADS
-	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t	*memctl = &immap->im_memctl;
 	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
 #endif
@@ -71,7 +71,7 @@
 #endif
 
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 		/* set the default sector offset */
@@ -88,20 +88,20 @@
 
 #ifndef CONFIG_MPC8266ADS
 	/* Remap FLASH according to real size */
-	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
 				(memctl->memc_br1 & ~(BR_BA_MSK));
 #endif
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -336,7 +336,7 @@
 					*addr = 0xFFFFFFFF;	/* reset bank */
 					return 1;
 				}
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0xFFFFFFFF;	/* reset bank */
 					return 1;
@@ -461,7 +461,7 @@
 	start = get_timer (0);
 	flag  = 0;
 	while (((csr = *addr) & 0x80808080) != 0x80808080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			flag = 1;
 			break;
 		}
@@ -499,7 +499,7 @@
 
 	start = get_timer (0);
 	while(*addr != 0x80808080){
-		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout on clearing Block Lock Bit\n");
 			*addr = 0xFFFFFFFF;	/* reset bank */
 			return 1;
diff --git a/board/freescale/mpc8266ads/mpc8266ads.c b/board/freescale/mpc8266ads/mpc8266ads.c
index 090a534..66acc41 100644
--- a/board/freescale/mpc8266ads/mpc8266ads.c
+++ b/board/freescale/mpc8266ads/mpc8266ads.c
@@ -224,7 +224,7 @@
 
 void reset_phy(void)
 {
-    volatile bcsr_t  *bcsr           = (bcsr_t *)CFG_BCSR;
+    volatile bcsr_t  *bcsr           = (bcsr_t *)CONFIG_SYS_BCSR;
 
     /* reset the FEC port */
     bcsr->bcsr1                    &= ~FETH_RST;
@@ -234,8 +234,8 @@
 
 int board_early_init_f (void)
 {
-    volatile bcsr_t  *bcsr         = (bcsr_t *)CFG_BCSR;
-    volatile pci_ic_t *pci_ic      = (pci_ic_t *) CFG_PCI_INT;
+    volatile bcsr_t  *bcsr         = (bcsr_t *)CONFIG_SYS_BCSR;
+    volatile pci_ic_t *pci_ic      = (pci_ic_t *) CONFIG_SYS_PCI_INT;
 
     bcsr->bcsr1                    = ~FETHIEN & ~RS232EN_1 & ~RS232EN_2;
 
@@ -254,17 +254,17 @@
 phys_size_t initdram(int board_type)
 {
 	/* Autoinit part stolen from board/sacsng/sacsng.c */
-    volatile immap_t *immap         = (immap_t *)CFG_IMMR;
+    volatile immap_t *immap         = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8260_t *memctl   = &immap->im_memctl;
     volatile uchar c = 0xff;
-    volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
-    uint  psdmr = CFG_PSDMR;
+    volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+    uint  psdmr = CONFIG_SYS_PSDMR;
     int i;
 
     uint   psrt = 0x21;					/* for no SPD */
     uint   chipselects = 1;				/* for no SPD */
-    uint   sdram_size = CFG_SDRAM_SIZE * 1024 * 1024;	/* for no SPD */
-    uint   or = CFG_OR2_PRELIM;				/* for no SPD */
+    uint   sdram_size = CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CONFIG_SYS_OR2_PRELIM;				/* for no SPD */
     uint   data_width;
     uint   rows;
     uint   banks;
@@ -286,7 +286,7 @@
     /*
      * Read the SDRAM SPD EEPROM via I2C.
      */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
     i2c_read(SDRAM_SPD_ADDR, 0, 1, &data, 1);
     spd_size = data;
@@ -506,13 +506,13 @@
      *  accessing the SDRAM with a single-byte transaction."
      *
      * The appropriate BRx/ORx registers have already been set when we
-     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
      */
 
-    memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
     memctl->memc_psrt  = psrt;
 
-    memctl->memc_br2 = CFG_BR2_PRELIM;
+    memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
     memctl->memc_or2 = or;
 
     memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
@@ -536,7 +536,7 @@
 	{
 	ramaddr += sdram_size;
 
-		memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
 		memctl->memc_or3 = or;
 
 		memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
index ebb703d..9ffd4bf 100644
--- a/board/freescale/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -36,8 +36,8 @@
 
 int board_early_init_f(void)
 {
-#ifndef CFG_8313ERDB_BROKEN_PMC
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		gd->flags |= GD_FLG_SILENT;
@@ -55,28 +55,28 @@
 #ifndef CONFIG_NAND_SPL
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI1_MEM_BASE,
-		phys_start: CFG_PCI1_MEM_PHYS,
-		size: CFG_PCI1_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI1_MMIO_BASE,
-		phys_start: CFG_PCI1_MMIO_PHYS,
-		size: CFG_PCI1_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI1_IO_BASE,
-		phys_start: CFG_PCI1_IO_PHYS,
-		size: CFG_PCI1_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
@@ -88,14 +88,14 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 	warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF;
 #endif
 
@@ -135,13 +135,13 @@
 void board_init_f(ulong bootflag)
 {
 	board_early_init_f();
-	NS16550_init((NS16550_t)(CFG_IMMR + 0x4500),
-	             CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE);
+	NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
+	             CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
 	puts("NAND boot... ");
 	init_timebase();
 	initdram(0);
-	relocate_code(CFG_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
-	              CFG_NAND_U_BOOT_RELOC);
+	relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
+	              CONFIG_SYS_NAND_U_BOOT_RELOC);
 }
 
 void board_init_r(gd_t *gd, ulong dest_addr)
@@ -155,8 +155,8 @@
 		return;
 
 	if (c == '\n')
-		NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), '\r');
+		NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
 
-	NS16550_putc((NS16550_t)(CFG_IMMR + 0x4500), c);
+	NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
 }
 #endif
diff --git a/board/freescale/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
index 128cd40..99e8a43 100644
--- a/board/freescale/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -35,7 +35,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 static void resume_from_sleep(void)
 {
 	u32 magic = *(u32 *)0;
@@ -58,15 +58,15 @@
  */
 static long fixed_sdram(void)
 {
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 
-#ifndef CFG_RAMBOOT
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
 	/*
 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
@@ -75,29 +75,29 @@
 	udelay(50000);
 
 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
 
 	/* Currently we use only one CS, so disable the other bank. */
 	im->ddr.cs_config[1] = 0;
 
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CFG_SDRAM_CFG | SDRAM_CFG_BI;
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG | SDRAM_CFG_BI;
 	else
 #endif
-		im->ddr.sdram_cfg = CFG_SDRAM_CFG;
+		im->ddr.sdram_cfg = CONFIG_SYS_SDRAM_CFG;
 
-	im->ddr.sdram_cfg2 = CFG_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE_2;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE_2;
 
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	sync();
 
 	/* enable DDR controller */
@@ -109,7 +109,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile lbus83xx_t *lbc = &im->lbus;
 	u32 msize;
 
@@ -120,11 +120,11 @@
 	msize = fixed_sdram();
 
 	/* Local Bus setup lbcr and mrtpr */
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	sync();
 
-#ifndef CFG_8313ERDB_BROKEN_PMC
+#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		resume_from_sleep();
 #endif
diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c
index 0330218..ea4b04f 100644
--- a/board/freescale/mpc8315erdb/mpc8315erdb.c
+++ b/board/freescale/mpc8315erdb/mpc8315erdb.c
@@ -35,7 +35,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
 		gd->flags |= GD_FLG_SILENT;
@@ -48,7 +48,7 @@
 	u8 val8;
 	i2c_set_bus_num(0);
 
-	if (i2c_read(CFG_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
+	if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
 		return val8;
 	else
 		return 0;
@@ -76,28 +76,28 @@
 
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI_MEM_BASE,
-		phys_start: CFG_PCI_MEM_PHYS,
-		size: CFG_PCI_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI_MMIO_BASE,
-		phys_start: CFG_PCI_MMIO_PHYS,
-		size: CFG_PCI_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI_IO_BASE,
-		phys_start: CFG_PCI_IO_PHYS,
-		size: CFG_PCI_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
@@ -109,10 +109,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
diff --git a/board/freescale/mpc8315erdb/sdram.c b/board/freescale/mpc8315erdb/sdram.c
index 3714c2c..ead7b1e 100644
--- a/board/freescale/mpc8315erdb/sdram.c
+++ b/board/freescale/mpc8315erdb/sdram.c
@@ -56,13 +56,13 @@
  */
 static long fixed_sdram(void)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE  & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE  & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
-	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 
 	/*
 	 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
@@ -71,27 +71,27 @@
 	udelay(50000);
 
 	im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 
 	/* Currently we use only one CS, so disable the other bank. */
 	im->ddr.cs_config[1] = 0;
 
-	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
 
 	if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
-		im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG | SDRAM_CFG_BI;
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
 	else
-		im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
+		im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
 
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
 
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	sync();
 
 	/* enable DDR controller */
@@ -103,7 +103,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	u32 msize;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index f5220ab..8680a19 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -75,14 +75,14 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
@@ -95,12 +95,12 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1) {
@@ -109,18 +109,18 @@
 	}
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	__asm__ __volatile__ ("sync");
 	udelay(200);
 
@@ -137,28 +137,28 @@
 
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI1_MEM_BASE,
-		phys_start: CFG_PCI1_MEM_PHYS,
-		size: CFG_PCI1_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI1_MMIO_BASE,
-		phys_start: CFG_PCI1_MMIO_PHYS,
-		size: CFG_PCI1_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI1_IO_BASE,
-		phys_start: CFG_PCI1_IO_PHYS,
-		size: CFG_PCI1_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
@@ -167,10 +167,10 @@
 	clk->occr |= 0xe0000000;
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	mpc83xx_pci_init(1, reg, 0);
@@ -186,7 +186,7 @@
 }
 #endif
 
-#if defined(CFG_I2C_MAC_OFFSET)
+#if defined(CONFIG_SYS_I2C_MAC_OFFSET)
 int mac_read_from_eeprom(void)
 {
 	uchar buf[28];
@@ -196,9 +196,9 @@
 	unsigned char enetvar[32];
 
 	/* Read MAC addresses from EEPROM */
-	if (eeprom_read(CFG_I2C_EEPROM_ADDR, CFG_I2C_MAC_OFFSET, buf, 28)) {
+	if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
 		printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
-		       CFG_I2C_EEPROM_ADDR);
+		       CONFIG_SYS_I2C_EEPROM_ADDR);
 	} else {
 		if (crc32(crc, buf, 24) == *(unsigned int *)&buf[24]) {
 			printf("Reading MAC from EEPROM\n");
diff --git a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
index 4ad6e9d..d4d4479 100644
--- a/board/freescale/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -76,7 +76,7 @@
 
 int board_early_init_f(void)
 {
-	volatile u8 *bcsr = (volatile u8 *)CFG_BCSR;
+	volatile u8 *bcsr = (volatile u8 *)CONFIG_SYS_BCSR;
 
 	/* Enable flash write */
 	bcsr[9] &= ~0x08;
@@ -96,14 +96,14 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 
 	msize = fixed_sdram();
 
@@ -116,12 +116,12 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1) {
@@ -130,21 +130,21 @@
 	}
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 128)
+#if (CONFIG_SYS_DDR_SIZE != 128)
 #warning Currenly any ddr size other than 128 is not supported
 #endif
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	__asm__ __volatile__ ("sync");
 	udelay(200);
 
diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
index b030422..2a48dd2 100644
--- a/board/freescale/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -67,7 +67,7 @@
 	volatile pcictrl83xx_t *pci_ctrl;
 	volatile pciconf83xx_t *pci_conf;
 
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
 	pci_ctrl = immr->pci_ctrl;
@@ -93,7 +93,7 @@
 	hose[0].first_busno = 0;
 	hose[0].last_busno = 0xff;
 	pci_setup_indirect(&hose[0],
-			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
 	reg16 = 0xff;
 
 	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
@@ -134,7 +134,7 @@
 	u32 val32;
 	u32 dev;
 
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) & immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
@@ -161,10 +161,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
 
 	/*
@@ -172,26 +172,26 @@
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr =
 	    POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI IO space */
-	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 
 	/*
 	 * Configure PCI Inbound Translation Windows
 	 */
-	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
-	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+	pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+	pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
 	pci_ctrl[0].piebar1 = 0x0;
 	pci_ctrl[0].piwar1 =
 	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
@@ -209,31 +209,31 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose[0].regions + 0,
-		       CFG_PCI_MEM_BASE,
-		       CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose[0].regions + 1,
-		       CFG_PCI_MMIO_BASE,
-		       CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose[0].regions + 2,
-		       CFG_PCI_IO_BASE,
-		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 
 	/* System memory space */
 	pci_set_region(hose[0].regions + 3,
-		       CFG_PCI_SLV_MEM_LOCAL,
-		       CFG_PCI_SLV_MEM_BUS,
-		       CFG_PCI_SLV_MEM_SIZE,
+		       CONFIG_SYS_PCI_SLV_MEM_LOCAL,
+		       CONFIG_SYS_PCI_SLV_MEM_BUS,
+		       CONFIG_SYS_PCI_SLV_MEM_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	hose[0].region_count = 4;
 
 	pci_setup_indirect(&hose[0],
-			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 
diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
index ef947fe..fa44360 100644
--- a/board/freescale/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -44,12 +44,12 @@
 
 int board_early_init_f (void)
 {
-	volatile u8* bcsr = (volatile u8*)CFG_BCSR;
+	volatile u8* bcsr = (volatile u8*)CONFIG_SYS_BCSR;
 
 	/* Enable flash write */
 	bcsr[1] &= ~0x01;
 
-#ifdef CFG_USE_MPC834XSYS_USB_PHY
+#ifdef CONFIG_SYS_USE_MPC834XSYS_USB_PHY
 	/* Use USB PHY on SYS board */
 	bcsr[5] |= 0x02;
 #endif
@@ -61,14 +61,14 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
 #else
@@ -96,12 +96,12 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1);
 	     ddr_size = ddr_size>>1, ddr_size_log2++) {
@@ -109,36 +109,36 @@
 			return -1;
 		}
 	}
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
 #ifdef CONFIG_DDR_II
-	im->ddr.csbnds[2].csbnds = CFG_DDR_CS2_BNDS;
-	im->ddr.cs_config[2] = CFG_DDR_CS2_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[2].csbnds = CONFIG_SYS_DDR_CS2_BNDS;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CS2_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
 	im->ddr.cs_config[1] = 0;
 	im->ddr.cs_config[3] = 0;
 
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 
 	im->ddr.sdram_cfg =
 		SDRAM_CFG_SREN
@@ -150,9 +150,9 @@
 	/* for 32-bit mode burst length is 8 */
 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 #endif
-	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 #endif
 	udelay(200);
 
@@ -160,7 +160,7 @@
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 	return msize;
 }
-#endif/*!CFG_SPD_EEPROM*/
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
 
 
 int checkboard (void)
@@ -181,41 +181,41 @@
 /*
  * if MPC8349EMDS is soldered with SDRAM
  */
-#if defined(CFG_BR2_PRELIM)  \
-	&& defined(CFG_OR2_PRELIM) \
-	&& defined(CFG_LBLAWBAR2_PRELIM) \
-	&& defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
 
 void sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile lbus83xx_t *lbc= &immap->lbus;
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
 
 	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->mrtpr = CFG_LBC_MRTPR;
-	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller Machine Mode Register.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 
-	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 	asm("sync");
 	/*1 times*/
 	*sdram_addr = 0xff;
@@ -243,12 +243,12 @@
 	udelay(100);
 
 	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
@@ -273,14 +273,14 @@
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat &= ~SPI_CS_MASK;
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat |=  SPI_CS_MASK;
 }
diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
index 9c19e30..ad7bf5d 100644
--- a/board/freescale/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -33,21 +33,21 @@
 
 static struct pci_region pci1_regions[] = {
 	{
-		bus_start: CFG_PCI1_MEM_BASE,
-		phys_start: CFG_PCI1_MEM_PHYS,
-		size: CFG_PCI1_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI1_IO_BASE,
-		phys_start: CFG_PCI1_IO_PHYS,
-		size: CFG_PCI1_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
 		flags: PCI_REGION_IO
 	},
 	{
-		bus_start: CFG_PCI1_MMIO_BASE,
-		phys_start: CFG_PCI1_MMIO_PHYS,
-		size: CFG_PCI1_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 };
@@ -55,21 +55,21 @@
 #ifdef CONFIG_MPC83XX_PCI2
 static struct pci_region pci2_regions[] = {
 	{
-		bus_start: CFG_PCI2_MEM_BASE,
-		phys_start: CFG_PCI2_MEM_PHYS,
-		size: CFG_PCI2_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI2_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
+		size: CONFIG_SYS_PCI2_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI2_IO_BASE,
-		phys_start: CFG_PCI2_IO_PHYS,
-		size: CFG_PCI2_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI2_IO_BASE,
+		phys_start: CONFIG_SYS_PCI2_IO_PHYS,
+		size: CONFIG_SYS_PCI2_IO_SIZE,
 		flags: PCI_REGION_IO
 	},
 	{
-		bus_start: CFG_PCI2_MMIO_BASE,
-		phys_start: CFG_PCI2_MMIO_PHYS,
-		size: CFG_PCI2_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
+		size: CONFIG_SYS_PCI2_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 };
@@ -135,7 +135,7 @@
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 #ifndef CONFIG_MPC83XX_PCI2
@@ -152,10 +152,10 @@
 	udelay(2000);
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 
 	udelay(2000);
@@ -170,7 +170,7 @@
 #else
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
@@ -181,10 +181,10 @@
 	udelay(2000);
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 
 	udelay(2000);
diff --git a/board/freescale/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
index 0a20e2b..3169536 100644
--- a/board/freescale/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -42,11 +42,11 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 ddr_size;		/* The size of RAM, in bytes */
 	u32 ddr_size_log2 = 0;
 
-	for (ddr_size = CFG_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
+	for (ddr_size = CONFIG_SYS_DDR_SIZE * 0x100000; ddr_size > 1; ddr_size >>= 1) {
 		if (ddr_size & 1) {
 			return -1;
 		}
@@ -55,11 +55,11 @@
 
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 
 	/* Only one CS0 for DDR */
 	im->ddr.csbnds[0].csbnds = 0x0000000f;
-	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
 
 	debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
 	debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
@@ -67,15 +67,15 @@
 	debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
 	debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
 
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
 	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
 	im->ddr.sdram_mode =
 	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
 	im->ddr.sdram_interval =
 	    (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
 						       SDRAM_INTERVAL_BSTOPRE_SHIFT);
-	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 
 	udelay(200);
 
@@ -87,7 +87,7 @@
 	debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
 	debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
 
-	return CFG_DDR_SIZE;
+	return CONFIG_SYS_DDR_SIZE;
 }
 #endif
 
@@ -130,7 +130,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 #ifdef CONFIG_DDR_ECC
 	volatile ddr83xx_t *ddr = &im->ddr;
@@ -140,7 +140,7 @@
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #ifdef CONFIG_SPD_EEPROM
 	msize = spd_sdram();
 #else
@@ -196,7 +196,7 @@
 	   don't enable compact flash for U-Boot.
 	 */
 
-	vsc7385_cpuctrl = (volatile u32 *)(CFG_VSC7385_BASE + 0x1c0c0);
+	vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
 	*vsc7385_cpuctrl |= 0x0c;
 #endif
 
@@ -220,11 +220,11 @@
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
 		0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
 	};
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile lbus83xx_t *lbus = &immap->lbus;
 
-	lbus->bank[3].br = CFG_BR3_PRELIM;
-	lbus->bank[3].or = CFG_OR3_PRELIM;
+	lbus->bank[3].br = CONFIG_SYS_BR3_PRELIM;
+	lbus->bank[3].or = CONFIG_SYS_OR3_PRELIM;
 
 	/* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
 	   GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
@@ -265,26 +265,26 @@
 	unsigned int orig_bus = i2c_get_bus_num();
 	u8 i2c_data;
 
-#ifdef CFG_I2C_RTC_ADDR
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
 	u8 ds1339_data[17];
 #endif
 
-#ifdef CFG_I2C_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 	static u8 eeprom_data[] =	/* HRCW data */
 	{
 		0xAA, 0x55, 0xAA,       /* Preamble */
 		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
 		0x02, 0x40,	        /* RCWL ADDR=0x0_0900 */
-		(CFG_HRCW_LOW >> 24) & 0xFF,
-		(CFG_HRCW_LOW >> 16) & 0xFF,
-		(CFG_HRCW_LOW >> 8) & 0xFF,
-		CFG_HRCW_LOW & 0xFF,
+		(CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
+		(CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
+		(CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
+		CONFIG_SYS_HRCW_LOW & 0xFF,
 		0x7C,		        /* ACS=0, BYTE_EN=1111, CONT=1 */
 		0x02, 0x41,	        /* RCWH ADDR=0x0_0904 */
-		(CFG_HRCW_HIGH >> 24) & 0xFF,
-		(CFG_HRCW_HIGH >> 16) & 0xFF,
-		(CFG_HRCW_HIGH >> 8) & 0xFF,
-		CFG_HRCW_HIGH & 0xFF
+		(CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
+		(CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
+		(CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
+		CONFIG_SYS_HRCW_HIGH & 0xFF
 	};
 
 	u8 data[sizeof(eeprom_data)];
@@ -292,22 +292,22 @@
 
 	printf("Board revision: ");
 	i2c_set_bus_num(1);
-	if (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+	if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 		printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
-	else if (i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
+	else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
 		printf("%u.%u (PCF8475)\n",  (i2c_data & 0x02) >> 1, i2c_data & 0x01);
 	else {
 		printf("Unknown\n");
 		rc = 1;
 	}
 
-#ifdef CFG_I2C_EEPROM_ADDR
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR
 	i2c_set_bus_num(0);
 
-	if (i2c_read(CFG_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
+	if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
 		if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
 			if (i2c_write
-			    (CFG_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
+			    (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
 			     sizeof(eeprom_data)) != 0) {
 				puts("Failure writing the HRCW to EEPROM via I2C.\n");
 				rc = 1;
@@ -319,10 +319,10 @@
 	}
 #endif
 
-#ifdef CFG_I2C_RTC_ADDR
+#ifdef CONFIG_SYS_I2C_RTC_ADDR
 	i2c_set_bus_num(1);
 
-	if (i2c_read(CFG_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
+	if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
 	    == 0) {
 
 		/* Work-around for MPC8349E-mITX bug #13601.
@@ -366,7 +366,7 @@
 		 */
 
 		if (i2c_write
-		    (CFG_I2C_RTC_ADDR, 0, 1, ds1339_data,
+		    (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
 		     sizeof(ds1339_data))) {
 			puts("Failure writing to the RTC via I2C.\n");
 			rc = 1;
diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
index d33edf3..fd2c172 100644
--- a/board/freescale/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -37,8 +37,8 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_mpc8349itx_config_table[] = {
@@ -92,7 +92,7 @@
 	u32 dev;
 	struct pci_controller *hose;
 
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) & immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
@@ -111,8 +111,8 @@
 #ifdef CONFIG_HARD_I2C
 	i2c_set_bus_num(1);
 	/* Read the PCI_M66EN jumper setting */
-	if ((i2c_read(CFG_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
-	    (i2c_read(CFG_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
+	if ((i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0) ||
+	    (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &reg8, sizeof(reg8)) == 0)) {
 		if (reg8 & I2C_8574_PCI66)
 			clk->occr = 0xff000000;	/* 66 MHz PCI */
 		else
@@ -150,10 +150,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_32M;
 
 	/*
@@ -161,18 +161,18 @@
 	 */
 
 	/* PCI1 mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | POCMR_CM_256M;
 
 	/* PCI1 IO space */
-	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | POCMR_CM_16M;
 
 	/* PCI1 mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_CM_256M;
 
 	/*
@@ -192,19 +192,19 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI1_MEM_BASE,
-		       CFG_PCI1_MEM_PHYS,
-		       CFG_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+		       CONFIG_SYS_PCI1_MEM_BASE,
+		       CONFIG_SYS_PCI1_MEM_PHYS,
+		       CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI1_MMIO_BASE,
-		       CFG_PCI1_MMIO_PHYS, CFG_PCI1_MMIO_SIZE, PCI_REGION_MEM);
+		       CONFIG_SYS_PCI1_MMIO_BASE,
+		       CONFIG_SYS_PCI1_MMIO_PHYS, CONFIG_SYS_PCI1_MMIO_SIZE, PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI1_IO_BASE,
-		       CFG_PCI1_IO_PHYS, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+		       CONFIG_SYS_PCI1_IO_BASE,
+		       CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	/* System memory space */
 	pci_set_region(hose->regions + 3,
@@ -215,7 +215,7 @@
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 
@@ -251,18 +251,18 @@
 	 */
 
 	/* PCI2 mem space - prefetch */
-	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | POCMR_CM_256M;
 
 	/* PCI2 IO space */
-	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | POCMR_CM_16M;
 
 	/* PCI2 mmio - non-prefetch mem space */
-	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_CM_256M;
 
 	/*
@@ -283,19 +283,19 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI2_MEM_BASE,
-		       CFG_PCI2_MEM_PHYS,
-		       CFG_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_PHYS,
+		       CONFIG_SYS_PCI2_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI2_MMIO_BASE,
-		       CFG_PCI2_MMIO_PHYS, CFG_PCI2_MMIO_SIZE, PCI_REGION_MEM);
+		       CONFIG_SYS_PCI2_MMIO_BASE,
+		       CONFIG_SYS_PCI2_MMIO_PHYS, CONFIG_SYS_PCI2_MMIO_SIZE, PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI2_IO_BASE,
-		       CFG_PCI2_IO_PHYS, CFG_PCI2_IO_SIZE, PCI_REGION_IO);
+		       CONFIG_SYS_PCI2_IO_BASE,
+		       CONFIG_SYS_PCI2_IO_PHYS, CONFIG_SYS_PCI2_IO_SIZE, PCI_REGION_IO);
 
 	/* System memory space */
 	pci_set_region(hose->regions + 3,
@@ -306,7 +306,7 @@
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR + 0x8380), (CFG_IMMR + 0x8384));
+			   (CONFIG_SYS_IMMR + 0x8380), (CONFIG_SYS_IMMR + 0x8384));
 
 	pci_register_hose(hose);
 
diff --git a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
index 5c3b5db..fc0a0e5 100644
--- a/board/freescale/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -92,8 +92,8 @@
 int board_early_init_f(void)
 {
 
-	u8 *bcsr = (u8 *)CFG_BCSR;
-	const immap_t *immr = (immap_t *)CFG_IMMR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
+	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 
 	/* Enable flash write */
 	bcsr[0xa] &= ~0x04;
@@ -124,14 +124,14 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
 #else
@@ -159,12 +159,12 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1) {
@@ -173,42 +173,42 @@
 	}
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currenly any ddr size other than 256 is not supported
 #endif
 #ifdef CONFIG_DDR_II
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 #else
 	im->ddr.csbnds[0].csbnds = 0x00000007;
 	im->ddr.csbnds[1].csbnds = 0x0008000f;
 
-	im->ddr.cs_config[0] = CFG_DDR_CONFIG;
-	im->ddr.cs_config[1] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
+	im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
 
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.sdram_cfg = CFG_DDR_CONTROL;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 #endif
 	udelay(200);
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
 	return msize;
 }
-#endif				/*!CFG_SPD_EEPROM */
+#endif				/*!CONFIG_SYS_SPD_EEPROM */
 
 int checkboard(void)
 {
@@ -219,34 +219,34 @@
 /*
  * if MPC8360EMDS is soldered with SDRAM
  */
-#if defined(CFG_BR2_PRELIM)  \
-	&& defined(CFG_OR2_PRELIM) \
-	&& defined(CFG_LBLAWBAR2_PRELIM) \
-	&& defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
 
 void sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile lbus83xx_t *lbc = &immap->lbus;
-	uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
+	uint *sdram_addr = (uint *) CONFIG_SYS_LBC_SDRAM_BASE;
 
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
 	/*setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->mrtpr = CFG_LBC_MRTPR;
-	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller Machine Mode Register.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_5;	/* Normal Operation */
-	lbc->lsdmr = CFG_LBC_LSDMR_1;	/* Precharge All Banks */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;	/* Normal Operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;	/* Precharge All Banks */
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
@@ -254,7 +254,7 @@
 	/*
 	 * We need do 8 times auto refresh operation.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 	asm("sync");
 	*sdram_addr = 0xff;	/* 1 times */
 	udelay(100);
@@ -274,13 +274,13 @@
 	udelay(100);
 
 	/* Mode register write operation */
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	*(sdram_addr + 0xcc) = 0xff;
 	udelay(100);
 
 	/* Normal operation */
-	lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
@@ -294,7 +294,7 @@
 #if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
-	const immap_t *immr = (immap_t *)CFG_IMMR;
+	const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 
 	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
index 4a0d460..935aca26 100644
--- a/board/freescale/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -67,7 +67,7 @@
 	volatile pcictrl83xx_t *pci_ctrl;
 	volatile pciconf83xx_t *pci_conf;
 
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
 	pci_ctrl = immr->pci_ctrl;
@@ -93,7 +93,7 @@
 	hose[0].first_busno = 0;
 	hose[0].last_busno = 0xff;
 	pci_setup_indirect(&hose[0],
-			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
 	reg16 = 0xff;
 
 	pci_hose_read_config_word(&hose[0], PCI_BDF(0, 0, 0),
@@ -134,7 +134,7 @@
 	u32 val32;
 	u32 dev;
 
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) & immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
@@ -161,10 +161,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
 
 	/*
@@ -172,26 +172,26 @@
 	 */
 
 	/* PCI mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr =
 	    POCMR_EN | POCMR_SE | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI mmio - non-prefetch mem space */
-	pci_pot[1].potar = (CFG_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI IO space */
-	pci_pot[2].potar = (CFG_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 
 	/*
 	 * Configure PCI Inbound Translation Windows
 	 */
-	pci_ctrl[0].pitar1 = (CFG_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
-	pci_ctrl[0].pibar1 = (CFG_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
+	pci_ctrl[0].pitar1 = (CONFIG_SYS_PCI_SLV_MEM_LOCAL >> 12) & PITAR_TA_MASK;
+	pci_ctrl[0].pibar1 = (CONFIG_SYS_PCI_SLV_MEM_BUS >> 12) & PIBAR_MASK;
 	pci_ctrl[0].piebar1 = 0x0;
 	pci_ctrl[0].piwar1 =
 	    PIWAR_EN | PIWAR_PF | PIWAR_RTT_SNOOP | PIWAR_WTT_SNOOP |
@@ -209,31 +209,31 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose[0].regions + 0,
-		       CFG_PCI_MEM_BASE,
-		       CFG_PCI_MEM_PHYS,
-		       CFG_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
+		       CONFIG_SYS_PCI_MEM_BASE,
+		       CONFIG_SYS_PCI_MEM_PHYS,
+		       CONFIG_SYS_PCI_MEM_SIZE, PCI_REGION_MEM | PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose[0].regions + 1,
-		       CFG_PCI_MMIO_BASE,
-		       CFG_PCI_MMIO_PHYS, CFG_PCI_MMIO_SIZE, PCI_REGION_MEM);
+		       CONFIG_SYS_PCI_MMIO_BASE,
+		       CONFIG_SYS_PCI_MMIO_PHYS, CONFIG_SYS_PCI_MMIO_SIZE, PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose[0].regions + 2,
-		       CFG_PCI_IO_BASE,
-		       CFG_PCI_IO_PHYS, CFG_PCI_IO_SIZE, PCI_REGION_IO);
+		       CONFIG_SYS_PCI_IO_BASE,
+		       CONFIG_SYS_PCI_IO_PHYS, CONFIG_SYS_PCI_IO_SIZE, PCI_REGION_IO);
 
 	/* System memory space */
 	pci_set_region(hose[0].regions + 3,
-		       CFG_PCI_SLV_MEM_LOCAL,
-		       CFG_PCI_SLV_MEM_BUS,
-		       CFG_PCI_SLV_MEM_SIZE,
+		       CONFIG_SYS_PCI_SLV_MEM_LOCAL,
+		       CONFIG_SYS_PCI_SLV_MEM_BUS,
+		       CONFIG_SYS_PCI_SLV_MEM_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	hose[0].region_count = 4;
 
 	pci_setup_indirect(&hose[0],
-			   (CFG_IMMR + 0x8300), (CFG_IMMR + 0x8304));
+			   (CONFIG_SYS_IMMR + 0x8300), (CONFIG_SYS_IMMR + 0x8304));
 
 	pci_register_hose(hose);
 
diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c
index 61d7000..af3b8ce 100644
--- a/board/freescale/mpc8360erdk/mpc8360erdk.c
+++ b/board/freescale/mpc8360erdk/mpc8360erdk.c
@@ -214,7 +214,7 @@
 
 int board_early_init_r(void)
 {
-	void *reg = (void *)(CFG_IMMR + 0x14a8);
+	void *reg = (void *)(CONFIG_SYS_IMMR + 0x14a8);
 	u32 val;
 
 	/*
@@ -233,12 +233,12 @@
 
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1)
@@ -248,18 +248,18 @@
 	im->sysconf.ddrlaw[0].ar =
 	    LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 	udelay(200);
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
@@ -271,14 +271,14 @@
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 	extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 	msize = fixed_sdram();
 
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
@@ -300,28 +300,28 @@
 
 static struct pci_region pci_regions[] = {
 	{
-		.bus_start = CFG_PCI1_MEM_BASE,
-		.phys_start = CFG_PCI1_MEM_PHYS,
-		.size = CFG_PCI1_MEM_SIZE,
+		.bus_start = CONFIG_SYS_PCI1_MEM_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MEM_PHYS,
+		.size = CONFIG_SYS_PCI1_MEM_SIZE,
 		.flags = PCI_REGION_MEM | PCI_REGION_PREFETCH,
 	},
 	{
-		.bus_start = CFG_PCI1_MMIO_BASE,
-		.phys_start = CFG_PCI1_MMIO_PHYS,
-		.size = CFG_PCI1_MMIO_SIZE,
+		.bus_start = CONFIG_SYS_PCI1_MMIO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_MMIO_PHYS,
+		.size = CONFIG_SYS_PCI1_MMIO_SIZE,
 		.flags = PCI_REGION_MEM,
 	},
 	{
-		.bus_start = CFG_PCI1_IO_BASE,
-		.phys_start = CFG_PCI1_IO_PHYS,
-		.size = CFG_PCI1_IO_SIZE,
+		.bus_start = CONFIG_SYS_PCI1_IO_BASE,
+		.phys_start = CONFIG_SYS_PCI1_IO_PHYS,
+		.size = CONFIG_SYS_PCI1_IO_SIZE,
 		.flags = PCI_REGION_IO,
 	},
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions, };
@@ -338,10 +338,10 @@
 	udelay(2000);
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	mpc83xx_pci_init(1, reg, 0);
diff --git a/board/freescale/mpc8360erdk/nand.c b/board/freescale/mpc8360erdk/nand.c
index 8b44a0f..8e22e13 100644
--- a/board/freescale/mpc8360erdk/nand.c
+++ b/board/freescale/mpc8360erdk/nand.c
@@ -18,7 +18,7 @@
 #include <linux/mtd/fsl_upm.h>
 #include <nand.h>
 
-static struct immap *im = (struct immap *)CFG_IMMR;
+static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
 
 static const u32 upm_array[] = {
 	0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words  0 to  3 */
@@ -70,7 +70,7 @@
 
 static struct fsl_upm_nand fun = {
 	.upm = {
-		.io_addr = (void *)CFG_NAND_BASE,
+		.io_addr = (void *)CONFIG_SYS_NAND_BASE,
 	},
 	.width = 8,
 	.upm_cmd_offset = 8,
diff --git a/board/freescale/mpc837xemds/mpc837xemds.c b/board/freescale/mpc837xemds/mpc837xemds.c
index 8003ec1..6c537e2 100644
--- a/board/freescale/mpc837xemds/mpc837xemds.c
+++ b/board/freescale/mpc837xemds/mpc837xemds.c
@@ -24,7 +24,7 @@
 
 int board_early_init_f(void)
 {
-	u8 *bcsr = (u8 *)CFG_BCSR;
+	u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
 
 	/* Enable flash write */
 	bcsr[0x9] &= ~0x04;
@@ -32,7 +32,7 @@
 	bcsr[0xe] = 0xff;
 
 #ifdef CONFIG_FSL_SERDES
-	immap_t *immr = (immap_t *)CFG_IMMR;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	u32 spridr = in_be32(&immr->sysconf.spridr);
 
 	/* we check only part num, and don't look for CPU revisions */
@@ -77,7 +77,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
@@ -104,43 +104,43 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
-#if (CFG_DDR_SIZE != 512)
+#if (CONFIG_SYS_DDR_SIZE != 512)
 #warning Currenly any ddr size other than 512 is not supported
 #endif
-	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 	udelay(50000);
 
-	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 	udelay(1000);
 
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 	udelay(1000);
 
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	__asm__ __volatile__("sync");
 	udelay(1000);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 	udelay(2000);
-	return CFG_DDR_SIZE;
+	return CONFIG_SYS_DDR_SIZE;
 }
-#endif /*!CFG_SPD_EEPROM */
+#endif /*!CONFIG_SYS_SPD_EEPROM */
 
 int checkboard(void)
 {
diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c
index ab90979..24cc130 100644
--- a/board/freescale/mpc837xemds/pci.c
+++ b/board/freescale/mpc837xemds/pci.c
@@ -21,28 +21,28 @@
 #if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI_MEM_BASE,
-		phys_start: CFG_PCI_MEM_PHYS,
-		size: CFG_PCI_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI_MMIO_BASE,
-		phys_start: CFG_PCI_MMIO_PHYS,
-		size: CFG_PCI_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI_IO_BASE,
-		phys_start: CFG_PCI_IO_PHYS,
-		size: CFG_PCI_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
@@ -52,10 +52,10 @@
 	udelay(2000);
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	udelay(2000);
diff --git a/board/freescale/mpc837xerdb/mpc837xerdb.c b/board/freescale/mpc837xerdb/mpc837xerdb.c
index e547b51..18a21a1 100644
--- a/board/freescale/mpc837xerdb/mpc837xerdb.c
+++ b/board/freescale/mpc837xerdb/mpc837xerdb.c
@@ -20,17 +20,17 @@
 #include <spd_sdram.h>
 #include <vsc7385.h>
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("Testing DRAM from 0x%08x to 0x%08x\n",
-	       CFG_MEMTEST_START,
-	       CFG_MEMTEST_END);
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
 
 	printf("DRAM test phase 1:\n");
 	for (p = pstart; p < pend; p++)
@@ -66,7 +66,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	immap_t *im = (immap_t *) CFG_IMMR;
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
@@ -92,40 +92,40 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	immap_t *im = (immap_t *) CFG_IMMR;
-	u32 msize = CFG_DDR_SIZE * 1024 * 1024;
+	immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
+	u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
 	u32 msize_log2 = __ilog2(msize);
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
 
-	im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
+	im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
 	udelay(50000);
 
-	im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
 	udelay(1000);
 
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
 	udelay(1000);
 
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_mode2 = CFG_DDR_MODE2;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	sync();
 	udelay(1000);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 	udelay(2000);
-	return CFG_DDR_SIZE;
+	return CONFIG_SYS_DDR_SIZE;
 }
-#endif	/*!CFG_SPD_EEPROM */
+#endif	/*!CONFIG_SYS_SPD_EEPROM */
 
 int checkboard(void)
 {
@@ -136,7 +136,7 @@
 int board_early_init_f(void)
 {
 #ifdef CONFIG_FSL_SERDES
-	immap_t *immr = (immap_t *)CFG_IMMR;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	u32 spridr = in_be32(&immr->sysconf.spridr);
 
 	/* we check only part num, and don't look for CPU revisions */
diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c
index 26e7320..8bb31fc 100644
--- a/board/freescale/mpc837xerdb/pci.c
+++ b/board/freescale/mpc837xerdb/pci.c
@@ -17,28 +17,28 @@
 #if defined(CONFIG_PCI)
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI_MEM_BASE,
-		phys_start: CFG_PCI_MEM_PHYS,
-		size: CFG_PCI_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI_MEM_PHYS,
+		size: CONFIG_SYS_PCI_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI_MMIO_BASE,
-		phys_start: CFG_PCI_MMIO_PHYS,
-		size: CFG_PCI_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
+		size: CONFIG_SYS_PCI_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI_IO_BASE,
-		phys_start: CFG_PCI_IO_PHYS,
-		size: CFG_PCI_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI_IO_BASE,
+		phys_start: CONFIG_SYS_PCI_IO_PHYS,
+		size: CONFIG_SYS_PCI_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
 
 void pci_init_board(void)
 {
-	volatile immap_t *immr = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
 	volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
 	struct pci_region *reg[] = { pci_regions };
@@ -48,10 +48,10 @@
 	udelay(2000);
 
 	/* Configure PCI Local Access Windows */
-	pci_law[0].bar = CFG_PCI_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
 
-	pci_law[1].bar = CFG_PCI_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	mpc83xx_pci_init(1, reg, 0);
diff --git a/board/freescale/mpc8536ds/law.c b/board/freescale/mpc8536ds/law.c
index cdf5215..8013d41 100644
--- a/board/freescale/mpc8536ds/law.c
+++ b/board/freescale/mpc8536ds/law.c
@@ -28,15 +28,15 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_128M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 };
 
diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c
index 3066b24..f634e17 100644
--- a/board/freescale/mpc8536ds/mpc8536ds.c
+++ b/board/freescale/mpc8536ds/mpc8536ds.c
@@ -86,34 +86,34 @@
 
 phys_size_t fixed_sdram (void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 	uint d_init;
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 
-	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE_1;
-	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
-	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
-	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 
 #if defined (CONFIG_DDR_ECC)
-	ddr->err_int_en = CFG_DDR_ERR_INT_EN;
-	ddr->err_disable = CFG_DDR_ERR_DIS;
-	ddr->err_sbe = CFG_DDR_SBE;
+	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 #endif
 	asm("sync;isync");
 
 	udelay(500);
 
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	d_init = 1;
@@ -156,7 +156,7 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint sdrs2_io_sel =
 		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
@@ -176,7 +176,7 @@
 
 #ifdef CONFIG_PCIE3
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie3_hose;
 	int pcie_ep = (host_agent == 1);
@@ -194,23 +194,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE3_MEM_BASE,
-			       CFG_PCIE3_MEM_PHYS,
-			       CFG_PCIE3_MEM_SIZE,
+			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_PHYS,
+			       CONFIG_SYS_PCIE3_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE3_IO_BASE,
-			       CFG_PCIE3_IO_PHYS,
-			       CFG_PCIE3_IO_SIZE,
+			       CONFIG_SYS_PCIE3_IO_BASE,
+			       CONFIG_SYS_PCIE3_IO_PHYS,
+			       CONFIG_SYS_PCIE3_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -234,7 +234,7 @@
 
 #ifdef CONFIG_PCIE1
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
@@ -253,32 +253,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE1_MEM_BASE,
-			       CFG_PCIE1_MEM_PHYS,
-			       CFG_PCIE1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE1_IO_BASE,
-			       CFG_PCIE1_IO_PHYS,
-			       CFG_PCIE1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE1_MEM_BASE2,
-			       CFG_PCIE1_MEM_PHYS2,
-			       CFG_PCIE1_MEM_SIZE2,
+			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_PHYS2,
+			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -303,7 +303,7 @@
 
 #ifdef CONFIG_PCIE2
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie2_hose;
 	int pcie_ep = (host_agent == 3);
@@ -321,32 +321,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE2_MEM_BASE,
-			       CFG_PCIE2_MEM_PHYS,
-			       CFG_PCIE2_MEM_SIZE,
+			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_PHYS,
+			       CONFIG_SYS_PCIE2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE2_IO_BASE,
-			       CFG_PCIE2_IO_PHYS,
-			       CFG_PCIE2_IO_SIZE,
+			       CONFIG_SYS_PCIE2_IO_BASE,
+			       CONFIG_SYS_PCIE2_IO_PHYS,
+			       CONFIG_SYS_PCIE2_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE2_MEM_BASE2,
-			       CFG_PCIE2_MEM_PHYS2,
-			       CFG_PCIE2_MEM_SIZE2,
+			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_PHYS2,
+			       CONFIG_SYS_PCIE2_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -370,7 +370,7 @@
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -394,31 +394,31 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
-#ifdef CFG_PCI1_MEM_BASE2
+#ifdef CONFIG_SYS_PCI1_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCI1_MEM_BASE2,
-			       CFG_PCI1_MEM_PHYS2,
-			       CFG_PCI1_MEM_SIZE2,
+			       CONFIG_SYS_PCI1_MEM_BASE2,
+			       CONFIG_SYS_PCI1_MEM_PHYS2,
+			       CONFIG_SYS_PCI1_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -442,7 +442,7 @@
 int board_early_init_r(void)
 {
 	unsigned int i;
-	const unsigned int flashbase = CFG_FLASH_BASE;
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = 1;
 
 	/*
@@ -610,7 +610,7 @@
 
 int is_sata_supported(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint sdrs2_io_sel =
 		(gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
diff --git a/board/freescale/mpc8536ds/tlb.c b/board/freescale/mpc8536ds/tlb.c
index 28a9fa8..7ccc150 100644
--- a/board/freescale/mpc8536ds/tlb.c
+++ b/board/freescale/mpc8536ds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -47,23 +47,23 @@
 
 	/* TLB 1 */
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_1M, 1),
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CFG_PCI1_IO_PHYS, CFG_PCI1_IO_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256K, 1),
 };
diff --git a/board/freescale/mpc8540ads/law.c b/board/freescale/mpc8540ads/law.c
index 3b8bd05..7dd8f29 100644
--- a/board/freescale/mpc8540ads/law.c
+++ b/board/freescale/mpc8540ads/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index 005e4d9..7dccd37 100644
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -71,7 +71,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -116,8 +116,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -137,10 +137,10 @@
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
 	} else {
 		/*
@@ -155,7 +155,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 		udelay(200);
 
 		/*
@@ -176,52 +176,52 @@
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
-	lbc->br2 = CFG_BR2_PRELIM;
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -234,15 +234,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -251,14 +251,14 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
   #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c
index 4fe2862..2ec3ccc 100644
--- a/board/freescale/mpc8540ads/tlb.c
+++ b/board/freescale/mpc8540ads/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -87,7 +87,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -95,7 +95,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -103,7 +103,7 @@
 	 * TLB 7:	16K	Non-cacheable, guarded
 	 * 0xf8000000	16K	BCSR registers
 	 */
-	SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_16K, 1),
 
@@ -117,11 +117,11 @@
 	 * Likely it needs to be increased by two for these entries.
 	 */
 #error("Update the number of table entries in tlb1_entry")
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 8, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_64M, 1),
 #endif
diff --git a/board/freescale/mpc8541cds/law.c b/board/freescale/mpc8541cds/law.c
index fbf2bdc..8e3de22 100644
--- a/board/freescale/mpc8541cds/law.c
+++ b/board/freescale/mpc8541cds/law.c
@@ -47,12 +47,12 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c
index de3a791..7c35c35 100644
--- a/board/freescale/mpc8541cds/mpc8541cds.c
+++ b/board/freescale/mpc8541cds/mpc8541cds.c
@@ -200,7 +200,7 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -258,7 +258,7 @@
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -290,8 +290,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -337,56 +337,56 @@
 void
 sdram_init(void)
 {
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
 
 	puts("    SDRAM: ");
 
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 	asm("msync");
 
-	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 	asm("msync");
 
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * Determine which address lines to use baed on CPU board rev.
 	 */
 	cpu_board_rev = get_cpu_board_revision();
-	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 	} else {
 		/*
 		 * Assume something unable to identify itself is
 		 * really old, and likely has lines 16/17 mapped.
 		 */
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 	}
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -396,7 +396,7 @@
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -406,7 +406,7 @@
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -415,7 +415,7 @@
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c
index c5434a0..bf957c0 100644
--- a/board/freescale/mpc8541cds/tlb.c
+++ b/board/freescale/mpc8541cds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xa0000000	256M	PCI2 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	PCI2 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,7 +88,7 @@
 	 * 0xe200_0000	16M	PCI1 IO
 	 * 0xe300_0000	16M	PCI2 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -96,7 +96,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
diff --git a/board/freescale/mpc8544ds/law.c b/board/freescale/mpc8544ds/law.c
index 54cf36b..317ba26 100644
--- a/board/freescale/mpc8544ds/law.c
+++ b/board/freescale/mpc8544ds/law.c
@@ -28,15 +28,15 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_NONCACHE_BASE, LAWAR_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
 	/* contains both PCIE3 MEM & IO space */
-	SET_LAW(CFG_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_4M, LAW_TRGT_IF_PCIE_3),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c
index eaf6fa3..826180c 100644
--- a/board/freescale/mpc8544ds/mpc8544ds.c
+++ b/board/freescale/mpc8544ds/mpc8544ds.c
@@ -44,9 +44,9 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	if ((uint)&gur->porpllsr != 0xe00e0000) {
 		printf("immap size error %lx\n",(ulong)&gur->porpllsr);
@@ -108,7 +108,7 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -125,7 +125,7 @@
 
 #ifdef CONFIG_PCIE3
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie3_hose;
 	int pcie_ep = (host_agent == 1);
@@ -143,32 +143,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE3_MEM_BASE,
-			       CFG_PCIE3_MEM_PHYS,
-			       CFG_PCIE3_MEM_SIZE,
+			       CONFIG_SYS_PCIE3_MEM_BASE,
+			       CONFIG_SYS_PCIE3_MEM_PHYS,
+			       CONFIG_SYS_PCIE3_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE3_IO_BASE,
-			       CFG_PCIE3_IO_PHYS,
-			       CFG_PCIE3_IO_SIZE,
+			       CONFIG_SYS_PCIE3_IO_BASE,
+			       CONFIG_SYS_PCIE3_IO_PHYS,
+			       CONFIG_SYS_PCIE3_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE3_MEM_BASE2,
-			       CFG_PCIE3_MEM_PHYS2,
-			       CFG_PCIE3_MEM_SIZE2,
+			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_PHYS2,
+			       CONFIG_SYS_PCIE3_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -185,7 +185,7 @@
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
-		in_be32((u32 *)CFG_PCIE3_MEM_BASE);
+		in_be32((u32 *)CONFIG_SYS_PCIE3_MEM_BASE);
 	} else {
 		printf ("    PCIE3: disabled\n");
 	}
@@ -197,7 +197,7 @@
 
 #ifdef CONFIG_PCIE1
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep = (host_agent == 5);
@@ -215,32 +215,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE1_MEM_BASE,
-			       CFG_PCIE1_MEM_PHYS,
-			       CFG_PCIE1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE1_IO_BASE,
-			       CFG_PCIE1_IO_PHYS,
-			       CFG_PCIE1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE1_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE1_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE1_MEM_BASE2,
-			       CFG_PCIE1_MEM_PHYS2,
-			       CFG_PCIE1_MEM_SIZE2,
+			       CONFIG_SYS_PCIE1_MEM_BASE2,
+			       CONFIG_SYS_PCIE1_MEM_PHYS2,
+			       CONFIG_SYS_PCIE1_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -265,7 +265,7 @@
 
 #ifdef CONFIG_PCIE2
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie2_hose;
 	int pcie_ep = (host_agent == 3);
@@ -283,32 +283,32 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE2_MEM_BASE,
-			       CFG_PCIE2_MEM_PHYS,
-			       CFG_PCIE2_MEM_SIZE,
+			       CONFIG_SYS_PCIE2_MEM_BASE,
+			       CONFIG_SYS_PCIE2_MEM_PHYS,
+			       CONFIG_SYS_PCIE2_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE2_IO_BASE,
-			       CFG_PCIE2_IO_PHYS,
-			       CFG_PCIE2_IO_SIZE,
+			       CONFIG_SYS_PCIE2_IO_BASE,
+			       CONFIG_SYS_PCIE2_IO_PHYS,
+			       CONFIG_SYS_PCIE2_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
-#ifdef CFG_PCIE2_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE2_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE2_MEM_BASE2,
-			       CFG_PCIE2_MEM_PHYS2,
-			       CFG_PCIE2_MEM_SIZE2,
+			       CONFIG_SYS_PCIE2_MEM_BASE2,
+			       CONFIG_SYS_PCIE2_MEM_PHYS2,
+			       CONFIG_SYS_PCIE2_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -332,7 +332,7 @@
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -356,31 +356,31 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
-#ifdef CFG_PCIE3_MEM_BASE2
+#ifdef CONFIG_SYS_PCIE3_MEM_BASE2
 		/* outbound memory */
 		pci_set_region(hose->regions + 3,
-			       CFG_PCIE3_MEM_BASE2,
-			       CFG_PCIE3_MEM_PHYS2,
-			       CFG_PCIE3_MEM_SIZE2,
+			       CONFIG_SYS_PCIE3_MEM_BASE2,
+			       CONFIG_SYS_PCIE3_MEM_PHYS2,
+			       CONFIG_SYS_PCIE3_MEM_SIZE2,
 			       PCI_REGION_MEM);
 		hose->region_count++;
 #endif
@@ -470,7 +470,7 @@
 {
 #ifdef CONFIG_TSEC_ENET
 	struct tsec_info_struct tsec_info[2];
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	int num = 0;
 
diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c
index 40e0499..c7442b2 100644
--- a/board/freescale/mpc8544ds/tlb.c
+++ b/board/freescale/mpc8544ds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 	/*
@@ -45,28 +45,28 @@
 	 * 0xfc000000	64M	Covers FLASH at 0xFE800000 and 0xFF800000
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 	/*
 	 * TLB 1:	1G	Non-cacheable, guarded
 	 * 0x80000000	1G	PCIE  8,9,a,b
 	 */
-	SET_TLB_ENTRY(1, CFG_PCIE_PHYS, CFG_PCIE_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_PHYS, CONFIG_SYS_PCIE_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI_PHYS + 0x10000000, CFG_PCI_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -75,7 +75,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe100_0000	255M	PCI IO range
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
@@ -83,7 +83,7 @@
 	 * TLB 5:	64M	Non-cacheable, guarded
 	 * 0xf8000000	64M	PIXIS 0xF8000000 - 0xFBFFFFFF
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 };
diff --git a/board/freescale/mpc8548cds/law.c b/board/freescale/mpc8548cds/law.c
index 34b9d1c..98748aa 100644
--- a/board/freescale/mpc8548cds/law.c
+++ b/board/freescale/mpc8548cds/law.c
@@ -51,22 +51,22 @@
  */
 
 struct law_entry law_table[] = {
-#ifdef CFG_PCI1_MEM_PHYS
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+#ifdef CONFIG_SYS_PCI1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
 #endif
-#ifdef CFG_PCI2_MEM_PHYS
-	SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+#ifdef CONFIG_SYS_PCI2_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 #endif
-#ifdef CFG_PCIE1_MEM_PHYS
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+#ifdef CONFIG_SYS_PCIE1_MEM_PHYS
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
 #endif
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-#ifdef CFG_RIO_MEM_PHYS
-	SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 #endif
 };
 
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c
index 84d3850..875628d 100644
--- a/board/freescale/mpc8548cds/mpc8548cds.c
+++ b/board/freescale/mpc8548cds/mpc8548cds.c
@@ -49,8 +49,8 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -106,7 +106,7 @@
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -140,8 +140,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -174,46 +174,46 @@
 void
 sdram_init(void)
 {
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
 
 	puts("    SDRAM: ");
 
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 	asm("msync");
 
-	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 	asm("msync");
 
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
 	cpu_board_rev = get_cpu_board_revision();
-	lsdmr_common = CFG_LBC_LSDMR_COMMON;
-	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -223,7 +223,7 @@
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -233,7 +233,7 @@
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -242,7 +242,7 @@
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -290,14 +290,14 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 	struct pci_config_table *table;
@@ -323,24 +323,24 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
 
@@ -392,7 +392,7 @@
 
 #ifdef CONFIG_PCIE1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -412,23 +412,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE1_MEM_BASE,
-			       CFG_PCIE1_MEM_PHYS,
-			       CFG_PCIE1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE1_IO_BASE,
-			       CFG_PCIE1_IO_PHYS,
-			       CFG_PCIE1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c
index ab99af7..eab212a 100644
--- a/board/freescale/mpc8548cds/tlb.c
+++ b/board/freescale/mpc8548cds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_BOOT_BLOCK, CFG_BOOT_BLOCK,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,22 +54,22 @@
 	 * TLB 1:	1G	Non-cacheable, guarded
 	 * 0x80000000	1G	PCI1/PCIE  8,9,a,b
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI_PHYS, CFG_PCI_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_PHYS, CONFIG_SYS_PCI_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1G, 1),
 
-#ifdef CFG_RIO_MEM_PHYS
+#ifdef CONFIG_SYS_RIO_MEM_PHYS
 	/*
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/*
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 #endif
@@ -80,7 +80,7 @@
 	 * 0xe210_0000	1M	PCI2 IO
 	 * 0xe300_0000	1M	PCIe IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -88,7 +88,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_CACHE_BASE, CFG_LBC_CACHE_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_CACHE_BASE, CONFIG_SYS_LBC_CACHE_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -96,7 +96,7 @@
 	 * TLB 7:	64M	Non-cacheable, guarded
 	 * 0xf8000000	64M	CADMUS registers, relocated L2SRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_NONCACHE_BASE, CFG_LBC_NONCACHE_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_64M, 1),
 };
diff --git a/board/freescale/mpc8555cds/law.c b/board/freescale/mpc8555cds/law.c
index fbf2bdc..8e3de22 100644
--- a/board/freescale/mpc8555cds/law.c
+++ b/board/freescale/mpc8555cds/law.c
@@ -47,12 +47,12 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_2),
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c
index 826056a..4cd25b6 100644
--- a/board/freescale/mpc8555cds/mpc8555cds.c
+++ b/board/freescale/mpc8555cds/mpc8555cds.c
@@ -198,7 +198,7 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* PCI slot in USER bits CSR[6:7] by convention. */
 	uint pci_slot = get_pci_slot ();
@@ -256,7 +256,7 @@
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -290,8 +290,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -337,55 +337,55 @@
 void
 sdram_init(void)
 {
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint cpu_board_rev;
 	uint lsdmr_common;
 
 	puts("    SDRAM: ");
 
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 	asm("msync");
 
-	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 	asm("msync");
 
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * Determine which address lines to use baed on CPU board rev.
 	 */
 	cpu_board_rev = get_cpu_board_revision();
-	lsdmr_common = CFG_LBC_LSDMR_COMMON;
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
 	if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_0) {
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 	} else if (cpu_board_rev == MPC85XX_CPU_BOARD_REV_1_1) {
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 	} else {
 		/*
 		 * Assume something unable to identify itself is
 		 * really old, and likely has lines 16/17 mapped.
 		 */
-		lsdmr_common |= CFG_LBC_LSDMR_BSMA1617;
+		lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1617;
 	}
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -395,7 +395,7 @@
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -405,7 +405,7 @@
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -414,7 +414,7 @@
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c
index c5434a0..bf957c0 100644
--- a/board/freescale/mpc8555cds/tlb.c
+++ b/board/freescale/mpc8555cds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xa0000000	256M	PCI2 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	PCI2 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,7 +88,7 @@
 	 * 0xe200_0000	16M	PCI1 IO
 	 * 0xe300_0000	16M	PCI2 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -96,7 +96,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
diff --git a/board/freescale/mpc8560ads/law.c b/board/freescale/mpc8560ads/law.c
index 3b8bd05..7dd8f29 100644
--- a/board/freescale/mpc8560ads/law.c
+++ b/board/freescale/mpc8560ads/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 851fc57..4fe1d85 100644
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -217,7 +217,7 @@
 void reset_phy (void)
 {
 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
-	volatile bcsr_t *bcsr = (bcsr_t *) CFG_BCSR;
+	volatile bcsr_t *bcsr = (bcsr_t *) CONFIG_SYS_BCSR;
 #endif
 	/* reset Giga bit Ethernet port if needed here */
 
@@ -275,7 +275,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	    uint temp_ddrdll = 0;
 
 	    /*
@@ -320,8 +320,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -341,10 +341,10 @@
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
 	} else {
 		/*
@@ -359,7 +359,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
 		udelay(200);
 
 		/*
@@ -380,52 +380,52 @@
 void
 sdram_init(void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("    SDRAM: ");
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
-	lbc->br2 = CFG_BR2_PRELIM;
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 	asm("sync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -438,15 +438,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -455,14 +455,14 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
   #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c
index 4fe2862..2ec3ccc 100644
--- a/board/freescale/mpc8560ads/tlb.c
+++ b/board/freescale/mpc8560ads/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -87,7 +87,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -95,7 +95,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -103,7 +103,7 @@
 	 * TLB 7:	16K	Non-cacheable, guarded
 	 * 0xf8000000	16K	BCSR registers
 	 */
-	SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_16K, 1),
 
@@ -117,11 +117,11 @@
 	 * Likely it needs to be increased by two for these entries.
 	 */
 #error("Update the number of table entries in tlb1_entry")
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 8, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_64M, 1),
 #endif
diff --git a/board/freescale/mpc8568mds/bcsr.c b/board/freescale/mpc8568mds/bcsr.c
index 791a50f..30676e1 100644
--- a/board/freescale/mpc8568mds/bcsr.c
+++ b/board/freescale/mpc8568mds/bcsr.c
@@ -27,9 +27,9 @@
 
 void enable_8568mds_duart()
 {
-	volatile uint* duart_mux	= (uint *)(CFG_CCSRBAR + 0xe0060);
-	volatile uint* devices		= (uint *)(CFG_CCSRBAR + 0xe0070);
-	volatile u8 *bcsr		= (u8 *)(CFG_BCSR);
+	volatile uint* duart_mux	= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
+	volatile uint* devices		= (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
+	volatile u8 *bcsr		= (u8 *)(CONFIG_SYS_BCSR);
 
 	*duart_mux = 0x80000000;	/* Set the mux to Duart on PMUXCR */
 	*devices  = 0;			/* Enable all peripheral devices */
@@ -38,21 +38,21 @@
 
 void enable_8568mds_flash_write()
 {
-	volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] |= 0x01;
 }
 
 void disable_8568mds_flash_write()
 {
-	volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[9] &= ~(0x01);
 }
 
 void enable_8568mds_qe_mdio()
 {
-	u8 *bcsr = (u8 *)(CFG_BCSR);
+	u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	bcsr[7] |= 0x01;
 }
@@ -60,7 +60,7 @@
 #if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
 void reset_8568mds_uccs(void)
 {
-	volatile u8 *bcsr = (u8 *)(CFG_BCSR);
+	volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
 
 	/* Turn off UCC1 & UCC2 */
 	out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
diff --git a/board/freescale/mpc8568mds/law.c b/board/freescale/mpc8568mds/law.c
index 3bc24c5..da7b6dc 100644
--- a/board/freescale/mpc8568mds/law.c
+++ b/board/freescale/mpc8568mds/law.c
@@ -50,13 +50,13 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_SRIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO),
 	/* LBC window - maps 256M.  That's SDRAM, BCSR, PIBs, and Flash */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c
index f9e35cc..eab1900 100644
--- a/board/freescale/mpc8568mds/mpc8568mds.c
+++ b/board/freescale/mpc8568mds/mpc8568mds.c
@@ -123,10 +123,10 @@
 	enable_8568mds_qe_mdio();
 #endif
 
-#ifdef CFG_I2C2_OFFSET
+#ifdef CONFIG_SYS_I2C2_OFFSET
 	/* Enable I2C2_SCL and I2C2_SDA */
 	volatile struct par_io *port_c;
-	port_c = (struct par_io*)(CFG_IMMR + 0xe0140);
+	port_c = (struct par_io*)(CONFIG_SYS_IMMR + 0xe0140);
 	port_c->cpdir2 |= 0x0f000000;
 	port_c->cppar2 &= ~0x0f000000;
 	port_c->cppar2 |= 0x0a000000;
@@ -158,7 +158,7 @@
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -192,8 +192,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -223,44 +223,44 @@
 void
 sdram_init(void)
 {
-#if defined(CFG_OR2_PRELIM) && defined(CFG_BR2_PRELIM)
+#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
 	puts("    SDRAM: ");
 
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or2 = CFG_OR2_PRELIM;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM;
 	asm("msync");
 
-	lbc->br2 = CFG_BR2_PRELIM;
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
 	asm("msync");
 
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * MPC8568 uses "new" 15-16 style addressing.
 	 */
-	lsdmr_common = CFG_LBC_LSDMR_COMMON;
-	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -270,7 +270,7 @@
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -280,7 +280,7 @@
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -289,7 +289,7 @@
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -371,7 +371,7 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 
@@ -379,7 +379,7 @@
 {
 	pib_init();
 
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -403,23 +403,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-				CFG_PCI1_MEM_BASE,
-				CFG_PCI1_MEM_PHYS,
-				CFG_PCI1_MEM_SIZE,
+				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_PHYS,
+				CONFIG_SYS_PCI1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-				CFG_PCI1_IO_BASE,
-				CFG_PCI1_IO_PHYS,
-				CFG_PCI1_IO_SIZE,
+				CONFIG_SYS_PCI1_IO_BASE,
+				CONFIG_SYS_PCI1_IO_PHYS,
+				CONFIG_SYS_PCI1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -440,7 +440,7 @@
 
 #ifdef CONFIG_PCIE1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -460,23 +460,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-				CFG_PCIE1_MEM_BASE,
-				CFG_PCIE1_MEM_PHYS,
-				CFG_PCIE1_MEM_SIZE,
+				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-				CFG_PCIE1_IO_BASE,
-				CFG_PCIE1_IO_PHYS,
-				CFG_PCIE1_IO_SIZE,
+				CONFIG_SYS_PCIE1_IO_BASE,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;
diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c
index 7565176..1077552 100644
--- a/board/freescale/mpc8568mds/tlb.c
+++ b/board/freescale/mpc8568mds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -47,7 +47,7 @@
 	 * 0xff000000	16M	FLASH (upper half)
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x1000000, CFG_FLASH_BASE + 0x1000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x1000000, CONFIG_SYS_FLASH_BASE + 0x1000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -55,7 +55,7 @@
 	 * TLBe 1:	16M	Non-cacheable, guarded
 	 * 0xfe000000	16M	FLASH (lower half)
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_16M, 1),
 
@@ -64,7 +64,7 @@
 	 * 0x80000000	512M	PCI1 MEM
 	 * 0xa0000000	512M	PCIe MEM
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_1G, 1),
 
@@ -74,7 +74,7 @@
 	 * 0xe200_0000	8M	PCI1 IO
 	 * 0xe280_0000	8M	PCIe IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_64M, 1),
 
@@ -82,7 +82,7 @@
 	 * TLBe 4:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
@@ -92,7 +92,7 @@
 	 * 0xf8008000	32K PIB (CS4)
 	 * 0xf8010000	32K PIB (CS5)
 	 */
-	SET_TLB_ENTRY(1, CFG_BCSR_BASE, CFG_BCSR_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256K, 1),
 };
diff --git a/board/freescale/mpc8572ds/law.c b/board/freescale/mpc8572ds/law.c
index d69b593..9f11902 100644
--- a/board/freescale/mpc8572ds/law.c
+++ b/board/freescale/mpc8572ds/law.c
@@ -28,13 +28,13 @@
 #include <asm/mmu.h>
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
-	SET_LAW(CFG_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE3_MEM_PHYS, LAWAR_SIZE_512M, LAW_TRGT_IF_PCIE_3),
+	SET_LAW(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_4K, LAW_TRGT_IF_LBC),
 };
 
diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c
index 70b548b..b6eb28e 100644
--- a/board/freescale/mpc8572ds/mpc8572ds.c
+++ b/board/freescale/mpc8572ds/mpc8572ds.c
@@ -83,34 +83,34 @@
 
 phys_size_t fixed_sdram (void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr= &immap->im_ddr;
 	uint d_init;
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
 
-	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE_1;
-	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
-	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
-	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 
 #if defined (CONFIG_DDR_ECC)
-	ddr->err_int_en = CFG_DDR_ERR_INT_EN;
-	ddr->err_disable = CFG_DDR_ERR_DIS;
-	ddr->err_sbe = CFG_DDR_SBE;
+	ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
+	ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
+	ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 #endif
 	asm("sync;isync");
 
 	udelay(500);
 
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 
 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 	d_init = 1;
@@ -148,7 +148,7 @@
 #ifdef CONFIG_PCI
 void pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
@@ -168,7 +168,7 @@
 
 #ifdef CONFIG_PCIE3
 	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
+		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 		extern void fsl_pci_init(struct pci_controller *hose);
 		struct pci_controller *hose = &pcie3_hose;
 		int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
@@ -188,23 +188,23 @@
 
 			/* inbound */
 			pci_set_region(hose->regions + 0,
-					CFG_PCI_MEMORY_BUS,
-					CFG_PCI_MEMORY_PHYS,
-					CFG_PCI_MEMORY_SIZE,
+					CONFIG_SYS_PCI_MEMORY_BUS,
+					CONFIG_SYS_PCI_MEMORY_PHYS,
+					CONFIG_SYS_PCI_MEMORY_SIZE,
 					PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 			/* outbound memory */
 			pci_set_region(hose->regions + 1,
-					CFG_PCIE3_MEM_BASE,
-					CFG_PCIE3_MEM_PHYS,
-					CFG_PCIE3_MEM_SIZE,
+					CONFIG_SYS_PCIE3_MEM_BASE,
+					CONFIG_SYS_PCIE3_MEM_PHYS,
+					CONFIG_SYS_PCIE3_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(hose->regions + 2,
-					CFG_PCIE3_IO_BASE,
-					CFG_PCIE3_IO_PHYS,
-					CFG_PCIE3_IO_SIZE,
+					CONFIG_SYS_PCIE3_IO_BASE,
+					CONFIG_SYS_PCIE3_IO_PHYS,
+					CONFIG_SYS_PCIE3_IO_SIZE,
 					PCI_REGION_IO);
 
 			hose->region_count = 3;
@@ -225,7 +225,7 @@
 
 			pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 					PCI_BASE_ADDRESS_1, &temp32);
-			if (temp32 >= CFG_PCIE3_MEM_PHYS) {
+			if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
 				debug(" uli1572 read to %x\n", temp32);
 				in_be32((unsigned *)temp32);
 			}
@@ -240,7 +240,7 @@
 
 #ifdef CONFIG_PCIE2
 	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 		extern void fsl_pci_init(struct pci_controller *hose);
 		struct pci_controller *hose = &pcie2_hose;
 		int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
@@ -259,23 +259,23 @@
 
 			/* inbound */
 			pci_set_region(hose->regions + 0,
-					CFG_PCI_MEMORY_BUS,
-					CFG_PCI_MEMORY_PHYS,
-					CFG_PCI_MEMORY_SIZE,
+					CONFIG_SYS_PCI_MEMORY_BUS,
+					CONFIG_SYS_PCI_MEMORY_PHYS,
+					CONFIG_SYS_PCI_MEMORY_SIZE,
 					PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 			/* outbound memory */
 			pci_set_region(hose->regions + 1,
-					CFG_PCIE2_MEM_BASE,
-					CFG_PCIE2_MEM_PHYS,
-					CFG_PCIE2_MEM_SIZE,
+					CONFIG_SYS_PCIE2_MEM_BASE,
+					CONFIG_SYS_PCIE2_MEM_PHYS,
+					CONFIG_SYS_PCIE2_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(hose->regions + 2,
-					CFG_PCIE2_IO_BASE,
-					CFG_PCIE2_IO_PHYS,
-					CFG_PCIE2_IO_SIZE,
+					CONFIG_SYS_PCIE2_IO_BASE,
+					CONFIG_SYS_PCIE2_IO_PHYS,
+					CONFIG_SYS_PCIE2_IO_SIZE,
 					PCI_REGION_IO);
 
 			hose->region_count = 3;
@@ -297,7 +297,7 @@
 #endif
 #ifdef CONFIG_PCIE1
 	{
-		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+		volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 		extern void fsl_pci_init(struct pci_controller *hose);
 		struct pci_controller *hose = &pcie1_hose;
 		int pcie_ep = (host_agent == 1) || (host_agent == 4) ||
@@ -316,23 +316,23 @@
 
 			/* inbound */
 			pci_set_region(hose->regions + 0,
-					CFG_PCI_MEMORY_BUS,
-					CFG_PCI_MEMORY_PHYS,
-					CFG_PCI_MEMORY_SIZE,
+					CONFIG_SYS_PCI_MEMORY_BUS,
+					CONFIG_SYS_PCI_MEMORY_PHYS,
+					CONFIG_SYS_PCI_MEMORY_SIZE,
 					PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 			/* outbound memory */
 			pci_set_region(hose->regions + 1,
-					CFG_PCIE1_MEM_BASE,
-					CFG_PCIE1_MEM_PHYS,
-					CFG_PCIE1_MEM_SIZE,
+					CONFIG_SYS_PCIE1_MEM_BASE,
+					CONFIG_SYS_PCIE1_MEM_PHYS,
+					CONFIG_SYS_PCIE1_MEM_SIZE,
 					PCI_REGION_MEM);
 
 			/* outbound io */
 			pci_set_region(hose->regions + 2,
-					CFG_PCIE1_IO_BASE,
-					CFG_PCIE1_IO_PHYS,
-					CFG_PCIE1_IO_SIZE,
+					CONFIG_SYS_PCIE1_IO_BASE,
+					CONFIG_SYS_PCIE1_IO_PHYS,
+					CONFIG_SYS_PCIE1_IO_SIZE,
 					PCI_REGION_IO);
 
 			hose->region_count = 3;
@@ -360,7 +360,7 @@
 int board_early_init_r(void)
 {
 	unsigned int i;
-	const unsigned int flashbase = CFG_FLASH_BASE;
+	const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 	const u8 flash_esel = 2;
 
 	/*
diff --git a/board/freescale/mpc8572ds/tlb.c b/board/freescale/mpc8572ds/tlb.c
index 965356a..46d9e4a 100644
--- a/board/freescale/mpc8572ds/tlb.c
+++ b/board/freescale/mpc8572ds/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -52,32 +52,32 @@
 		      0, 0, BOOKE_PAGESZ_4K, 1),
 
 	/* *I*G* - CCSRBAR */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
 	/* W**G* - Flash/promjet, localbus */
 	/* This will be changed to *I*G* after relocation to RAM. */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS, CFG_PCIE3_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS, CONFIG_SYS_PCIE3_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_1G, 1),
 
 	/* *I*G* - PCI */
-	SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x40000000, CFG_PCIE3_MEM_PHYS + 0x40000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_PCIE3_MEM_PHYS + 0x50000000, CFG_PCIE3_MEM_PHYS + 0x50000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 
 	/* *I*G* - PCI I/O */
-	SET_TLB_ENTRY(1, CFG_PCIE3_IO_PHYS, CFG_PCIE3_IO_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_PHYS, CONFIG_SYS_PCIE3_IO_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_256K, 1),
 };
diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c
index 91b922b..2aad28a 100644
--- a/board/freescale/mpc8610hpcd/law.c
+++ b/board/freescale/mpc8610hpcd/law.c
@@ -29,16 +29,16 @@
 
 struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
-	SET_LAW(CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
-	SET_LAW(CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
+	SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2),
+	SET_LAW(CONFIG_SYS_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCI_1)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
index 130f7aa..5faeca1 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c
@@ -48,7 +48,7 @@
 /* called before any console output */
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 
 	gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
@@ -98,7 +98,7 @@
 
 int checkboard(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
 
 	printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
@@ -129,7 +129,7 @@
 	dram_size = fixed_sdram();
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	puts(" DDR: ");
 	return dram_size;
 #endif
@@ -153,8 +153,8 @@
 
 long int fixed_sdram(void)
 {
-#if !defined(CFG_RAMBOOT)
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 	uint d_init;
 
@@ -201,7 +201,7 @@
 
 	return 512 * 1024 * 1024;
 #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 
 #endif
@@ -242,7 +242,7 @@
 
 void pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
@@ -255,7 +255,7 @@
 
 #ifdef CONFIG_PCIE1
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_configured = (io_sel == 1) || (io_sel == 4);
@@ -271,23 +271,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			 CFG_PCI_MEMORY_BUS,
-			 CFG_PCI_MEMORY_PHYS,
-			 CFG_PCI_MEMORY_SIZE,
+			 CONFIG_SYS_PCI_MEMORY_BUS,
+			 CONFIG_SYS_PCI_MEMORY_PHYS,
+			 CONFIG_SYS_PCI_MEMORY_SIZE,
 			 PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			 CFG_PCIE1_MEM_BASE,
-			 CFG_PCIE1_MEM_PHYS,
-			 CFG_PCIE1_MEM_SIZE,
+			 CONFIG_SYS_PCIE1_MEM_BASE,
+			 CONFIG_SYS_PCIE1_MEM_PHYS,
+			 CONFIG_SYS_PCIE1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			 CFG_PCIE1_IO_BASE,
-			 CFG_PCIE1_IO_PHYS,
-			 CFG_PCIE1_IO_SIZE,
+			 CONFIG_SYS_PCIE1_IO_BASE,
+			 CONFIG_SYS_PCIE1_IO_PHYS,
+			 CONFIG_SYS_PCIE1_IO_SIZE,
 			 PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -312,7 +312,7 @@
 
 #ifdef CONFIG_PCIE2
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie2_hose;
 
@@ -330,23 +330,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			 CFG_PCI_MEMORY_BUS,
-			 CFG_PCI_MEMORY_PHYS,
-			 CFG_PCI_MEMORY_SIZE,
+			 CONFIG_SYS_PCI_MEMORY_BUS,
+			 CONFIG_SYS_PCI_MEMORY_PHYS,
+			 CONFIG_SYS_PCI_MEMORY_SIZE,
 			 PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			 CFG_PCIE2_MEM_BASE,
-			 CFG_PCIE2_MEM_PHYS,
-			 CFG_PCIE2_MEM_SIZE,
+			 CONFIG_SYS_PCIE2_MEM_BASE,
+			 CONFIG_SYS_PCIE2_MEM_PHYS,
+			 CONFIG_SYS_PCIE2_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			 CFG_PCIE2_IO_BASE,
-			 CFG_PCIE2_IO_PHYS,
-			 CFG_PCIE2_IO_SIZE,
+			 CONFIG_SYS_PCIE2_IO_BASE,
+			 CONFIG_SYS_PCIE2_IO_PHYS,
+			 CONFIG_SYS_PCIE2_IO_SIZE,
 			 PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -370,7 +370,7 @@
 
 #ifdef CONFIG_PCI1
  {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 	int pci_agent = (host_agent >= 4) && (host_agent <= 6);
@@ -383,23 +383,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			 CFG_PCI_MEMORY_BUS,
-			 CFG_PCI_MEMORY_PHYS,
-			 CFG_PCI_MEMORY_SIZE,
+			 CONFIG_SYS_PCI_MEMORY_BUS,
+			 CONFIG_SYS_PCI_MEMORY_PHYS,
+			 CONFIG_SYS_PCI_MEMORY_SIZE,
 			 PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			 CFG_PCI1_MEM_BASE,
-			 CFG_PCI1_MEM_PHYS,
-			 CFG_PCI1_MEM_SIZE,
+			 CONFIG_SYS_PCI1_MEM_BASE,
+			 CONFIG_SYS_PCI1_MEM_PHYS,
+			 CONFIG_SYS_PCI1_MEM_SIZE,
 			 PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			 CFG_PCI1_IO_BASE,
-			 CFG_PCI1_IO_PHYS,
-			 CFG_PCI1_IO_SIZE,
+			 CONFIG_SYS_PCI1_IO_BASE,
+			 CONFIG_SYS_PCI1_IO_PHYS,
+			 CONFIG_SYS_PCI1_IO_SIZE,
 			 PCI_REGION_IO);
 
 		hose->region_count = 3;
diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
index 4db941c..cd25d4a 100644
--- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
+++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c
@@ -43,7 +43,7 @@
 
 void diu_set_pixel_clock(unsigned int pixclock)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	volatile unsigned int *guts_clkdvdr = &gur->clkdvdr;
 	unsigned long speed_ccb, temp, pixval;
@@ -137,7 +137,7 @@
 }
 
 U_BOOT_CMD(
-	diufb, CFG_MAXARGS, 1, mpc8610diu_init_show_bmp,
+	diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp,
 	"diufb init | addr - Init or Display BMP file\n",
 	"init\n    - initialize DIU\n"
 	"addr\n    - display bmp at address 'addr'\n"
diff --git a/board/freescale/mpc8641hpcn/law.c b/board/freescale/mpc8641hpcn/law.c
index 2d6c3c1..182b4c5 100644
--- a/board/freescale/mpc8641hpcn/law.c
+++ b/board/freescale/mpc8641hpcn/law.c
@@ -47,18 +47,18 @@
 
 struct law_entry law_table[] = {
 #if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
 #endif
-	SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
-	SET_LAW((CFG_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW((CONFIG_SYS_FLASH_BASE & 0xfe000000), LAW_SIZE_32M, LAW_TRGT_IF_LBC),
 #if !defined(CONFIG_SPD_EEPROM)
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
 #endif
-	SET_LAW(CFG_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+	SET_LAW(CONFIG_SYS_RIO_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/mpc8641hpcn/mpc8641hpcn.c b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
index 97f7f49..fcaaacb 100644
--- a/board/freescale/mpc8641hpcn/mpc8641hpcn.c
+++ b/board/freescale/mpc8641hpcn/mpc8641hpcn.c
@@ -65,7 +65,7 @@
 	dram_size = fixed_sdram();
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	puts("    DDR: ");
 	return dram_size;
 #endif
@@ -89,23 +89,23 @@
 long int
 fixed_sdram(void)
 {
-#if !defined(CFG_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
-	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
-	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
-	ddr->sdram_ocd_cntl = CFG_DDR_OCD_CTRL;
-	ddr->sdram_ocd_status = CFG_DDR_OCD_STATUS;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
+	ddr->sdram_ocd_cntl = CONFIG_SYS_DDR_OCD_CTRL;
+	ddr->sdram_ocd_status = CONFIG_SYS_DDR_OCD_STATUS;
 
 #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000008D;
@@ -117,16 +117,16 @@
 
 #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg_1 = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg_1 = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 #else
-	ddr->sdram_cfg_1 = CFG_DDR_CONTROL;
-	ddr->sdram_cfg_2 = CFG_DDR_CONTROL2;
+	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CONTROL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 #endif
 	asm("sync; isync");
 
 	udelay(500);
 #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
@@ -164,7 +164,7 @@
 
 void pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
@@ -172,7 +172,7 @@
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 #ifdef DEBUG
@@ -194,23 +194,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -228,8 +228,8 @@
 		 * Activate ULI1575 legacy chip by performing a fake
 		 * memory access.  Needed to make ULI RTC work.
 		 */
-		in_be32((unsigned *) ((char *)(CFG_PCI1_MEM_BASE
-				       + CFG_PCI1_MEM_SIZE - 0x1000000)));
+		in_be32((unsigned *) ((char *)(CONFIG_SYS_PCI1_MEM_BASE
+				       + CONFIG_SYS_PCI1_MEM_SIZE - 0x1000000)));
 
 	} else {
 		puts("PCI-EXPRESS 1: Disabled\n");
@@ -241,30 +241,30 @@
 
 #ifdef CONFIG_PCI2
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci2_hose;
 
 
 	/* inbound */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI_MEMORY_BUS,
-		       CFG_PCI_MEMORY_PHYS,
-		       CFG_PCI_MEMORY_SIZE,
+		       CONFIG_SYS_PCI_MEMORY_BUS,
+		       CONFIG_SYS_PCI_MEMORY_PHYS,
+		       CONFIG_SYS_PCI_MEMORY_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	/* outbound memory */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI2_MEM_BASE,
-		       CFG_PCI2_MEM_PHYS,
-		       CFG_PCI2_MEM_SIZE,
+		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_PHYS,
+		       CONFIG_SYS_PCI2_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* outbound io */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI2_IO_BASE,
-		       CFG_PCI2_IO_PHYS,
-		       CFG_PCI2_IO_SIZE,
+		       CONFIG_SYS_PCI2_IO_BASE,
+		       CONFIG_SYS_PCI2_IO_PHYS,
+		       CONFIG_SYS_PCI2_IO_SIZE,
 		       PCI_REGION_IO);
 
 	hose->region_count = 3;
diff --git a/board/funkwerk/vovpn-gw/flash.c b/board/funkwerk/vovpn-gw/flash.c
index 0308611..fd3b16e 100644
--- a/board/funkwerk/vovpn-gw/flash.c
+++ b/board/funkwerk/vovpn-gw/flash.c
@@ -27,7 +27,7 @@
 
 #include <common.h>
 
-flash_info_t				flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t				flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define FLASH_CMD_READ_ID		0x90
 #define FLASH_CMD_READ_STATUS		0x70
@@ -46,7 +46,7 @@
 
 #define FLASH_WRITE_BUFFER_SIZE		32
 
-#ifdef CFG_FLASH_16BIT
+#ifdef CONFIG_SYS_FLASH_16BIT
 #define FLASH_WORD_SIZE			unsigned short
 #define FLASH_ID_MASK			0xffff
 #define FLASH_CMD_ADDR_SHIFT		0
@@ -130,10 +130,10 @@
 	unsigned long	size;
 	int		i;
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
-	size = flash_get((volatile FLASH_WORD_SIZE *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get((volatile FLASH_WORD_SIZE *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH Size=0x%08lx\n", size);
 		return (0);
@@ -145,10 +145,10 @@
 		      flash_info[0].start[1] - 1,
 		      &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_FLASH,
-		      CFG_MONITOR_FLASH+CFG_MONITOR_LEN-1,
+		      CONFIG_SYS_MONITOR_FLASH,
+		      CONFIG_SYS_MONITOR_FLASH+CONFIG_SYS_MONITOR_LEN-1,
 		      &flash_info[0]);
 #endif
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -265,7 +265,7 @@
 		udelay (1000);
 
 		while (((status = *addr) & FLASH_STATUS_DONE) != FLASH_STATUS_DONE) {
-			if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf("Flash erase timeout at address %lx\n", info->start[sect]);
 				*addr = FLASH_CMD_SUSPEND_ERASE;
 				*addr = FLASH_CMD_RESET;
@@ -307,7 +307,7 @@
 			enable_interrupts();
 		}
 
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (-1);
 		}
 	}
@@ -337,7 +337,7 @@
 				break;
 			}
 		}
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = FLASH_CMD_RESET;
 			return (-1);
 		}
@@ -367,7 +367,7 @@
 	addr = (volatile FLASH_WORD_SIZE *)(info->start[0]);
 	dst = (volatile FLASH_WORD_SIZE *) udst;
 
-#ifdef CFG_FLASH_16BIT
+#ifdef CONFIG_SYS_FLASH_16BIT
 #error NYI
 #else
 	while (cnt > 0) {
@@ -435,7 +435,7 @@
 	/* wait for error or finish */
 	start = get_timer (0);
 	while(!(addr[0] & FLASH_STATUS_DONE)){
-		if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Flash protect timeout at address %lx\n",  info->start[sector]);
 			addr[0] = FLASH_CMD_RESET;
 			return (1);
diff --git a/board/funkwerk/vovpn-gw/vovpn-gw.c b/board/funkwerk/vovpn-gw/vovpn-gw.c
index 1c3f627..8c4abdd 100644
--- a/board/funkwerk/vovpn-gw/vovpn-gw.c
+++ b/board/funkwerk/vovpn-gw/vovpn-gw.c
@@ -189,7 +189,7 @@
 	unsigned short val;
 #endif
 
-	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
 
 	/* Reset the PHY */
 	iop->pdat &= 0xfff7ffff;	/* PA12 = |SWITCH_RESET */
@@ -198,12 +198,12 @@
 	iop->pdat |= 0x00080000;
 	for (i=0; i<100; i++) {
 		udelay(20000);
-		if (bb_miiphy_read("FCC1 ETHERNET", CFG_PHY_ADDR,2,&val ) == 0) {
+		if (bb_miiphy_read("FCC1 ETHERNET", CONFIG_SYS_PHY_ADDR,2,&val ) == 0) {
 			break;
 		}
 	}
 	/* initialize switch */
-	m88e6060_initialize( CFG_PHY_ADDR );
+	m88e6060_initialize( CONFIG_SYS_PHY_ADDR );
 #endif
 }
 
@@ -233,7 +233,7 @@
 	volatile unsigned char *dummy;
 	int i;
 
-	immap = (immap_t *) CFG_IMMR;
+	immap = (immap_t *) CONFIG_SYS_IMMR;
 	memctl = &immap->im_memctl;
 
 #if 0
@@ -272,7 +272,7 @@
 	unsigned char c;
 	int i;
 
-	immap = (immap_t *) CFG_IMMR;
+	immap = (immap_t *) CONFIG_SYS_IMMR;
 	memctl = &immap->im_memctl;
 
 
@@ -289,7 +289,7 @@
 	memctl->memc_mamr = 0x00044440;
 #endif
 	/* enable buffers (DSP, DPRAM) */
-	iop = ioport_addr((immap_t *)CFG_IMMR, 0);
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0);
 	iop->pdat &= 0xfffbffff;	/* PA13 = |EN_M_BCTL1 */
 
 	/* destroy DPRAM magic */
@@ -310,7 +310,7 @@
 {
 	volatile ioport_t *iop;
 
-	iop = ioport_addr((immap_t *)CFG_IMMR, 2);
+	iop = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 2);
 	iop->pdat |= 0x00002000;	/* PC18 = HW_RESET */
 	return 1;
 }
@@ -320,16 +320,16 @@
 
 phys_size_t initdram (int board_type)
 {
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	volatile immap_t *immap;
 	volatile memctl8260_t *memctl;
 	volatile uchar *ramaddr;
 	int i;
 	uchar c;
 
-	immap = (immap_t *) CFG_IMMR;
+	immap = (immap_t *) CONFIG_SYS_IMMR;
 	memctl = &immap->im_memctl;
-	ramaddr = (uchar *) CFG_SDRAM_BASE;
+	ramaddr = (uchar *) CONFIG_SYS_SDRAM_BASE;
 	c = 0xff;
 
 	immap->im_siu_conf.sc_ppc_acr  = 0x02;
@@ -338,30 +338,30 @@
 	immap->im_siu_conf.sc_tescr1   = 0x00000000;
 	immap->im_siu_conf.sc_tescr2   = 0x00000000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_SDRAM_BASE | CFG_BR1_PRELIM;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_BR1_PRELIM;
 
 	/* Precharge all banks */
-	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
 	*ramaddr = c;
 
 	/* CBR refresh */
-	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
 
 	/* Mode Register write */
-	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
 	*ramaddr = c;
 
 	/* Refresh enable */
-	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
 	*ramaddr = c;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
-	return (CFG_SDRAM_SIZE);
+	return (CONFIG_SYS_SDRAM_SIZE);
 }
 
 int checkboard (void)
diff --git a/board/g2000/g2000.c b/board/g2000/g2000.c
index 647f4b7..48fc643 100644
--- a/board/g2000/g2000.c
+++ b/board/g2000/g2000.c
@@ -33,7 +33,7 @@
 #define MEM_SDTR1_INIT_VAL      0x00854005
 #define SDRAM0_CFG_ENABLE       0x80000000
 
-#define CFG_SDRAM_SIZE          0x04000000      /* 64 MB */
+#define CONFIG_SYS_SDRAM_SIZE          0x04000000      /* 64 MB */
 
 int board_early_init_f (void)
 {
@@ -77,8 +77,8 @@
 	/*
 	 * Set NAND-FLASH GPIO signals to default
 	 */
-	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CFG_NAND_CLE | CFG_NAND_ALE));
-	out32(GPIO0_OR, in32(GPIO0_OR) | CFG_NAND_CE);
+	out32(GPIO0_OR, in32(GPIO0_OR) & ~(CONFIG_SYS_NAND_CLE | CONFIG_SYS_NAND_ALE));
+	out32(GPIO0_OR, in32(GPIO0_OR) | CONFIG_SYS_NAND_CE);
 #endif
 
 	return (0);
@@ -127,7 +127,7 @@
 	udelay(500);
 	mtsdram0( mem_mcopt1, MEM_MCOPT1_INIT_VAL|SDRAM0_CFG_ENABLE );
 
-	return (CFG_SDRAM_SIZE); /* CFG_SDRAM_SIZE is in G2000.h */
+	return (CONFIG_SYS_SDRAM_SIZE); /* CONFIG_SYS_SDRAM_SIZE is in G2000.h */
  }
 
 
@@ -151,11 +151,11 @@
 
 #if defined(CONFIG_CMD_NAND)
 #include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	nand_probe(CFG_NAND_BASE);
+	nand_probe(CONFIG_SYS_NAND_BASE);
 	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 		print_size(nand_dev_desc[0].totlen, "\n");
 	}
diff --git a/board/g2000/strataflash.c b/board/g2000/strataflash.c
index 8446e02..effe65a 100644
--- a/board/g2000/strataflash.c
+++ b/board/g2000/strataflash.c
@@ -101,7 +101,7 @@
 
 #define NUM_ERASE_REGIONS 4
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -116,7 +116,7 @@
 static ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
 static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 /*-----------------------------------------------------------------------
@@ -176,14 +176,14 @@
 	 *
 	 */
 
-	address = CFG_FLASH_BASE;
+	address = CONFIG_SYS_FLASH_BASE;
 	size = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		size += flash_info[i].size = flash_get_size(address, i);
-		address += CFG_FLASH_INCREMENT;
+		address += CONFIG_SYS_FLASH_INCREMENT;
 		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
 				flash_info[0].size, flash_info[i].size<<20);
@@ -192,14 +192,14 @@
 
 #if 0 /* test-only */
 	/* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
 #else
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-		       - CFG_MONITOR_LEN,
+		       - CONFIG_SYS_MONITOR_LEN,
 		       - 1, &flash_info[1]);
 #endif
 
@@ -273,7 +273,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		int k;
 		int size;
 		int erased;
@@ -353,7 +353,7 @@
 		wp = cp;
 	}
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while(cnt >= info->portwidth) {
 		i = info->buffer_size > cnt? cnt: info->buffer_size;
 		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
@@ -374,7 +374,7 @@
 		wp += info->portwidth;
 		cnt -= info->portwidth;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 	if (cnt == 0) {
 		return (0);
 	}
@@ -716,7 +716,7 @@
 	return flash_full_status_check(info, 0, info->write_tout, "write");
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* loop through the sectors from the highest address
  * when the passed address is greater or equal to the sector address
@@ -790,4 +790,4 @@
 	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/gaisler/gr_cpci_ax2000/u-boot.lds b/board/gaisler/gr_cpci_ax2000/u-boot.lds
index 3958670..a087631 100644
--- a/board/gaisler/gr_cpci_ax2000/u-boot.lds
+++ b/board/gaisler/gr_cpci_ax2000/u-boot.lds
@@ -61,7 +61,7 @@
 
 		*(.start)
 		cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
  * no global data accesses please.
diff --git a/board/gaisler/gr_ep2s60/u-boot.lds b/board/gaisler/gr_ep2s60/u-boot.lds
index 100350d..e461a36 100644
--- a/board/gaisler/gr_ep2s60/u-boot.lds
+++ b/board/gaisler/gr_ep2s60/u-boot.lds
@@ -61,7 +61,7 @@
 
 		*(.start)
 		cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
  * no global data accesses please.
diff --git a/board/gaisler/gr_xc3s_1500/u-boot.lds b/board/gaisler/gr_xc3s_1500/u-boot.lds
index 3848c68..ddd27d4 100644
--- a/board/gaisler/gr_xc3s_1500/u-boot.lds
+++ b/board/gaisler/gr_xc3s_1500/u-boot.lds
@@ -61,7 +61,7 @@
 
 		*(.start)
 		cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
  * no global data accesses please.
diff --git a/board/gaisler/grsim/u-boot.lds b/board/gaisler/grsim/u-boot.lds
index 1e8bb69..a9cc7ca 100644
--- a/board/gaisler/grsim/u-boot.lds
+++ b/board/gaisler/grsim/u-boot.lds
@@ -60,7 +60,7 @@
 
 		*(.start)
 		cpu/leon3/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
  * no global data accesses please.
diff --git a/board/gaisler/grsim_leon2/u-boot.lds b/board/gaisler/grsim_leon2/u-boot.lds
index 2a22082..b3462d4 100644
--- a/board/gaisler/grsim_leon2/u-boot.lds
+++ b/board/gaisler/grsim_leon2/u-boot.lds
@@ -60,7 +60,7 @@
 
 		*(.start)
 		cpu/leon2/start.o (.text)
-/* 8k is the same as the PROM offset from end of main memory, (CFG_PROM_SIZE) */
+/* 8k is the same as the PROM offset from end of main memory, (CONFIG_SYS_PROM_SIZE) */
 		. = ALIGN(8192);
 /* PROM CODE, Will be relocated to the end of memory,
  * no global data accesses please.
diff --git a/board/gcplus/flash.c b/board/gcplus/flash.c
index 48f33b2..8511582 100644
--- a/board/gcplus/flash.c
+++ b/board/gcplus/flash.c
@@ -29,7 +29,7 @@
 #include <common.h>
 #include <linux/byteorder/swab.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -67,7 +67,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -83,8 +83,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_FLASH_BASE,
-		      CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+		      CONFIG_SYS_FLASH_BASE,
+		      CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_ENV_ADDR,
@@ -207,10 +207,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf("** ERROR: sector count %d > max (%d) **\n",
-		       info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+		       info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -282,7 +282,7 @@
 			while (((status =
 				 *addr) & (FPW) 0x00800080) !=
 			       (FPW) 0x00800080) {
-				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -418,7 +418,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/gen860t/beeper.c b/board/gen860t/beeper.c
index b4c2c89..b472b91 100644
--- a/board/gen860t/beeper.c
+++ b/board/gen860t/beeper.c
@@ -43,7 +43,7 @@
  */
 void init_beeper (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_RST1 | TGCR_STP1;
 	immap->im_cpmtimer.cpmt_tmr1 = ((33 << TMR_PS_SHIFT) & TMR_PS_MSK)
@@ -62,7 +62,7 @@
 {
 #define FREQ_LIMIT	2500
 
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Compute timer ticks given desired frequency.  The timer is set up
@@ -79,7 +79,7 @@
  */
 void beeper_on (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr &= ~TGCR_STP1;
 }
@@ -89,7 +89,7 @@
  */
 void beeper_off (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	immap->im_cpmtimer.cpmt_tgcr |= TGCR_STP1;
 }
@@ -104,7 +104,7 @@
  */
 void set_beeper_volume (int steps)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	int i;
 
 	if (steps >= 0) {
diff --git a/board/gen860t/flash.c b/board/gen860t/flash.c
index a46e7e6..827d9e0 100644
--- a/board/gen860t/flash.c
+++ b/board/gen860t/flash.c
@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -41,15 +41,15 @@
  * Use buffered writes to flash by default - they are about 32x faster than
  * single byte writes.
  */
-#ifndef  CFG_GEN860T_FLASH_USE_WRITE_BUFFER
-#define CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#ifndef  CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
+#define CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
 #endif
 
 /*
  * Max time to wait (in mS) for flash device to allocate a write buffer.
  */
-#ifndef CFG_FLASH_ALLOC_BUFFER_TOUT
-#define CFG_FLASH_ALLOC_BUFFER_TOUT		100
+#ifndef CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT
+#define CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT		100
 #endif
 
 /*
@@ -94,7 +94,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -109,12 +109,12 @@
 unsigned long
 flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
-	for (i= 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i= 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -139,7 +139,7 @@
 	 * Remap FLASH according to real size
 	 */
 	memctl->memc_or0 |= (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 |= (CFG_FLASH_BASE & BR_BA_MSK);
+	memctl->memc_br0 |= (CONFIG_SYS_FLASH_BASE & BR_BA_MSK);
 
 	PRINTF("## After remap:\n"
 		   "  BR0: 0x%08x    OR0: 0x%08x\n", memctl->memc_br0, memctl->memc_or0);
@@ -147,17 +147,17 @@
 	/*
 	 * Re-do sizing to get full correct info
 	 */
-	size_b0 = flash_get_size ((vu_char *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((vu_char *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/*
 	 * Monitor protection is ON by default
 	 */
 	flash_protect(FLAG_PROTECT_SET,
-			  CFG_MONITOR_BASE,
-			  CFG_MONITOR_BASE + monitor_flash_len - 1,
+			  CONFIG_SYS_MONITOR_BASE,
+			  CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			  &flash_info[0]);
 #endif
 
@@ -307,10 +307,10 @@
 			return (NO_FLASH);
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-				info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+				info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 	return (info->size);
 }
@@ -385,7 +385,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & SCS_SR7) != SCS_SR7) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = SCS_BLOCK_ERASE_SUSPEND_CMD;
 					*addr = SCS_READ_CMD;
@@ -408,7 +408,7 @@
 }
 
 
-#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
 /*
  * Allocate a flash buffer, fill it with data and write it to the flash.
  * 0 - OK
@@ -451,10 +451,10 @@
 	 */
 	*block_addr_p = SCS_WRITE_BUF_CMD;
 	while ((*block_addr_p & SCS_XSR7) != SCS_XSR7) {
-		if (get_timer(time) >  CFG_FLASH_ALLOC_BUFFER_TOUT) {
+		if (get_timer(time) >  CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT) {
 			PRINTF("%s:%d: Buffer allocation timeout @ 0x%p (waited %d mS)\n",
 				   __FUNCTION__, __LINE__, block_addr_p,
-				   CFG_FLASH_ALLOC_BUFFER_TOUT);
+				   CONFIG_SYS_FLASH_ALLOC_BUFFER_TOUT);
 			return 1;
 		}
 		*block_addr_p = SCS_WRITE_BUF_CMD;
@@ -478,9 +478,9 @@
 #if 1
 	time = get_timer(0);
 	while ((*block_addr_p & SCS_SR7) != SCS_SR7) {
-		if (get_timer(time) >  CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(time) >  CONFIG_SYS_FLASH_WRITE_TOUT) {
 			PRINTF("%s:%d: Write timeout @ 0x%p (waited %d mS)\n",
-				   __FUNCTION__, __LINE__, block_addr_p, CFG_FLASH_WRITE_TOUT);
+				   __FUNCTION__, __LINE__, block_addr_p, CONFIG_SYS_FLASH_WRITE_TOUT);
 			return 1;
 		}
 	}
@@ -502,7 +502,7 @@
 write_buff(flash_info_t *info_p, uchar *src_p, ulong addr, ulong count)
 {
 	int rc = 0;
-#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
 #define FLASH_WRITE_BUF_SIZE	0x00000020	/* 32 bytes */
 	int i;
 	uint bufs;
@@ -520,7 +520,7 @@
 		return 4;
 	}
 
-#ifdef CFG_GEN860T_FLASH_USE_WRITE_BUFFER
+#ifdef CONFIG_SYS_GEN860T_FLASH_USE_WRITE_BUFFER
 	sp = src_p;
 	dp = (uchar *)addr;
 
@@ -632,7 +632,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & SCS_SR7) != SCS_SR7) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = SCS_READ_CMD;
 			return (1);
 		}
diff --git a/board/gen860t/fpga.c b/board/gen860t/fpga.c
index 1e6bdf1..29cad2e 100644
--- a/board/gen860t/fpga.c
+++ b/board/gen860t/fpga.c
@@ -161,7 +161,7 @@
  */
 void fpga_reset (int assert)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	PRINTF ("%s:%d: RESET ", __FUNCTION__, __LINE__);
 	if (assert) {
@@ -210,7 +210,7 @@
  */
 int fpga_pgm_fn (int assert, int flush, int cookie)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	PRINTF ("%s:%d: FPGA PROGRAM ", __FUNCTION__, __LINE__);
 
@@ -233,7 +233,7 @@
  */
 int fpga_init_fn (int cookie)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	PRINTF ("%s:%d: INIT check... ", __FUNCTION__, __LINE__);
 	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_INIT_BIT_NUM)) {
@@ -251,7 +251,7 @@
  */
 int fpga_done_fn (int cookie)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	PRINTF ("%s:%d: DONE check... ", __FUNCTION__, __LINE__);
 	if (immap->im_cpm.cp_pbdat & (0x80000000 >> FPGA_DONE_BIT_NUM)) {
diff --git a/board/gen860t/gen860t.c b/board/gen860t/gen860t.c
index 5c497b6..008f765 100644
--- a/board/gen860t/gen860t.c
+++ b/board/gen860t/gen860t.c
@@ -160,7 +160,7 @@
  */
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	upmconfig (UPMA,
@@ -171,14 +171,14 @@
 	/*
 	 * Setup MAMR register
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	/*
 	 * Map CS1* to SDRAM bank
 	 */
-	memctl->memc_or1 = CFG_OR1;
-	memctl->memc_br1 = CFG_BR1;
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
 
 	/*
 	 * Perform SDRAM initialization sequence:
@@ -235,7 +235,7 @@
  */
 int misc_init_r (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	/*
diff --git a/board/genietv/flash.c b/board/genietv/flash.c
index 7292c9c..5313ad8 100644
--- a/board/genietv/flash.c
+++ b/board/genietv/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -42,20 +42,20 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	    flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	/* Detect size */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* Setup offsets */
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -322,7 +322,7 @@
 
 	while ((addr[0] & 0xFF) != 0xFF)
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -454,7 +454,7 @@
 	    start = get_timer (0);
 	    while ((*cdest ^ *cdata) & 0x80)
 	    {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	    }
diff --git a/board/genietv/genietv.c b/board/genietv/genietv.c
index fc21169..0a015ea 100644
--- a/board/genietv/genietv.c
+++ b/board/genietv/genietv.c
@@ -29,7 +29,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-#define CFG_PA7		0x0100
+#define CONFIG_SYS_PA7		0x0100
 
 /* ------------------------------------------------------------------------- */
 
@@ -104,7 +104,7 @@
 #if 0
 static void PrintState (void)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &im->im_memctl;
 
 	printf ("\n0 - FLASH: B=%08x O=%08x", memctl->memc_br0,
@@ -120,18 +120,18 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &im->im_memctl;
 	long int size_b0, size_b1, size8;
 
 	/* Enable SDRAM */
 
 	/* Configuring PA7 for general purpouse output pin */
-	im->im_ioport.iop_papar &= ~CFG_PA7;	/* 0 = general purpouse */
-	im->im_ioport.iop_padir |= CFG_PA7;	/* 1 = output */
+	im->im_ioport.iop_papar &= ~CONFIG_SYS_PA7;	/* 0 = general purpouse */
+	im->im_ioport.iop_padir |= CONFIG_SYS_PA7;	/* 1 = output */
 
 	/* Enable SDRAM - PA7 = 1 */
-	im->im_ioport.iop_padat |= CFG_PA7;	/* value of PA7 */
+	im->im_ioport.iop_padat |= CONFIG_SYS_PA7;	/* value of PA7 */
 
 	/*
 	 * Preliminary prescaler for refresh (depends on number of
@@ -139,9 +139,9 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 
-	memctl->memc_mbmr = CFG_MBMR_8COL;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
 
 	upmconfig (UPMB, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
@@ -152,11 +152,11 @@
 	 * SDRAM size has been determined.
 	 */
 
-	memctl->memc_or1 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
 	memctl->memc_br1 =
 		((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
 
-	memctl->memc_or2 = 0xF0000000 | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or2 = 0xF0000000 | CONFIG_SYS_OR_TIMING_SDRAM;
 	memctl->memc_br2 =
 		((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V);
 
@@ -168,14 +168,14 @@
 	memctl->memc_mcr = 0x80804105;	/* SDRAM bank 1 */
 
 	/* Execute refresh 8 times */
-	memctl->memc_mbmr = (CFG_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
+	memctl->memc_mbmr = (CONFIG_SYS_MBMR_8COL & ~MBMR_TLFB_MSK) | MBMR_TLFB_8X;
 
 	memctl->memc_mcr = 0x80802130;	/* SDRAM bank 0 - execute twice */
 
 	memctl->memc_mcr = 0x80804130;	/* SDRAM bank 1 - execute twice */
 
 	/* Execute refresh 4 times */
-	memctl->memc_mbmr = CFG_MBMR_8COL;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;
 
 	/*
 	 * Check Bank 0 Memory Size for re-configuration
@@ -187,7 +187,7 @@
 	PrintState ();
 #endif
 /*    printf ("\nChecking bank1..."); */
-	size8 = dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE1_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	size_b0 = size8;
@@ -201,17 +201,17 @@
 	 * Final mapping: map bigger bank first
 	 */
 
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
 
 	if (size_b1 > 0) {
 		/*
 		 * Position Bank 1 immediately above Bank 0
 		 */
 		memctl->memc_or2 =
-			((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br2 =
-			((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
+			((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) +
 			(size_b0 & BR_BA_MSK);
 	} else {
 		/*
@@ -221,14 +221,14 @@
 		 */
 		memctl->memc_br2 = 0;
 		/* adjust refresh rate depending on SDRAM type, one bank */
-		memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 	}
 
 	/* If no memory detected, disable SDRAM */
 	if ((size_b0 + size_b1) == 0) {
 		printf ("disabling SDRAM!\n");
 		/* Disable SDRAM - PA7 = 1 */
-		im->im_ioport.iop_padat &= ~CFG_PA7;	/* value of PA7 */
+		im->im_ioport.iop_padat &= ~CONFIG_SYS_PA7;	/* value of PA7 */
 	}
 /*	else */
 /*    printf("done! (%08lx)\n", size_b0 + size_b1); */
@@ -269,8 +269,8 @@
 
 #if defined(CONFIG_CMD_PCMCIA)
 
-#ifdef	CFG_PCMCIA_MEM_ADDR
-volatile unsigned char *pcmcia_mem = (unsigned char *) CFG_PCMCIA_MEM_ADDR;
+#ifdef	CONFIG_SYS_PCMCIA_MEM_ADDR
+volatile unsigned char *pcmcia_mem = (unsigned char *) CONFIG_SYS_PCMCIA_MEM_ADDR;
 #endif
 
 int pcmcia_init (void)
@@ -281,10 +281,10 @@
 	/*
 	 ** Enable the PCMCIA for a Flash card.
 	 */
-	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
 
 #if 0
-	pcmp->pcmc_pbr0 = CFG_PCMCIA_MEM_ADDR;
+	pcmp->pcmc_pbr0 = CONFIG_SYS_PCMCIA_MEM_ADDR;
 	pcmp->pcmc_por0 = 0xc00ff05d;
 #endif
 
diff --git a/board/gth/ee_access.c b/board/gth/ee_access.c
index 716c90e..2a33a0e 100644
--- a/board/gth/ee_access.c
+++ b/board/gth/ee_access.c
@@ -152,7 +152,7 @@
   int i;
   int Value;
   u8 Result=0;
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
   u32 Flags;
 #endif
 
@@ -162,7 +162,7 @@
     /* Small delay between pulses */
     udelay(1);
 
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
     /* Disable irq */
     save_flags(Flags);
     cli();
@@ -182,7 +182,7 @@
     if(Value)
       Value=1;
 
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
     /* Enable irq */
     restore_flags(Flags);
 #endif
@@ -205,7 +205,7 @@
      Write LSb first */
   int i;
   int Value;
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
   u32 Flags;
 #endif
 
@@ -216,7 +216,7 @@
     udelay(1);
     Value = Byte&1;
 
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
     /* Disable irq */
     save_flags(Flags);
     cli();
@@ -237,7 +237,7 @@
 
     WRITE_PORT(1);
 
-#ifndef CFG_IMMR
+#ifndef CONFIG_SYS_IMMR
     /* Enable irq */
     restore_flags(Flags);
 #endif
@@ -289,7 +289,7 @@
   int i;
   u8 Tx[10];
   int tmp;
-  volatile immap_t *immap = (immap_t *)CFG_IMMR;
+  volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 
   while(0){
     tmp = 1-tmp;
diff --git a/board/gth/ee_dev.h b/board/gth/ee_dev.h
index 417c7b6..3004b46 100644
--- a/board/gth/ee_dev.h
+++ b/board/gth/ee_dev.h
@@ -9,10 +9,10 @@
 
 #define E_DEBUG(fmt,args...) if( Debug ) printk(KERN_DEBUG"EE: " fmt, ##args)
 
-#define PORT_B_PAR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbpar
-#define PORT_B_ODR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbodr
-#define PORT_B_DIR ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdir
-#define PORT_B_DAT ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat
+#define PORT_B_PAR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbpar
+#define PORT_B_ODR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbodr
+#define PORT_B_DIR ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdir
+#define PORT_B_DAT ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat
 
 #define SET_PORT_B_INPUT(Mask)  PORT_B_DIR &= ~(Mask)
 #define SET_PORT_B_OUTPUT(Mask) PORT_B_DIR |= Mask
diff --git a/board/gth/flash.c b/board/gth/flash.c
index 11e105e..169270b 100644
--- a/board/gth/flash.c
+++ b/board/gth/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -44,7 +44,7 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
@@ -54,7 +54,7 @@
 	return(0x1fffff);
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	{
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
@@ -90,45 +90,45 @@
 	  size_b1 = 0;
 
 	  /* Remap FLASH according to real size */
-	  memctl->memc_or0 = CFG_OR0_PRELIM;
-	  memctl->memc_br0 = CFG_BR0_PRELIM;
+	  memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
+	  memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
 
 	  /* Re-do sizing to get full correct info */
-	  size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	  size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	  /* monitor protection ON by default */
 	  (void)flash_protect(FLAG_PROTECT_SET,
-			    CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE+monitor_flash_len-1,
+			    CONFIG_SYS_MONITOR_BASE,
+			    CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 #endif
 
 	if (size_b1)
 	{
-	  /* memctl->memc_or1 = CFG_OR1_PRELIM;
-	     memctl->memc_br1 = CFG_BR1_PRELIM; */
+	  /* memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	     memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM; */
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					 &flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		(void)flash_protect(FLAG_PROTECT_SET,
-				    CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE+monitor_flash_len-1,
+				    CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 				    &flash_info[1]);
 #endif
 	}
 	else
 	{
-/*	    memctl->memc_or1 = CFG_OR1_PRELIM;
- FIXME	    memctl->memc_br1 = CFG_BR1_PRELIM;  */
+/*	    memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+ FIXME	    memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;  */
 
 		flash_info[1].flash_id = FLASH_UNKNOWN;
 		flash_info[1].sector_count = -1;
@@ -501,7 +501,7 @@
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
 #endif
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -638,7 +638,7 @@
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
 #endif
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/gth/gth.c b/board/gth/gth.c
index 788a6a0..4399db2 100644
--- a/board/gth/gth.c
+++ b/board/gth/gth.c
@@ -38,7 +38,7 @@
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	int Id = 0;
 	int Rev = 0;
 	u32 Pbdat;
@@ -162,7 +162,7 @@
 
 int _initsdram (uint base, uint * noMbytes)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *mc = &immap->im_memctl;
 	volatile u32 *memptr;
 
@@ -235,7 +235,7 @@
 
 void _sdramdisable (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_br1 = 0x00000000;
@@ -345,7 +345,7 @@
 static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 {
 	u16 data;
-	volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+	volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
 
 	if ((System != FAILSAFE_BOOT) & (System != SYSTEM_BOOT)) {
 		printf ("Invalid system data %u, setting failsafe\n", System);
@@ -376,12 +376,12 @@
 static void maybe_update_restart_reason (volatile u32 * addr32)
 {
 	/* Update addr if sw wd restart */
-	volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+	volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
 	volatile u16 *addr_16 = (u16 *) addr32;
 	u32 rsr;
 
 	/* Dont reset register now */
-	rsr = ((volatile immap_t *) CFG_IMMR)->im_clkrst.car_rsr;
+	rsr = ((volatile immap_t *) CONFIG_SYS_IMMR)->im_clkrst.car_rsr;
 
 	rsr >>= 24;
 
@@ -419,7 +419,7 @@
 	int i;
 	volatile u32 *raddr;
 
-	raddr = (u32 *) (CFG_FLASH_BASE + POWER_OFFSET);
+	raddr = (u32 *) (CONFIG_SYS_FLASH_BASE + POWER_OFFSET);
 
 	if (*raddr == 0xFFFFFFFF) {
 		/* Nothing written */
@@ -456,7 +456,7 @@
 	u8 system;
 	u8 count;
 
-	addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
+	addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
 
 	if (*addr == 0xFFFF) {
 		printf ("*** No bootdata exists. ***\n");
@@ -528,7 +528,7 @@
 	u8 Tx[5];
 	int page;
 	int read = 0;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* Kill fpga */
 	immap->im_ioport.iop_papar &= ~(PA_FL_CONFIG | PA_FL_CE);
diff --git a/board/gth/pcmcia.c b/board/gth/pcmcia.c
index cffcbde..a4db16d 100644
--- a/board/gth/pcmcia.c
+++ b/board/gth/pcmcia.c
@@ -31,10 +31,10 @@
 
 	debug ("hardware_enable: GTH Slot %c\n", 'A' + slot);
 
-	immap = (immap_t *) CFG_IMMR;
-	sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
-	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
-	cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
+	cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
 
 	/* clear interrupt state, and disable interrupts */
 	pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
diff --git a/board/gth2/flash.c b/board/gth2/flash.c
index f96edff..1b3c43c 100644
--- a/board/gth2/flash.c
+++ b/board/gth2/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * flash_init()
diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c
index cea65c6..59873d5 100644
--- a/board/gth2/gth2.c
+++ b/board/gth2/gth2.c
@@ -154,19 +154,19 @@
 	   We need to map it into a 32 bit addresses */
 	write_one_tlb(20,                 /* index */
 		      0x01ffe000,         /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
 		      0x3C000017,         /* Lo0 */
 		      0x3C200017);        /* Lo1 */
 
 	write_one_tlb(21,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
 
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
 
@@ -209,7 +209,7 @@
 static void write_bootdata (volatile u16 * addr, u8 System, u8 Count)
 {
 	u16 data;
-	volatile u16 *flash = (u16 *) (CFG_FLASH_BASE);
+	volatile u16 *flash = (u16 *) (CONFIG_SYS_FLASH_BASE);
 
 	switch(System){
 	case FAILSAFE_BOOT:
@@ -302,7 +302,7 @@
 	u8 system = FAILSAFE_BOOT;
 	u8 count;
 
-	addr = (u16 *) (CFG_FLASH_BASE + BOOTDATA_OFFSET);
+	addr = (u16 *) (CONFIG_SYS_FLASH_BASE + BOOTDATA_OFFSET);
 
 	if (*addr == 0xFFFF) {
 		printf ("*** No bootdata exists. ***\n");
diff --git a/board/gth2/lowlevel_init.S b/board/gth2/lowlevel_init.S
index 4c4f0eb..bc31c00 100644
--- a/board/gth2/lowlevel_init.S
+++ b/board/gth2/lowlevel_init.S
@@ -6,7 +6,7 @@
 #include <asm/mipsregs.h>
 
 #define CP0_Config0		$16
-#define MEM_1MS			((CFG_MHZ) * 1000)
+#define MEM_1MS			((CONFIG_SYS_MHZ) * 1000)
 #define GPIO_RJ1LY     (1<<22)
 #define GPIO_CFRESET   (1<<10)
 
diff --git a/board/gw8260/flash.c b/board/gw8260/flash.c
index 6cf311f..6035f69 100644
--- a/board/gw8260/flash.c
+++ b/board/gw8260/flash.c
@@ -54,7 +54,7 @@
 #include <common.h>
 #include <mpc8260.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static ulong flash_get_size (vu_long *addr, flash_info_t *info);
 static int write_word (flash_info_t *info, ulong dest, ulong data);
@@ -82,21 +82,21 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
     /* for now, only support the 4 MB Flash SIMM */
-    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 
     /*
      * protect monitor and environment sectors
      */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 
@@ -110,7 +110,7 @@
 		  &flash_info[0]);
 #endif
 
-    return (CFG_FLASH0_SIZE * 1024 * 1024);  /*size*/
+    return (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);  /*size*/
 }
 
 /*********************************************************************/
@@ -357,7 +357,7 @@
     last  = start;
     addr = (vu_long*)(info->start[l_sect]);
     while ((addr[0] & 0x80808080) != 0x80808080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -512,7 +512,7 @@
     /* data polling for D7 */
     start = get_timer (0);
     while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    return (1);
 	}
     }
diff --git a/board/gw8260/gw8260.c b/board/gw8260/gw8260.c
index 42c9e0d..28f5ca9 100644
--- a/board/gw8260/gw8260.c
+++ b/board/gw8260/gw8260.c
@@ -226,7 +226,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
 /*								     */
@@ -256,7 +256,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -319,7 +319,7 @@
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_SDRAM_BASE;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_SDRAM_BASE;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -346,9 +346,9 @@
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -373,8 +373,8 @@
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_SDRAM_BASE;
-	const unsigned int size = (CFG_SDRAM_SIZE * 1024 * 1024) / 4;
+		(volatile unsigned int *) CONFIG_SYS_SDRAM_BASE;
+	const unsigned int size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -391,9 +391,9 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -451,7 +451,7 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -483,8 +483,8 @@
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_SDRAM_BASE;
-	const unsigned long size = (CFG_SDRAM_SIZE * 1024 * 1024) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_SDRAM_BASE;
+	const unsigned long size = (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024) / 8;
 
 	unsigned int i;
 
@@ -557,21 +557,21 @@
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1)) {
 		printf ("Testing RAM ... ");
 	}
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		if (mem_test_data () == 1) {
 			return 1;
 		}
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		if (mem_test_address () == 1) {
 			return 1;
 		}
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		if (mem_test_walk () == 1) {
 			return 1;
@@ -584,7 +584,7 @@
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /*********************************************************************/
 /* NAME: initdram() -  initializes SDRAM controller		     */
@@ -593,11 +593,11 @@
 /*   Initializes the MPC8260's SDRAM controller.		     */
 /*								     */
 /* INPUTS:							     */
-/*   CFG_IMMR	    -  MPC8260 Internal memory map		     */
-/*   CFG_SDRAM_BASE -  Physical start address of SDRAM		     */
-/*   CFG_PSDMR -       SDRAM mode register			     */
-/*   CFG_MPTPR -       Memory refresh timer prescaler register	     */
-/*   CFG_SDRAM0_SIZE - SDRAM size				     */
+/*   CONFIG_SYS_IMMR	    -  MPC8260 Internal memory map		     */
+/*   CONFIG_SYS_SDRAM_BASE -  Physical start address of SDRAM		     */
+/*   CONFIG_SYS_PSDMR -       SDRAM mode register			     */
+/*   CONFIG_SYS_MPTPR -       Memory refresh timer prescaler register	     */
+/*   CONFIG_SYS_SDRAM0_SIZE - SDRAM size				     */
 /*								     */
 /* RETURNS:							     */
 /*   SDRAM size in bytes					     */
@@ -608,10 +608,10 @@
 /*********************************************************************/
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
-	ulong psdmr = CFG_PSDMR;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	/*
@@ -631,11 +631,11 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr = c;
@@ -651,7 +651,7 @@
 	*ramaddr = c;
 
 	/* return total ram size */
-	return (CFG_SDRAM0_SIZE * 1024 * 1024);
+	return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
 }
 
 /*********************************************************************/
diff --git a/board/hermes/flash.c b/board/hermes/flash.c
index 799fe83..888231c 100644
--- a/board/hermes/flash.c
+++ b/board/hermes/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -58,20 +58,20 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) |
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
 				(memctl->memc_br0 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -376,7 +376,7 @@
 	last  = start;
 	addr = (vu_char*)(info->start[l_sect]);
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -449,7 +449,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/hermes/hermes.c b/board/hermes/hermes.c
index f9b5720..9a3e5f6 100644
--- a/board/hermes/hermes.c
+++ b/board/hermes/hermes.c
@@ -136,7 +136,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size, size8, size9;
 
@@ -153,8 +153,8 @@
 	/*
 	 * Map controller banks 1 to the SDRAM banks at preliminary address
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
 	/* HERMES-PRO boards have only one bank SDRAM */
 
@@ -179,7 +179,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -187,7 +187,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
@@ -195,7 +195,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {					/* back to 8 columns            */
 		size = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -203,7 +203,7 @@
 	udelay (1000);
 
 	memctl->memc_or1 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	udelay (10000);
 
@@ -223,7 +223,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -264,7 +264,7 @@
 
 static ulong board_init (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	ulong reg, revision, speed = 100;
 	int ethspeed;
 	char *s;
@@ -403,7 +403,7 @@
  */
 void hermes_start_lxt980 (int speed)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile cpm8xx_t *cp = (cpm8xx_t *) & (immr->im_cpm);
 	volatile scc_t *sp = (scc_t *) & (cp->cp_scc[SCC_SM]);
 	volatile cbd_t *bd;
@@ -595,7 +595,7 @@
 
 void show_boot_progress (int status)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	if (status < -32) status = -1;	/* let things compatible */
 	status ^= 0x0F;
diff --git a/board/hidden_dragon/early_init.S b/board/hidden_dragon/early_init.S
index 07dafb7..531dcdf 100644
--- a/board/hidden_dragon/early_init.S
+++ b/board/hidden_dragon/early_init.S
@@ -32,68 +32,68 @@
 
 #if defined(USE_DINK32)
   /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
-  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
 #else
-  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
 #endif
 
 	.text
 
 	/* Values to program into memory controller registers */
 tbl:	.long	MCCR1, MCCR1VAL
-	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
 	.long	MCCR3
-	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
-		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
-		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
 	.long	MCCR4
-	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
-		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
-		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
-		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
-		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
-		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
-		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
 	.long	MSAR1
-	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR1
-	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MSAR2
-	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR2
-	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR1
-	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR1
-	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR2
-	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR2
-	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	0
 
 
@@ -123,7 +123,7 @@
 	/* set bank enable bits */
 	lis	r0, MBER@h
 	ori	r0, 0, MBER@l
-	li	r1, CFG_BANK_ENABLE
+	li	r1, CONFIG_SYS_BANK_ENABLE
 	stwbrx	r0, 0, r3
 	eieio
 	stb	r1, 0(r4)
@@ -145,8 +145,8 @@
 	eieio
 
 	/* set up stack pointer */
-	lis	r1, CFG_INIT_SP_OFFSET@h
-	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
 	mtlr	r10
 	blr
diff --git a/board/hidden_dragon/flash.c b/board/hidden_dragon/flash.c
index 10293b4..2ce1dc4 100644
--- a/board/hidden_dragon/flash.c
+++ b/board/hidden_dragon/flash.c
@@ -33,11 +33,11 @@
 #define ROM_CS0_START	0xFF800000
 #define ROM_CS1_START	0xFF000000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
@@ -120,10 +120,10 @@
 {
 	unsigned long i;
 	unsigned char j;
-	static const ulong flash_banks[] = CFG_FLASH_BANKS;
+	static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		flash_info_t *const pflinfo = &flash_info[i];
 
 		pflinfo->flash_id = FLASH_UNKNOWN;
@@ -135,10 +135,10 @@
 	{
 		register unsigned char temp;
 
-		CONFIG_READ_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+		CONFIG_READ_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
 				  temp);
 		temp &= ~0x20;	/* clear BIOSWP bit */
-		CONFIG_WRITE_BYTE (CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
+		CONFIG_WRITE_BYTE (CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR,
 				   temp);
 	}
 
@@ -205,10 +205,10 @@
 		}
 		/* Protect monitor and environment sectors
 		 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE,
-			       CFG_MONITOR_BASE + monitor_flash_len - 1,
+			       CONFIG_SYS_MONITOR_BASE,
+			       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			       &flash_info[0]);
 #endif
 
@@ -426,7 +426,7 @@
 						       start[0]) << sh8b));
 	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
 	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -565,7 +565,7 @@
 		start = get_timer (0);
 		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/hidden_dragon/hidden_dragon.c b/board/hidden_dragon/hidden_dragon.c
index 2d7a787..027aa45 100644
--- a/board/hidden_dragon/hidden_dragon.c
+++ b/board/hidden_dragon/hidden_dragon.c
@@ -52,7 +52,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
diff --git a/board/hmi1001/hmi1001.c b/board/hmi1001/hmi1001.c
index 8cfd75b..9cbed4b 100644
--- a/board/hmi1001/hmi1001.c
+++ b/board/hmi1001/hmi1001.c
@@ -33,7 +33,7 @@
 #include <asm/processor.h>
 #include <malloc.h>
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -76,14 +76,14 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 	uint svr, pvr;
 
@@ -105,9 +105,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -129,7 +129,7 @@
 	}
 
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -147,7 +147,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -193,8 +193,8 @@
 
 struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
 {
-	kbd_data->s1 = *((volatile uchar*)(CFG_STATUS1_BASE));
-	kbd_data->s2 = *((volatile uchar*)(CFG_STATUS2_BASE));
+	kbd_data->s1 = *((volatile uchar*)(CONFIG_SYS_STATUS1_BASE));
+	kbd_data->s2 = *((volatile uchar*)(CONFIG_SYS_STATUS2_BASE));
 
 	return kbd_data;
 }
@@ -300,9 +300,9 @@
 {
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
 	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
 	return 0;
 }
 #ifdef	CONFIG_PCI
diff --git a/board/hymod/bsp.c b/board/hymod/bsp.c
index 12f1402..1848bb3 100644
--- a/board/hymod/bsp.c
+++ b/board/hymod/bsp.c
@@ -304,7 +304,7 @@
 do_eecl (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	uchar data[HYMOD_EEPROM_SIZE];
-	uint addr = CFG_I2C_EEPROM_ADDR;
+	uint addr = CONFIG_SYS_I2C_EEPROM_ADDR;
 
 	switch (argc) {
 
diff --git a/board/hymod/eeprom.c b/board/hymod/eeprom.c
index c9b9b18..4d48d7d 100644
--- a/board/hymod/eeprom.c
+++ b/board/hymod/eeprom.c
@@ -36,7 +36,7 @@
 static int
 hymod_eeprom_load (int which, hymod_eeprom_t *ep)
 {
-	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
 		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
 	unsigned offset = 0;
 	uchar data[HYMOD_EEPROM_MAXLEN], *dp, *edp;
@@ -466,7 +466,7 @@
 static int
 hymod_eeprom_fetch(int which, char *filename, ulong addr)
 {
-	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
 		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
 	hymod_eehdr_t *hp = (hymod_eehdr_t *)&data[0];
 	ulong crc;
@@ -635,7 +635,7 @@
 hymod_eeprom_read (int which, hymod_eeprom_t *ep)
 {
 	char *label = which ? "mezzanine" : "main";
-	unsigned dev_addr = CFG_I2C_EEPROM_ADDR | \
+	unsigned dev_addr = CONFIG_SYS_I2C_EEPROM_ADDR | \
 		(which ? HYMOD_EEOFF_MEZZ : HYMOD_EEOFF_MAIN);
 	char filename[50], prompt[50], *dir;
 	int serno, count = 0, rc;
@@ -682,7 +682,7 @@
 		printf ("*** fetching %s board EEPROM contents from server\n",
 			label);
 
-		rc = hymod_eeprom_fetch (which, filename, CFG_LOAD_ADDR);
+		rc = hymod_eeprom_fetch (which, filename, CONFIG_SYS_LOAD_ADDR);
 
 		if (rc == 0) {
 			puts ("*** fetch failed - ignoring eeprom contents\n");
diff --git a/board/hymod/env.c b/board/hymod/env.c
index 062553b..c0e2cd5 100644
--- a/board/hymod/env.c
+++ b/board/hymod/env.c
@@ -35,7 +35,7 @@
 env_callback (uchar *name, uchar *value)
 {
 	hymod_conf_t *cp = &gd->bd->bi_hymod_conf;
-	char ov[CFG_CBSIZE], nv[CFG_CBSIZE], *p, *q, *nn, c, *curver, *newver;
+	char ov[CONFIG_SYS_CBSIZE], nv[CONFIG_SYS_CBSIZE], *p, *q, *nn, c, *curver, *newver;
 	int override = 1, append = 0, remove = 0, nnl, ovl, nvl;
 
 	nn = (char *)name;
@@ -205,7 +205,7 @@
 	if ((path = getenv ("global_env_path")) == NULL || *path == '\0')
 		path = def_global_env_path;
 
-	if (fetch_and_parse (path, CFG_LOAD_ADDR, env_callback) == 0) {
+	if (fetch_and_parse (path, CONFIG_SYS_LOAD_ADDR, env_callback) == 0) {
 		puts ("*** Fetch of global environment failed!\n");
 		return;
 	}
diff --git a/board/hymod/flash.c b/board/hymod/flash.c
index ad0a229..e2cf38c 100644
--- a/board/hymod/flash.c
+++ b/board/hymod/flash.c
@@ -27,7 +27,7 @@
 #include <mpc8260.h>
 #include <board/hymod/flash.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Protection Flags:
@@ -95,7 +95,7 @@
 			(unsigned long)word, (unsigned long)base);
 	}
 
-	if (fip->sector_count >= CFG_MAX_FLASH_SECT)
+	if (fip->sector_count >= CONFIG_SYS_MAX_FLASH_SECT)
 		panic ("\ntoo many sectors (%d) in flash at address 0x%08lx",
 			fip->sector_count, (unsigned long)base);
 
@@ -198,7 +198,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	do {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			retval = 1;
 			goto done;
 		}
@@ -228,30 +228,30 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	bank_probe (&flash_info[0], (bank_addr_t)CFG_FLASH_BASE);
+	bank_probe (&flash_info[0], (bank_addr_t)CONFIG_SYS_FLASH_BASE);
 
 	/*
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE == CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE == CONFIG_SYS_FLASH_BASE
 	(void)flash_protect (FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
-#if defined(CFG_FLASH_ENV_ADDR)
+#if defined(CONFIG_SYS_FLASH_ENV_ADDR)
 	(void)flash_protect (FLAG_PROTECT_SET,
-		      CFG_FLASH_ENV_ADDR,
-#if defined(CFG_FLASH_ENV_BUF)
-		      CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_BUF - 1,
+		      CONFIG_SYS_FLASH_ENV_ADDR,
+#if defined(CONFIG_SYS_FLASH_ENV_BUF)
+		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_BUF - 1,
 #else
-		      CFG_FLASH_ENV_ADDR + CFG_FLASH_ENV_SIZE - 1,
+		      CONFIG_SYS_FLASH_ENV_ADDR + CONFIG_SYS_FLASH_ENV_SIZE - 1,
 #endif
 		      &flash_info[0]);
 #endif
@@ -368,7 +368,7 @@
 			do {
 				now = get_timer (start);
 
-				if (now - estart > CFG_FLASH_ERASE_TOUT) {
+				if (now - estart > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (sect %d)\n", sect);
 					haderr = 1;
 					rcode = 1;
diff --git a/board/hymod/hymod.c b/board/hymod/hymod.c
index 91aaab1..2af3049 100644
--- a/board/hymod/hymod.c
+++ b/board/hymod/hymod.c
@@ -255,7 +255,7 @@
 int
 board_postclk_init (void)
 {
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/*
 	 * Initialise the FS6377 clock chip
@@ -347,16 +347,16 @@
 int
 misc_init_f (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 	printf ("UPMs:  ");
 
 	upmconfig (UPMB, upmb_table, sizeof upmb_table / sizeof upmb_table[0]);
-	memctl->memc_mbmr = CFG_MBMR;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR;
 
 	upmconfig (UPMC, upmc_table, sizeof upmc_table / sizeof upmc_table[0]);
-	memctl->memc_mcmr = CFG_MCMR;
+	memctl->memc_mcmr = CONFIG_SYS_MCMR;
 
 	printf ("configured\n");
 	return (0);
@@ -367,10 +367,10 @@
 phys_size_t
 initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
-	ulong psdmr = CFG_PSDMR;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	/*
@@ -390,11 +390,11 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr = c;
@@ -409,7 +409,7 @@
 	memctl->memc_psdmr = psdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*ramaddr = c;
 
-	return (CFG_SDRAM_SIZE << 20);
+	return (CONFIG_SYS_SDRAM_SIZE << 20);
 }
 
 /* ------------------------------------------------------------------------- */
@@ -517,18 +517,18 @@
 #ifdef CONFIG_SHOW_ACTIVITY
 void board_show_activity (ulong timebase)
 {
-#ifdef CFG_HYMOD_DBLEDS
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+#ifdef CONFIG_SYS_HYMOD_DBLEDS
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8260_t *iop = &immr->im_ioport;
 	static int shift = 0;
 
-	if ((timestamp % CFG_HZ) == 0) {
+	if ((timestamp % CONFIG_SYS_HZ) == 0) {
 		if (++shift > 3)
 			shift = 0;
 		iop->iop_pdatd =
 				(iop->iop_pdatd & ~0x0f000000) | (1 << (24 + shift));
 	}
-#endif /* CFG_HYMOD_DBLEDS */
+#endif /* CONFIG_SYS_HYMOD_DBLEDS */
 }
 
 void show_activity(int arg)
diff --git a/board/hymod/input.c b/board/hymod/input.c
index 63aa13c..998132d 100644
--- a/board/hymod/input.c
+++ b/board/hymod/input.c
@@ -24,7 +24,7 @@
 #include <common.h>
 
 /* imports from common/main.c */
-extern char console_buffer[CFG_CBSIZE];
+extern char console_buffer[CONFIG_SYS_CBSIZE];
 
 int
 hymod_get_serno (const char *prompt)
diff --git a/board/icecube/flash.c b/board/icecube/flash.c
index 0aa78eb..7a433b3 100644
--- a/board/icecube/flash.c
+++ b/board/icecube/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 
 #ifndef CONFIG_FLASH_CFI_DRIVER
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -66,12 +66,12 @@
 	int i;
 	extern void flash_preinit(void);
 	extern void flash_afterinit(ulong);
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	flash_preinit();
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		memset(&flash_info[i], 0, sizeof(flash_info_t));
 
 		flash_info[i].size =
@@ -80,12 +80,12 @@
 		size += flash_info[i].size;
 		flashbase += 0x800000;
 	}
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -122,14 +122,14 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->size &&
 			info->start[0] <= base && base <= info->start[0] + info->size - 1)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -360,7 +360,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -374,14 +374,14 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
 		}
 
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
 			putc ('.');
 			last = get_timer(0);
 		}
@@ -482,7 +482,7 @@
 
 	/* data polling for D7 */
 	while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW)0x00F000F0;	/* reset bank */
 			res = 1;
 		}
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index d84ab3a..7524461 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -87,7 +87,7 @@
 #define lite5200b_wakeup()
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -130,7 +130,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -141,7 +141,7 @@
 	ulong dramsize2 = 0;
 	uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -162,9 +162,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -190,10 +190,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -215,7 +215,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -233,7 +233,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -263,7 +263,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup and enable SDRAM chip selects */
@@ -282,9 +282,9 @@
 
 	/* find RAM size */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -295,12 +295,12 @@
 	/* set SDRAM end address according to size */
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* Retrieve amount of SDRAM available */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -340,9 +340,9 @@
 {
 	if (size == 0x800000) { /* adjust mapping */
 		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CFG_BOOTCS_START | size);
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
 		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CFG_BOOTCS_START | size, size);
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 }
 
diff --git a/board/icu862/flash.c b/board/icu862/flash.c
index e6382f5..2afeff4 100644
--- a/board/icu862/flash.c
+++ b/board/icu862/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -50,13 +50,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -92,19 +92,19 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -468,7 +468,7 @@
 	while ((addr[0] & 0xFFFFFFFF) != 0xFFFFFFFF)
 #endif
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			puts ("Timeout\n");
 			return 1;
 		}
@@ -606,7 +606,7 @@
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080))
 #endif
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/icu862/icu862.c b/board/icu862/icu862.c
index 18aa8bf..b99d256 100644
--- a/board/icu862/icu862.c
+++ b/board/icu862/icu862.c
@@ -96,7 +96,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -111,7 +111,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -120,10 +120,10 @@
 	 * preliminary address - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -143,7 +143,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE1_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE1_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -151,7 +151,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE1_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE1_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
@@ -159,7 +159,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {					/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -172,7 +172,7 @@
 	 */
 	if ((size_b0 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
@@ -180,12 +180,12 @@
 	 * Final mapping
 	 */
 
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;					/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -206,7 +206,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/icu862/pcmcia.c b/board/icu862/pcmcia.c
index 20922d8..a4c0b54 100644
--- a/board/icu862/pcmcia.c
+++ b/board/icu862/pcmcia.c
@@ -22,8 +22,8 @@
 	volatile cpm8xx_t	*cp;
 	uint reg;
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	* Configure Port B for TPS2205 PC-Card Power-Interface Switch
@@ -58,10 +58,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/* Configure Port B for TPS2205 PC-Card Power-Interface Switch */
 	cfg_port_B ();
@@ -165,9 +165,9 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* Shut down */
 	cp->cp_pbdat &= ~(TPS2205_SHDN);
@@ -198,9 +198,9 @@
 			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
 	* and assert RESET signal
diff --git a/board/idmr/flash.c b/board/idmr/flash.c
index 33512b8..57c9948 100644
--- a/board/idmr/flash.c
+++ b/board/idmr/flash.c
@@ -23,11 +23,11 @@
 
 #include <common.h>
 
-#define PHYS_FLASH_1 CFG_FLASH_BASE
+#define PHYS_FLASH_1 CONFIG_SYS_FLASH_BASE
 #define FLASH_BANK_SIZE 0x800000
 #define EN29LV640 0x227e227e
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 void flash_print_info (flash_info_t * info)
 {
@@ -75,15 +75,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(AMD_MANUFACT & FLASH_VENDMASK) |
 			(EN29LV640 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -96,8 +96,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + 0x2ffff, &flash_info[0]);
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + 0x2ffff, &flash_info[0]);
 
 	return size;
 }
@@ -111,8 +111,8 @@
 #define CMD_PROGRAM		0x00A0
 #define CMD_UNLOCK_BYPASS	0x0020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555<<1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA<<1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555<<1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA<<1)))
 
 #define BIT_ERASE_DONE		0x0080
 #define BIT_RDY_MASK		0x0080
@@ -191,7 +191,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+				if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip1 = TMO;
 					break;
@@ -280,7 +280,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer (0) > CFG_FLASH_ERASE_TOUT * CFG_HZ / 1000) {
+		if (get_timer (0) > CONFIG_SYS_FLASH_ERASE_TOUT * CONFIG_SYS_HZ / 1000) {
 			chip1 = ERR | TMO;
 			break;
 		}
diff --git a/board/idmr/idmr.c b/board/idmr/idmr.c
index 4f073fc..3771c19 100644
--- a/board/idmr/idmr.c
+++ b/board/idmr/idmr.c
@@ -35,7 +35,7 @@
 	/*
 	 * After reset, CS0 is configured to cover entire address space. We
 	 * need to configure it to its proper values, so that writes to
-	 * CFG_SDRAM_BASE and vicinity during SDRAM controller setup below do
+	 * CONFIG_SYS_SDRAM_BASE and vicinity during SDRAM controller setup below do
 	 * now fall under CS0 (see 16.3.1 of the MCF5271 Reference Manual).
 	 */
 
@@ -99,7 +99,7 @@
 	 * PS: 16 bit
 	 */
 	mbar_writeLong(MCF_SDRAMC_DACR0,
-			MCF_SDRAMC_DACRn_BA(CFG_SDRAM_BASE>>18) |
+			MCF_SDRAMC_DACRn_BA(CONFIG_SYS_SDRAM_BASE>>18) |
 			MCF_SDRAMC_DACRn_BA(0x00) |
 			MCF_SDRAMC_DACRn_CASL(0x03) |
 			MCF_SDRAMC_DACRn_CBM(0x03) |
@@ -117,7 +117,7 @@
 			MCF_SDRAMC_DACRn_IP);
 
 	/* Write to this block to initiate precharge */
-	*(volatile u16 *)(CFG_SDRAM_BASE) = 0xa5a5;
+	*(volatile u16 *)(CONFIG_SYS_SDRAM_BASE) = 0xa5a5;
 
 	/*
 	 * Wait at least 20ns to allow banks to precharge (t_RP = 20ns). We
@@ -153,9 +153,9 @@
 	 * Burst Type = Sequential
 	 * Burst Length = 1
 	 */
-	*(volatile u32 *)(CFG_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
+	*(volatile u32 *)(CONFIG_SYS_SDRAM_BASE + 0x1800) = 0xa5a5a5a5;
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 };
 
 
diff --git a/board/idmr/mii.c b/board/idmr/mii.c
index 78a7028..e79fa19 100644
--- a/board/idmr/mii.c
+++ b/board/idmr/mii.c
@@ -38,14 +38,14 @@
 {
 	if (setclear) {
 		/* Enable Ethernet pins */
-		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CFG_FECI2C);
+		mbar_writeByte(MCF_GPIO_PAR_FECI2C, CONFIG_SYS_FECI2C);
 	} else {
 	}
 
 	return 0;
 }
 
-#if defined(CFG_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
+#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII)
 #include <miiphy.h>
 
 /* Make MII read/write commands for the FEC. */
@@ -131,9 +131,9 @@
 
 	return (mii_reply & 0xffff);	/* data read from phy */
 }
-#endif				/* CFG_DISCOVER_PHY || CONFIG_CMD_MII */
+#endif				/* CONFIG_SYS_DISCOVER_PHY || CONFIG_CMD_MII */
 
-#if defined(CFG_DISCOVER_PHY)
+#if defined(CONFIG_SYS_DISCOVER_PHY)
 int mii_discover_phy(struct eth_device *dev)
 {
 #define MAX_PHY_PASSES 11
@@ -198,7 +198,7 @@
 
 	return phyaddr;
 }
-#endif				/* CFG_DISCOVER_PHY */
+#endif				/* CONFIG_SYS_DISCOVER_PHY */
 
 void mii_init(void) __attribute__((weak,alias("__mii_init")));
 
diff --git a/board/ids8247/config.mk b/board/ids8247/config.mk
index 136cdb8..2a7f3dd 100644
--- a/board/ids8247/config.mk
+++ b/board/ids8247/config.mk
@@ -25,7 +25,7 @@
 # IDS 8247 Board
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_IDS8247.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_IDS8247.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/ids8247/flash.c b/board/ids8247/flash.c
index 5800ce2..5107553 100644
--- a/board/ids8247/flash.c
+++ b/board/ids8247/flash.c
@@ -31,11 +31,11 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -84,16 +84,16 @@
 {
 	unsigned long size_b0;
 	int i;
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
-	size_b0 = flash_get_size ((FPW *) CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -105,11 +105,11 @@
 
 	flash_get_offsets (0xff800000, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	(void) flash_protect (FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 				&flash_info[0]);
 #endif
 
@@ -258,10 +258,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -332,7 +332,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			    if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -472,7 +472,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/ids8247/ids8247.c b/board/ids8247/ids8247.c
index 065014a..68b7070 100644
--- a/board/ids8247/ids8247.c
+++ b/board/ids8247/ids8247.c
@@ -254,7 +254,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -265,7 +265,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -278,7 +278,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 	long psize, lsize;
@@ -286,15 +286,15 @@
 	psize = 16 * 1024 * 1024;
 	lsize = 0;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	psize = try_init (memctl, CFG_PSDMR, CFG_OR2,
-						  (uchar *) CFG_SDRAM_BASE);
-#endif /* CFG_RAMBOOT */
+	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR2,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -315,8 +315,8 @@
 {
 	ulong totlen = 0;
 
-	debug ("Probing at 0x%.8x\n", CFG_NAND0_BASE);
-	totlen += nand_probe (CFG_NAND0_BASE);
+	debug ("Probing at 0x%.8x\n", CONFIG_SYS_NAND0_BASE);
+	totlen += nand_probe (CONFIG_SYS_NAND0_BASE);
 
 	printf ("%4lu MB\n", totlen >>20);
 }
diff --git a/board/impa7/flash.c b/board/impa7/flash.c
index 1dea22b..d0c5880 100644
--- a/board/impa7/flash.c
+++ b/board/impa7/flash.c
@@ -28,7 +28,7 @@
 #define MAIN_SECT_SIZE  0x20000
 #define PARAM_SECT_SIZE 0x4000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -39,15 +39,15 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT & FLASH_VENDMASK) |
 			(INTEL_ID_28F320B3T & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else if (i == 1)
@@ -69,8 +69,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -175,7 +175,7 @@
 
 			while ((*addr & 0x00800080) != 0x00800080) {
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0x00B000B0;	/* suspend erase */
 					*addr = 0x00FF00FF;	/* reset to read mode */
 					rc = ERR_TIMOUT;
@@ -243,7 +243,7 @@
 
 	/* wait while polling the status register */
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
 			/* suspend program command */
 			*addr = 0x00B000B0;
diff --git a/board/incaip/flash.c b/board/incaip/flash.c
index 74dd6fe..cc11e24 100644
--- a/board/incaip/flash.c
+++ b/board/incaip/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/inca-ip.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -73,7 +73,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		ulong flashbase = (i == 0) ? PHYS_FLASH_1 : PHYS_FLASH_2;
 		ulong * buscon = (ulong *)
 			((i == 0) ? INCA_IP_EBU_EBU_BUSCON0 : INCA_IP_EBU_EBU_BUSCON2);
@@ -96,12 +96,12 @@
 		size += flash_info[i].size;
 	}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -173,13 +173,13 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->start[0] <= base && base < info->start[0] + info->size)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -484,7 +484,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -498,14 +498,14 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
 		}
 
 		/* show that we're waiting */
-		if ((get_timer(last)) > CFG_HZ) {	/* every second */
+		if ((get_timer(last)) > CONFIG_SYS_HZ) {	/* every second */
 			putc ('.');
 			last = get_timer(0);
 		}
@@ -609,7 +609,7 @@
 
     /* data polling for D7 */
     while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00F000F0;	/* reset bank */
 	    res = 1;
 	}
@@ -655,7 +655,7 @@
     start = get_timer (0);
 
     while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
 	    res = 1;
 	}
diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c
index 6fe852c..3b30970 100644
--- a/board/incaip/incaip.c
+++ b/board/incaip/incaip.c
@@ -40,16 +40,16 @@
 {
 	/* The only supported SDRAM data width is 16bit.
 	 */
-#define CFG_DW	2
+#define CONFIG_SYS_DW	2
 
 	/* The only supported number of SDRAM banks is 4.
 	 */
-#define CFG_NB	4
+#define CONFIG_SYS_NB	4
 
 	ulong cfgpb0 = *INCA_IP_SDRAM_MC_CFGPB0;
 	int   cols   = cfgpb0 & 0xF;
 	int   rows   = (cfgpb0 & 0xF0) >> 4;
-	ulong size   = (1 << (rows + cols)) * CFG_DW * CFG_NB;
+	ulong size   = (1 << (rows + cols)) * CONFIG_SYS_DW * CONFIG_SYS_NB;
 
 	return size;
 }
@@ -75,7 +75,7 @@
 		{
 			*INCA_IP_SDRAM_MC_CFGPB0 = (0x14 << 8) |
 			                           (rows << 4) | cols;
-			size = get_ram_size((long *)CFG_SDRAM_BASE,
+			size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
 			                                     max_sdram_size());
 
 			if (size > max_size)
diff --git a/board/inka4x0/inka4x0.c b/board/inka4x0/inka4x0.c
index a2e35ff..507196b 100644
--- a/board/inka4x0/inka4x0.c
+++ b/board/inka4x0/inka4x0.c
@@ -45,7 +45,7 @@
 #error "INKA4x0 SDRAM: invalid chip type specified!"
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -88,14 +88,14 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -116,9 +116,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -140,7 +140,7 @@
 	}
 
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -149,7 +149,7 @@
 	} else {
 		dramsize = 0;
 	}
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -179,7 +179,7 @@
 	i = getenv_r("brightness", tmp, sizeof(tmp));
 	br = (i > 0)
 		? (int) simple_strtoul (tmp, NULL, 10)
-		: CFG_BRIGHTNESS;
+		: CONFIG_SYS_BRIGHTNESS;
 	if (br > 255)
 		br = 255;
 
diff --git a/board/innokom/flash.c b/board/innokom/flash.c
index 7f17ba6..8c95341 100644
--- a/board/innokom/flash.c
+++ b/board/innokom/flash.c
@@ -72,7 +72,7 @@
 #define MAIN_SECT_SIZE  0x00020000	/* 128k per sector                  */
 #endif
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /**
  * flash_init: - initialize data structures for flash chips
@@ -85,14 +85,14 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT & FLASH_VENDMASK) |
 			(INTEL_ID_28F128J3 & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
 		switch (i) {
 			case 0:
@@ -110,8 +110,8 @@
 
 	/* Protect u-boot sectors */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + (256*1024) - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + (256*1024) - 1,
 			&flash_info[0]);
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -135,7 +135,7 @@
 {
 	int i, j;
 
-	for (j=0; j<CFG_MAX_FLASH_BANKS; j++) {
+	for (j=0; j<CONFIG_SYS_MAX_FLASH_BANKS; j++) {
 
 		switch (info->flash_id & FLASH_VENDMASK) {
 
@@ -235,7 +235,7 @@
 
 			while ((*addr & 0x0080) != 0x0080) {
 				PRINTK(".");
-				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = 0x00B0; /* suspend erase*/
 					*addr = 0x00FF; /* read mode    */
 					rc = ERR_TIMOUT;
@@ -306,7 +306,7 @@
 
 	/* wait while polling the status register */
 	while(((val = *addr) & 0x80) != 0x80) {
-		if (get_timer_masked() > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			rc = ERR_TIMOUT;
 			*addr = 0xB0; /* suspend program command */
 			goto outahere;
diff --git a/board/innokom/lowlevel_init.S b/board/innokom/lowlevel_init.S
index 4c9f10f..9892430 100644
--- a/board/innokom/lowlevel_init.S
+++ b/board/innokom/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -54,71 +54,71 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 /*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
 /*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
 /*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
 /* */
@@ -168,17 +168,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CFG_MSC0_VAL
+	ldr     r2,   =CONFIG_SYS_MSC0_VAL
 	str     r2,   [r1, #MSC0_OFFSET]
 	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CFG_MSC1_VAL
+	ldr     r2,  =CONFIG_SYS_MSC1_VAL
 	str     r2,  [r1, #MSC1_OFFSET]
 	ldr     r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CFG_MSC2_VAL
+	ldr     r2,  =CONFIG_SYS_MSC2_VAL
 	str     r2,  [r1, #MSC2_OFFSET]
 	ldr     r2,  [r1, #MSC2_OFFSET]
 
@@ -187,37 +187,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CFG_MECR_VAL
+	ldr     r2,  =CONFIG_SYS_MECR_VAL
 	str     r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CFG_MCMEM0_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 	str     r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CFG_MCMEM1_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 	str     r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CFG_MCATT0_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 	str     r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CFG_MCATT1_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 	str     r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CFG_MCIO0_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 	str     r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CFG_MCIO1_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 	str     r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
@@ -239,7 +239,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr	r3,	=CFG_MDREFR_VAL
+	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
@@ -269,7 +269,7 @@
 	/* Step 4a: assert MDREFR:K?RUN and configure                       */
 	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 
-	ldr	r4,	=CFG_MDREFR_VAL
+	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
 	ldr	r4,	[r1, #MDREFR_OFFSET]
 
@@ -292,7 +292,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
 	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -325,7 +325,7 @@
 	/*          Jan 2003, Errata #116, page 30.                         */
 
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2, [r3]
 	str	r2, [r3]
 	str	r2, [r3]
@@ -345,7 +345,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,  =CFG_MDMRS_VAL
+	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 	str     r2,  [r1, #MDMRS_OFFSET]
 
 
diff --git a/board/integratorap/flash.c b/board/integratorap/flash.c
index b120d63..0492be7 100644
--- a/board/integratorap/flash.c
+++ b/board/integratorap/flash.c
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -88,7 +88,7 @@
 {
 	int i;
 	ulong size = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -104,8 +104,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	return size;
 }
@@ -223,10 +223,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -318,7 +318,7 @@
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
 					if (get_timer_masked () >
-					CFG_FLASH_ERASE_TOUT) {
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
 					*addr = (FPW) 0x00B000B0;
@@ -454,7 +454,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c
index 687c486..ddacabb 100644
--- a/board/integratorap/integratorap.c
+++ b/board/integratorap/integratorap.c
@@ -519,7 +519,7 @@
  * can be divided by 16 or 256
  * and is a 16-bit counter
  */
-/* U-Boot expects a 32 bit timer running at CFG_HZ*/
+/* U-Boot expects a 32 bit timer running at CONFIG_SYS_HZ*/
 static ulong timestamp;		/* U-Boot ticks since startup	      */
 static ulong total_count = 0;	/* Total timer count		      */
 static ulong lastdec;		/* Timer reading at last call	      */
@@ -527,12 +527,12 @@
 static ulong div_timer	 = 1;	/* Divisor to convert timer reading
 				 * change to U-Boot ticks
 				 */
-/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
 
 #define TIMER_LOAD_VAL 0x0000FFFFL
-#define READ_TIMER ((*(volatile ulong *)(CFG_TIMERBASE+4)) & 0x0000FFFFL)
+#define READ_TIMER ((*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4)) & 0x0000FFFFL)
 
-/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
  *  - unless otherwise stated
  */
 
@@ -543,7 +543,7 @@
 int interrupt_init (void)
 {
 	/* Load timer with initial value */
-	*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
 	/* Set timer to be
 	 *	enabled		  1
 	 *	free-running	  0
@@ -551,12 +551,12 @@
 	 *	divider 256	 10
 	 *	XX		 00
 	 */
-	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x00000088;
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x00000088;
 	total_count = 0;
 	/* init the timestamp and lastdec value */
 	reset_timer_masked();
 
-	div_timer  = CFG_HZ_CLOCK / CFG_HZ;
+	div_timer  = CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ;
 	div_timer /= div_clock;
 
 	return (0);
@@ -588,7 +588,7 @@
 	ulong tmo, tmp;
 
 	/* Convert to U-Boot ticks */
-	tmo  = usec * CFG_HZ;
+	tmo  = usec * CONFIG_SYS_HZ;
 	tmo /= (1000000L);
 
 	tmp  = get_timer_masked();	/* get current timestamp */
@@ -647,7 +647,7 @@
  */
 ulong get_tbclk (void)
 {
-	return CFG_HZ_CLOCK/div_clock;
+	return CONFIG_SYS_HZ_CLOCK/div_clock;
 }
 
 int board_eth_init(bd_t *bis)
diff --git a/board/integratorcp/flash.c b/board/integratorcp/flash.c
index 7effea6..5059dae 100644
--- a/board/integratorcp/flash.c
+++ b/board/integratorcp/flash.c
@@ -37,7 +37,7 @@
 #define DEBUG
 
 #define PHYS_FLASH_SECT_SIZE	0x00040000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -106,23 +106,23 @@
 	else
 		nbanks = 1;
 
-	if (nbanks > CFG_MAX_FLASH_BANKS)
-		nbanks = CFG_MAX_FLASH_BANKS;
+	if (nbanks > CONFIG_SYS_MAX_FLASH_BANKS)
+		nbanks = CONFIG_SYS_MAX_FLASH_BANKS;
 
 	/* Enable flash write */
 	cpcr[1] |= 3;
 
 	for (i = 0; i < nbanks; i++) {
-		flash_get_size ((FPW *)(CFG_FLASH_BASE + size), &flash_info[i]);
-		flash_get_offsets (CFG_FLASH_BASE + size, &flash_info[i]);
+		flash_get_size ((FPW *)(CONFIG_SYS_FLASH_BASE + size), &flash_info[i]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size, &flash_info[i]);
 		size += flash_info[i].size;
 	}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 #endif
 
 #ifdef CONFIG_ENV_IS_IN_FLASH
@@ -228,8 +228,8 @@
 	else
 		nsects = 64;
 
-	if (nsects > CFG_MAX_FLASH_SECT)
-		nsects = CFG_MAX_FLASH_SECT;
+	if (nsects > CONFIG_SYS_MAX_FLASH_SECT)
+		nsects = CONFIG_SYS_MAX_FLASH_SECT;
 
 	/* Write auto select command: read Manufacturer ID */
 	addr[0x5555] = (FPW) 0x00AA00AA;
@@ -280,10 +280,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -308,7 +308,7 @@
 
 	reset_timer_masked();
 	while (((status = *addr) & (FPW)0x00800080) != 0x00800080) {
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout");
 			break;
 		}
@@ -384,7 +384,7 @@
 				enable_interrupts();
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = (FPW)0x00700070;
 					status = *addr;
 					if ((status & (FPW) 0x00400040) == (FPW) 0x00400040) {
@@ -538,7 +538,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 #ifdef DEBUG
 			*addr = (FPW) 0x00700070;
 			status = *addr;
diff --git a/board/integratorcp/integratorcp.c b/board/integratorcp/integratorcp.c
index 220513f..72629ce 100644
--- a/board/integratorcp/integratorcp.c
+++ b/board/integratorcp/integratorcp.c
@@ -143,7 +143,7 @@
  * can be divided by 16 or 256
  * and can be set up as a 32-bit timer
  */
-/* U-Boot expects a 32 bit timer, running at CFG_HZ */
+/* U-Boot expects a 32 bit timer, running at CONFIG_SYS_HZ */
 /* Keep total timer count to avoid losing decrements < div_timer */
 static unsigned long long total_count = 0;
 static unsigned long long lastdec;	 /* Timer reading at last call	   */
@@ -151,13 +151,13 @@
 static unsigned long long div_timer = 1; /* Divisor to convert timer reading
 					  * change to U-Boot ticks
 					  */
-/* CFG_HZ = CFG_HZ_CLOCK/(div_clock * div_timer) */
+/* CONFIG_SYS_HZ = CONFIG_SYS_HZ_CLOCK/(div_clock * div_timer) */
 static ulong timestamp;		/* U-Boot ticks since startup	      */
 
 #define TIMER_LOAD_VAL ((ulong)0xFFFFFFFF)
-#define READ_TIMER (*(volatile ulong *)(CFG_TIMERBASE+4))
+#define READ_TIMER (*(volatile ulong *)(CONFIG_SYS_TIMERBASE+4))
 
-/* all function return values in U-Boot ticks i.e. (1/CFG_HZ) sec
+/* all function return values in U-Boot ticks i.e. (1/CONFIG_SYS_HZ) sec
  *  - unless otherwise stated
  */
 
@@ -166,7 +166,7 @@
 int interrupt_init (void)
 {
 	/* Load timer with initial value */
-	*(volatile ulong *)(CFG_TIMERBASE + 0) = TIMER_LOAD_VAL;
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 0) = TIMER_LOAD_VAL;
 	/* Set timer to be
 	 *	enabled		  1
 	 *	periodic	  1
@@ -176,12 +176,12 @@
 	 *	32 bit		  1
 	 *	wrapping	  0
 	 */
-	*(volatile ulong *)(CFG_TIMERBASE + 8) = 0x000000C2;
+	*(volatile ulong *)(CONFIG_SYS_TIMERBASE + 8) = 0x000000C2;
 	/* init the timestamp */
 	total_count = 0ULL;
 	reset_timer_masked();
 
-	div_timer  = (unsigned long long)(CFG_HZ_CLOCK / CFG_HZ);
+	div_timer  = (unsigned long long)(CONFIG_SYS_HZ_CLOCK / CONFIG_SYS_HZ);
 	div_timer /= div_clock;
 
 	return (0);
@@ -212,7 +212,7 @@
 	ulong tmo, tmp;
 
 	/* Convert to U-Boot ticks */
-	tmo  = usec * CFG_HZ;
+	tmo  = usec * CONFIG_SYS_HZ;
 	tmo /= (1000000L);
 
 	tmp  = get_timer_masked();	/* get current timestamp */
@@ -275,5 +275,5 @@
  */
 ulong get_tbclk (void)
 {
-	return (ulong)(((unsigned long long)CFG_HZ_CLOCK)/div_clock);
+	return (ulong)(((unsigned long long)CONFIG_SYS_HZ_CLOCK)/div_clock);
 }
diff --git a/board/ip860/flash.c b/board/ip860/flash.c
index 10a96c5..6491af2 100644
--- a/board/ip860/flash.c
+++ b/board/ip860/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -50,7 +50,7 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t	*immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t	*immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t	*memctl = &immap->im_memctl;
 	volatile ip860_bcsr_t	*bcsr   = (ip860_bcsr_t *)BCSR_BASE;
 	unsigned long size;
@@ -61,7 +61,7 @@
 	 */
 	bcsr->bd_ctrl |= BD_CTRL_FLWE;
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -75,22 +75,22 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br1 = (CFG_FLASH_BASE & BR_BA_MSK) |
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br1 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) |
 				(memctl->memc_br1 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -309,7 +309,7 @@
 			udelay (1000);
 
 			while ((*addr & 0x00800080) != 0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0xFFFFFFFF;	/* reset bank */
 					return 1;
@@ -434,7 +434,7 @@
 	start = get_timer (0);
 	flag  = 0;
 	while (((csr = *addr) & 0x00800080) != 0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			flag = 1;
 			break;
 		}
diff --git a/board/ip860/ip860.c b/board/ip860/ip860.c
index 375cd4d..e2a1851 100644
--- a/board/ip860/ip860.c
+++ b/board/ip860/ip860.c
@@ -87,12 +87,12 @@
 /* ------------------------------------------------------------------------- */
 int board_early_init_f(void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 /* init BCSR chipselect line for ip860_get_clk_freq() and ip860_get_dram_size() */
-    memctl->memc_or4 = CFG_OR4;
-    memctl->memc_br4 = CFG_BR4;
+    memctl->memc_or4 = CONFIG_SYS_OR4;
+    memctl->memc_br4 = CONFIG_SYS_BR4;
 
     return 0;
 }
@@ -139,7 +139,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 	ulong refresh_val;
@@ -167,8 +167,8 @@
 	/*
 	 * Map controller banks 2 to the SDRAM address
 	 */
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 
 	/* IP860 boards have only one bank SDRAM */
 
@@ -197,7 +197,7 @@
 	udelay (1000);
 
 	memctl->memc_or2 = ((-size) & 0xFFFF0000) | SDRAM_TIMING;
-	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	udelay (10000);
 
@@ -205,34 +205,34 @@
 	 * Also, map other memory to correct position
 	 */
 
-#if (defined(CFG_OR1) && defined(CFG_BR1_PRELIM))
-	memctl->memc_or1 = CFG_OR1;
-	memctl->memc_br1 = CFG_BR1;
+#if (defined(CONFIG_SYS_OR1) && defined(CONFIG_SYS_BR1_PRELIM))
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
 #endif
 
-#if defined(CFG_OR3) && defined(CFG_BR3)
-	memctl->memc_or3 = CFG_OR3;
-	memctl->memc_br3 = CFG_BR3;
+#if defined(CONFIG_SYS_OR3) && defined(CONFIG_SYS_BR3)
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
 #endif
 
-#if defined(CFG_OR4) && defined(CFG_BR4)
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+#if defined(CONFIG_SYS_OR4) && defined(CONFIG_SYS_BR4)
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 #endif
 
-#if defined(CFG_OR5) && defined(CFG_BR5)
-	memctl->memc_or5 = CFG_OR5;
-	memctl->memc_br5 = CFG_BR5;
+#if defined(CONFIG_SYS_OR5) && defined(CONFIG_SYS_BR5)
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
 #endif
 
-#if defined(CFG_OR6) && defined(CFG_BR6)
-	memctl->memc_or6 = CFG_OR6;
-	memctl->memc_br6 = CFG_BR6;
+#if defined(CONFIG_SYS_OR6) && defined(CONFIG_SYS_BR6)
+	memctl->memc_or6 = CONFIG_SYS_OR6;
+	memctl->memc_br6 = CONFIG_SYS_BR6;
 #endif
 
-#if defined(CFG_OR7) && defined(CFG_BR7)
-	memctl->memc_or7 = CFG_OR7;
-	memctl->memc_br7 = CFG_BR7;
+#if defined(CONFIG_SYS_OR7) && defined(CONFIG_SYS_BR7)
+	memctl->memc_or7 = CONFIG_SYS_OR7;
+	memctl->memc_br7 = CONFIG_SYS_BR7;
 #endif
 
 	return (size);
@@ -251,7 +251,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 						   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -263,7 +263,7 @@
 
 void reset_phy (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	ulong mask = PB_ENET_RESET | PB_ENET_JABD;
 	ulong reg;
 
diff --git a/board/iphase4539/flash.c b/board/iphase4539/flash.c
index 098dcc2..3dfee1f 100644
--- a/board/iphase4539/flash.c
+++ b/board/iphase4539/flash.c
@@ -31,7 +31,7 @@
 #include <flash.h>
 #include <asm/io.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 extern int hwc_flash_size(void);
 static ulong flash_get_size (u32 addr, flash_info_t *info);
@@ -52,26 +52,26 @@
 	unsigned int bank = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = 0;
 		flash_info[i].size = 0;
 	}
 
 	/* Initialise the BOOT Flash */
-	if (bank == CFG_MAX_FLASH_BANKS) {
+	if (bank == CONFIG_SYS_MAX_FLASH_BANKS) {
 		puts ("Warning: not all Flashes are initialised !");
 		return flash_size;
 	}
 
-	bank_size = flash_get_size (CFG_FLASH_BASE, flash_info + bank);
+	bank_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info + bank);
 	if (bank_size) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
-    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_MAX_FLASH_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MAX_FLASH_SIZE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      flash_info + bank);
 #endif
 
@@ -85,8 +85,8 @@
 
 		/* HWC protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_FLASH_BASE,
-			      CFG_FLASH_BASE + 0x10000 - 1,
+			      CONFIG_SYS_FLASH_BASE,
+			      CONFIG_SYS_FLASH_BASE + 0x10000 - 1,
 			      flash_info + bank);
 
 		flash_size += bank_size;
@@ -144,10 +144,10 @@
 	case AMD_ID_LV033C:
 		info->flash_id += FLASH_AM033C;
 		info->size = hwc_flash_size();
-		if (info->size > CFG_MAX_FLASH_SIZE) {
+		if (info->size > CONFIG_SYS_MAX_FLASH_SIZE) {
 			printf("U-Boot supports only %d MB\n",
-			       CFG_MAX_FLASH_SIZE);
-			info->size = CFG_MAX_FLASH_SIZE;
+			       CONFIG_SYS_MAX_FLASH_SIZE);
+			info->size = CONFIG_SYS_MAX_FLASH_SIZE;
 		}
 		info->sector_count = info->size / 0x10000;
 		break;				/* => 4 MB		*/
@@ -281,7 +281,7 @@
 	last  = start;
 	addr = info->start[l_sect];
 	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -421,7 +421,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((in32(dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 		iobarrier_rw();
diff --git a/board/iphase4539/iphase4539.c b/board/iphase4539/iphase4539.c
index e5d0254..7fec2cc 100644
--- a/board/iphase4539/iphase4539.c
+++ b/board/iphase4539/iphase4539.c
@@ -195,16 +195,16 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *base;
 	ulong maxsize;
 	int i;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	immap->im_siu_conf.sc_ppc_acr = 0x00000026;
 	immap->im_siu_conf.sc_ppc_alrh = 0x01276345;
 	immap->im_siu_conf.sc_ppc_alrl = 0x89ABCDEF;
@@ -217,7 +217,7 @@
 	/* Init Main SDRAM */
 #define OP_VALUE   0x404A241A
 #define OP_VALUE_M (OP_VALUE & 0x87FFFFFF);
-	base = (uchar *) CFG_SDRAM_BASE;
+	base = (uchar *) CONFIG_SYS_SDRAM_BASE;
 	memctl->memc_psdmr = 0x28000000 | OP_VALUE_M;
 	*base = 0xFF;
 	memctl->memc_psdmr = 0x08000000 | OP_VALUE_M;
diff --git a/board/ispan/ispan.c b/board/ispan/ispan.c
index 12fb91f..9254e0a 100644
--- a/board/ispan/ispan.c
+++ b/board/ispan/ispan.c
@@ -39,31 +39,31 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
-#define CFG_FCC3 (CONFIG_ETHER_INDEX == 3)
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC3 (CONFIG_ETHER_INDEX == 3)
 
 const iop_conf_t iop_conf_tab[4][32] = {
     /* Port A */
     {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
-	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
-	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
-	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
-	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
-	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL   */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS   */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER */
 	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25 */
 	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24 */
 	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23 */
 	/* PA22 */ { 0,          0,   0,   0,   0,   0 }, /* PA22 */
-	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
 	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13 */
 	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12 */
 	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11 */
@@ -82,34 +82,34 @@
 
     /* Port B */
     {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
-	/* PB17 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
-	/* PB16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
-	/* PB15 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
-	/* PB14 */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
-	/* PB13 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
-	/* PB12 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
-	/* PB11 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
-	/* PB10 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
-	/* PB9  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
-	/* PB8  */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
-	/* PB7  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
-	/* PB6  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
-	/* PB5  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
-	/* PB4  */ { CFG_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB17 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_DV  */
+	/* PB16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RX_ER  */
+	/* PB15 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_ER  */
+	/* PB14 */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TX_EN  */
+	/* PB13 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII COL    */
+	/* PB12 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII CRS    */
+	/* PB11 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[3] */
+	/* PB10 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[2] */
+	/* PB9  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[1] */
+	/* PB8  */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII RxD[0] */
+	/* PB7  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[0] */
+	/* PB6  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[1] */
+	/* PB5  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[2] */
+	/* PB4  */ { CONFIG_SYS_FCC3,   1,   0,   1,   0,   0 }, /* FCC3 MII TxD[3] */
 	/* PB3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
 	/* PB2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
 	/* PB1  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
@@ -131,9 +131,9 @@
 	/* PC21 */ { 0,          0,   0,   0,   0,   0 }, /* PC21 */
 	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20 */
 	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19 */
-	/* PC18 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
+	/* PC18 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Rx Clock (CLK14) */
 	/* PC17 */ { 0,          0,   0,   0,   0,   0 }, /* PC17 */
-	/* PC16 */ { CFG_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
+	/* PC16 */ { CONFIG_SYS_FCC3,   1,   0,   0,   0,   0 }, /* FCC3 MII Tx Clock (CLK16) */
 	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15 */
 	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14 */
 	/* PC13 */ { 0,          0,   0,   0,   0,   0 }, /* PC13 */
@@ -179,8 +179,8 @@
 	/* PD9  */ { 1,          1,   0,   1,   0,   0 }, /* SMC1 SMTXD */
 	/* PD8  */ { 1,          1,   0,   0,   0,   0 }, /* SMC1 SMRXD */
 	/* PD7  */ { 0,          0,   0,   0,   0,   0 }, /* PD7 */
-	/* PD6  */ { CFG_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
-	/* PD5  */ { CFG_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
+	/* PD6  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   1 }, /* MII PHY Reset  */
+	/* PD5  */ { CONFIG_SYS_FCC3,   0,   0,   1,   0,   0 }, /* MII PHY Enable */
 	/* PD4  */ { 0,          0,   0,   0,   0,   0 }, /* PD4 */
 	/* PD3  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
 	/* PD2  */ { 0,          0,   0,   0,   0,   0 }, /* pin doesn't exist */
@@ -360,8 +360,8 @@
 {
 	long maxsize = hwc_main_sdram_size();
 
-#if !defined(CFG_RAMBOOT) && !defined(CFG_USE_FIRMWARE)
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT) && !defined(CONFIG_SYS_USE_FIRMWARE)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar *base;
 	int i;
@@ -375,37 +375,37 @@
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 	immap->im_siu_conf.sc_ltescr1  = 0x00004000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* Initialise 60x bus SDRAM */
-	base = (uchar *)(CFG_SDRAM_BASE | 0x110);
-	memctl->memc_psrt  = CFG_PSRT;
-	memctl->memc_or1   = CFG_60x_OR;
-	memctl->memc_br1   = CFG_SDRAM_BASE | CFG_60x_BR;
+	base = (uchar *)(CONFIG_SYS_SDRAM_BASE | 0x110);
+	memctl->memc_psrt  = CONFIG_SYS_PSRT;
+	memctl->memc_or1   = CONFIG_SYS_60x_OR;
+	memctl->memc_br1   = CONFIG_SYS_SDRAM_BASE | CONFIG_SYS_60x_BR;
 
-	memctl->memc_psdmr = CFG_PSDMR | 0x28000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x28000000;
 	*base = 0xFF;
-	memctl->memc_psdmr = CFG_PSDMR | 0x08000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x08000000;
 	for (i = 0; i < 8; i++)
 		*base = 0xFF;
-	memctl->memc_psdmr = CFG_PSDMR | 0x18000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x18000000;
 	*base = 0xFF;
-	memctl->memc_psdmr = CFG_PSDMR | 0x40000000;
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | 0x40000000;
 
 	/* Initialise local bus SDRAM */
-	base = (uchar *)CFG_LSDRAM_BASE;
-	memctl->memc_lsrt  = CFG_LSRT;
-	memctl->memc_or2   = CFG_LOC_OR;
-	memctl->memc_br2   = CFG_LSDRAM_BASE | CFG_LOC_BR;
+	base = (uchar *)CONFIG_SYS_LSDRAM_BASE;
+	memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+	memctl->memc_or2   = CONFIG_SYS_LOC_OR;
+	memctl->memc_br2   = CONFIG_SYS_LSDRAM_BASE | CONFIG_SYS_LOC_BR;
 
-	memctl->memc_lsdmr = CFG_LSDMR | 0x28000000;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x28000000;
 	*base = 0xFF;
-	memctl->memc_lsdmr = CFG_LSDMR | 0x08000000;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x08000000;
 	for (i = 0; i < 8; i++)
 		*base = 0xFF;
-	memctl->memc_lsdmr = CFG_LSDMR | 0x18000000;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x18000000;
 	*base = 0xFF;
-	memctl->memc_lsdmr = CFG_LSDMR | 0x40000000;
+	memctl->memc_lsdmr = CONFIG_SYS_LSDMR | 0x40000000;
 
 	/* We must be able to test a location outsize the maximum legal size
 	 * to find out THAT we are outside; but this address still has to be
@@ -420,7 +420,7 @@
 
 	if (maxsize != hwc_main_sdram_size())
 		puts("Oops: memory test has not found all memory!\n");
-#endif /* !CFG_RAMBOOT && !CFG_USE_FIRMWARE */
+#endif /* !CONFIG_SYS_RAMBOOT && !CONFIG_SYS_USE_FIRMWARE */
 
 	/* Return total RAM size (size of 60x SDRAM) */
 	return maxsize;
diff --git a/board/ivm/flash.c b/board/ivm/flash.c
index 29821ba..cf309d7 100644
--- a/board/ivm/flash.c
+++ b/board/ivm/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -50,13 +50,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -72,22 +72,22 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
 				BR_MS_GPCM | BR_PS_16 | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -383,10 +383,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	saddr[0] = 0x00FF;		/* restore read mode */
@@ -454,7 +454,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & 0x0080) != 0x0080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0x00FF;	/* reset to read mode */
 					return 1;
@@ -583,7 +583,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & 0x0080) != 0x0080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = 0x00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/ivm/ivm.c b/board/ivm/ivm.c
index 4882f04..9bec198 100644
--- a/board/ivm/ivm.c
+++ b/board/ivm/ivm.c
@@ -161,28 +161,28 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 	long int size_b0;
 
 	/* enable SDRAM clock ("switch on" SDRAM) */
-	immr->im_cpm.cp_pbpar &= ~(CFG_PB_SDRAM_CLKE);	/* GPIO */
-	immr->im_cpm.cp_pbodr &= ~(CFG_PB_SDRAM_CLKE);	/* active output */
-	immr->im_cpm.cp_pbdir |= CFG_PB_SDRAM_CLKE;	/* output */
-	immr->im_cpm.cp_pbdat |= CFG_PB_SDRAM_CLKE;	/* assert SDRAM CLKE */
+	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_SDRAM_CLKE);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_SDRAM_CLKE);	/* active output */
+	immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_SDRAM_CLKE;	/* output */
+	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_SDRAM_CLKE;	/* assert SDRAM CLKE */
 	udelay (1);
 
 	/*
 	 * Map controller bank 1 for ELIC SACCO
 	 */
-	memctl->memc_or1 = CFG_OR1;
-	memctl->memc_br1 = CFG_BR1;
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
 
 	/*
 	 * Map controller bank 2 for ELIC EPIC
 	 */
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 
 	/*
 	 * Configure UPMA for SHARC
@@ -194,15 +194,15 @@
 	/*
 	 * Map controller bank 4 for HDLC Address space
 	 */
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 #endif
 
 	/*
 	 * Map controller bank 5 for SHARC
 	 */
-	memctl->memc_or5 = CFG_OR5;
-	memctl->memc_br5 = CFG_BR5;
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
 
 	memctl->memc_mamr = 0x00001000;
 
@@ -212,17 +212,17 @@
 	upmconfig (UPMB, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
 
-	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MBMR_8COL;	/* refresh not enabled yet */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;	/* refresh not enabled yet */
 
 	udelay (200);
 	memctl->memc_mcr = 0x80806105;	/* precharge */
@@ -251,10 +251,10 @@
 	 * Check Bank 0 Memory Size for re-configuration
 	 */
 	size_b0 =
-		dram_size (CFG_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
+		dram_size (CONFIG_SYS_MBMR_8COL, (long *) SDRAM_BASE3_PRELIM,
 			   SDRAM_MAX_SIZE);
 
-	memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 
 	return (size_b0);
 }
@@ -272,7 +272,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	memctl->memc_mbmr = mamr_value;
@@ -284,13 +284,13 @@
 
 void reset_phy (void)
 {
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* De-assert Ethernet Powerdown */
-	immr->im_cpm.cp_pbpar &= ~(CFG_PB_ETH_POWERDOWN);	/* GPIO */
-	immr->im_cpm.cp_pbodr &= ~(CFG_PB_ETH_POWERDOWN);	/* active output */
-	immr->im_cpm.cp_pbdir |= CFG_PB_ETH_POWERDOWN;	/* output */
-	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN);	/* Enable PHY power */
+	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* active output */
+	immr->im_cpm.cp_pbdir |= CONFIG_SYS_PB_ETH_POWERDOWN;	/* output */
+	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* Enable PHY power */
 	udelay (1000);
 
 	/*
@@ -302,13 +302,13 @@
 	 * Note: The RESET pin is high active, but there is an
 	 *       inverter on the SPD823TS board...
 	 */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_ETH_RESET);
-	immr->im_ioport.iop_pcdir |= CFG_PC_ETH_RESET;
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_ETH_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_ETH_RESET;
 	/* assert RESET signal of PHY */
-	immr->im_ioport.iop_pcdat &= ~(CFG_PC_ETH_RESET);
+	immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_ETH_RESET);
 	udelay (10);
 	/* de-assert RESET signal of PHY */
-	immr->im_ioport.iop_pcdat |= CFG_PC_ETH_RESET;
+	immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_ETH_RESET;
 	udelay (10);
 }
 
@@ -332,21 +332,21 @@
 
 void ide_set_reset (int on)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Configure PC for IDE Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 	} else {		/* release RESET */
-		immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+		immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 	}
 
 	/* program port pin as GPIO output */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/ixdp425/flash.c b/board/ixdp425/flash.c
index 0bae9e0..f1d9190 100644
--- a/board/ixdp425/flash.c
+++ b/board/ixdp425/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -81,8 +81,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + _bss_start - _armboot_start,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -198,10 +198,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -270,7 +270,7 @@
 				 *addr) & (FPW) 0x00800080) !=
 			       (FPW) 0x00800080) {
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase         */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -406,7 +406,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/ixdp425/ixdp425.c b/board/ixdp425/ixdp425.c
index b379c75..43ac8f6 100644
--- a/board/ixdp425/ixdp425.c
+++ b/board/ixdp425/ixdp425.c
@@ -54,25 +54,25 @@
 	/*
 	 * Get realtek RTL8305 switch and SLIC out of reset
 	 */
-	GPIO_OUTPUT_SET(CFG_GPIO_SWITCH_RESET_N);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_SWITCH_RESET_N);
-	GPIO_OUTPUT_SET(CFG_GPIO_SLIC_RESET_N);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_SLIC_RESET_N);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SWITCH_RESET_N);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SWITCH_RESET_N);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SLIC_RESET_N);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SLIC_RESET_N);
 
 	/*
 	 * Setup GPIO's for PCI INTA & INTB
 	 */
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA_N);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA_N);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB_N);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB_N);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA_N);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA_N);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB_N);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB_N);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
 	*IXP425_GPIO_GPCLKR = 0x01FF01FF;
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PCI_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_EXTBUS_CLK);
 #endif
 
 	return 0;
diff --git a/board/jse/flash.c b/board/jse/flash.c
index c462fe0..92acdb1 100644
--- a/board/jse/flash.c
+++ b/board/jse/flash.c
@@ -32,10 +32,10 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-#if CFG_MAX_FLASH_BANKS != 1
-#error "CFG_MAX_FLASH_BANKS must be 1"
+#if CONFIG_SYS_MAX_FLASH_BANKS != 1
+#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
 #endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	*/
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -281,7 +281,7 @@
 	last = start;
 	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
 	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return -1;
 		}
@@ -510,7 +510,7 @@
 		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/jse/jse.c b/board/jse/jse.c
index 9290814..6a6b9dd 100644
--- a/board/jse/jse.c
+++ b/board/jse/jse.c
@@ -67,7 +67,7 @@
 
 	/* EBC0_B1CR: BAS=x, BS=0(1MB), BU=3(R/W), BW=0(8bits) */
 	mtdcr (ebccfga, pb1cr);
-	mtdcr (ebccfgd, CFG_SYSTEMACE_BASE | 0x00018000);
+	mtdcr (ebccfgd, CONFIG_SYS_SYSTEMACE_BASE | 0x00018000);
 
 	/* Enable the /PerWE output as /PerWE, instead of /PCIINT. */
 	/* CPC0_CR1 |= PCIPW */
@@ -95,11 +95,11 @@
 
 	/* check that the SystemACE chip is alive. */
 	printf ("ACE:   ");
-	vers = readw (CFG_SYSTEMACE_BASE + 0x16);
+	vers = readw (CONFIG_SYS_SYSTEMACE_BASE + 0x16);
 	printf ("SystemACE %u.%u (build %u)",
 		(vers >> 12) & 0x0f, (vers >> 8) & 0x0f, vers & 0xff);
 
-	status = readl (CFG_SYSTEMACE_BASE + 0x04);
+	status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
 #ifdef DEBUG
 	printf (" STATUS=0x%08x", status);
 #endif
@@ -110,23 +110,23 @@
 
 		if (status & 0x04) {
 			/* CONTROLREG = CFGPROG */
-			writew (0x1000, CFG_SYSTEMACE_BASE + 0x18);
+			writew (0x1000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
 			udelay (500);
 			/* CONTROLREG = CFGRESET */
-			writew (0x0080, CFG_SYSTEMACE_BASE + 0x18);
+			writew (0x0080, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
 			udelay (500);
-			writew (0x0000, CFG_SYSTEMACE_BASE + 0x18);
+			writew (0x0000, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
 			/* CONTROLREG = CFGSTART */
-			writew (0x0020, CFG_SYSTEMACE_BASE + 0x18);
+			writew (0x0020, CONFIG_SYS_SYSTEMACE_BASE + 0x18);
 
-			status = readl (CFG_SYSTEMACE_BASE + 0x04);
+			status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
 		}
 	}
 
 	/* Wait for the SystemACE to program its chain of devices. */
 	while ((status & 0x84) == 0x00) {
 		udelay (500);
-		status = readl (CFG_SYSTEMACE_BASE + 0x04);
+		status = readl (CONFIG_SYS_SYSTEMACE_BASE + 0x04);
 	}
 
 	if (status & 0x04)
diff --git a/board/jse/sdram.c b/board/jse/sdram.c
index 8ba6c45..a1f526d 100644
--- a/board/jse/sdram.c
+++ b/board/jse/sdram.c
@@ -151,7 +151,7 @@
 	/* Start memory test. */
 	printf ("test: %u MB - ", SDRAM_LEN / 1048576);
 
-	sdram = (unsigned long *) CFG_SDRAM_BASE;
+	sdram = (unsigned long *) CONFIG_SYS_SDRAM_BASE;
 
 	printf ("write - ");
 	for (idx = 2; idx < SDRAM_LEN / 4; idx += 2) {
diff --git a/board/jupiter/jupiter.c b/board/jupiter/jupiter.c
index 7913c75..6e752c6 100644
--- a/board/jupiter/jupiter.c
+++ b/board/jupiter/jupiter.c
@@ -45,7 +45,7 @@
 #define SDRAM_CONFIG2	0x88b70004
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -88,7 +88,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -98,7 +98,7 @@
 	ulong dramsize2 = 0;
 	uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -119,9 +119,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -147,10 +147,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -172,7 +172,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -190,7 +190,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -244,9 +244,9 @@
 {
 	if (size == 0x1000000) { /* adjust mapping */
 		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CFG_BOOTCS_START | size);
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
 		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CFG_BOOTCS_START | size, size);
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 #if defined(CONFIG_MPC5200)
 	*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 25); /* disable CS_BOOT */
diff --git a/board/keymile/common/common.c b/board/keymile/common/common.c
index 18982cd..61276d2 100644
--- a/board/keymile/common/common.c
+++ b/board/keymile/common/common.c
@@ -196,9 +196,9 @@
 	unsigned long	crc;
 	unsigned long	crceeprom;
 
-	crc = ivm_calc_crc (buf, CFG_IVM_EEPROM_PAGE_LEN - 2);
-	crceeprom = (buf[CFG_IVM_EEPROM_PAGE_LEN - 1] + \
-			buf[CFG_IVM_EEPROM_PAGE_LEN - 2] * 256);
+	crc = ivm_calc_crc (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2);
+	crceeprom = (buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 1] + \
+			buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN - 2] * 256);
 	if (crc != crceeprom) {
 		printf ("Error CRC Block: %d EEprom: calculated: %lx EEprom: %lx\n",
 			block, crc, crceeprom);
@@ -209,7 +209,7 @@
 
 static int ivm_analyze_block2 (unsigned char *buf, int len)
 {
-	unsigned char	valbuf[CFG_IVM_EEPROM_PAGE_LEN];
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
 	unsigned long	count;
 
 	/* IVM_MacAddress */
@@ -238,21 +238,21 @@
 int ivm_analyze_eeprom (unsigned char *buf, int len)
 {
 	unsigned short	val;
-	unsigned char	valbuf[CFG_IVM_EEPROM_PAGE_LEN];
+	unsigned char	valbuf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN];
 	unsigned char	*tmp;
 
 	if (ivm_check_crc (buf, 0) != 0)
 		return -1;
 
-	ivm_get_value (buf, CFG_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1);
-	val = ivm_get_value (buf, CFG_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1);
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_BoardId", 0, 1);
+	val = ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_HWKey", 6, 1);
 	if (val != 0xffff) {
 		sprintf ((char *)valbuf, "%x", ((val /100) % 10));
 		ivm_set_value ("IVM_HWVariant", (char *)valbuf);
 		sprintf ((char *)valbuf, "%x", (val % 100));
 		ivm_set_value ("IVM_HWVersion", (char *)valbuf);
 	}
-	ivm_get_value (buf, CFG_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0);
+	ivm_get_value (buf, CONFIG_SYS_IVM_EEPROM_PAGE_LEN, "IVM_Functions", 12, 0);
 
 	GET_STRING("IVM_Symbol", IVM_POS_SYMBOL_ONLY, 8)
 	GET_STRING("IVM_DeviceName", IVM_POS_SHORT_TEXT, 64)
@@ -283,9 +283,9 @@
 	GET_STRING("IVM_CustomerID", IVM_POS_CUSTOMER_ID, 32)
 	GET_STRING("IVM_CustomerProductID", IVM_POS_CUSTOMER_PROD_ID, 32)
 
-	if (ivm_check_crc (&buf[CFG_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
+	if (ivm_check_crc (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], 2) != 0)
 		return -2;
-	ivm_analyze_block2 (&buf[CFG_IVM_EEPROM_PAGE_LEN * 2], CFG_IVM_EEPROM_PAGE_LEN);
+	ivm_analyze_block2 (&buf[CONFIG_SYS_IVM_EEPROM_PAGE_LEN * 2], CONFIG_SYS_IVM_EEPROM_PAGE_LEN);
 
 	return 0;
 }
@@ -293,13 +293,13 @@
 int ivm_read_eeprom (void)
 {
 	I2C_MUX_DEVICE *dev = NULL;
-	uchar i2c_buffer[CFG_IVM_EEPROM_MAX_LEN];
+	uchar i2c_buffer[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
 	uchar	*buf;
-	unsigned dev_addr = CFG_IVM_EEPROM_ADR;
+	unsigned dev_addr = CONFIG_SYS_IVM_EEPROM_ADR;
 
 	/* First init the Bus, select the Bus */
-#if defined(CFG_I2C_IVM_BUS)
-	dev = i2c_mux_ident_muxstring ((uchar *)CFG_I2C_IVM_BUS);
+#if defined(CONFIG_SYS_I2C_IVM_BUS)
+	dev = i2c_mux_ident_muxstring ((uchar *)CONFIG_SYS_I2C_IVM_BUS);
 #else
 	buf = (unsigned char *) getenv ("EEprom_ivm");
 	if (buf != NULL)
@@ -315,24 +315,24 @@
 	if (buf != NULL)
 		dev_addr = simple_strtoul ((char *)buf, NULL, 16);
 
-	if (eeprom_read (dev_addr, 0, i2c_buffer, CFG_IVM_EEPROM_MAX_LEN) != 0) {
+	if (eeprom_read (dev_addr, 0, i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN) != 0) {
 		printf ("Error reading EEprom\n");
 		return -2;
 	}
 
-	return ivm_analyze_eeprom (i2c_buffer, CFG_IVM_EEPROM_MAX_LEN);
+	return ivm_analyze_eeprom (i2c_buffer, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
 }
 
-#if defined(CFG_I2C_INIT_BOARD)
+#if defined(CONFIG_SYS_I2C_INIT_BOARD)
 #define DELAY_ABORT_SEQ		62
-#define DELAY_HALF_PERIOD	(500 / (CFG_I2C_SPEED / 1000))
+#define DELAY_HALF_PERIOD	(500 / (CONFIG_SYS_I2C_SPEED / 1000))
 
 #if defined(CONFIG_MGCOGE)
 #define SDA_MASK	0x00010000
 #define SCL_MASK	0x00020000
 static void set_pin (int state, unsigned long mask)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
 
 	if (state)
 		iop->pdat |= (mask);
@@ -344,7 +344,7 @@
 
 static int get_pin (unsigned long mask)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
 
 	iop->pdir &= ~(mask);
 	return (0 != (iop->pdat & (mask)));
@@ -373,7 +373,7 @@
 #if defined(CONFIG_HARD_I2C)
 static void setports (int gpio)
 {
-	volatile ioport_t *iop = ioport_addr ((immap_t *)CFG_IMMR, 3);
+	volatile ioport_t *iop = ioport_addr ((immap_t *)CONFIG_SYS_IMMR, 3);
 
 	if (gpio) {
 		iop->ppar &= ~(SDA_MASK | SCL_MASK);
@@ -474,7 +474,7 @@
 void i2c_init_board(void)
 {
 #if defined(CONFIG_HARD_I2C)
-	volatile immap_t *immap = (immap_t *)CFG_IMMR ;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR ;
 	volatile i2c8260_t *i2c	= (i2c8260_t *)&immap->im_i2c;
 
 	/* disable I2C controller first, otherwhise it thinks we want to    */
diff --git a/board/keymile/mgcoge/mgcoge.c b/board/keymile/mgcoge/mgcoge.c
index 31703ab..7d4d9e6 100644
--- a/board/keymile/mgcoge/mgcoge.c
+++ b/board/keymile/mgcoge/mgcoge.c
@@ -238,7 +238,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -249,7 +249,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -262,20 +262,20 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 	long psize;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	psize = try_init (memctl, CFG_PSDMR, CFG_OR1,
-						  (uchar *) CFG_SDRAM_BASE);
-#endif /* CFG_RAMBOOT */
+	psize = try_init (memctl, CONFIG_SYS_PSDMR, CONFIG_SYS_OR1,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -295,8 +295,8 @@
 int board_early_init_r (void)
 {
 	/* setup the UPIOx */
-	*(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
-	*(char *)(CFG_PIGGY_BASE + 0x03) = 0x15;
+	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
+	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x15;
 	return 0;
 }
 
@@ -332,12 +332,12 @@
 			"err:%s\n", fdt_strerror (nodeoffset));
 	}
 	/* update Flash addr, size */
-	flash_data[2] = cpu_to_be32 (CFG_FLASH_BASE);
-	flash_data[3] = cpu_to_be32 (CFG_FLASH_SIZE);
+	flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+	flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
 	flash_data[4] = cpu_to_be32 (1);
 	flash_data[5] = cpu_to_be32 (0);
-	flash_data[6] = cpu_to_be32 (CFG_FLASH_BASE_1);
-	flash_data[7] = cpu_to_be32 (CFG_FLASH_SIZE_1);
+	flash_data[6] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE_1);
+	flash_data[7] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE_1);
 	nodeoffset = fdt_path_offset (blob, "/localbus");
 	if (nodeoffset >= 0) {
 		ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
diff --git a/board/keymile/mgsuvd/mgsuvd.c b/board/keymile/mgsuvd/mgsuvd.c
index ecc8d75..912e177 100644
--- a/board/keymile/mgsuvd/mgsuvd.c
+++ b/board/keymile/mgsuvd/mgsuvd.c
@@ -70,7 +70,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -83,7 +83,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/*
 	 * The following value is used as an address (i.e. opcode) for
@@ -98,17 +98,17 @@
 	 *       |  +----------- Operating Mode = Standard
 	 *       +-------------- Write Burst Mode = Programmed Burst Length
 	 */
-	memctl->memc_mar = CFG_MAR;
+	memctl->memc_mar = CONFIG_SYS_MAR;
 
 	/*
 	 * Map controller banks 1 to the SDRAM banks 1 at
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mbmr = CFG_MBMR & (~(MBMR_PTBE));	/* no refresh yet */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR & (~(MBMR_PTBE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -142,8 +142,8 @@
 int board_early_init_r(void)
 {
 	/* setup the UPIOx */
-	*(char *)(CFG_PIGGY_BASE + 0x02) = 0xc0;
-	*(char *)(CFG_PIGGY_BASE + 0x03) = 0x35;
+	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x02) = 0xc0;
+	*(char *)(CONFIG_SYS_PIGGY_BASE + 0x03) = 0x35;
 	return 0;
 }
 
diff --git a/board/korat/config.mk b/board/korat/config.mk
index fa8374f..73180db 100644
--- a/board/korat/config.mk
+++ b/board/korat/config.mk
@@ -35,7 +35,7 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8CFF0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8CFF0000
 endif
 
 ifeq ($(perm),1)
diff --git a/board/korat/init.S b/board/korat/init.S
index bf8b2c8..ea43a1f 100644
--- a/board/korat/init.S
+++ b/board/korat/init.S
@@ -50,27 +50,27 @@
 	 * generated dynamically in the SPD DDR2 detection routine.
 	 */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0,
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0,
 		  AC_R|AC_W|AC_X|SA_G )
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry( CFG_PCI_MEMBASE + 0x00000000, SZ_256M,
-		  CFG_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x00000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x00000000, 1, AC_R|AC_W|SA_G|SA_I )
 
-	tlbentry( CFG_PCI_MEMBASE + 0x10000000, SZ_256M,
-		  CFG_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x10000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x10000000, 1, AC_R|AC_W|SA_G|SA_I )
 
-	tlbentry( CFG_PCI_MEMBASE + 0x20000000, SZ_256M,
-		  CFG_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x20000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x20000000, 1, AC_R|AC_W|SA_G|SA_I )
 
-	tlbentry( CFG_PCI_MEMBASE + 0x30000000, SZ_256M,
-		  CFG_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE + 0x30000000, SZ_256M,
+		  CONFIG_SYS_PCI_MEMBASE + 0x30000000, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for EBC */
-	tlbentry( CFG_CPLD_BASE, SZ_1K, CFG_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CPLD_BASE, SZ_1K, CONFIG_SYS_CPLD_BASE, 1, AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
 	/* I wonder why this must be executable -- lrj@acm.org 2007-10-08 */
diff --git a/board/korat/korat.c b/board/korat/korat.c
index 8787e23..5ad75f7 100644
--- a/board/korat/korat.c
+++ b/board/korat/korat.c
@@ -38,7 +38,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 ulong flash_get_size(ulong base, int banknum);
 
@@ -46,11 +46,11 @@
 void korat_buzzer(int const on)
 {
 	if (on) {
-		out_8((u8 *) CFG_CPLD_BASE + 0x05,
-		      in_8((u8 *) CFG_CPLD_BASE + 0x05) | 0x80);
+		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) | 0x80);
 	} else {
-		out_8((u8 *) CFG_CPLD_BASE + 0x05,
-		      in_8((u8 *) CFG_CPLD_BASE + 0x05) & ~0x80);
+		out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05,
+		      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x05) & ~0x80);
 	}
 }
 #endif
@@ -66,16 +66,16 @@
 
 	extern void korat_branch_absolute(uint32_t addr);
 
-	for (mscount = 0;  mscount < CFG_KORAT_MAN_RESET_MS; ++mscount) {
+	for (mscount = 0;  mscount < CONFIG_SYS_KORAT_MAN_RESET_MS; ++mscount) {
 		udelay(1000);
-		if (gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_)) {
+		if (gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_)) {
 			/* This call does not return. */
 			korat_branch_absolute(
-				CFG_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
+				CONFIG_SYS_FLASH1_TOP - 2 * CONFIG_ENV_SECT_SIZE - 4);
 		}
 	}
 	korat_buzzer(1);
-	while (!gpio_read_in_bit(CFG_GPIO_RESET_PRESSED_))
+	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_RESET_PRESSED_))
 		udelay(1000);
 
 	korat_buzzer(0);
@@ -115,33 +115,33 @@
 	 * Take sim card reader and CF controller out of reset.  Also enable PHY
 	 * auto-detect until board-specific PHY resets are available.
 	 */
-	out_8((u8 *) CFG_CPLD_BASE + 0x02, 0xC0);
+	out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x02, 0xC0);
 
 	/* Configure the two Ethernet PHYs.  For each PHY, configure for fiber
 	 * if the SFP module is present, and for copper if it is not present.
 	 */
 	for (eth = 0; eth < 2; ++eth) {
-		if (gpio_read_in_bit(CFG_GPIO_SFP0_PRESENT_ + eth)) {
+		if (gpio_read_in_bit(CONFIG_SYS_GPIO_SFP0_PRESENT_ + eth)) {
 			/* SFP module not present: configure PHY for copper. */
 			/* Set PHY to autonegotate 10 MB, 100MB, or 1 GB */
-			out_8((u8 *) CFG_CPLD_BASE + 0x03,
-			      in_8((u8 *) CFG_CPLD_BASE + 0x03) |
+			out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+			      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) |
 			      0x06 << (4 * eth));
 		} else {
 			/* SFP module present: configure PHY for fiber and
 			   enable output */
-			gpio_write_bit(CFG_GPIO_PHY0_FIBER_SEL + eth, 1);
-			gpio_write_bit(CFG_GPIO_SFP0_TX_EN_ + eth, 0);
+			gpio_write_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL + eth, 1);
+			gpio_write_bit(CONFIG_SYS_GPIO_SFP0_TX_EN_ + eth, 0);
 		}
 	}
 	/* enable Ethernet: set GPIO45 and GPIO46 to 1 */
-	gpio_write_bit(CFG_GPIO_PHY0_EN, 1);
-	gpio_write_bit(CFG_GPIO_PHY1_EN, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_EN, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_EN, 1);
 
 	/* Wait 1 ms, then enable Fiber signal detect to PHYs. */
 	udelay(1000);
-	out_8((u8 *) CFG_CPLD_BASE + 0x03,
-	      in_8((u8 *) CFG_CPLD_BASE + 0x03) | 0x88);
+	out_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03,
+	      in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0x03) | 0x88);
 
 	/* select Ethernet (and optionally IIC1) pins */
 	mfsdr(SDR0_PFC1, sdr0_pfc1);
@@ -176,8 +176,8 @@
 	if (1 != banknum)
 		return 0;
 
-	info->size		= CFG_FLASH0_SIZE;
-	info->sector_count	= CFG_FLASH0_SIZE / 0x20000;
+	info->size		= CONFIG_SYS_FLASH0_SIZE;
+	info->sector_count	= CONFIG_SYS_FLASH0_SIZE / 0x20000;
 	info->flash_id		= 0x01000000;
 	info->portwidth		= 2;
 	info->chipwidth		= 2;
@@ -192,12 +192,12 @@
 	info->manufacturer_id	= 1;
 	info->device_id		= 0x007E;
 
-#if CFG_FLASH0_SIZE == 0x01000000
+#if CONFIG_SYS_FLASH0_SIZE == 0x01000000
 	info->device_id2	= 0x2101;
-#elif CFG_FLASH0_SIZE == 0x04000000
+#elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
 	info->device_id2	= 0x2301;
 #else
-#error Unable to set device_id2 for current CFG_FLASH0_SIZE
+#error Unable to set device_id2 for current CONFIG_SYS_FLASH0_SIZE
 #endif
 
 	info->ext_addr		= 0x0040;
@@ -349,13 +349,13 @@
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
-	uint32_t const flash1_size = gd->bd->bi_flashsize - CFG_FLASH0_SIZE;
+	uint32_t const flash1_size = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
 	char const *const act = getenv("usbact");
 
 	/*
 	 * Re-do FLASH1 sizing and adjust flash start and offset.
 	 */
-	gd->bd->bi_flashstart = CFG_FLASH1_TOP - flash1_size;
+	gd->bd->bi_flashstart = CONFIG_SYS_FLASH1_TOP - flash1_size;
 	gd->bd->bi_flashoffset = 0;
 
 	mtdcr(ebccfga, pb1cr);
@@ -375,23 +375,23 @@
 	 * environment
 	 */
 	gd->bd->bi_flashoffset =
-		CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CFG_FLASH1_ADDR;
+		CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - CONFIG_SYS_FLASH1_ADDR;
 
 	mtdcr(ebccfga, pb1cr);
 	pbcr = mfdcr(ebccfgd);
-	size_val = ffs(gd->bd->bi_flashsize - CFG_FLASH0_SIZE) - 21;
+	size_val = ffs(gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE) - 21;
 	pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 	mtdcr(ebccfga, pb1cr);
 	mtdcr(ebccfgd, pbcr);
 
 	/* Monitor protection ON by default */
 #if defined(CONFIG_KORAT_PERMANENT)
-	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 			    flash_info + 1);
 #else
-	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-			    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 			    flash_info);
 #endif
 	/* Env protection ON by default */
@@ -536,7 +536,7 @@
 
 	set_serial_number();
 	set_mac_addresses();
-	gpio_write_bit(CFG_GPIO_ATMEGA_RESET_, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_ATMEGA_RESET_, 1);
 
 	return 0;
 }
@@ -544,20 +544,20 @@
 int checkboard(void)
 {
 	char const *const s = getenv("serial#");
-	u8 const rev = in_8((u8 *) CFG_CPLD_BASE + 0);
+	u8 const rev = in_8((u8 *) CONFIG_SYS_CPLD_BASE + 0);
 
 	printf("Board: Korat, Rev. %X", rev);
 	if (s)
 		printf(", serial# %s", s);
 
 	printf(".\n       Ethernet PHY 0: ");
-	if (gpio_read_out_bit(CFG_GPIO_PHY0_FIBER_SEL))
+	if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY0_FIBER_SEL))
 		printf("fiber");
 	else
 		printf("copper");
 
 	printf(", PHY 1: ");
-	if (gpio_read_out_bit(CFG_GPIO_PHY1_FIBER_SEL))
+	if (gpio_read_out_bit(CONFIG_SYS_GPIO_PHY1_FIBER_SEL))
 		printf("fiber");
 	else
 		printf("copper");
@@ -644,7 +644,7 @@
  * inbound map (PIM). But the bootstrap config choices are limited and
  * may not be sufficient for a given board.
  */
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*
@@ -660,9 +660,9 @@
 	 */
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
 	out32r(PCIX0_PMM0PCILA,
-	       CFG_PCI_MEMBASE);		/* PMM0 PCI Low Address */
+	       CONFIG_SYS_PCI_MEMBASE);		/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
@@ -670,9 +670,9 @@
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute */
 						/* - disabled b4 setting */
 	out32r(PCIX0_PMM1LA,
-	       CFG_PCI_MEMBASE + 0x20000000);	/* PMM0 Local Address */
+	       CONFIG_SYS_PCI_MEMBASE + 0x20000000);	/* PMM0 Local Address */
 	out32r(PCIX0_PMM1PCILA,
-	       CFG_PCI_MEMBASE + 0x20000000);	/* PMM0 PCI Low Address */
+	       CONFIG_SYS_PCI_MEMBASE + 0x20000000);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, */
 						/* and enable region */
@@ -688,8 +688,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -708,9 +708,9 @@
 	 */
 	pci_write_config_dword(PCI_BDF(0x0, 0xC, 0x0), 0xE4, 0x00000020);
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -771,7 +771,7 @@
 	val[0] = 1;				/* chip select number */
 	val[1] = 0;				/* always 0 */
 	val[2] = gd->bd->bi_flashstart;
-	val[3] = gd->bd->bi_flashsize - CFG_FLASH0_SIZE;
+	val[3] = gd->bd->bi_flashsize - CONFIG_SYS_FLASH0_SIZE;
 	rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges",
 				  val, sizeof(val), 1);
 	if (rc)
diff --git a/board/korat/u-boot.lds b/board/korat/u-boot.lds
index b20fb1c..3cfec83 100644
--- a/board/korat/u-boot.lds
+++ b/board/korat/u-boot.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/kup/common/flash.c b/board/kup/common/flash.c
index 7688ce2..134a9d5 100644
--- a/board/kup/common/flash.c
+++ b/board/kup/common/flash.c
@@ -25,12 +25,12 @@
 #include <mpc8xx.h>
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
 #define CONFIG_FLASH_16BIT
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -43,13 +43,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -64,17 +64,17 @@
 
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V | BR_PS_16;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -325,7 +325,7 @@
 #else
 			while ((sect_addr[0] & 0x00800080) != 0x00800080) {
 #endif
-				if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					return 1;
 				}
@@ -467,7 +467,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_short *)dest) & 0x0080) != (high_data & 0x0080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
@@ -507,7 +507,7 @@
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
 #endif
 
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/kup/common/kup.c b/board/kup/common/kup.c
index d018e3c..fec5407 100644
--- a/board/kup/common/kup.c
+++ b/board/kup/common/kup.c
@@ -27,7 +27,7 @@
 
 int misc_init_f (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile sysconf8xx_t *siu = &immap->im_siu_conf;
 
 	while (siu->sc_sipend & 0x20000000) {
@@ -47,7 +47,7 @@
 #ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* We have one led for both pcmcia slots */
 	if (status) {		/* led on */
@@ -60,7 +60,7 @@
 
 void poweron_key (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	immap->im_ioport.iop_pcpar &= ~(PC_SWITCH1);
 	immap->im_ioport.iop_pcdir &= ~(PC_SWITCH1);
diff --git a/board/kup/common/load_sernum_ethaddr.c b/board/kup/common/load_sernum_ethaddr.c
index b7b7499..741e9a5 100644
--- a/board/kup/common/load_sernum_ethaddr.c
+++ b/board/kup/common/load_sernum_ethaddr.c
@@ -33,8 +33,8 @@
  * The KUP Hardware Information Block is defined as
  * follows:
  * - located in first flash bank
- * - starts at offset CFG_HWINFO_OFFSET
- * - size CFG_HWINFO_SIZE
+ * - starts at offset CONFIG_SYS_HWINFO_OFFSET
+ * - size CONFIG_SYS_HWINFO_SIZE
  *
  * Internal structure:
  * - sequence of ASCII character lines
@@ -55,15 +55,15 @@
 {
 	unsigned char *hwi;
 	char *var;
-	unsigned char hwi_stack[CFG_HWINFO_SIZE];
+	unsigned char hwi_stack[CONFIG_SYS_HWINFO_SIZE];
 	char *p;
 
-	hwi = (unsigned char *) (CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
-	if (*((unsigned long *) hwi) != (unsigned long) CFG_HWINFO_MAGIC) {
+	hwi = (unsigned char *) (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
+	if (*((unsigned long *) hwi) != (unsigned long) CONFIG_SYS_HWINFO_MAGIC) {
 		printf ("HardwareInfo not found!\n");
 		return;
 	}
-	memcpy (hwi_stack, hwi, CFG_HWINFO_SIZE);
+	memcpy (hwi_stack, hwi, CONFIG_SYS_HWINFO_SIZE);
 
 	/*
 	 ** ethaddr
@@ -72,7 +72,7 @@
 	if (var) {
 		var += sizeof (ETHADDR_TOKEN) - 1;
 		p = strchr (var, '\r');
-		if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
+		if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
 			*p = '\0';
 			setenv ("ethaddr", var);
 			*p = '\r';
@@ -85,7 +85,7 @@
 	if (var) {
 		var += sizeof (LCD_TOKEN) - 1;
 		p = strchr (var, '\r');
-		if ((unsigned char *)p < hwi + CFG_HWINFO_SIZE) {
+		if ((unsigned char *)p < hwi + CONFIG_SYS_HWINFO_SIZE) {
 			*p = '\0';
 			setenv ("lcd", var);
 			*p = '\r';
diff --git a/board/kup/common/pcmcia.c b/board/kup/common/pcmcia.c
index 8f0cf17..ce6b186 100644
--- a/board/kup/common/pcmcia.c
+++ b/board/kup/common/pcmcia.c
@@ -30,10 +30,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	* Configure SIUMCR to enable PCMCIA port B
@@ -125,9 +125,9 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/* remove all power */
 	if (slot)
@@ -162,9 +162,9 @@
 	if (!slot) /* Slot A is not configurable */
 		return 0;
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
diff --git a/board/kup/kup4k/kup4k.c b/board/kup/kup4k/kup4k.c
index 66d6180..df3ffb4 100644
--- a/board/kup/kup4k/kup4k.c
+++ b/board/kup/kup4k/kup4k.c
@@ -119,7 +119,7 @@
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	uchar *latch,rev,mod;
 
 	/*
@@ -139,7 +139,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0 = 0;
 	long int size_b1 = 0;
@@ -154,7 +154,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -163,14 +163,14 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
-/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
+/*	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	*/
 
-/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
-/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
+/*	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	*/
+/*	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;	*/
 
 
-	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -204,7 +204,7 @@
 	size_b0 = 0x00800000;
 	size_b1 = 0x00800000;
 	size_b2 = 0x00800000;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 	udelay (1000);
 	memctl->memc_or1 = 0xFF800A00;
 	memctl->memc_br1 = 0x00000081;
@@ -216,7 +216,7 @@
 	size_b0 = 0x01000000;
 	size_b1 = 0x01000000;
 	size_b2 = 0x01000000;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 	udelay (1000);
 	memctl->memc_or1 = 0xFF000A00;
 	memctl->memc_br1 = 0x00000081;
@@ -236,7 +236,7 @@
 int misc_init_r (void)
 {
 #ifdef CONFIG_STATUS_LED
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 #endif
 #ifdef CONFIG_KUP4K_LOGO
 	bd_t *bd = gd->bd;
@@ -263,7 +263,7 @@
 	FB_INFO_S1D13xxx fb_info;
 	S1D_INDEX s1dReg;
 	S1D_VALUE s1dValue;
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl;
 	ushort i;
 	uchar *fb;
diff --git a/board/kup/kup4x/kup4x.c b/board/kup/kup4x/kup4x.c
index f07ef18..c5b742d 100644
--- a/board/kup/kup4x/kup4x.c
+++ b/board/kup/kup4x/kup4x.c
@@ -114,7 +114,7 @@
 
 int checkboard (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile uchar *latch;
 	uchar rev, mod;
@@ -136,7 +136,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0 = 0;
 	long int size_b1 = 0;
@@ -151,7 +151,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -160,13 +160,13 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-/*	memctl->memc_or1 = CFG_OR1_PRELIM;	*/
-/*	memctl->memc_br1 = CFG_BR1_PRELIM;	*/
+/*	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;	*/
+/*	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;	*/
 
-/*	memctl->memc_or2 = CFG_OR2_PRELIM;	*/
-/*	memctl->memc_br2 = CFG_BR2_PRELIM;	*/
+/*	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;	*/
+/*	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;	*/
 
-	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -207,7 +207,7 @@
 	size_b1 = 0x00800000;
 	size_b2 = 0x00800000;
 	size_b3 = 0x00800000;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 	udelay (1000);
 	memctl->memc_or1 = 0xFF800A00;
 	memctl->memc_br1 = 0x00000081;
@@ -222,7 +222,7 @@
 	size_b1 = 0x01000000;
 	size_b2 = 0x01000000;
 	size_b3 = 0x01000000;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 	udelay (1000);
 	memctl->memc_or1 = 0xFF000A00;
 	memctl->memc_br1 = 0x00000081;
@@ -251,7 +251,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile long int *addr;
 	ulong cnt, val;
@@ -294,7 +294,7 @@
 
 int misc_init_r (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 #ifdef CONFIG_IDE_LED
 	/* Configure PA8 as output port */
diff --git a/board/lantec/flash.c b/board/lantec/flash.c
index e08da33..97ed054 100644
--- a/board/lantec/flash.c
+++ b/board/lantec/flash.c
@@ -31,7 +31,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -51,7 +51,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -65,13 +65,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -116,25 +116,25 @@
 		memctl->memc_br1, memctl->memc_or1);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | \
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | \
 				BR_MS_GPCM | BR_PS_32 | BR_V;
 
 	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -147,26 +147,26 @@
 #endif
 
 	if (size_b1) {
-		memctl->memc_or5 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br5 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_or5 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br5 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_PS_32 | BR_V;
 
 		DEBUGF("## BR5: 0x%08x    OR5: 0x%08x\n",
 			memctl->memc_br5, memctl->memc_or5);
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
 		flash_info[1].size = size_b1;
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -491,7 +491,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -614,7 +614,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/lantec/lantec.c b/board/lantec/lantec.c
index 46f4da9..6d3486c 100644
--- a/board/lantec/lantec.c
+++ b/board/lantec/lantec.c
@@ -111,7 +111,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0;
 	int i;
@@ -122,7 +122,7 @@
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
 
-	memctl->memc_mptpr = CFG_MPTPR_1BK_8K /* XXX CFG_MPTPR XXX */ ;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K /* XXX CONFIG_SYS_MPTPR XXX */ ;
 
 	/* burst length=4, burst type=sequential, CAS latency=2 */
 	memctl->memc_mar = 0x00000088;
@@ -130,11 +130,11 @@
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
 	/* initialize memory address register */
-	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
 
 	/* mode initialization (offset 5) */
 	udelay (200);		/* 0x80006105 */
@@ -170,17 +170,17 @@
 	/*
 	 * Check Bank 0 Memory Size for re-configuration
 	 */
-	size_b0 = dram_size (CFG_MAMR_8COL,
+	size_b0 = dram_size (CONFIG_SYS_MAMR_8COL,
 			     (long *) SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
-	memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
 
 	/*
 	 * Final mapping:
 	 */
 
-	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 	udelay (1000);
 
 	return (size_b0);
@@ -199,7 +199,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/lart/flash.c b/board/lart/flash.c
index 4326d07..29a331e 100644
--- a/board/lart/flash.c
+++ b/board/lart/flash.c
@@ -41,7 +41,7 @@
 #define PUZZLE_FROM_FLASH(x)	data_from_flash((x))
 #define PUZZLE_TO_FLASH(x)	data_to_flash((x))
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x00FF00FF
@@ -74,15 +74,15 @@
     int i, j;
     ulong size = 0;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	ulong flashbase = 0;
 	flash_info[i].flash_id =
 	  (INTEL_MANUFACT & FLASH_VENDMASK) |
 	  (INTEL_ID_28F160F3B & FLASH_TYPEMASK);
 	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
@@ -104,8 +104,8 @@
     /* Protect monitor and environment sectors
      */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + monitor_flash_len - 1,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,
@@ -305,7 +305,7 @@
 	    do
 	    {
 		/* check timeout */
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
 		{
 		    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
 		    result = BIT_TIMEOUT;
@@ -383,7 +383,7 @@
     do
     {
 	/* check timeout */
-	if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+	if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
 	{
 	    *addr = PUZZLE_TO_FLASH(CMD_SUSPEND);
 	    result = BIT_TIMEOUT;
diff --git a/board/linkstation/avr.c b/board/linkstation/avr.c
index a689c63..fda1b91 100644
--- a/board/linkstation/avr.c
+++ b/board/linkstation/avr.c
@@ -79,8 +79,8 @@
 
 void init_AVR_DUART (void)
 {
-	NS16550_t AVR_port = (NS16550_t) CFG_NS16550_COM2;
-	int clock_divisor = CFG_NS16550_CLK / 16 / 9600;
+	NS16550_t AVR_port = (NS16550_t) CONFIG_SYS_NS16550_COM2;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / 9600;
 
 	/*
 	 * AVR port init sequence taken from
@@ -105,12 +105,12 @@
 
 static inline int avr_tstc(void)
 {
-	return (NS16550_tstc((NS16550_t)CFG_NS16550_COM2));
+	return (NS16550_tstc((NS16550_t)CONFIG_SYS_NS16550_COM2));
 }
 
 static inline char avr_getc(void)
 {
-	return (NS16550_getc((NS16550_t)CFG_NS16550_COM2));
+	return (NS16550_getc((NS16550_t)CONFIG_SYS_NS16550_COM2));
 }
 
 static int push_timeout(char button_code)
diff --git a/board/linkstation/hwctl.c b/board/linkstation/hwctl.c
index 2e5b5c8..9fd56ae 100644
--- a/board/linkstation/hwctl.c
+++ b/board/linkstation/hwctl.c
@@ -21,7 +21,7 @@
 
 #define mdelay(n)	udelay((n)*1000)
 
-#define AVR_PORT CFG_NS16550_COM2
+#define AVR_PORT CONFIG_SYS_NS16550_COM2
 
 /* 2005.5.10 BUFFALO add */
 /*--------------------------------------------------------------*/
diff --git a/board/linkstation/ide.c b/board/linkstation/ide.c
index 02086a0..2c89d62 100644
--- a/board/linkstation/ide.c
+++ b/board/linkstation/ide.c
@@ -37,7 +37,7 @@
 #define IT8212_PCI_IdeBusSkewCONTROL	0x4c
 #define IT8212_PCI_IdeDrivingCURRENT	0x42
 
-extern ulong ide_bus_offset[CFG_IDE_MAXBUS];
+extern ulong ide_bus_offset[CONFIG_SYS_IDE_MAXBUS];
 extern struct pci_controller hose;
 
 int ide_preinit (void)
@@ -47,7 +47,7 @@
 	int l;
 
 	status = 1;
-	for (l = 0; l < CFG_IDE_MAXBUS; l++) {
+	for (l = 0; l < CONFIG_SYS_IDE_MAXBUS; l++) {
 		ide_bus_offset[l] = -ATA_STATUS;
 	}
 	devbusfn = pci_find_device(PCI_VENDOR_ID_CMD, PCI_DEVICE_ID_SII_680, 0);
diff --git a/board/linkstation/linkstation.c b/board/linkstation/linkstation.c
index afb96ae..c0d43eb 100644
--- a/board/linkstation/linkstation.c
+++ b/board/linkstation/linkstation.c
@@ -53,7 +53,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	return (get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE));
+	return (get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE));
 }
 
 /*
diff --git a/board/logodl/flash.c b/board/logodl/flash.c
index 4d9c118..593943f 100644
--- a/board/logodl/flash.c
+++ b/board/logodl/flash.c
@@ -28,7 +28,7 @@
 #define FLASH_BANK_SIZE 0x1000000
 #define MAIN_SECT_SIZE  0x20000		/* 2x64k = 128k per sector */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -59,7 +59,7 @@
 static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
 #define write_word(in, de, da)   write_word_amd(in, de, da)
 static void flash_get_offsets(ulong base, flash_info_t *info);
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 static void flash_sync_real_protect(flash_info_t *info);
 #endif
 
@@ -73,15 +73,15 @@
     int i, j;
     ulong size = 0;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	ulong flashbase = 0;
 	flash_info[i].flash_id =
 	  (FLASH_MAN_AMD & FLASH_VENDMASK) |
 	  (FLASH_AM640U & FLASH_TYPEMASK);
 	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 	switch (i)
 	{
 	   case 0:
@@ -104,8 +104,8 @@
     /* Protect monitor and environment sectors
      */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + _bss_start - _armboot_start,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,
@@ -373,7 +373,7 @@
 	return (info->size);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 
@@ -510,7 +510,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -703,7 +703,7 @@
 
     /* data polling for D7 */
     while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00F000F0;	/* reset bank */
 	    res = 1;
 	}
@@ -749,7 +749,7 @@
     start = get_timer (0);
 
     while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
 	    res = 1;
 	}
@@ -764,7 +764,7 @@
     return (res);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 int flash_real_protect (flash_info_t * info, long sector, int prot)
diff --git a/board/logodl/logodl.c b/board/logodl/logodl.c
index 897787b..c57210a 100644
--- a/board/logodl/logodl.c
+++ b/board/logodl/logodl.c
@@ -77,17 +77,17 @@
 
 	case 0:
 		if (state==1) {
-			CFG_LED_A_CR = CFG_LED_A_BIT;
+			CONFIG_SYS_LED_A_CR = CONFIG_SYS_LED_A_BIT;
 		} else if (state==0) {
-			CFG_LED_A_SR = CFG_LED_A_BIT;
+			CONFIG_SYS_LED_A_SR = CONFIG_SYS_LED_A_BIT;
 		}
 		break;
 
 	case 1:
 		if (state==1) {
-			CFG_LED_B_CR = CFG_LED_B_BIT;
+			CONFIG_SYS_LED_B_CR = CONFIG_SYS_LED_B_BIT;
 		} else if (state==0) {
-			CFG_LED_B_SR = CFG_LED_B_BIT;
+			CONFIG_SYS_LED_B_SR = CONFIG_SYS_LED_B_BIT;
 		}
 		break;
 	}
diff --git a/board/logodl/lowlevel_init.S b/board/logodl/lowlevel_init.S
index 4c9f10f..9892430 100644
--- a/board/logodl/lowlevel_init.S
+++ b/board/logodl/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -54,71 +54,71 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 /*	ldr	r3,	=MSC1		/  low - bank 2 Lubbock Registers / SRAM */
-/*	ldr	r2,	=CFG_MSC1_VAL	/  high - bank 3 Ethernet Controller */
+/*	ldr	r2,	=CONFIG_SYS_MSC1_VAL	/  high - bank 3 Ethernet Controller */
 /*	str	r2,	[r3]		/  need to set MSC1 before trying to write to the HEX LEDs */
 /*	ldr	r2,	[r3]		/  need to read it back to make sure the value latches (see MSC section of manual) */
 /* */
@@ -168,17 +168,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CFG_MSC0_VAL
+	ldr     r2,   =CONFIG_SYS_MSC0_VAL
 	str     r2,   [r1, #MSC0_OFFSET]
 	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CFG_MSC1_VAL
+	ldr     r2,  =CONFIG_SYS_MSC1_VAL
 	str     r2,  [r1, #MSC1_OFFSET]
 	ldr     r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CFG_MSC2_VAL
+	ldr     r2,  =CONFIG_SYS_MSC2_VAL
 	str     r2,  [r1, #MSC2_OFFSET]
 	ldr     r2,  [r1, #MSC2_OFFSET]
 
@@ -187,37 +187,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CFG_MECR_VAL
+	ldr     r2,  =CONFIG_SYS_MECR_VAL
 	str     r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CFG_MCMEM0_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 	str     r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CFG_MCMEM1_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 	str     r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CFG_MCATT0_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 	str     r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CFG_MCATT1_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 	str     r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CFG_MCIO0_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 	str     r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CFG_MCIO1_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 	str     r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
@@ -239,7 +239,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr	r3,	=CFG_MDREFR_VAL
+	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
 	ldr	r2,	=0xFFF
 	and	r3,	r3, r2
 	ldr	r4,	=0x03ca4000
@@ -269,7 +269,7 @@
 	/* Step 4a: assert MDREFR:K?RUN and configure                       */
 	/*          MDREFR:K1DB2 and MDREFR:K2DB2 as desired.               */
 
-	ldr	r4,	=CFG_MDREFR_VAL
+	ldr	r4,	=CONFIG_SYS_MDREFR_VAL
 	str	r4,	[r1, #MDREFR_OFFSET]	/* write back MDREFR        */
 	ldr	r4,	[r1, #MDREFR_OFFSET]
 
@@ -292,7 +292,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
 	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -325,7 +325,7 @@
 	/*          Jan 2003, Errata #116, page 30.                         */
 
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2, [r3]
 	str	r2, [r3]
 	str	r2, [r3]
@@ -345,7 +345,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,  =CFG_MDMRS_VAL
+	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 	str     r2,  [r1, #MDMRS_OFFSET]
 
 
diff --git a/board/lpc2292sodimm/flash.c b/board/lpc2292sodimm/flash.c
index 449a768..a7e175d 100644
--- a/board/lpc2292sodimm/flash.c
+++ b/board/lpc2292sodimm/flash.c
@@ -28,7 +28,7 @@
 #define SST_ADDR2 ((volatile ushort*)(SST_BASEADDR + (0x2AAA << 1)))
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
 extern int lpc2292_flash_erase(flash_info_t *, int, int);
diff --git a/board/lpd7a40x/flash.c b/board/lpd7a40x/flash.c
index ec43807..e3558d2 100644
--- a/board/lpd7a40x/flash.c
+++ b/board/lpd7a40x/flash.c
@@ -33,7 +33,7 @@
 #define FLASH_BANK_SIZE 0x1000000	/* 16MB (2 x 8 MB) */
 #define MAIN_SECT_SIZE  0x40000		/* 256KB (2 x 128kB) */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x00FF00FF
@@ -66,17 +66,17 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT     & FLASH_VENDMASK) |
 			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
-			flashbase = CFG_FLASH_BASE;
+			flashbase = CONFIG_SYS_FLASH_BASE;
 		else
 			panic ("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++) {
@@ -92,8 +92,8 @@
 	 * Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -297,7 +297,7 @@
 			/* wait until flash is ready */
 			do {
 				/* check timeout */
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = CMD_STATUS_RESET;
 					result = BIT_TIMEOUT;
 					break;
@@ -392,7 +392,7 @@
 	/* wait until flash is ready */
 	do {
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			*addr = CMD_SUSPEND;
 			result = BIT_TIMEOUT;
 			break;
diff --git a/board/lubbock/flash.c b/board/lubbock/flash.c
index 3ff19bc..a4b201e 100644
--- a/board/lubbock/flash.c
+++ b/board/lubbock/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -85,8 +85,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -203,10 +203,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -276,7 +276,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -410,7 +410,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/lubbock/lowlevel_init.S b/board/lubbock/lowlevel_init.S
index 2a9bcbf..db6f69d 100644
--- a/board/lubbock/lowlevel_init.S
+++ b/board/lubbock/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
    .macro CPWAIT reg
@@ -51,67 +51,67 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 	/* ---------------------------------------------------------------- */
@@ -149,17 +149,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CFG_MSC0_VAL
+	ldr     r2,   =CONFIG_SYS_MSC0_VAL
 	str     r2,   [r1, #MSC0_OFFSET]
 	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CFG_MSC1_VAL
+	ldr     r2,  =CONFIG_SYS_MSC1_VAL
 	str     r2,  [r1, #MSC1_OFFSET]
 	ldr     r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CFG_MSC2_VAL
+	ldr     r2,  =CONFIG_SYS_MSC2_VAL
 	str     r2,  [r1, #MSC2_OFFSET]
 	ldr     r2,  [r1, #MSC2_OFFSET]
 
@@ -168,37 +168,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CFG_MECR_VAL
+	ldr     r2,  =CONFIG_SYS_MECR_VAL
 	str     r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CFG_MCMEM0_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 	str     r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CFG_MCMEM1_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 	str     r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CFG_MCATT0_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 	str     r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CFG_MCATT1_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 	str     r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CFG_MCIO0_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 	str     r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CFG_MCIO1_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 	str     r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
@@ -214,7 +214,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr     r3,     =CFG_MDREFR_VAL
+	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
 	ldr     r2,     =0xFFF
 	and     r3,     r3,  r2
 	ldr	r4,	=0x03ca4000
@@ -244,7 +244,7 @@
 
 	/* set MDREFR according to user define with exception of a few bits */
 
-	ldr     r4,     =CFG_MDREFR_VAL
+	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
 	orr	r4,	r4,	#(MDREFR_SLFRSH)
 	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
 	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
@@ -259,7 +259,7 @@
 
 	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
 
-	ldr     r4,     =CFG_MDREFR_VAL
+	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
 	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 	ldr     r4,     [r1, #MDREFR_OFFSET]
 
@@ -267,7 +267,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
 	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -294,7 +294,7 @@
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
@@ -314,7 +314,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,  =CFG_MDMRS_VAL
+	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 	str     r2,  [r1, #MDMRS_OFFSET]
 
 
diff --git a/board/lwmon/flash.c b/board/lwmon/flash.c
index 8d98545..f71cc24 100644
--- a/board/lwmon/flash.c
+++ b/board/lwmon/flash.c
@@ -28,7 +28,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -40,14 +40,14 @@
 
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
  */
 static ulong flash_get_size (vu_long *addr, flash_info_t *info);
 static int write_data (flash_info_t *info, ulong dest, ulong data);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int write_data_buf (flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 static void flash_get_offsets (ulong base, flash_info_t *info);
@@ -57,13 +57,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -108,25 +108,25 @@
 		memctl->memc_br1, memctl->memc_or1);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+	memctl->memc_or0 = (-size_b0 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
 				OR_CSNT_SAM | OR_ACS_DIV1;
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V;
 
 	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -139,27 +139,27 @@
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CFG_OR_TIMING_FLASH |
+		memctl->memc_or1 = (-size_b1 & 0xFFFF8000) | CONFIG_SYS_OR_TIMING_FLASH |
 					OR_CSNT_SAM | OR_ACS_DIV1;
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 					BR_PS_32 | BR_V;
 
 		debug ("## BR1: 0x%08x    OR1: 0x%08x\n",
 			memctl->memc_br1, memctl->memc_or1);
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
 		flash_info[1].size = size_b1;
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -342,10 +342,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = 0x00FF00FF;		/* restore read mode */
@@ -409,7 +409,7 @@
 			udelay (1000);
 			/* This takes awfully long - up to 50 ms and more */
 			while (((status = *addr) & 0x00800080) != 0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0x00FF00FF; /* reset to read mode */
 					return 1;
@@ -435,7 +435,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & 0x00800080) != 0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0x00B000B0; /* suspend erase	  */
 					*addr = 0x00FF00FF; /* reset to read mode */
@@ -504,10 +504,10 @@
 	/*
 	 * handle FLASH_WIDTH aligned part
 	 */
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while(cnt >= FLASH_WIDTH) {
-		i = CFG_FLASH_BUFFER_SIZE > cnt ?
-		    (cnt & ~(FLASH_WIDTH - 1)) : CFG_FLASH_BUFFER_SIZE;
+		i = CONFIG_SYS_FLASH_BUFFER_SIZE > cnt ?
+		    (cnt & ~(FLASH_WIDTH - 1)) : CONFIG_SYS_FLASH_BUFFER_SIZE;
 		if((rc = write_data_buf(info, wp, src,i)) != 0)
 			return rc;
 		wp += i;
@@ -526,7 +526,7 @@
 		wp  += FLASH_WIDTH;
 		cnt -= FLASH_WIDTH;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 
 	if (cnt == 0) {
 		return (0);
@@ -594,7 +594,7 @@
 	if (flag)
 		enable_interrupts();
 
-	if (flash_status_check(addr, CFG_FLASH_WRITE_TOUT, "write") != 0) {
+	if (flash_status_check(addr, CONFIG_SYS_FLASH_WRITE_TOUT, "write") != 0) {
 		return (1);
 	}
 
@@ -603,7 +603,7 @@
 	return (0);
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 /*-----------------------------------------------------------------------
  * Write a buffer to Flash, returns:
  * 0 - OK
@@ -627,7 +627,7 @@
 	*addr = 0x00500050;		/* clear status */
 	*addr = 0x00e800e8;		/* write buffer */
 
-	if((retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+	if((retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
 					 "write to buffer")) == 0) {
 		cnt = len / FLASH_WIDTH;
 		*addr = (cnt-1) | ((cnt-1) << 16);
@@ -635,14 +635,14 @@
 			*dst++ = *src++;
 		}
 		*addr = 0x00d000d0;		/* write buffer confirm */
-		retcode = flash_status_check(addr, CFG_FLASH_BUFFER_WRITE_TOUT,
+		retcode = flash_status_check(addr, CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT,
 						 "buffer write");
 	}
 	*addr = 0x00FF00FF;	/* restore read mode */
 	*addr = 0x00500050;	/* clear status */
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
 
 /*-----------------------------------------------------------------------
  */
diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 4a2d8e4..aadd254 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c
@@ -66,7 +66,7 @@
  */
 const uint sdram_table[] =
 {
-#if defined(CFG_MEMORY_75) || defined(CFG_MEMORY_8E)
+#if defined(CONFIG_SYS_MEMORY_75) || defined(CONFIG_SYS_MEMORY_8E)
 	/*
 	 * Single Read. (Offset 0 in UPM RAM)
 	 */
@@ -114,7 +114,7 @@
 	0x7FFFFC07, /* last */
 		    0xFFFFFCFF, 0xFFFFFCFF, 0xFFFFFCFF,
 #endif
-#ifdef CFG_MEMORY_7E
+#ifdef CONFIG_SYS_MEMORY_7E
 	/*
 	 * Single Read. (Offset 0 in UPM RAM)
 	 */
@@ -211,7 +211,7 @@
  ***********************************************************************/
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 	long int size_b0;
 	long int size8, size9;
@@ -222,19 +222,19 @@
 	 */
 	upmconfig (UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* burst length=4, burst type=sequential, CAS latency=2 */
-	memctl->memc_mar = CFG_MAR;
+	memctl->memc_mar = CONFIG_SYS_MAR;
 
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
 	/* initialize memory address register */
-	memctl->memc_mamr = CFG_MAMR_8COL;	/* refresh not enabled yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;	/* refresh not enabled yet */
 
 	/* mode initialization (offset 5) */
 	udelay (200);				/* 0x80006105 */
@@ -268,22 +268,22 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *)SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-		memctl->memc_mamr = CFG_MAMR_9COL | MAMR_PTAE;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL | MAMR_PTAE;
 		udelay (500);
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL | MAMR_PTAE;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL | MAMR_PTAE;
 		udelay (500);
 	}
 
@@ -293,7 +293,7 @@
 
 	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) |
 			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
-	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 	udelay (1000);
 
 	return (size_b0);
@@ -327,7 +327,7 @@
  ***********************************************************************/
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -359,7 +359,7 @@
  ***********************************************************************/
 int board_early_init_f (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* Disable Ethernet TENA on Port B
 	 * Necessary because of pull up in COM3 port.
@@ -437,7 +437,7 @@
 
 /* maximum number of "magic" key codes that can be assigned */
 
-static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
 
 static uchar *key_match (uchar *);
 
@@ -481,7 +481,7 @@
 	uchar val, errcd;
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	gd->kbd_status = 0;
 
@@ -862,7 +862,7 @@
 	int i;
 
 #if 0 /* Done in kbd_init */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
 	/* Read keys */
@@ -887,7 +887,7 @@
 );
 
 /* Read and set LSB switch */
-#define CFG_PC_TXD1_ENA		0x0008		/* PC.12 */
+#define CONFIG_SYS_PC_TXD1_ENA		0x0008		/* PC.12 */
 
 /***********************************************************************
 F* Function:     int do_lsb (cmd_tbl_t *cmdtp, int flag,
@@ -920,7 +920,7 @@
 int do_lsb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	uchar val;
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	switch (argc) {
 	case 1:					/* lsb - print setting */
@@ -932,14 +932,14 @@
 
 		if (strcmp (argv[1], "on") == 0) {
 			val |= 0x20;
-			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdat |= CFG_PC_TXD1_ENA;
-			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
 		} else if (strcmp (argv[1], "off") == 0) {
 			val &= ~0x20;
-			immr->im_ioport.iop_pcpar &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdat &= ~(CFG_PC_TXD1_ENA);
-			immr->im_ioport.iop_pcdir |= CFG_PC_TXD1_ENA;
+			immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_TXD1_ENA);
+			immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_TXD1_ENA;
 		} else {
 			break;
 		}
@@ -980,7 +980,7 @@
  ***********************************************************************/
 uchar pic_read (uchar reg)
 {
-	return (i2c_reg_read (CFG_I2C_PICIO_ADDR, reg));
+	return (i2c_reg_read (CONFIG_SYS_I2C_PICIO_ADDR, reg));
 }
 
 /***********************************************************************
@@ -1001,7 +1001,7 @@
  ***********************************************************************/
 void pic_write (uchar reg, uchar val)
 {
-	i2c_reg_write (CFG_I2C_PICIO_ADDR, reg, val);
+	i2c_reg_write (CONFIG_SYS_I2C_PICIO_ADDR, reg, val);
 }
 
 /*---------------------- Board Control Functions ----------------------*/
@@ -1022,7 +1022,7 @@
 void board_poweroff (void)
 {
     /* Turn battery off */
-    ((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
+    ((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~(1 << (31 - 13));
 
     while (1);
 }
diff --git a/board/lwmon/pcmcia.c b/board/lwmon/pcmcia.c
index 8825bd9..ad2e60d 100644
--- a/board/lwmon/pcmcia.c
+++ b/board/lwmon/pcmcia.c
@@ -51,10 +51,10 @@
 #endif
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	 * Configure SIUMCR to enable PCMCIA port B
@@ -108,8 +108,8 @@
 
 	/*  switch VCC on */
 	val |= MAX1604_OP_SUS | MAX1604_VCCBON;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	udelay(500000);
 
@@ -137,13 +137,13 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* remove all power, put output in high impedance state */
 	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	/* Configure PCMCIA General Control Register */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
@@ -181,8 +181,8 @@
 		" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 		'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	 * Disable PCMCIA buffers (isolate the interface)
 	 * and assert RESET signal
@@ -199,8 +199,8 @@
 	 */
 	debug ("PCMCIA power OFF\n");
 	val  = MAX1604_VCCBHIZ | MAX1604_VPPBHIZ;
-	i2c_init  (CFG_I2C_SPEED, CFG_I2C_SLAVE);
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_init  (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 
 	val = 0;
 	switch(vcc) {
@@ -216,7 +216,7 @@
 		pcmp->pcmc_pipr,
 		(pcmp->pcmc_pipr & 0x00008000) ? "only 5 V" : "can do 3.3V");
 
-	i2c_write (CFG_I2C_POWER_A_ADDR, 0, 0, &val, 1);
+	i2c_write (CONFIG_SYS_I2C_POWER_A_ADDR, 0, 0, &val, 1);
 	if (val) {
 		debug ("PCMCIA powered at %sV\n",
 			(val & MAX1604_VCC_35) ? "3.3" : "5.0");
diff --git a/board/lwmon5/config.mk b/board/lwmon5/config.mk
index bf2b879..3c6d041 100644
--- a/board/lwmon5/config.mk
+++ b/board/lwmon5/config.mk
@@ -35,5 +35,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/lwmon5/init.S b/board/lwmon5/init.S
index 5aade72..718cec6 100644
--- a/board/lwmon5/init.S
+++ b/board/lwmon5/init.S
@@ -47,7 +47,7 @@
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry(CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 1, AC_R|AC_W|AC_X|SA_G)
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -55,28 +55,28 @@
 	 * routine.
 	 */
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry(CFG_INIT_RAM_ADDR, SZ_4K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry(CONFIG_SYS_INIT_RAM_ADDR, SZ_4K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G)
 #endif
 
 	/* TLB-entry for PCI Memory */
-	tlbentry(CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry(CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry(CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1, AC_R|AC_W|SA_G|SA_I)
 
 	/* TLB-entry for the FPGA Chip select 2 */
-	tlbentry(CFG_FPGA_BASE_0, SZ_1M, CFG_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_FPGA_BASE_0, SZ_1M, CONFIG_SYS_FPGA_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for the FPGA Chip select 3 */
-	tlbentry(CFG_FPGA_BASE_1, SZ_1M, CFG_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_FPGA_BASE_1, SZ_1M, CONFIG_SYS_FPGA_BASE_1, 1,AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for the LIME Controller */
-	tlbentry(CFG_LIME_BASE_0, SZ_16M, CFG_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_1, SZ_16M, CFG_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_2, SZ_16M, CFG_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
-	tlbentry(CFG_LIME_BASE_3, SZ_16M, CFG_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_0, SZ_16M, CONFIG_SYS_LIME_BASE_0, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_1, SZ_16M, CONFIG_SYS_LIME_BASE_1, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_2, SZ_16M, CONFIG_SYS_LIME_BASE_2, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
+	tlbentry(CONFIG_SYS_LIME_BASE_3, SZ_16M, CONFIG_SYS_LIME_BASE_3, 1, AC_R|AC_W|AC_X|SA_I|SA_G)
 
 	/* TLB-entry for Internal Registers & OCM */
 	tlbentry(0xe0000000, SZ_16M, 0xe0000000, 0,  AC_R|AC_W|AC_X|SA_I)
diff --git a/board/lwmon5/kbd.c b/board/lwmon5/kbd.c
index 1e5349a..0a8787a 100644
--- a/board/lwmon5/kbd.c
+++ b/board/lwmon5/kbd.c
@@ -74,7 +74,7 @@
 
 /* maximum number of "magic" key codes that can be assigned */
 
-static uchar kbd_addr = CFG_I2C_KEYBD_ADDR;
+static uchar kbd_addr = CONFIG_SYS_I2C_KEYBD_ADDR;
 
 static uchar *key_match (uchar *);
 
@@ -106,7 +106,7 @@
 	uchar val, errcd;
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	gd->kbd_status = 0;
 
@@ -412,7 +412,7 @@
 	int i;
 
 #if 0 /* Done in kbd_init */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 
 	/* Read keys */
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c
index 8975bfd..aa62f37 100644
--- a/board/lwmon5/lwmon5.c
+++ b/board/lwmon5/lwmon5.c
@@ -27,7 +27,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 ulong flash_get_size(ulong base, int banknum);
 int misc_init_r_kbd(void);
@@ -94,24 +94,24 @@
 	reg = 0;
 	mtsdr(sdr_pci0, 0x00000000 | reg);
 
-	gpio_write_bit(CFG_GPIO_FLASH_WP, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_FLASH_WP, 1);
 
-#if CONFIG_POST & CFG_POST_BSPEC1
-	gpio_write_bit(CFG_GPIO_HIGHSIDE, 1);
+#if CONFIG_POST & CONFIG_SYS_POST_BSPEC1
+	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 1);
 
 	reg = 0; /* reuse as counter */
-	out_be32((void *)CFG_DSPIC_TEST_ADDR,
-		in_be32((void *)CFG_DSPIC_TEST_ADDR)
-			& ~CFG_DSPIC_TEST_MASK);
-	while (!gpio_read_in_bit(CFG_GPIO_DSPIC_READY) && reg++ < 1000) {
+	out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+		in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR)
+			& ~CONFIG_SYS_DSPIC_TEST_MASK);
+	while (!gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY) && reg++ < 1000) {
 		udelay(1000);
 	}
-	gpio_write_bit(CFG_GPIO_HIGHSIDE, 0);
-	if (gpio_read_in_bit(CFG_GPIO_DSPIC_READY)) {
+	gpio_write_bit(CONFIG_SYS_GPIO_HIGHSIDE, 0);
+	if (gpio_read_in_bit(CONFIG_SYS_GPIO_DSPIC_READY)) {
 		/* set "boot error" flag */
-		out_be32((void *)CFG_DSPIC_TEST_ADDR,
-			in_be32((void *)CFG_DSPIC_TEST_ADDR) |
-			CFG_DSPIC_TEST_MASK);
+		out_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR,
+			in_be32((void *)CONFIG_SYS_DSPIC_TEST_ADDR) |
+			CONFIG_SYS_DSPIC_TEST_MASK);
 	}
 #endif
 
@@ -123,14 +123,14 @@
 	 * MDIO address. A 2nd reset at this time will make sure, that the
 	 * correct address is latched.
 	 */
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
 	udelay(1000);
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 0);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 0);
 	udelay(1000);
-	gpio_write_bit(CFG_GPIO_PHY0_RST, 1);
-	gpio_write_bit(CFG_GPIO_PHY1_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY0_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_PHY1_RST, 1);
 
 	return 0;
 }
@@ -194,7 +194,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[1]);
 
@@ -338,7 +338,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -352,14 +352,14 @@
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2); /* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2); /* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
@@ -374,8 +374,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -389,13 +389,13 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -410,7 +410,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -460,8 +460,8 @@
 	/*
 	 * Toggle watchdog output
 	 */
-	val = gpio_read_out_bit(CFG_GPIO_WATCHDOG) == 0 ? 1 : 0;
-	gpio_write_bit(CFG_GPIO_WATCHDOG, val);
+	val = gpio_read_out_bit(CONFIG_SYS_GPIO_WATCHDOG) == 0 ? 1 : 0;
+	gpio_write_bit(CONFIG_SYS_GPIO_WATCHDOG, val);
 }
 
 int do_eeprom_wp(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
@@ -472,9 +472,9 @@
 	}
 
 	if ((strcmp(argv[1], "on") == 0)) {
-		gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 1);
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 1);
 	} else if ((strcmp(argv[1], "off") == 0)) {
-		gpio_write_bit(CFG_GPIO_EEPROM_EXT_WP, 0);
+		gpio_write_bit(CONFIG_SYS_GPIO_EEPROM_EXT_WP, 0);
 	} else {
 		printf("Usage:\n%s\n", cmdtp->usage);
 		return 1;
@@ -528,23 +528,23 @@
 	/*
 	 * Reset Lime controller
 	 */
-	gpio_write_bit(CFG_GPIO_LIME_S, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_S, 1);
 	udelay(500);
-	gpio_write_bit(CFG_GPIO_LIME_RST, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LIME_RST, 1);
 
 	/* Lime memory clock adjusted to 100MHz */
-	out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_100MHZ);
+	out_be32((void *)CONFIG_SYS_LIME_SDRAM_CLOCK, CONFIG_SYS_LIME_CLOCK_100MHZ);
 	/* Wait untill time expired. Because of requirements in lime manual */
 	udelay(300);
 	/* Write lime controller memory parameters */
-	out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
 
 	mb862xx.winSizeX = 640;
 	mb862xx.winSizeY = 480;
 	mb862xx.gdfBytesPP = 2;
 	mb862xx.gdfIndex = GDF_15BIT_555RGB;
 
-	return CFG_LIME_BASE_0;
+	return CONFIG_SYS_LIME_BASE_0;
 }
 
 #define DEFAULT_BRIGHTNESS 0x64
@@ -553,12 +553,12 @@
 {
 	if (brightness > 0) {
 		/* pwm duty, lamp on */
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), brightness);
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x701);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), brightness);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x701);
 	} else {
 		/* lamp off */
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000024), 0x00);
-		out_be32((void *)(CFG_FPGA_BASE_0 + 0x00000020), 0x00);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000024), 0x00);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE_0 + 0x00000020), 0x00);
 	}
 }
 
@@ -595,5 +595,5 @@
 
 void board_reset(void)
 {
-	gpio_write_bit(CFG_GPIO_BOARD_RESET, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_BOARD_RESET, 1);
 }
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index 189e824..72968d7 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -45,10 +45,10 @@
  * memory.
  *
  * If at some time this restriction doesn't apply anymore, just define
- * CFG_ENABLE_SDRAM_CACHE in the board config file and this code should setup
+ * CONFIG_SYS_ENABLE_SDRAM_CACHE in the board config file and this code should setup
  * everything correctly.
  */
-#ifdef CFG_ENABLE_SDRAM_CACHE
+#ifdef CONFIG_SYS_ENABLE_SDRAM_CACHE
 #define MY_TLB_WORD2_I_ENABLE	0			/* enable caching on SDRAM */
 #else
 #define MY_TLB_WORD2_I_ENABLE	TLB_WORD2_I_ENABLE	/* disable caching on SDRAM */
@@ -116,7 +116,7 @@
 	 * Because of 440EPx errata CHIP 11, we don't touch the last 256
 	 * bytes of SDRAM.
 	 */
-	bytes_remaining = num_bytes - CFG_MEM_TOP_HIDE;
+	bytes_remaining = num_bytes - CONFIG_SYS_MEM_TOP_HIDE;
 
 	/*
 	 * We have to write the ECC bytes by zeroing and flushing in smaller
@@ -252,29 +252,29 @@
 	/* -----------------------------------------------------------+
 	 * Perform data eye search if requested.
 	 * ----------------------------------------------------------*/
-	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 		    TLB_WORD2_I_ENABLE);
 	denali_core_search_data_eye();
-	remove_tlb(CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20);
 #endif
 
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-	program_tlb(0, CFG_SDRAM_BASE, CFG_MBYTES_SDRAM << 20,
+	program_tlb(0, CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MBYTES_SDRAM << 20,
 		    MY_TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual address
 	 * with cache enabled. This is done for fast ECC generation.
 	 */
-	program_tlb(0, CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.
 	 */
-	program_ecc(CFG_DDR_CACHED_ADDR, CFG_MBYTES_SDRAM << 20, 0);
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, CONFIG_SYS_MBYTES_SDRAM << 20, 0);
 #endif
 
 	/*
@@ -284,5 +284,5 @@
 	 */
 	set_mcsr(get_mcsr());
 
-	return (CFG_MBYTES_SDRAM << 20);
+	return (CONFIG_SYS_MBYTES_SDRAM << 20);
 }
diff --git a/board/lwmon5/u-boot.lds b/board/lwmon5/u-boot.lds
index b20fb1c..3cfec83 100644
--- a/board/lwmon5/u-boot.lds
+++ b/board/lwmon5/u-boot.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFF8000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/m501sk/eeprom.c b/board/m501sk/eeprom.c
index d86392f..d1a46f3 100644
--- a/board/m501sk/eeprom.c
+++ b/board/m501sk/eeprom.c
@@ -23,13 +23,13 @@
 
 #include <common.h>
 #include <i2c.h>
-#ifdef CFG_EEPROM_AT24C16
+#ifdef CONFIG_SYS_EEPROM_AT24C16
 #undef DEBUG
 
 void eeprom_init(void)
 {
 #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C)
-	i2c_init(CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 #endif
 }
 
@@ -53,10 +53,10 @@
 }
 
 /*
- * for CFG_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 2 (16-bit EEPROM address) offset is
  *   0x000nxxxx for EEPROM address selectors at n, offset xxxx in EEPROM.
  *
- * for CFG_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
+ * for CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 (8-bit EEPROM page address) offset is
  *   0x00000nxx for EEPROM address selectors and page number at n.
  */
 int eeprom_write(unsigned dev_addr, unsigned offset, uchar *buffer,
@@ -76,8 +76,8 @@
 		}
 	}
 
-#if defined(CFG_EEPROM_PAGE_WRITE_DELAY_MS)
-	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
+#if defined(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS)
+	udelay(CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 #endif
 
 	return 0;
@@ -89,11 +89,11 @@
 	unsigned char chip;
 
 	/* Probe the chip address */
-#if CFG_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
+#if CONFIG_SYS_I2C_EEPROM_ADDR_LEN == 1 && !defined(CONFIG_SPI_X)
 	chip = offset >> 8; /* block number */
 #else
 	chip = offset >> 16; /* block number */
-#endif /* CFG_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
+#endif /* CONFIG_SYS_I2C_EEPROM_ADDR_LEN, CONFIG_SPI_X */
 
 	chip |= dev_addr; /* insert device address */
 	return (i2c_probe(chip));
diff --git a/board/matrix_vision/mvbc_p/mvbc_p.c b/board/matrix_vision/mvbc_p/mvbc_p.c
index c88c4a6..a300342 100644
--- a/board/matrix_vision/mvbc_p/mvbc_p.c
+++ b/board/matrix_vision/mvbc_p/mvbc_p.c
@@ -85,9 +85,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -193,13 +193,13 @@
 
 void flash_afterinit(ulong size)
 {
-	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CFG_BOOTCS_START |
+	out_be32((u32*)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_BOOTCS_START |
 		size));
-	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CFG_BOOTCS_START |
+	out_be32((u32*)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_BOOTCS_START |
 		size));
-	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CFG_BOOTCS_START | size,
+	out_be32((u32*)MPC5XXX_BOOTCS_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 		size));
-	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CFG_BOOTCS_START | size,
+	out_be32((u32*)MPC5XXX_CS0_STOP, STOP_REG(CONFIG_SYS_BOOTCS_START | size,
 		size));
 }
 
diff --git a/board/matrix_vision/mvblm7/fpga.c b/board/matrix_vision/mvblm7/fpga.c
index a60af01..7527d16 100644
--- a/board/matrix_vision/mvblm7/fpga.c
+++ b/board/matrix_vision/mvblm7/fpga.c
@@ -79,7 +79,7 @@
 
 int fpga_config_fn(int assert, int flush, int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	u32 dvo = gpio->dat;
 
@@ -97,7 +97,7 @@
 
 int fpga_done_fn(int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int result = 0;
 
@@ -114,7 +114,7 @@
 
 int fpga_status_fn(int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int result = 0;
 
@@ -130,7 +130,7 @@
 
 int fpga_clk_fn(int assert_clk, int flush, int cookie)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	u32 dvo = gpio->dat;
 
@@ -148,7 +148,7 @@
 
 static inline int _write_fpga(u8 val, int dump)
 {
-	volatile immap_t *im = (volatile immap_t *)CFG_IMMR;
+	volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
 	volatile gpio83xx_t *gpio = (volatile gpio83xx_t *)&im->gpio[0];
 	int i;
 	u32 dvo = gpio->dat;
diff --git a/board/matrix_vision/mvblm7/mvblm7.c b/board/matrix_vision/mvblm7/mvblm7.c
index 3dcff67..6984af9 100644
--- a/board/matrix_vision/mvblm7/mvblm7.c
+++ b/board/matrix_vision/mvblm7/mvblm7.c
@@ -38,50 +38,50 @@
 
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1);
 	     ddr_size = ddr_size >> 1, ddr_size_log2++) {
 		if (ddr_size & 1)
 			return -1;
 	}
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) &
 		LAWAR_SIZE);
 
-	im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
-	im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
-	im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
-	im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
-	im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
-	im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
-	im->ddr.sdram_mode = CFG_DDR_MODE;
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
-	im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
+	im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
+	im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
+	im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
+	im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
 
 	udelay(300);
 
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 
-	return CFG_DDR_SIZE;
+	return CONFIG_SYS_DDR_SIZE;
 }
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *im = (immap_t *) CFG_IMMR;
+	volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
 		return -1;
 
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 	msize = fixed_sdram();
 
 	/* return total bus RAM size(bytes) */
@@ -132,14 +132,14 @@
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat &= ~MVBLM7_MMC_CS;
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0];
+	volatile gpio83xx_t *iopd = &((immap_t *)CONFIG_SYS_IMMR)->gpio[0];
 
 	iopd->dat |= ~MVBLM7_MMC_CS;
 }
diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c
index ef34a6b..9f31719 100644
--- a/board/matrix_vision/mvblm7/pci.c
+++ b/board/matrix_vision/mvblm7/pci.c
@@ -52,21 +52,21 @@
 
 static struct pci_region pci_regions[] = {
 	{
-		bus_start: CFG_PCI1_MEM_BASE,
-		phys_start: CFG_PCI1_MEM_PHYS,
-		size: CFG_PCI1_MEM_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MEM_BASE,
+		phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
+		size: CONFIG_SYS_PCI1_MEM_SIZE,
 		flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
 	},
 	{
-		bus_start: CFG_PCI1_MMIO_BASE,
-		phys_start: CFG_PCI1_MMIO_PHYS,
-		size: CFG_PCI1_MMIO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
+		phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
+		size: CONFIG_SYS_PCI1_MMIO_SIZE,
 		flags: PCI_REGION_MEM
 	},
 	{
-		bus_start: CFG_PCI1_IO_BASE,
-		phys_start: CFG_PCI1_IO_PHYS,
-		size: CFG_PCI1_IO_SIZE,
+		bus_start: CONFIG_SYS_PCI1_IO_BASE,
+		phys_start: CONFIG_SYS_PCI1_IO_PHYS,
+		size: CONFIG_SYS_PCI1_IO_SIZE,
 		flags: PCI_REGION_IO
 	}
 };
@@ -85,7 +85,7 @@
 	struct pci_region *reg[] = { pci_regions };
 
 	load_fpga = 1;
-	immr = (immap_t *) CFG_IMMR;
+	immr = (immap_t *) CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *) &immr->clk;
 	pci_ctrl = immr->pci_ctrl;
 	pci_law = immr->sysconf.pcilaw;
@@ -121,10 +121,10 @@
 	for (i = 0; i < 1000; ++i)
 		udelay(1000);
 
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LBLAWAR_EN | LBLAWAR_1GB;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
 
 	warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM;
diff --git a/board/mbx8xx/csr.h b/board/mbx8xx/csr.h
index 832e924..d1a58b6 100644
--- a/board/mbx8xx/csr.h
+++ b/board/mbx8xx/csr.h
@@ -54,7 +54,7 @@
 #define SR2_RDY         0x02    /* Flash programming status bit             */
 #define SR2_FT          0x01    /* Reserved for Factory test purposes       */
 
-#define MBX_CSR1 (*((uchar *)CFG_CSR_BASE))
-#define MBX_CSR2 (*((uchar *)CFG_CSR_BASE + 1))
+#define MBX_CSR1 (*((uchar *)CONFIG_SYS_CSR_BASE))
+#define MBX_CSR2 (*((uchar *)CONFIG_SYS_CSR_BASE + 1))
 
 #endif /* __csr_h */
diff --git a/board/mbx8xx/flash.c b/board/mbx8xx/flash.c
index a491f7b..2ec420d 100644
--- a/board/mbx8xx/flash.c
+++ b/board/mbx8xx/flash.c
@@ -32,7 +32,7 @@
 #include <mpc8xx.h>
 #include "vpd.h"
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -51,13 +51,13 @@
     ulong addr;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
     totsize = 0;
     addr = 0xfc000000;
-    for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+    for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 	size = flash_get_size((vu_long *)addr, &flash_info[i]);
 	if (flash_info[i].flash_id == FLASH_UNKNOWN)
 	  break;
@@ -66,7 +66,7 @@
     }
 
     addr = 0xfe000000;
-    for(i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+    for(i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 
 	size = flash_get_size((vu_long *)addr, &flash_info[i]);
 	if (flash_info[i].flash_id == FLASH_UNKNOWN)
@@ -75,11 +75,11 @@
 	addr += size;
     }
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
     /* monitor protection ON by default */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 
@@ -274,7 +274,7 @@
     last  = start;
     addr = (vu_long*)(info->start[l_sect]);
     while ((addr[0] & 0x80808080) != 0x80808080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -397,7 +397,7 @@
     /* data polling for D7 */
     start = get_timer (0);
     while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    return (1);
 	}
     }
diff --git a/board/mbx8xx/mbx8xx.c b/board/mbx8xx/mbx8xx.c
index 414d879..af4f57d 100644
--- a/board/mbx8xx/mbx8xx.c
+++ b/board/mbx8xx/mbx8xx.c
@@ -121,7 +121,7 @@
 
 void mbx_init (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 	ulong speed, refclock, plprcr, sccr;
 	ulong br0_32 = memctl->memc_br0 & 0x400;
@@ -147,21 +147,21 @@
 	immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
 	sccr = immr->im_clkrst.car_sccr;
 	sccr &= SCCR_MASK;
-	sccr |= CFG_SCCR;
+	sccr |= CONFIG_SYS_SCCR;
 	immr->im_clkrst.car_sccr = sccr;
 
 	speed = board_get_cpufreq ();
 	refclock = get_reffreq ();
 
-#if ((CFG_PLPRCR & PLPRCR_MF_MSK) != 0)
-	plprcr = CFG_PLPRCR;
+#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
+	plprcr = CONFIG_SYS_PLPRCR;
 #else
 	plprcr = immr->im_clkrst.car_plprcr;
 	plprcr &= PLPRCR_MF_MSK;	/* isolate MF field */
-	plprcr |= CFG_PLPRCR;		/* reset control bits   */
+	plprcr |= CONFIG_SYS_PLPRCR;		/* reset control bits   */
 #endif
 
-#ifdef CFG_USE_OSCCLK			/* See doc/README.MBX ! */
+#ifdef CONFIG_SYS_USE_OSCCLK			/* See doc/README.MBX ! */
 	plprcr |= ((speed + refclock / 2) / refclock - 1) << 20;
 #endif
 
@@ -181,24 +181,24 @@
 	case 40:
 		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
 		memctl->memc_or0 = 0xFF800930;
-		memctl->memc_or4 = CFG_NVRAM_OR | 0x920;
-		memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x920;
+		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
 		break;
 	case 50:
 		memctl->memc_br0 = 0xFE000000 | br0_32 | 1;
 		memctl->memc_or0 = 0xFF800940;
-		memctl->memc_or4 = CFG_NVRAM_OR | 0x930;
-		memctl->memc_br4 = CFG_NVRAM_BASE | 0x401;
+		memctl->memc_or4 = CONFIG_SYS_NVRAM_OR | 0x930;
+		memctl->memc_br4 = CONFIG_SYS_NVRAM_BASE | 0x401;
 		break;
 	default:
 		hang ();
 		break;
 	}
 #ifdef CONFIG_USE_PCI
-	memctl->memc_or5 = CFG_PCIMEM_OR;
-	memctl->memc_br5 = CFG_PCIMEM_BASE | 0x001;
-	memctl->memc_or6 = CFG_PCIBRIDGE_OR;
-	memctl->memc_br6 = CFG_PCIBRIDGE_BASE | 0x001;
+	memctl->memc_or5 = CONFIG_SYS_PCIMEM_OR;
+	memctl->memc_br5 = CONFIG_SYS_PCIMEM_BASE | 0x001;
+	memctl->memc_or6 = CONFIG_SYS_PCIBRIDGE_OR;
+	memctl->memc_br6 = CONFIG_SYS_PCIBRIDGE_BASE | 0x001;
 #endif
 	/*
 	 * FIXME: I do not understand why I have to call this to
@@ -306,7 +306,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long ram_sz = 0;
 	unsigned long dimm_sz = 0;
@@ -354,24 +354,24 @@
 		dimm_bank = dimm_sz / 2;
 		if (!dimm_sz) {
 			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
-			memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
 			memctl->memc_br2 = 0;
 			memctl->memc_br3 = 0;
 		} else if (ram_sz > dimm_bank) {
 			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
-			memctl->memc_br1 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_br1 = CONFIG_SYS_SDRAM_BASE | 0x81;
 			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
-			memctl->memc_br2 = (CFG_SDRAM_BASE + ram_sz) | 0x81;
+			memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE + ram_sz) | 0x81;
 			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
-			memctl->memc_br3 = (CFG_SDRAM_BASE + ram_sz + dimm_bank) \
+			memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + ram_sz + dimm_bank) \
 								     | 0x81;
 		} else {
 			memctl->memc_or2 = ~(dimm_bank - 1) | 0x400;
-			memctl->memc_br2 = CFG_SDRAM_BASE | 0x81;
+			memctl->memc_br2 = CONFIG_SYS_SDRAM_BASE | 0x81;
 			memctl->memc_or3 = ~(dimm_bank - 1) | 0x400;
-			memctl->memc_br3 = (CFG_SDRAM_BASE + dimm_bank) | 0x81;
+			memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE + dimm_bank) | 0x81;
 			memctl->memc_or1 = ~(ram_sz - 1) | 0x400;
-			memctl->memc_br1 = (CFG_SDRAM_BASE + dimm_sz) | 0x81;
+			memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE + dimm_sz) | 0x81;
 		}
 	}
 
diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c
index a02c848..69368d8 100644
--- a/board/mbx8xx/pcmcia.c
+++ b/board/mbx8xx/pcmcia.c
@@ -88,10 +88,10 @@
 
 	udelay (10000);
 
-	immap = (immap_t *) CFG_IMMR;
-	sysp = (sysconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_siu_conf));
-	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CFG_IMMR)->im_pcmcia));
-	cp = (cpm8xx_t *) (&(((immap_t *) CFG_IMMR)->im_cpm));
+	immap = (immap_t *) CONFIG_SYS_IMMR;
+	sysp = (sysconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp = (pcmconf8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_pcmcia));
+	cp = (cpm8xx_t *) (&(((immap_t *) CONFIG_SYS_IMMR)->im_cpm));
 
 	/* clear interrupt state, and disable interrupts */
 	pcmp->pcmc_pscr = PCMCIA_MASK (_slot_);
diff --git a/board/mbx8xx/vpd.c b/board/mbx8xx/vpd.c
index 6f88352..3bc251d 100644
--- a/board/mbx8xx/vpd.c
+++ b/board/mbx8xx/vpd.c
@@ -47,7 +47,7 @@
 #define IIC_BD_FREE    (BD_IIC_START + 3*sizeof(cbd_t))
 
 /* FIXME -- replace 0x2000 with offsetof */
-#define VPD_P ((vpd_t *)(CFG_IMMR + 0x2000 + CFG_DPRAMVPD))
+#define VPD_P ((vpd_t *)(CONFIG_SYS_IMMR + 0x2000 + CONFIG_SYS_DPRAMVPD))
 
 /* transmit/receive buffers */
 #define IIC_RX_LENGTH 128
@@ -69,7 +69,7 @@
 
 void vpd_init(void)
 {
-    volatile immap_t  *im = (immap_t *)CFG_IMMR;
+    volatile immap_t  *im = (immap_t *)CONFIG_SYS_IMMR;
     volatile cpm8xx_t *cp = &(im->im_cpm);
     volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
     volatile iic_t *iip;
@@ -120,7 +120,7 @@
  */
 int vpd_read(uint iic_device, uchar *buf, int count, int offset)
 {
-    volatile immap_t  *im = (immap_t *)CFG_IMMR;
+    volatile immap_t  *im = (immap_t *)CONFIG_SYS_IMMR;
     volatile cpm8xx_t *cp = &(im->im_cpm);
     volatile i2c8xx_t *i2c = (i2c8xx_t *)&(im->im_i2c);
     volatile iic_t *iip;
diff --git a/board/mcc200/auto_update.c b/board/mcc200/auto_update.c
index 2ed66dd..49213d0 100644
--- a/board/mcc200/auto_update.c
+++ b/board/mcc200/auto_update.c
@@ -25,7 +25,7 @@
 #include <usb.h>
 #include <part.h>
 
-#ifdef CFG_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
 #include <hush.h>
 #endif
 
@@ -40,8 +40,8 @@
 #error "must define CONFIG_USB_STORAGE"
 #endif
 
-#ifndef CFG_HUSH_PARSER
-#error "must define CFG_HUSH_PARSER"
+#ifndef CONFIG_SYS_HUSH_PARSER
+#error "must define CONFIG_SYS_HUSH_PARSER"
 #endif
 
 #if !defined(CONFIG_CMD_FAT)
diff --git a/board/mcc200/mcc200.c b/board/mcc200/mcc200.c
index 65b8184..14cf08d 100644
--- a/board/mcc200/mcc200.c
+++ b/board/mcc200/mcc200.c
@@ -47,7 +47,7 @@
 extern int do_auto_update(void);
 ulong flash_get_size (ulong base, int banknum);
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -92,7 +92,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
@@ -101,7 +101,7 @@
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
 	uint svr, pvr;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -122,9 +122,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -150,10 +150,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -175,7 +175,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -193,7 +193,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -237,7 +237,7 @@
 	/*
 	 * Check if boot FLASH isn't max size
 	 */
-	if (gd->bd->bi_flashsize < (0 - CFG_FLASH_BASE)) {
+	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH_BASE)) {
 		/* adjust mapping */
 		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
 			START_REG(gd->bd->bi_flashstart);
@@ -247,31 +247,31 @@
 		/*
 		 * Re-check to get correct base address
 		 */
-		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
 
 		/*
 		 * Re-do flash protection upon new addresses
 		 */
 		flash_protect (FLAG_PROTECT_CLEAR,
 			       gd->bd->bi_flashstart, 0xffffffff,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Monitor protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Environment protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
 			       CONFIG_ENV_ADDR,
 			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Redundant environment protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
 			       CONFIG_ENV_ADDR_REDUND,
 			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 	}
 
 	if (gd->bd->bi_flashsize > (32 << 20)) {
@@ -325,6 +325,6 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
diff --git a/board/ml2/flash.c b/board/ml2/flash.c
index ad0f075..c125d41 100644
--- a/board/ml2/flash.c
+++ b/board/ml2/flash.c
@@ -22,7 +22,7 @@
 
 #define FLASH_BANK_SIZE (64*1024*1024)
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define SECT_SIZE		(512*1024)
 
@@ -61,16 +61,16 @@
 	int i, j;
 	ulong size = 0;
 
-	for(i=0;i<CFG_MAX_FLASH_BANKS;i++) {
+	for(i=0;i<CONFIG_SYS_MAX_FLASH_BANKS;i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id = (INTEL_MANUFACT & FLASH_VENDMASK) |
 								 (INTEL_ID_28F128J3A & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i==0)
-			flashbase = CFG_FLASH_BASE;
+			flashbase = CONFIG_SYS_FLASH_BASE;
 		else
 			panic("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++)
diff --git a/board/ml2/serial.c b/board/ml2/serial.c
index c18815b..d9113ab 100644
--- a/board/ml2/serial.c
+++ b/board/ml2/serial.c
@@ -25,26 +25,26 @@
 #include <command.h>
 #include <configs/ML2.h>
 
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
 #include <ns16550.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#if (defined CFG_INIT_CHAN1) || (defined CFG_INIT_CHAN2)
-const NS16550_t COM_PORTS[] = { (NS16550_t) CFG_NS16550_COM1,
-	(NS16550_t) CFG_NS16550_COM2
+#if (defined CONFIG_SYS_INIT_CHAN1) || (defined CONFIG_SYS_INIT_CHAN2)
+const NS16550_t COM_PORTS[] = { (NS16550_t) CONFIG_SYS_NS16550_COM1,
+	(NS16550_t) CONFIG_SYS_NS16550_COM2
 };
 #endif
 
 int serial_init (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	(void) NS16550_init (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	(void) NS16550_init (COM_PORTS[1], clock_divisor);
 #endif
 	return 0;
@@ -54,29 +54,29 @@
 void serial_putc (const char c)
 {
 	if (c == '\n')
-		NS16550_putc (COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc (COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc (COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int serial_getc (void)
 {
-	return NS16550_getc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int serial_tstc (void)
 {
-	return NS16550_tstc (COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc (COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void serial_setbrg (void)
 {
-	int clock_divisor = CFG_NS16550_CLK / 16 / gd->baudrate;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / gd->baudrate;
 
-#ifdef CFG_INIT_CHAN1
+#ifdef CONFIG_SYS_INIT_CHAN1
 	NS16550_reinit (COM_PORTS[0], clock_divisor);
 #endif
-#ifdef CFG_INIT_CHAN2
+#ifdef CONFIG_SYS_INIT_CHAN2
 	NS16550_reinit (COM_PORTS[1], clock_divisor);
 #endif
 }
diff --git a/board/modnet50/flash.c b/board/modnet50/flash.c
index fb12e03..4c31143 100644
--- a/board/modnet50/flash.c
+++ b/board/modnet50/flash.c
@@ -76,7 +76,7 @@
 #define AVAIL_SIZE		(DEVICE_SIZE*MAX_FLASH_DEVICES - RESERVED_CELLS*CELL_SIZE)
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 static __u16 toggling_bits;
 
 
@@ -120,8 +120,8 @@
 	case AMD_ID_LV160B:
 		info->flash_id +=
 			(FLASH_AM160LV | FLASH_AM160B) & FLASH_TYPEMASK;
-		info->sector_count = CFG_MAX_FLASH_SECT;
-		info->size = CFG_FLASH_SIZE;
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		info->size = CONFIG_SYS_FLASH_SIZE;
 		/* 1*16K Boot Block
 		   2*8K Parameter Block
 		   1*32K Small Main Block */
@@ -130,7 +130,7 @@
 		info->start[2] = baseaddr + 0x6000;
 		info->start[3] = baseaddr + 0x8000;
 		for (i = 1; i < info->sector_count; i++)
-			info->start[3 + i] = baseaddr + i * CFG_MAIN_SECT_SIZE;
+			info->start[3 + i] = baseaddr + i * CONFIG_SYS_MAIN_SECT_SIZE;
 		break;
 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -160,12 +160,12 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
-	size = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -176,8 +176,8 @@
 	 * protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -345,7 +345,7 @@
 					/* arm simple, non interrupt dependent timer */
 					reset_timer_masked ();
 					while (flash_check_erase_amd (info->start[sect])) {
-						if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+						if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 							printf ("timeout!\n");
 							/* OOPS: reach timeout,
 							 * try to reset chip
@@ -449,7 +449,7 @@
 	reset_timer_masked ();
 
 	while (flash_check_write_amd (dest)) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			printf ("timeout! @ %08lX\n", dest);
 			/* OOPS: reach timeout,
 			 *       try to reset chip */
diff --git a/board/motionpro/motionpro.c b/board/motionpro/motionpro.c
index 3b34062..842bce6 100644
--- a/board/motionpro/motionpro.c
+++ b/board/motionpro/motionpro.c
@@ -96,7 +96,7 @@
 	return;
 }
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 /*
  * Helper function to initialize SDRAM controller.
  */
@@ -126,7 +126,7 @@
 	/* normal operation */
 	*(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 }
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 
 /*
@@ -135,7 +135,7 @@
 phys_size_t initdram(int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* According to AN3221 (MPC5200B SDRAM Initialization and
@@ -153,9 +153,9 @@
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
 
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -178,14 +178,14 @@
 	/* let SDRAM CS1 start right after CS0 and disable it */
 	*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize;
 
-#else /* !CFG_RAMBOOT */
+#else /* !CONFIG_SYS_RAMBOOT */
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
 	if (dramsize >= 0x13)
 		dramsize = (1 << (dramsize - 0x13)) << 20;
 	else
 		dramsize = 0;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/* return total ram size */
 	return dramsize;
diff --git a/board/mousse/flash.c b/board/mousse/flash.c
index 2c32b8f..d729f33 100644
--- a/board/mousse/flash.c
+++ b/board/mousse/flash.c
@@ -50,7 +50,7 @@
 #define PRIVATE
 #endif
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define SLEEP_DELAY    166
 #define FLASH_SECTOR_SIZE   (64*1024)
diff --git a/board/mousse/mousse.c b/board/mousse/mousse.c
index 7b61266..6a12b57 100644
--- a/board/mousse/mousse.c
+++ b/board/mousse/mousse.c
@@ -58,7 +58,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	return CFG_RAM_SIZE;
+	return CONFIG_SYS_RAM_SIZE;
 }
 
 
diff --git a/board/mousse/mousse.h b/board/mousse/mousse.h
index 5468314..10a0062 100644
--- a/board/mousse/mousse.h
+++ b/board/mousse/mousse.h
@@ -204,17 +204,17 @@
 #define PROMISE_MBAR5  (PROMISE_MBAR0 + 0x5000)
 
 /* ATA/66 Controller offsets */
-#define CFG_ATA_BASE_ADDR     PROMISE_MBAR0
-#define CFG_IDE_MAXBUS	       2 /* ide0/ide1 */
-#define CFG_IDE_MAXDEVICE      2 /* 2 drives per controller */
-#define CFG_ATA_IDE0_OFFSET    0
-#define CFG_ATA_IDE1_OFFSET    0x3000
+#define CONFIG_SYS_ATA_BASE_ADDR     PROMISE_MBAR0
+#define CONFIG_SYS_IDE_MAXBUS	       2 /* ide0/ide1 */
+#define CONFIG_SYS_IDE_MAXDEVICE      2 /* 2 drives per controller */
+#define CONFIG_SYS_ATA_IDE0_OFFSET    0
+#define CONFIG_SYS_ATA_IDE1_OFFSET    0x3000
 /*
  * Definitions for accessing IDE controller registers
  */
-#define CFG_ATA_DATA_OFFSET    0
-#define CFG_ATA_REG_OFFSET     0
-#define CFG_ATA_ALT_OFFSET    (0x1000)
+#define CONFIG_SYS_ATA_DATA_OFFSET    0
+#define CONFIG_SYS_ATA_REG_OFFSET     0
+#define CONFIG_SYS_ATA_ALT_OFFSET    (0x1000)
 
 /*
  * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_HIGH_ADRS, and RAM_LOW_ADRS
diff --git a/board/mp2usb/flash.c b/board/mp2usb/flash.c
index 527e74e..21a8ef9 100644
--- a/board/mp2usb/flash.c
+++ b/board/mp2usb/flash.c
@@ -30,10 +30,10 @@
 #include <common.h>
 #include <linux/byteorder/swab.h>
 
-#define CFG_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
 #define PHYS_FLASH_SECT_SIZE	0x00020000 /* 128 KB sectors (x1) */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 #define FLASH_PORT_WIDTH	ushort
 #define FLASH_PORT_WIDTHV	vu_short
@@ -77,7 +77,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -93,8 +93,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -220,10 +220,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) INTEL_RESET;		/* restore read mode */
@@ -303,7 +303,7 @@
 			*addr = (FPW) INTEL_CONFIRM;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) INTEL_SUSPEND;	/* suspend erase     */
 					*addr = (FPW) INTEL_RESET;	/* reset to read mode */
@@ -449,7 +449,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) INTEL_RESET;	/* restore read mode */
 			return (1);
 		}
@@ -500,7 +500,7 @@
 	reset_timer_masked ();
 
 	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -532,7 +532,7 @@
 				*addr = (FPW) INTEL_PROTECT;	/* set */
 				while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED)
 				{
-					if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+					if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
 					{
 						printf("Flash lock bit operation timed out\n");
 						rc = 1;
diff --git a/board/mpc8540eval/flash.c b/board/mpc8540eval/flash.c
index 98fd168..9df5bd9 100644
--- a/board/mpc8540eval/flash.c
+++ b/board/mpc8540eval/flash.c
@@ -31,13 +31,13 @@
 
 #include <common.h>
 
-#if !defined(CFG_NO_FLASH)
+#if !defined(CONFIG_SYS_NO_FLASH)
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -74,7 +74,7 @@
 	/* Init: enable write,
 	 * or we cannot even write flash commands
 	 */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 		/* set the default sector offset */
@@ -82,7 +82,7 @@
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -90,16 +90,16 @@
 	}
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -177,8 +177,8 @@
 	udelay(20);
 	asm("sync");
 
-#ifndef CFG_FLASH_CFI
-	printf("Not define CFG_FLASH_CFI\n");
+#ifndef CONFIG_SYS_FLASH_CFI
+	printf("Not define CONFIG_SYS_FLASH_CFI\n");
 	return (0);
 #else
 	value = addr[0];
@@ -237,7 +237,7 @@
 			break;
 	}
 #endif
-#endif		/*#ifdef CFG_FLASH_CFI*/
+#endif		/*#ifdef CONFIG_SYS_FLASH_CFI*/
 
 	if (big_endian==0) value = (addr[0] & 0xFF000000) >>8;
 	else value = (addr[0] & 0x00FF0000);
@@ -453,7 +453,7 @@
 							asm("sync");
 							return 1;
 						}
-						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+						if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 							printf ("Timeout\n");
 							*addr16 = 0xFFFF;	/* reset bank */
 							asm("sync");
@@ -505,7 +505,7 @@
 							asm("sync");
 							return 1;
 						}
-						if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+						if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 							printf ("Timeout\n");
 							*addr = 0xFFFFFFFF;	/* reset bank */
 							asm("sync");
@@ -693,7 +693,7 @@
 		/* data polling for D7 */
 		flag  = 0;
 		while (((csr = *addr) & ready) != ready) {
-			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+			if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flag = 1;
 				break;
 			}
@@ -751,7 +751,7 @@
 		/* data polling for D7 */
 		flag  = 0;
 		while (((csr = *addr) & ready) != ready) {
-			if ((now=get_timer(start)) > CFG_FLASH_WRITE_TOUT) {
+			if ((now=get_timer(start)) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flag = 1;
 				break;
 			}
@@ -815,7 +815,7 @@
 		start = get_timer (0);
 		flag  = 0;
 		while (((csr = *addr) & ready) != ready) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flag = 1;
 				break;
 			}
@@ -881,7 +881,7 @@
 	*addr = 0x70707070;	/* read status */
 	start = get_timer (0);
 	while((*addr & ready) != ready){
-		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout on clearing Block Lock Bit\n");
 			*addr = 0xFFFFFFFF;	/* reset bank */
 			asm("sync");
@@ -891,4 +891,4 @@
 	return 0;
 }
 
-#endif /* !CFG_NO_FLASH */
+#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/board/mpc8540eval/law.c b/board/mpc8540eval/law.c
index cfcd73e..9926d25 100644
--- a/board/mpc8540eval/law.c
+++ b/board/mpc8540eval/law.c
@@ -43,11 +43,11 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
 #ifndef CONFIG_RAM_AS_FLASH
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC),
 #endif
 };
 
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c
index 028a70f..9b564b8 100644
--- a/board/mpc8540eval/mpc8540eval.c
+++ b/board/mpc8540eval/mpc8540eval.c
@@ -36,7 +36,7 @@
 int board_pre_init (void)
 {
 #if defined(CONFIG_PCI)
-	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -53,10 +53,10 @@
 	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
 	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
-	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
-		|| (CFG_LBC_LCRR & 0x0f) == 8) {
+	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
+		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
 		printf ("\tLBC: %lu MHz\n",
-			sysinfo.freqSystemBus / 1000000/(CFG_LBC_LCRR & 0x0f));
+			sysinfo.freqSystemBus / 1000000/(CONFIG_SYS_LBC_LCRR & 0x0f));
 	} else {
 		printf("\tLBC: unknown\n");
 	}
@@ -69,12 +69,12 @@
 	long dram_size = 0;
 
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 
 #if defined(CONFIG_DDR_DLL)
@@ -94,42 +94,42 @@
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	return dram_size;
 #endif
 
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */
 	get_sys_info(&sysinfo);
 	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
-	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
-		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
 	} else {
-		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
 		udelay(200);
 		temp_lbcdll = gur->lbcdllcr;
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CFG_BR2_PRELIM;
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");
 	* (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 	asm("sync");
 	* (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 	asm("sync");
 	* (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	* (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 	asm("sync");
-	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	asm("sync");
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("sync");
 #endif
 
@@ -139,7 +139,7 @@
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+		volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -181,11 +181,11 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
@@ -221,15 +221,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-#ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -238,14 +238,14 @@
 	udelay(500);
 #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 #endif
 	asm("sync; isync; msync");
 	udelay(500);
 #endif
-	return (CFG_SDRAM_SIZE * 1024 * 1024);
+	return (CONFIG_SYS_SDRAM_SIZE * 1024 * 1024);
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c
index 1003bf6..06092f8 100644
--- a/board/mpc8540eval/tlb.c
+++ b/board/mpc8540eval/tlb.c
@@ -27,34 +27,34 @@
 #include <asm/mmu.h>
 
 struct fsl_e_tlb_entry tlb_table[] = {
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
-  #if defined(CFG_FLASH_PORT_WIDTH_16)
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+  #if defined(CONFIG_SYS_FLASH_PORT_WIDTH_16)
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_4M, 1),
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x400000, CFG_FLASH_BASE + 0x400000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x400000, CONFIG_SYS_FLASH_BASE + 0x400000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_4M, 1),
   #else
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_16M, 1),
   #endif
 
   #if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
   #endif
 
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
   #if defined(CONFIG_RAM_AS_FLASH)
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
   #else
@@ -62,15 +62,15 @@
   #endif
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_16K, 1),
 
-	SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_BCSR, CFG_BCSR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 9, BOOKE_PAGESZ_16K, 1),
 };
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 8454420..8990fc6 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -53,7 +53,7 @@
 extern int mem_test(ulong start, ulong ramsize, int quiet);
 
 #define I2C_BACKUP_ADDR 0x7C00		/* 0x200 bytes for backup */
-#define IMAGE_SIZE CFG_MONITOR_LEN	/* ugly, but it works for now */
+#define IMAGE_SIZE CONFIG_SYS_MONITOR_LEN	/* ugly, but it works for now */
 
 extern flash_info_t flash_info[];	/* info for FLASH chips */
 
@@ -270,7 +270,7 @@
 #if !defined(CONFIG_PATI)
 void get_backup_values(backup_t *buf)
 {
-	i2c_read(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
+	i2c_read(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)buf,sizeof(backup_t));
 }
 
 void set_backup_values(int overwrite)
@@ -298,7 +298,7 @@
 		return;
 	}
 	back.eth_addr[20]=0;
-	i2c_write(CFG_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR, I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
 }
 
 void clear_env_values(void)
@@ -308,8 +308,8 @@
 
 	memset(&back,0xff,sizeof(backup_t));
 	memset(env_crc,0x00,4);
-	i2c_write(CFG_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
-	i2c_write(CFG_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,I2C_BACKUP_ADDR,2,(void *)&back,sizeof(backup_t));
+	i2c_write(CONFIG_SYS_DEF_EEPROM_ADDR,CONFIG_ENV_OFFSET,2,(void *)env_crc,4);
 }
 
 /*
@@ -322,7 +322,7 @@
 	uchar buf[64];
 
 	/* read old CRC */
-	eeprom_read (CFG_DEF_EEPROM_ADDR,
+	eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR,
 		     CONFIG_ENV_OFFSET,
 		     (uchar *)&crc, sizeof(ulong));
 
@@ -333,7 +333,7 @@
 	while (len > 0) {
 		int n = (len > sizeof(buf)) ? sizeof(buf) : len;
 
-		eeprom_read (CFG_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
+		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, buf, n);
 		new = crc32 (new, buf, n);
 		len -= n;
 		off += n;
@@ -362,7 +362,7 @@
 	len=size;
 	off = sizeof(long);
 	while (len > off) {
-		eeprom_read (CFG_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+		eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
 		if(c != '=') {
 			*name++=c;
 			off++;
@@ -371,7 +371,7 @@
 			*name++='\0';
 			off++;
 			do {
-				eeprom_read (CFG_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
+				eeprom_read (CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+off, &c, 1);
 				*value++=c;
 				off++;
 				if(c == '\0')
@@ -485,7 +485,7 @@
 			}
 			else {
 				local_args[1] = NULL;
-				ld_addr=CFG_LOAD_ADDR;
+				ld_addr=CONFIG_SYS_LOAD_ADDR;
 				result=do_fdcboot(cmdtp, 0, 1, local_args);
 			}
 			result=mpl_prg_image((uchar *)ld_addr);
@@ -519,14 +519,14 @@
 			result = (int)simple_strtol(argv[2], NULL, 16);
 	    }
 	    src=(unsigned long)&result;
-	    src-=CFG_MEMTEST_START;
+	    src-=CONFIG_SYS_MEMTEST_START;
 	    src-=(100*1024); /* - 100k */
 	    src&=0xfff00000;
 	    size=0;
 	    do {
 		size++;
 			printf("\n\nPass %ld\n",size);
-			mem_test(CFG_MEMTEST_START,src,1);
+			mem_test(CONFIG_SYS_MEMTEST_START,src,1);
 			if(ctrlc())
 				break;
 			if(result>0)
diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c
index b2d4f6f..302d7a3 100644
--- a/board/mpl/common/flash.c
+++ b/board/mpl/common/flash.c
@@ -52,7 +52,7 @@
 #include <mpc5xx.h>
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 /*-----------------------------------------------------------------------
  * Functions
  */
@@ -89,7 +89,7 @@
  * The board_init_r will fill in wrong values in the board init structure,
  * but this will be fixed in the misc_init_r routine:
  * bd->bi_flashstart=0-flash_info[0].size
- * bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN
+ * bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN
  * bd->bi_flashoffset=0
  *
  */
@@ -174,13 +174,13 @@
 			"MPS" : "Flash");
 #endif /* #if !defined(CONFIG_PATI) */
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size_b0 = flash_get_size((vu_long *)CFG_MONITOR_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_MONITOR_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -188,10 +188,10 @@
 	}
 	/* protect the bootloader */
 	/* Monitor protection ON by default */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+monitor_flash_len-1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			&flash_info[0]);
 #endif
 #if !defined(CONFIG_PATI)
@@ -555,7 +555,7 @@
 	start = get_timer (0);
 	last  = start;
 	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return ERR_TIMOUT;
 		}
@@ -576,7 +576,7 @@
 	start = get_timer (0);
 	last  = start;
 	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return ERR_TIMOUT;
 		}
@@ -848,7 +848,7 @@
 			udelay(10);
 			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080)
 			{
-				if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 					return (1);
 			}
 			dest2[i] = (FLASH_WORD_SIZE)0x00FF00FF; /* return to read mode */
@@ -869,7 +869,7 @@
 			start = get_timer (0);
 			while ((dest2[i] & (FLASH_WORD_SIZE)0x00800080) !=
 				(data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-				if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+				if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 					return (1);
 				}
 			}
diff --git a/board/mpl/common/isa.c b/board/mpl/common/isa.c
index 51b2773..91829d4 100644
--- a/board/mpl/common/isa.c
+++ b/board/mpl/common/isa.c
@@ -113,9 +113,9 @@
 ********************************************************************************/
 unsigned char open_cfg_super_IO(int address)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
-	if(in8(CFG_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x55); /* open config */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x20); /* set address to DEV ID */
+	if(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 0x1)==0x40) /* ok Device ID is correct */
 		return TRUE;
 	else
 		return FALSE;
@@ -123,26 +123,26 @@
 
 void close_cfg_super_IO(int address)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0xAA); /* close config */
 }
 
 
 unsigned char read_cfg_super_IO(int address, unsigned char function, unsigned char regaddr)
 {
 	/* assuming config reg is open */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
-	return in8(CFG_ISA_IO_BASE_ADDRESS | address | 1);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	return in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1);
 }
 
 void write_cfg_super_IO(int address, unsigned char function, unsigned char regaddr, unsigned char data)
 {
 	/* assuming config reg is open */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
-	out8(CFG_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,0x7); /* points to the function reg */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,function); /* set the function no */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address,regaddr); /* sets the address in the function */
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS | address | 1,data); /* writes the data */
 }
 
 void isa_write_table(SIO_LOGDEV_TABLE *ldt,unsigned char ldev)
@@ -208,12 +208,12 @@
 
 #define cached_imr1	(unsigned char)cached_irq_mask
 #define cached_imr2	(unsigned char)(cached_irq_mask>>8)
-#define IMR_1		CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
-#define IMR_2		CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
-#define ICW1_1	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
-#define ICW1_2	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
-#define ICW2_1	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
-#define ICW2_2	CFG_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
+#define IMR_1		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_OCW1
+#define IMR_2		CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_OCW1
+#define ICW1_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW1
+#define ICW1_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW1
+#define ICW2_1	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT1_ICW2
+#define ICW2_2	CONFIG_SYS_ISA_IO_BASE_ADDRESS + PIIX4_ISA_INT2_ICW2
 #define ICW3_1	ICW2_1
 #define ICW3_2	ICW2_2
 #define ICW4_1	ICW2_1
diff --git a/board/mpl/common/kbd.c b/board/mpl/common/kbd.c
index b20b953..a457635 100644
--- a/board/mpl/common/kbd.c
+++ b/board/mpl/common/kbd.c
@@ -203,7 +203,7 @@
 	}
 }
 
-#ifdef CFG_CONSOLE_OVERWRITE_ROUTINE
+#ifdef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
 extern int overwrite_console (void);
 #else
 int overwrite_console (void)
@@ -452,22 +452,22 @@
  */
 unsigned char kbd_read_status(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT));
 }
 
 unsigned char kbd_read_input(void)
 {
-	return(in8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
+	return(in8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT));
 }
 
 void kbd_write_command(unsigned char cmd)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_COMMAND_PORT,cmd);
 }
 
 void kbd_write_output(unsigned char data)
 {
-	out8(CFG_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
+	out8(CONFIG_SYS_ISA_IO_BASE_ADDRESS + KDB_DATA_PORT, data);
 }
 
 int kbd_read_data(void)
diff --git a/board/mpl/common/usb_uhci.c b/board/mpl/common/usb_uhci.c
index 666b999..ad30442 100644
--- a/board/mpl/common/usb_uhci.c
+++ b/board/mpl/common/usb_uhci.c
@@ -621,7 +621,7 @@
 	pci_read_config_dword(busdevfunc,PCI_BASE_ADDRESS_4,&usb_base_addr);
 	USB_UHCI_PRINTF("IO Base Address = 0x%lx\n",usb_base_addr);
 	usb_base_addr&=0xFFFFFFF0;
-	usb_base_addr+=CFG_ISA_IO_BASE_ADDRESS;
+	usb_base_addr+=CONFIG_SYS_ISA_IO_BASE_ADDRESS;
 	rh.devnum = 0;
 	usb_init_skel();
 	reset_hc();
diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c
index cf0afd1..5eb90e5 100644
--- a/board/mpl/mip405/mip405.c
+++ b/board/mpl/mip405/mip405.c
@@ -250,7 +250,7 @@
 	unsigned char	bc;
 	unsigned long	sdram_tim, sdram_bank;
 
-	/*i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);*/
+	/*i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);*/
 	(void) get_clocks ();
 	gd->baudrate = 9600;
 	serial_init ();
@@ -320,7 +320,7 @@
 	serial_puts ("\n");
 #endif
 	i = 0;
-	baseaddr = CFG_SDRAM_BASE;
+	baseaddr = CONFIG_SYS_SDRAM_BASE;
 	while (sdram_table[i].sz != 0xff) {
 		if (sdram_table[i].boardtype == bc)
 			break;
@@ -679,7 +679,7 @@
 {
 	/* adjust flash start and size as well as the offset */
 	gd->bd->bi_flashstart=0-flash_info[0].size;
-	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
 	gd->bd->bi_flashoffset=0;
 
 	/* check, if RTC is running */
diff --git a/board/mpl/pati/cmd_pati.c b/board/mpl/pati/cmd_pati.c
index 91683a3..9d9531b 100644
--- a/board/mpl/pati/cmd_pati.c
+++ b/board/mpl/pati/cmd_pati.c
@@ -37,7 +37,7 @@
 extern void user_led1(int led_on);
 
 /* ------------------------------------------------------------------------- */
-#if defined(CFG_PCI_CON_DEVICE)
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
 extern void pci_con_disc(void);
 extern void pci_con_connect(void);
 #endif
@@ -378,7 +378,7 @@
 			user_led1(led_on);
 		return 0;
 	}
-#if defined(CFG_PCI_CON_DEVICE)
+#if defined(CONFIG_SYS_PCI_CON_DEVICE)
 	if (strcmp(argv[1], "con") == 0) {
 		pci_con_connect();
 		return 0;
diff --git a/board/mpl/pati/pati.c b/board/mpl/pati/pati.c
index 0883c42..85c5af9 100644
--- a/board/mpl/pati/pati.c
+++ b/board/mpl/pati/pati.c
@@ -224,7 +224,7 @@
 	/* rest standard operation programmed write burst length */
 	/* we have a x32 bit bus to the SDRAM, so shift the addr with 2 */
 	lmr<<=2;
-	in32(CFG_SDRAM_BASE + lmr);
+	in32(CONFIG_SYS_SDRAM_BASE + lmr);
 	/* ok, we're done, return SDRAM size */
 	return ((0x400000 << sdram_table[i].sz));		/* log2 value of 4MByte  */
 }
@@ -287,7 +287,7 @@
  ****************************************************************/
  void init_ios(void)
  {
-	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
 	unsigned long reg;
 	reg=sysconf->sc_sgpiocr; /* Data direction register */
@@ -304,7 +304,7 @@
 
 void user_led0(int led_on)
 {
-	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
 	unsigned long reg;
 	reg=sysconf->sc_sgpiodt2; /* Data register */
@@ -317,7 +317,7 @@
 
 void user_led1(int led_on)
 {
-	volatile immap_t * immr = (immap_t *) CFG_IMMR;
+	volatile immap_t * immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile sysconf5xx_t *sysconf = &immr->im_siu_conf;
 	unsigned long reg;
 	reg=sysconf->sc_sgpiodt2; /* Data register */
@@ -370,7 +370,7 @@
 }
 
 
-#ifdef CFG_PCI_CON_DEVICE
+#ifdef CONFIG_SYS_PCI_CON_DEVICE
 /************************************************************************
  * PCI Communication
  *
@@ -610,9 +610,9 @@
 	irq_free_handler(0x02);
 	pci_con_connect();
 }
-#endif /* #ifdef CFG_PCI_CON_DEVICE */
+#endif /* #ifdef CONFIG_SYS_PCI_CON_DEVICE */
 
 /*
  * Absolute environment address for linker file.
  */
-GEN_ABS(env_start, CONFIG_ENV_OFFSET + CFG_FLASH_BASE);
+GEN_ABS(env_start, CONFIG_ENV_OFFSET + CONFIG_SYS_FLASH_BASE);
diff --git a/board/mpl/pip405/pip405.c b/board/mpl/pip405/pip405.c
index 6cba892..3be0104 100644
--- a/board/mpl/pip405/pip405.c
+++ b/board/mpl/pip405/pip405.c
@@ -208,7 +208,7 @@
 #endif
 
 	/* Read Serial Presence Detect Information */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	dataout[0] = 0;
 	for (i = 0; i < 128; i++)
 		datain[i] = 127;
@@ -386,7 +386,7 @@
 	/* write SDRAM timing register */
 	mtdcr (memcfga, mem_sdtr1);
 	mtdcr (memcfgd, tmp);
-	baseaddr = CFG_SDRAM_BASE;
+	baseaddr = CONFIG_SYS_SDRAM_BASE;
 	bank_size = (((unsigned long) density) << 22) / 2;
 	/* insert AM value */
 	tmp = ((unsigned long) t->mode - 1) << 13;
@@ -663,7 +663,7 @@
 {
 	/* adjust flash start and size as well as the offset */
 	gd->bd->bi_flashstart=0-flash_info[0].size;
-	gd->bd->bi_flashsize=flash_info[0].size-CFG_MONITOR_LEN;
+	gd->bd->bi_flashsize=flash_info[0].size-CONFIG_SYS_MONITOR_LEN;
 	gd->bd->bi_flashoffset=0;
 
 	/* if PIP405 has booted from PCI, reset CCR0[24] as described in errata PCI_18 */
diff --git a/board/mpl/pip405/pip405.h b/board/mpl/pip405/pip405.h
index 5815786..704ab2c 100644
--- a/board/mpl/pip405/pip405.h
+++ b/board/mpl/pip405/pip405.h
@@ -35,7 +35,7 @@
 void user_led1(unsigned char on);
 
 
-#define PLD_BASE_ADDRESS		CFG_ISA_IO_BASE_ADDRESS + 0x800
+#define PLD_BASE_ADDRESS		CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x800
 #define PLD_PART_REG			PLD_BASE_ADDRESS + 0
 #define PLD_VERS_REG			PLD_BASE_ADDRESS + 1
 #define PLD_BOARD_CFG_REG		PLD_BASE_ADDRESS + 2
diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c
index 3895263..7abf9cf 100644
--- a/board/mpl/vcma9/flash.c
+++ b/board/mpl/vcma9/flash.c
@@ -30,7 +30,7 @@
 #define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
 #define MAIN_SECT_SIZE  0x10000	/* 64 KB */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x000000F0
@@ -41,8 +41,8 @@
 #define CMD_PROGRAM		0x000000A0
 #define CMD_UNLOCK_BYPASS	0x00000020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
 
 #define BIT_ERASE_DONE		0x00000080
 #define BIT_RDY_MASK		0x00000080
@@ -61,7 +61,7 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
@@ -75,8 +75,8 @@
 #error "Unknown flash configured"
 #endif
 			flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -111,8 +111,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -236,7 +236,7 @@
 
 				/* check timeout */
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip = TMO;
 					break;
@@ -331,7 +331,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip = ERR | TMO;
 			break;
 		}
diff --git a/board/mpr2/mpr2.c b/board/mpr2/mpr2.c
index 98557b4..0ec0c19 100644
--- a/board/mpr2/mpr2.c
+++ b/board/mpr2/mpr2.c
@@ -154,8 +154,8 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("SDRAM: %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("SDRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
diff --git a/board/ms7720se/ms7720se.c b/board/ms7720se/ms7720se.c
index af62cdf..f83c120 100644
--- a/board/ms7720se/ms7720se.c
+++ b/board/ms7720se/ms7720se.c
@@ -47,9 +47,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/ms7722se/ms7722se.c b/board/ms7722se/ms7722se.c
index cf02242..32234d3 100644
--- a/board/ms7722se/ms7722se.c
+++ b/board/ms7722se/ms7722se.c
@@ -47,9 +47,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/ms7750se/ms7750se.c b/board/ms7750se/ms7750se.c
index d2d824c..02ff0a3 100644
--- a/board/ms7750se/ms7750se.c
+++ b/board/ms7750se/ms7750se.c
@@ -39,9 +39,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c
index 157c72d..6b1e59f 100644
--- a/board/muas3001/muas3001.c
+++ b/board/muas3001/muas3001.c
@@ -232,7 +232,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -243,7 +243,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -256,30 +256,30 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	long psize;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long sizelittle, sizebig;
 #endif
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	sizelittle = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
-						  (uchar *) CFG_SDRAM_BASE);
-	sizebig = try_init (memctl, CFG_PSDMR_BIG, CFG_OR1_BIG,
-						  (uchar *) CFG_SDRAM_BASE);
+	sizelittle = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	sizebig = try_init (memctl, CONFIG_SYS_PSDMR_BIG, CONFIG_SYS_OR1_BIG,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 	if (sizelittle < sizebig) {
 		psize = sizebig;
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_LITTLE, CFG_OR1_LITTLE,
-						  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_LITTLE, CONFIG_SYS_OR1_LITTLE,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 	}
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -329,8 +329,8 @@
 			"err:%s\n", fdt_strerror(nodeoffset));
 	}
 	/* update Flash addr, size */
-	flash_data[2] = cpu_to_be32 (CFG_FLASH_BASE);
-	flash_data[3] = cpu_to_be32 (CFG_FLASH_SIZE);
+	flash_data[2] = cpu_to_be32 (CONFIG_SYS_FLASH_BASE);
+	flash_data[3] = cpu_to_be32 (CONFIG_SYS_FLASH_SIZE);
 	nodeoffset = fdt_path_offset (blob, "/localbus");
 	if (nodeoffset >= 0) {
 		ret = fdt_setprop (blob, nodeoffset, "ranges", flash_data,
diff --git a/board/mucmc52/mucmc52.c b/board/mucmc52/mucmc52.c
index 74417c4..7181bd8 100644
--- a/board/mucmc52/mucmc52.c
+++ b/board/mucmc52/mucmc52.c
@@ -37,7 +37,7 @@
 #include <asm/processor.h>
 #include <asm/io.h>
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -86,7 +86,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
@@ -96,7 +96,7 @@
 	ulong dramsize2 = 0;
 	uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -117,9 +117,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start (0);
-	test1 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size ((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size ((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start (0);
 		dramsize = test1;
@@ -146,10 +146,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start (0);
-	test2 = test1 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	test2 = test1 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	if (!dramsize) {
 		sdram_start (1);
-		test2 = get_ram_size ((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+		test2 = get_ram_size ((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	}
 	if (test1 > test2) {
 		sdram_start (0);
@@ -171,7 +171,7 @@
 		out_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS1CFG, dramsize); /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = in_be32 ((unsigned __iomem *)MPC5XXX_SDRAM_CS0CFG) & 0xFF;
@@ -189,7 +189,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	 /*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -239,8 +239,8 @@
 
 struct kbd_data_t* get_keys (struct kbd_data_t *kbd_data)
 {
-	kbd_data->s1 = in_8 ((volatile uchar*)CFG_STATUS1_BASE);
-	kbd_data->s2 = in_8 ((volatile uchar*)CFG_STATUS2_BASE);
+	kbd_data->s1 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS1_BASE);
+	kbd_data->s2 = in_8 ((volatile uchar*)CONFIG_SYS_STATUS2_BASE);
 
 	return kbd_data;
 }
@@ -339,14 +339,14 @@
 	free (str);
 #endif /* CONFIG_PREBOOT */
 
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), ' ');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), ' ');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), ' ');
 
 	return 0;
 }
@@ -354,25 +354,25 @@
 int board_early_init_r (void)
 {
 	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG, in_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_CFG) & ~0x1);
-	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CFG_FLASH_BASE));
-	out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CFG_FLASH_BASE));
+	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_START, START_REG(CONFIG_SYS_FLASH_BASE));
+	out_be32 ((unsigned __iomem *)MPC5XXX_CS0_START, START_REG(CONFIG_SYS_FLASH_BASE));
 	out_be32 ((unsigned __iomem *)MPC5XXX_BOOTCS_STOP,
-		STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
+		STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
 	out_be32 ((unsigned __iomem *)MPC5XXX_CS0_STOP,
-		STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE));
+		STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE));
 	return 0;
 }
 
 int last_stage_init (void)
 {
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x38), 'M');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x39), 'U');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3A), 'C');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3B), '.');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3C), 'M');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3D), 'C');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3E), '5');
-	out_8 ((volatile uchar *)(CFG_DISPLAY_BASE + 0x3F), '2');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x38), 'M');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x39), 'U');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3A), 'C');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3B), '.');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3C), 'M');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3D), 'C');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3E), '5');
+	out_8 ((volatile uchar *)(CONFIG_SYS_DISPLAY_BASE + 0x3F), '2');
 
 	return 0;
 }
diff --git a/board/munices/munices.c b/board/munices/munices.c
index 162f89c..c1207f1 100644
--- a/board/munices/munices.c
+++ b/board/munices/munices.c
@@ -27,7 +27,7 @@
 
 #include "mt48lc16m16a2-75.h"
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -70,7 +70,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -78,7 +78,7 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -99,9 +99,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000);
+	test1 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
 	sdram_start(1);
-	test2 = (ulong )get_ram_size((long *)CFG_SDRAM_BASE, 0x10000000);
+	test2 = (ulong )get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x10000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -121,7 +121,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -139,7 +139,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize + dramsize2;
 }
diff --git a/board/musenki/flash.c b/board/musenki/flash.c
index 46035d7..40965be 100644
--- a/board/musenki/flash.c
+++ b/board/musenki/flash.c
@@ -26,7 +26,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -46,7 +46,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -118,15 +118,15 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CFG_FLASH_BASE0_PRELIM);
+	DEBUGF("\n## Get flash bank 1 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE0_PRELIM);
 
-	size_b0 = flash_get_size((vu_char *)CFG_FLASH_BASE0_PRELIM, &flash_info[0]);
+	size_b0 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE0_PRELIM, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0: "
@@ -135,21 +135,21 @@
 			size_b0, size_b0<<20);
 	}
 
-	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CFG_FLASH_BASE1_PRELIM);
-	size_b1 = flash_get_size((vu_char *)CFG_FLASH_BASE1_PRELIM, &flash_info[1]);
+	DEBUGF("## Get flash bank 2 size @ 0x%08x\n",CONFIG_SYS_FLASH_BASE1_PRELIM);
+	size_b1 = flash_get_size((vu_char *)CONFIG_SYS_FLASH_BASE1_PRELIM, &flash_info[1]);
 
 	DEBUGF("## Prelim. Flash bank sizes: %08lx + 0x%08lx\n",size_b0,size_b1);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	DEBUGF("protect monitor %x @ %x\n", CFG_MONITOR_BASE, monitor_flash_len);
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	DEBUGF("protect monitor %x @ %x\n", CONFIG_SYS_MONITOR_BASE, monitor_flash_len);
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -164,13 +164,13 @@
 
 	if (size_b1) {
 		flash_info[1].size = size_b1;
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -343,10 +343,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = BS(0xFF);		/* restore read mode */
@@ -414,7 +414,7 @@
 			udelay (1000);
 
 			while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = BS(0xB0); /* suspend erase	  */
 					*addr = BS(0xFF); /* reset to read mode */
@@ -497,7 +497,7 @@
 	start = get_timer (0);
 
 	while (((status = BS(*addr)) & BYTEME(0x00800080)) != BYTEME(0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = BS(0xFF);	/* restore read mode */
 			return 1;
 		}
diff --git a/board/musenki/musenki.c b/board/musenki/musenki.c
index 6f9eeb2..30b95ce 100644
--- a/board/musenki/musenki.c
+++ b/board/musenki/musenki.c
@@ -53,7 +53,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
diff --git a/board/mvblue/flash.c b/board/mvblue/flash.c
index 0c0738c..2d6acf5 100644
--- a/board/mvblue/flash.c
+++ b/board/mvblue/flash.c
@@ -31,7 +31,7 @@
 	#define mvdebug(p)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define FLASH_BUS_WIDTH		8
 
@@ -65,7 +65,7 @@
 	unsigned long size_b0;
 	int i;
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -416,7 +416,7 @@
 	addr = (FDT *)(info->start[l_sect]);
 
 	while ((addr[0] & ERASE_CONFIRM_DATA) != ERASE_CONFIRM_DATA) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -554,7 +554,7 @@
 	start = get_timer (0);
 	addr = (vu_char *)dest;
 	while (( (*addr) & WRITE_CONFIRM_DATA) != (data & WRITE_CONFIRM_DATA)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			printf(" *** ERROR: Flash write timeout !");
 			return (1);
 		}
diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
index 056fee7..69abb06 100644
--- a/board/mvblue/mvblue.c
+++ b/board/mvblue/mvblue.c
@@ -38,8 +38,8 @@
 
 void init_2nd_DUART (void)
 {
-	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
-	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
+	NS16550_t console = (NS16550_t) CONFIG_SYS_NS16550_COM2;
+	int clock_divisor = CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE;
 
 	*(u8 *) (0xfc004511) = 0x1;
 	NS16550_init (console, clock_divisor);
@@ -84,7 +84,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -147,12 +147,12 @@
 void duart_setup (u32 base, u16 divisor)
 {
 	printf ("duart setup ...");
-	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
-	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x80);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 0), divisor & 0xff);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 1), divisor >> 8);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 3), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 4), 0x03);
+	out_8 ((u8 *) (CONFIG_SYS_ISA_IO + base + 2), 0x07);
 	printf ("done\n");
 }
 
diff --git a/board/mx1ads/syncflash.c b/board/mx1ads/syncflash.c
index 0ffc378..47f613c 100644
--- a/board/mx1ads/syncflash.c
+++ b/board/mx1ads/syncflash.c
@@ -31,7 +31,7 @@
 
 /* 4Mx16x2 IAM=0 CSD1 */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*  Following Setting is for CSD1	*/
 #define SFCTL			0x00221004
@@ -46,7 +46,7 @@
 #define CMD_LCR			(CMD_NORMAL + 0x60000000)	/* LCR Command			*/
 #define CMD_PROGRAM		(CMD_NORMAL + 0x70000000)
 
-#define MODE_REG_VAL		(CFG_FLASH_BASE+0x0008CC00)	/* Cas Latency 3		*/
+#define MODE_REG_VAL		(CONFIG_SYS_FLASH_BASE+0x0008CC00)	/* Cas Latency 3		*/
 
 /* LCR Command */
 #define LCR_READSTATUS		(0x0001C000)			/* 0x70				*/
@@ -60,12 +60,12 @@
 	u32 tmp,tmp1;
 
 	reg_SFCTL	= CMD_PROGRAM;
-	tmp		= __REG(CFG_FLASH_BASE);
+	tmp		= __REG(CONFIG_SYS_FLASH_BASE);
 
 	reg_SFCTL	= CMD_NORMAL;
 
 	reg_SFCTL	= CMD_LCR;			/* Activate LCR Mode		*/
-	tmp1		= __REG(CFG_FLASH_BASE + LCR_SR_CLEAR);
+	tmp1		= __REG(CONFIG_SYS_FLASH_BASE + LCR_SR_CLEAR);
 
 	return tmp;
 }
@@ -96,7 +96,7 @@
 	u32 tmp;
 
 	reg_SFCTL	= CMD_PREC;			/* Set Precharge Command	*/
-	tmp		= __REG(CFG_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
+	tmp		= __REG(CONFIG_SYS_FLASH_BASE + SYNCFLASH_A10); /* Issue Precharge All Command */
 }
 
 /* set SyncFlash to normal mode			*/
@@ -130,10 +130,10 @@
 	SF_PrechargeAll();
 
 	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
-	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
+	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE)  = 0;	/* Issue Erase Nvmode Reg Command */
 
 	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
-	__REG(CFG_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm		*/
+	__REG(CONFIG_SYS_FLASH_BASE + LCR_ERASE_NVMODE) = 0xC0C0C0C0;	/* Confirm		*/
 
 	while(!SF_Ready());
 }
@@ -142,10 +142,10 @@
 	SF_PrechargeAll();
 
 	reg_SFCTL	= CMD_LCR;			/* Set to LCR mode		*/
-	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
+	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0;	/* Issue Program Nvmode reg command */
 
 	reg_SFCTL	= CMD_NORMAL;			/* Return to Normal mode	*/
-	__REG(CFG_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0;	/* Confirm not needed	*/
+	__REG(CONFIG_SYS_FLASH_BASE+LCR_PROG_NVMODE) = 0xC0C0C0C0;	/* Confirm not needed	*/
 }
 
 /****************************************************************************************/
@@ -169,17 +169,17 @@
 	flash_info[i].flash_id	=  FLASH_MAN_MT | FLASH_MT28S4M16LC;
 
 	flash_info[i].size	= FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
 	for (j = 0; j < flash_info[i].sector_count; j++) {
-		flash_info[i].start[j] = CFG_FLASH_BASE + j * 0x00100000;
+		flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE + j * 0x00100000;
 	}
 
 	flash_protect(FLAG_PROTECT_SET,
-		CFG_FLASH_BASE,
-		CFG_FLASH_BASE + monitor_flash_len - 1,
+		CONFIG_SYS_FLASH_BASE,
+		CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		&flash_info[0]);
 
 	flash_protect(FLAG_PROTECT_SET,
@@ -281,7 +281,7 @@
 		SF_NvmodeErase();
 		SF_NvmodeWrite();
 
-		SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
+		SF_Erase(CONFIG_SYS_FLASH_BASE + (0x0100000 * sect));
 		SF_Normal();
 
 		printf("ok.\n");
diff --git a/board/mx1fs2/flash.c b/board/mx1fs2/flash.c
index 8be0f49..da4ebe6 100644
--- a/board/mx1fs2/flash.c
+++ b/board/mx1fs2/flash.c
@@ -28,7 +28,7 @@
 #define FLASH_BANK_SIZE MX1FS2_FLASH_BANK_SIZE
 #define MAIN_SECT_SIZE  MX1FS2_FLASH_SECT_SIZE
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips   */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips   */
 
 /*
  * NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
@@ -62,7 +62,7 @@
 static int write_word_intel(flash_info_t * info, FPWV * dest, FPW data);
 static int write_word_amd(flash_info_t * info, FPWV * dest, FPW data);
 #define write_word(in, de, da)   write_word_amd(in, de, da)
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 static void flash_sync_real_protect(flash_info_t * info);
 #endif
 
@@ -77,14 +77,14 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 		flash_info[i].flash_id =
 		    (FLASH_MAN_AMD & FLASH_VENDMASK) |
 		    (FLASH_AM640U & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		switch (i) {
 		case 0:
 			flashbase = MX1FS2_FLASH_BASE;
@@ -101,8 +101,8 @@
 
 	/* Protect monitor and environment sectors */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_FLASH_BASE,
-		      CFG_FLASH_BASE + _bss_start - _armboot_start,
+		      CONFIG_SYS_FLASH_BASE,
+		      CONFIG_SYS_FLASH_BASE + _bss_start - _armboot_start,
 		      &flash_info[0]);
 
 	flash_protect(FLAG_PROTECT_SET,
@@ -389,7 +389,7 @@
 }
 #endif /* 0 */
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 
@@ -528,7 +528,7 @@
 		udelay(1000);
 
 		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			if ((now = get_timer(0)) - start > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(0)) - start > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf("Timeout\n");
 
 				if (intel) {
@@ -720,7 +720,7 @@
 	/* data polling for D7 */
 	while (res == 0
 	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer(0) - start > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(0) - start > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00F000F0;	/* reset bank */
 			printf("SHA timeout\n");
 			res = 1;
@@ -768,7 +768,7 @@
 	start = get_timer(0);
 
 	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
 			res = 1;
 		}
@@ -783,7 +783,7 @@
 	return (res);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 int
diff --git a/board/mx1fs2/lowlevel_init.S b/board/mx1fs2/lowlevel_init.S
index 4b2cb48..56a4819 100644
--- a/board/mx1fs2/lowlevel_init.S
+++ b/board/mx1fs2/lowlevel_init.S
@@ -29,19 +29,19 @@
 
 /* Change PERCLK1DIV to 14 ie 14+1 */
 	ldr		r0,	=PCDR
-	ldr		r1,	=CFG_PCDR_VAL
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
 	str		r1,   [r0]
 
 /* set MCU PLL Control Register 0 */
 
 	ldr		r0,	=MPCTL0
-	ldr		r1,	=CFG_MPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
 	str		r1,   [r0]
 
 /* set MCU PLL Control Register 1 */
 
 	ldr		r0,	=MPCTL1
-	ldr		r1,	=CFG_MPCTL1_VAL
+	ldr		r1,	=CONFIG_SYS_MPCTL1_VAL
 	str		r1,   [r0]
 
 /* set mpll restart bit */
@@ -63,13 +63,13 @@
 /* set System PLL Control Register 0 */
 
 	ldr		r0,	=SPCTL0
-	ldr		r1,	=CFG_SPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
 	str		r1,   [r0]
 
 /* set System PLL Control Register 1 */
 
 	ldr		r0,	=SPCTL1
-	ldr		r1,	=CFG_SPCTL1_VAL
+	ldr		r1,	=CONFIG_SYS_SPCTL1_VAL
 	str		r1,   [r0]
 
 /* set spll restart bit */
@@ -89,11 +89,11 @@
 	bne		1b
 
 	ldr		r0,   =CSCR
-	ldr		r1,   =CFG_CSCR_VAL
+	ldr		r1,   =CONFIG_SYS_CSCR_VAL
 	str		r1,   [r0]
 
 	ldr		r0,   =GPCR
-	ldr		r1,   =CFG_GPCR_VAL
+	ldr		r1,   =CONFIG_SYS_GPCR_VAL
 	str		r1,   [r0]
 
 /*
@@ -122,43 +122,43 @@
 	MCR p15,0,r0,c1,c0,0
 
 	ldr		r0,	=GIUS(0)
-	ldr		r1,	=CFG_GIUS_A_VAL
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=FMCR
-	ldr		r1,	=CFG_FMCR_VAL
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0U
-	ldr		r1,	=CFG_CS0U_VAL
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0L
-	ldr		r1,	=CFG_CS0L_VAL
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1U
-	ldr		r1,	=CFG_CS1U_VAL
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1L
-	ldr		r1,	=CFG_CS1L_VAL
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4U
-	ldr		r1,	=CFG_CS4U_VAL
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4L
-	ldr		r1,	=CFG_CS4L_VAL
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5U
-	ldr		r1,	=CFG_CS5U_VAL
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5L
-	ldr		r1,	=CFG_CS5L_VAL
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
 	str		r1,   [r0]
 
 /* SDRAM Setup */
diff --git a/board/nc650/flash.c b/board/nc650/flash.c
index d23e976..8a0eab5 100644
--- a/board/nc650/flash.c
+++ b/board/nc650/flash.c
@@ -34,16 +34,16 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
-#define CFG_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+#define CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 				      OR_SCY_2_CLK | OR_EHTR | OR_BI)
 #endif
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -90,15 +90,15 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
-#ifdef CFG_OR_TIMING_FLASH_AT_50MHZ
+#ifdef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 	int scy, trlx, flash_or_timing, clk_diff;
 
-	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
-	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+	scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
 		trlx = OR_TRLX;
 		scy *= 2;
 	} else
@@ -134,11 +134,11 @@
 		scy = 1;
 
 	flash_or_timing = (scy << 4) | trlx |
-			  (CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+			  (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
 #endif
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -151,23 +151,23 @@
 	}
 
 	/* Remap FLASH according to real size */
-#ifndef CFG_OR_TIMING_FLASH_AT_50MHZ
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+#ifndef CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
 #else
 	memctl->memc_or0 = flash_or_timing | (-size_b0 & OR_AM_MSK);
 #endif
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	(void) flash_protect (FLAG_PROTECT_SET,
-				CFG_MONITOR_BASE,
-				CFG_MONITOR_BASE + monitor_flash_len - 1,
+				CONFIG_SYS_MONITOR_BASE,
+				CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 				&flash_info[0]);
 #endif
 
@@ -316,10 +316,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -390,7 +390,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			    if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -530,7 +530,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/nc650/nc650.c b/board/nc650/nc650.c
index 657abc4..056230d 100644
--- a/board/nc650/nc650.c
+++ b/board/nc650/nc650.c
@@ -130,7 +130,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -145,7 +145,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -154,10 +154,10 @@
 	 * preliminary address - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -177,14 +177,14 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
@@ -192,7 +192,7 @@
 		size_b0 = size9;
 	} else {
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 	}
 
@@ -202,7 +202,7 @@
 	 */
 	if ((size_b0 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
@@ -210,12 +210,12 @@
 	 * Final mapping
 	 */
 
-	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or3 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;					/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;					/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
@@ -224,7 +224,7 @@
 	upmconfig (UPMB, (uint *) nand_flash_table,
 			   sizeof (nand_flash_table) / sizeof (uint));
 
-	memctl->memc_mbmr = CFG_MBMR_NAND;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_NAND;
 
 	return (size_b0);
 }
@@ -241,7 +241,7 @@
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -269,7 +269,7 @@
 	   0 - cp850
 	   1 - kp852
 	*/
-	pParam = (char*)(CFG_CPLD_BASE);
+	pParam = (char*)(CONFIG_SYS_CPLD_BASE);
 	if( *pParam != 0)
 		iCompatMode = 1;
 
diff --git a/board/netphone/flash.c b/board/netphone/flash.c
index cf0bc09..8852127 100644
--- a/board/netphone/flash.c
+++ b/board/netphone/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,7 +38,7 @@
 
 unsigned long flash_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 #if CONFIG_NETPHONE_VERSION == 2
@@ -47,7 +47,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -58,17 +58,17 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -92,13 +92,13 @@
 			printf("## Unknown FLASH on Bank 1 - Size = 0x%08lx = %ld MB\n", size1, size1 << 20);
 
 		/* Remap FLASH according to real size */
-		memctl->memc_or4 = CFG_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
-		memctl->memc_br4 = (CFG_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
+		memctl->memc_or4 = CONFIG_SYS_OR_TIMING_FLASH | (-size1 & 0xFFFF8000);
+		memctl->memc_br4 = (CONFIG_SYS_FLASH_BASE4 & BR_BA_MSK) | (memctl->memc_br4 & ~(BR_BA_MSK));
 
 		/* Re-do sizing to get full correct info */
-		size1 = flash_get_size((vu_long *) CFG_FLASH_BASE4, &flash_info[1]);
+		size1 = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
 
-		flash_get_offsets(CFG_FLASH_BASE4, &flash_info[1]);
+		flash_get_offsets(CONFIG_SYS_FLASH_BASE4, &flash_info[1]);
 
 		size += size1;
 	} else
@@ -448,7 +448,7 @@
 	last = start;
 	addr = (vu_char *) (info->start[l_sect]);
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return 1;
 		}
@@ -521,7 +521,7 @@
 	/* data polling for D7 */
 	start = get_timer(0);
 	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/netphone/netphone.c b/board/netphone/netphone.c
index 38eb7c8..53d3172 100644
--- a/board/netphone/netphone.c
+++ b/board/netphone/netphone.c
@@ -356,7 +356,7 @@
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
 
 /* 8 */
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -406,7 +406,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -422,10 +422,10 @@
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -546,7 +546,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -602,13 +602,13 @@
 #include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
 	unsigned long totlen;
 
-	totlen = nand_probe(CFG_NAND_BASE);
+	totlen = nand_probe(CONFIG_SYS_NAND_BASE);
 	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
@@ -626,7 +626,7 @@
 
 static volatile int left_to_poll = PHONE_CONSOLE_POLL_HZ;	/* poll */
 
-/* called from timer interrupt every 1/CFG_HZ sec */
+/* called from timer interrupt every 1/CONFIG_SYS_HZ sec */
 void board_show_activity(ulong timestamp)
 {
 	if (left_to_poll > -PHONE_CONSOLE_POLL_HZ)
@@ -656,7 +656,7 @@
 
 #endif
 
-#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 int overwrite_console(void)
 {
 	/* printf("overwrite_console called\n"); */
@@ -679,16 +679,16 @@
 
 #if CONFIG_NETPHONE_VERSION == 2
 	/* assert peripheral reset */
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
 	for (i = 0; i < 10; i++)
 		udelay(1000);
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
 #endif
 	reset_phys();
 
 	/* check in order to enable the local console */
 	left_to_poll = PHONE_CONSOLE_POLL_HZ;
-	i = CFG_HZ * 2;
+	i = CONFIG_SYS_HZ * 2;
 	while (i > 0) {
 
 		if (tstc()) {
@@ -702,7 +702,7 @@
 			status_led_set(0, STATUS_LED_ON);
 			while (!drv_phone_is_idle()) {
 				do_poll();
-				udelay(1000000 / CFG_HZ);
+				udelay(1000000 / CONFIG_SYS_HZ);
 			}
 
 			console_assign(stdin, "phone");
@@ -712,7 +712,7 @@
 			break;
 		}
 
-		udelay(1000000 / CFG_HZ);
+		udelay(1000000 / CONFIG_SYS_HZ);
 		i--;
 		left_to_poll--;
 	}
diff --git a/board/netphone/phone_console.c b/board/netphone/phone_console.c
index 408ada0..d9b0ad3 100644
--- a/board/netphone/phone_console.c
+++ b/board/netphone/phone_console.c
@@ -46,43 +46,43 @@
 #define ROWS	24
 #define COLS	80
 
-#define REFRESH_HZ		(CFG_HZ/50)	/* refresh every 20ms */
-#define BLINK_HZ		(CFG_HZ/2)	/* cursor blink every 500ms */
+#define REFRESH_HZ		(CONFIG_SYS_HZ/50)	/* refresh every 20ms */
+#define BLINK_HZ		(CONFIG_SYS_HZ/2)	/* cursor blink every 500ms */
 
 /*************************************************************************************************/
 
-#define DISPLAY_BACKLIT_PORT	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat
+#define DISPLAY_BACKLIT_PORT	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat
 #define DISPLAY_BACKLIT_MASK	0x0010
 
 /*************************************************************************************************/
 
-#define KP_STABLE_HZ		(CFG_HZ/100)	/* stable for 10ms */
-#define KP_REPEAT_DELAY_HZ	(CFG_HZ/4)	/* delay before repeat 250ms */
-#define KP_REPEAT_HZ		(CFG_HZ/20)	/* repeat every 50ms */
-#define KP_FORCE_DELAY_HZ	(CFG_HZ/2)	/* key was force pressed */
-#define KP_IDLE_DELAY_HZ	(CFG_HZ/2)	/* key was released and idle */
+#define KP_STABLE_HZ		(CONFIG_SYS_HZ/100)	/* stable for 10ms */
+#define KP_REPEAT_DELAY_HZ	(CONFIG_SYS_HZ/4)	/* delay before repeat 250ms */
+#define KP_REPEAT_HZ		(CONFIG_SYS_HZ/20)	/* repeat every 50ms */
+#define KP_FORCE_DELAY_HZ	(CONFIG_SYS_HZ/2)	/* key was force pressed */
+#define KP_IDLE_DELAY_HZ	(CONFIG_SYS_HZ/2)	/* key was released and idle */
 
 #if CONFIG_NETPHONE_VERSION == 1
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
 #define KP_SPI_RXD_MASK 0x0008
 
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
 #define KP_SPI_TXD_MASK 0x0004
 
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
 #define KP_SPI_CLK_MASK 0x0001
 #elif CONFIG_NETPHONE_VERSION == 2
-#define KP_SPI_RXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_RXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define KP_SPI_RXD_MASK 0x00000008
 
-#define KP_SPI_TXD_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_TXD_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define KP_SPI_TXD_MASK 0x00000004
 
-#define KP_SPI_CLK_PORT (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
+#define KP_SPI_CLK_PORT (((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
 #define KP_SPI_CLK_MASK 0x00000002
 #endif
 
-#define KP_CS_PORT	(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat)
+#define KP_CS_PORT	(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat)
 #define KP_CS_MASK	0x00000010
 
 #define KP_SPI_RXD() (KP_SPI_RXD_PORT & KP_SPI_RXD_MASK)
@@ -983,7 +983,7 @@
 #if CONFIG_NETPHONE_VERSION == 1
 	col_mask = kp_data_transfer(val) & 0x0F;
 #elif CONFIG_NETPHONE_VERSION == 2
-	col_mask = ((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pedat & 0x0f;
+	col_mask = ((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pedat & 0x0f;
 	/* XXX FUCK FUCK FUCK FUCK FUCK!!!! */
 	col_mask = ((col_mask & 0x08) >> 3) |	/* BKBR1 */
 		   ((col_mask & 0x04) << 1) |	/* BKBR2 */
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index c144741..aa8a097 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -134,7 +134,7 @@
  */
 u32 get_serial_number(void)
 {
-	u32 serial = in_be32((u32 *)CFG_FLASH_BASE);
+	u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
 
 	if (serial == 0xffffffff)
 		return 0;
diff --git a/board/netstal/hcu5/README.txt b/board/netstal/hcu5/README.txt
index 75c0dd7..f649876 100644
--- a/board/netstal/hcu5/README.txt
+++ b/board/netstal/hcu5/README.txt
@@ -33,7 +33,7 @@
 On-Chip Memory
 --------------
 
-0xe0010000- 0xe0013fff   CFG_OCM_BASE
+0xe0010000- 0xe0013fff   CONFIG_SYS_OCM_BASE
 The 440EPx includes a 16K on-chip memory that can be placed however
 software chooses.
 
@@ -149,7 +149,7 @@
 	setup bd flash info
 	cpu_init_r: (cpu/ppc4xx/cpu_init.c)
 	    peripheral chip select in using defines like
-	    CFG_EBC_PB0A, CFG_EBC_PB0C from hcu5.h
+	    CONFIG_SYS_EBC_PB0A, CONFIG_SYS_EBC_PB0C from hcu5.h
 	mem_malloc_init
 	malloc_bin_reloc
 	spi_init (r or f)??? (CONFIG_ENV_IS_IN_EEPROM)
@@ -168,4 +168,4 @@
 Drivers for serial etc are found under drivers/
 
 Don't ask question if you did not look at the README !!
-Most CFG_* and CONFIG_* switches are mentioned/explained there.
+Most CONFIG_SYS_* and CONFIG_* switches are mentioned/explained there.
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index f3428c2..6f4ec29 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -26,7 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #undef BOOTSTRAP_OPTION_A_ACTIVE
 
@@ -40,9 +40,9 @@
 #define SDR0_ECID2		0x0082
 #define SDR0_ECID3		0x0083
 
-#define SYS_IO_ADDRESS			(CFG_CS_2 + 0x00e00000)
-#define SYS_SLOT_ADDRESS		(CFG_CPLD + 0x00400000)
-#define HCU_DIGITAL_IO_REGISTER	(CFG_CPLD + 0x0500000)
+#define SYS_IO_ADDRESS			(CONFIG_SYS_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS		(CONFIG_SYS_CPLD + 0x00400000)
+#define HCU_DIGITAL_IO_REGISTER	(CONFIG_SYS_CPLD + 0x0500000)
 #define HCU_SW_INSTALL_REQUESTED	0x10
 
 /*
@@ -212,7 +212,7 @@
  */
 u32 get_serial_number(void)
 {
-	u32 *serial = (u32 *)CFG_FLASH_BASE;
+	u32 *serial = (u32 *)CONFIG_SYS_FLASH_BASE;
 
 	if (in_be32(serial) == 0xffffffff)
 		return 0;
@@ -243,7 +243,7 @@
 #ifdef CONFIG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -399,18 +399,18 @@
 	 */
 	/* PMM0 Mask/Attribute - disabled b4 setting */
 	out32r(PCIX0_PMM0MA, 0x00000000);
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PMM0MA, 0xE0000001);
 
 	/* PMM0 Mask/Attribute - disabled b4 setting */
 	out32r(PCIX0_PMM1MA, 0x00000000);
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
 	/* PMM0 PCI Low Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	/* 512M + No prefetching, and enable region */
 	out32r(PCIX0_PMM1MA, 0xE0000001);
@@ -426,8 +426,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
diff --git a/board/netstal/hcu5/init.S b/board/netstal/hcu5/init.S
index d73c861..05b5e38 100644
--- a/board/netstal/hcu5/init.S
+++ b/board/netstal/hcu5/init.S
@@ -42,7 +42,7 @@
 	/* TLB#0: vxWorks needs this entry for the Machine Check interrupt, */
 	tlbentry( 0x40000000, SZ_256M, 0, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 	/* TLB#1: TLB-entry for DDR SDRAM (Up to 2GB) */
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, CFG_SDRAM_BASE, 0,
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, CONFIG_SYS_SDRAM_BASE, 0,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#2: TLB-entry for EBC */
@@ -53,7 +53,7 @@
 	 * off to use the speed up boot process. It is patched after relocation
 	 * to enable SA_I
 	 */
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_1M, CFG_BOOT_BASE_ADDR, 1,
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_1M, CONFIG_SYS_BOOT_BASE_ADDR, 1,
 		AC_R|AC_W|AC_X|SA_G)
 
 	/*
@@ -63,13 +63,13 @@
 	 */
 
 	/* TLB#4: */
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 1,
 		AC_R|AC_W|SA_G|SA_I )
 	/* TLB#5: */
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 1,
 		AC_R|AC_W|SA_G|SA_I )
 	/* TLB#6: */
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 1,
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 1,
 		AC_R|AC_W|SA_G|SA_I )
 
 	/* TLB-entry for Internal Registers & OCM */
@@ -87,20 +87,20 @@
 
 	/*		CAN */
 	/* TLB#10: */
-	tlbentry( CFG_CS_1, SZ_1K, CFG_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_1, SZ_1K, CONFIG_SYS_CS_1, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#11:  CPLD and IMC-Standard 32 MB */
-	tlbentry( CFG_CS_2, SZ_16M, CFG_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_2, SZ_16M, CONFIG_SYS_CS_2, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	/* TLB#12: */
-	tlbentry( CFG_CS_2 + 0x1000000, SZ_16M, CFG_CS_2 + 0x1000000, 1,
+	tlbentry( CONFIG_SYS_CS_2 + 0x1000000, SZ_16M, CONFIG_SYS_CS_2 + 0x1000000, 1,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	 /*		IMC-Fast 32 MB */
 	/* TLB#13: */
-	tlbentry( CFG_CS_3, SZ_16M, CFG_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_CS_3, SZ_16M, CONFIG_SYS_CS_3, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 	/* TLB#14: */
-	tlbentry( CFG_CS_3 + 0x1000000, SZ_16M, CFG_CS_3, 1,
+	tlbentry( CONFIG_SYS_CS_3 + 0x1000000, SZ_16M, CONFIG_SYS_CS_3, 1,
 		AC_R|AC_W|AC_X|SA_G|SA_I )
 
 	tlbtab_end
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index e5df62e..f59bd7d 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -263,20 +263,20 @@
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
-	remove_tlb(CFG_SDRAM_BASE, 256 << 20);
+	remove_tlb(CONFIG_SYS_SDRAM_BASE, 256 << 20);
 	program_tlb(0, 0, dram_size, TLB_WORD2_W_ENABLE | TLB_WORD2_I_ENABLE);
 
 	/*
 	 * Setup 2nd TLB with same physical address but different virtual
 	 * address with cache enabled. This is done for fast ECC generation.
 	 */
-	program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
+	program_tlb(0, CONFIG_SYS_DDR_CACHED_ADDR, dram_size, 0);
 
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.
 	 */
-	program_ecc(CFG_DDR_CACHED_ADDR, dram_size);
+	program_ecc(CONFIG_SYS_DDR_CACHED_ADDR, dram_size);
 #endif
 
 	return (dram_size);
diff --git a/board/netstal/hcu5/u-boot.lds b/board/netstal/hcu5/u-boot.lds
index c72e5ba..f857ef3 100644
--- a/board/netstal/hcu5/u-boot.lds
+++ b/board/netstal/hcu5/u-boot.lds
@@ -136,7 +136,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c
index ed171bf..66ed95f 100644
--- a/board/netstal/mcu25/mcu25.c
+++ b/board/netstal/mcu25/mcu25.c
@@ -74,9 +74,9 @@
 	mtdcr(cntrl1, CPC0_CR1_VALUE);
 	mtdcr(ecr, 0x60606000);
 	mtdcr(CPC0_EIRR, 0x7C000000);
-	out32(GPIO0_OR,		CFG_GPIO0_OR );
-	out32(GPIO0_TCR,	CFG_GPIO0_TCR);
-	out32(GPIO0_ODR,	CFG_GPIO0_ODR);
+	out32(GPIO0_OR,		CONFIG_SYS_GPIO0_OR );
+	out32(GPIO0_TCR,	CONFIG_SYS_GPIO0_TCR);
+	out32(GPIO0_ODR,	CONFIG_SYS_GPIO0_ODR);
 	mtspr(ccr0,      0x00700000);
 
 	return 0;
@@ -141,7 +141,7 @@
  */
 u32 get_serial_number(void)
 {
-	u32 serial = in_be32((u32 *)CFG_FLASH_BASE);
+	u32 serial = in_be32((u32 *)CONFIG_SYS_FLASH_BASE);
 
 	if (serial == 0xffffffff)
 		return 0;
diff --git a/board/netstar/flash.c b/board/netstar/flash.c
index 692c416..e9eca35 100644
--- a/board/netstar/flash.c
+++ b/board/netstar/flash.c
@@ -33,11 +33,11 @@
 
 #include "crcek.h"
 
-#if (CFG_MAX_FLASH_BANKS > 1)
+#if (CONFIG_SYS_MAX_FLASH_BANKS > 1)
 #error There is always only _one_ flash chip
 #endif
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define CMD_READ_ARRAY		0x000000f0
 #define CMD_UNLOCK1		0x000000aa
@@ -47,8 +47,8 @@
 #define CMD_PROGRAM		0x000000a0
 #define CMD_UNLOCK_BYPASS	0x00000020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002aa << 1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002aa << 1)))
 
 #define BIT_ERASE_DONE		0x00000080
 #define BIT_RDY_MASK		0x00000080
@@ -65,27 +65,27 @@
 	flash_info[0].flash_id = (AMD_MANUFACT & FLASH_VENDMASK) |
 				 (AMD_ID_LV800B & FLASH_TYPEMASK);
 	flash_info[0].size = PHYS_FLASH_1_SIZE;
-	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
 	for (i = 0; i < flash_info[0].sector_count; i++) {
 		switch (i) {
 		case 0: /* 16kB */
-			flash_info[0].start[0] = CFG_FLASH_BASE;
+			flash_info[0].start[0] = CONFIG_SYS_FLASH_BASE;
 			break;
 		case 1: /* 8kB */
-			flash_info[0].start[1] = CFG_FLASH_BASE + 0x4000;
+			flash_info[0].start[1] = CONFIG_SYS_FLASH_BASE + 0x4000;
 			break;
 		case 2: /* 8kB */
-			flash_info[0].start[2] = CFG_FLASH_BASE + 0x4000 +
+			flash_info[0].start[2] = CONFIG_SYS_FLASH_BASE + 0x4000 +
 						 0x2000;
 			break;
 		case 3: /* 32 KB */
-			flash_info[0].start[3] = CFG_FLASH_BASE + 0x4000 +
+			flash_info[0].start[3] = CONFIG_SYS_FLASH_BASE + 0x4000 +
 						 2 * 0x2000;
 			break;
 		case 4:
-			flash_info[0].start[4] = CFG_FLASH_BASE + 0x4000 +
+			flash_info[0].start[4] = CONFIG_SYS_FLASH_BASE + 0x4000 +
 						 2 * 0x2000 + 0x8000;
 			break;
 		default: /* 64kB */
@@ -196,7 +196,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer_masked() > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					rc = ERR_TIMOUT;
 					break;
@@ -254,7 +254,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			rc = ERR_TIMOUT;
 			break;
 		}
diff --git a/board/netta/codec.c b/board/netta/codec.c
index 01ab14b..844aa18 100644
--- a/board/netta/codec.c
+++ b/board/netta/codec.c
@@ -339,9 +339,9 @@
 
 /************************************************/
 
-#define PORTB		(((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat)
-#define PORTC		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat)
-#define PORTD		(((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat)
+#define PORTB		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_cpm.cp_pbdat)
+#define PORTC		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat)
+#define PORTD		(((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat)
 
 #define _PORTD_SET(mask, state) \
 	do { \
diff --git a/board/netta/dsp.c b/board/netta/dsp.c
index 3739e16..cd57647 100644
--- a/board/netta/dsp.c
+++ b/board/netta/dsp.c
@@ -95,7 +95,7 @@
 
 static inline void dsp_go_slow(void)
 {
-	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
 #if defined(CONFIG_NETTA_6412)
 	memctl->memc_or6 |= OR_SCY_15_CLK | OR_TRLX;
 #else
@@ -108,7 +108,7 @@
 
 static inline void dsp_go_fast(void)
 {
-	volatile memctl8xx_t *memctl = &((immap_t *)CFG_IMMR)->im_memctl;
+	volatile memctl8xx_t *memctl = &((immap_t *)CONFIG_SYS_IMMR)->im_memctl;
 #if defined(CONFIG_NETTA_6412)
 	memctl->memc_or6 = (memctl->memc_or6 & ~(OR_SCY_15_CLK | OR_TRLX)) | OR_SCY_0_CLK;
 #else
@@ -148,14 +148,14 @@
 static inline void dsp_reset(void)
 {
 #if defined(CONFIG_NETTA_6412)
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 15));
 	udelay(500);
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 15));
 	udelay(500);
 #else
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat &= ~(1 << (15 - 7));
 	udelay(250);
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pddat |=  (1 << (15 - 7));
 	udelay(250);
 #endif
 }
diff --git a/board/netta/flash.c b/board/netta/flash.c
index 531204c..45e6b30 100644
--- a/board/netta/flash.c
+++ b/board/netta/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -54,17 +54,17 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -427,7 +427,7 @@
 	last = start;
 	addr = (vu_char *) (info->start[l_sect]);
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return 1;
 		}
@@ -500,7 +500,7 @@
 	/* data polling for D7 */
 	start = get_timer(0);
 	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/netta/netta.c b/board/netta/netta.c
index bc31386..02fd94c 100644
--- a/board/netta/netta.c
+++ b/board/netta/netta.c
@@ -289,7 +289,7 @@
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
 
 /* 8 */
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -339,7 +339,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -355,10 +355,10 @@
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -505,7 +505,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -560,11 +560,11 @@
 #include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+	unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
 
 	printf ("%4lu MB\n", totlen >> 20);
 }
diff --git a/board/netta/pcmcia.c b/board/netta/pcmcia.c
index 66e6e51..ed58f2c 100644
--- a/board/netta/pcmcia.c
+++ b/board/netta/pcmcia.c
@@ -33,7 +33,7 @@
 
 static void cfg_vppd(int no)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
@@ -48,7 +48,7 @@
 
 static void set_vppd(int no, int what)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	if ((unsigned int)no >= sizeof(vppd_masks)/sizeof(vppd_masks[0]))
@@ -66,7 +66,7 @@
 
 static void cfg_vccd(int no)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
@@ -81,7 +81,7 @@
 
 static void set_vccd(int no, int what)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	if ((unsigned int)no >= sizeof(vccd_masks)/sizeof(vccd_masks[0]))
@@ -99,7 +99,7 @@
 
 static void cfg_oc(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask = oc_mask;
 
 	immap->im_ioport.iop_pcdir &= ~mask;
@@ -110,7 +110,7 @@
 
 static int get_oc(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask = oc_mask;
 	int what;
 
@@ -122,7 +122,7 @@
 
 static void cfg_shdn(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	mask = shdn_mask;
@@ -134,7 +134,7 @@
 
 static void set_shdn(int what)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	unsigned short mask;
 
 	mask = shdn_mask;
@@ -150,8 +150,8 @@
 	volatile immap_t	*immap;
 	volatile cpm8xx_t	*cp;
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 
 	cfg_vppd(0); cfg_vppd(1);	/* VPPD0,VPPD1 VAVPP => Hi-Z */
@@ -184,10 +184,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
 	cfg_ports ();
@@ -273,8 +273,8 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* Configure PCMCIA General Control Register */
 	debug ("Disable PCMCIA buffers and assert RESET\n");
@@ -307,9 +307,9 @@
 			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
 	* and assert RESET signal
diff --git a/board/netta2/flash.c b/board/netta2/flash.c
index cefff71..b63f459 100644
--- a/board/netta2/flash.c
+++ b/board/netta2/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -55,17 +55,17 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -425,7 +425,7 @@
 	last = start;
 	addr = (vu_char *) (info->start[l_sect]);
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return 1;
 		}
@@ -498,7 +498,7 @@
 	/* data polling for D7 */
 	start = get_timer(0);
 	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/netta2/netta2.c b/board/netta2/netta2.c
index 1dbdde1..2ce33cf 100644
--- a/board/netta2/netta2.c
+++ b/board/netta2/netta2.c
@@ -354,7 +354,7 @@
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
 
 /* 8 */
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -404,7 +404,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -420,10 +420,10 @@
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mbmr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -544,7 +544,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -600,13 +600,13 @@
 #include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
 	unsigned long totlen;
 
-	totlen = nand_probe(CFG_NAND_BASE);
+	totlen = nand_probe(CONFIG_SYS_NAND_BASE);
 	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
@@ -620,7 +620,7 @@
 
 #endif
 
-#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 int overwrite_console(void)
 {
 	/* printf("overwrite_console called\n"); */
@@ -645,10 +645,10 @@
 
 #if CONFIG_NETTA2_VERSION == 2
 	/* assert peripheral reset */
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat &= ~_BW(12);
 	for (i = 0; i < 10; i++)
 		udelay(1000);
-	((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
+	((volatile immap_t *)CONFIG_SYS_IMMR)->im_ioport.iop_pcdat |=  _BW(12);
 #endif
 	reset_phys();
 
diff --git a/board/netvia/flash.c b/board/netvia/flash.c
index 647f594..98479a5 100644
--- a/board/netvia/flash.c
+++ b/board/netvia/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *) FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -54,17 +54,17 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | (memctl->memc_br0 & ~(BR_BA_MSK));
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *) CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets(CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_FLASH_BASE, CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -427,7 +427,7 @@
 	last = start;
 	addr = (vu_char *) (info->start[l_sect]);
 	while ((addr[0] & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return 1;
 		}
@@ -500,7 +500,7 @@
 	/* data polling for D7 */
 	start = get_timer(0);
 	while ((*((vu_char *) dest) & 0x80) != (data & 0x80)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/netvia/netvia.c b/board/netvia/netvia.c
index 4140bac..0b032c4 100644
--- a/board/netvia/netvia.c
+++ b/board/netvia/netvia.c
@@ -247,7 +247,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -256,17 +256,17 @@
 	/*
 	 * Preliminary prescaler for refresh
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 
 	memctl->memc_mar = MAR_SDRAM_INIT;	/* 32-bit address to be output on the address bus if AMX = 0b11 */
 
     /*
      * Map controller bank 3 to the SDRAM bank at preliminary address.
      */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -282,7 +282,7 @@
 
 	udelay(1000);
 
-	memctl->memc_mamr = CFG_MAMR_9COL;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
 
 	size = SDRAM_MAX_SIZE;
 
@@ -358,7 +358,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -421,11 +421,11 @@
 #include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
-	unsigned long totlen = nand_probe(CFG_NAND_BASE);
+	unsigned long totlen = nand_probe(CONFIG_SYS_NAND_BASE);
 
 	printf ("%4lu MB\n", totlen >> 20);
 }
diff --git a/board/ns9750dev/flash.c b/board/ns9750dev/flash.c
index 2b62bef..5b56b98 100644
--- a/board/ns9750dev/flash.c
+++ b/board/ns9750dev/flash.c
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -88,7 +88,7 @@
 {
 	int i;
 	ulong size = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -104,8 +104,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
 			CONFIG_ENV_ADDR,
@@ -227,10 +227,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -322,7 +322,7 @@
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
 					if (get_timer_masked () >
-					CFG_FLASH_ERASE_TOUT) {
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
 					*addr = (FPW) 0x00B000B0;
@@ -458,7 +458,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/nx823/flash.c b/board/nx823/flash.c
index 581925e..194d841 100644
--- a/board/nx823/flash.c
+++ b/board/nx823/flash.c
@@ -27,7 +27,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 extern u_long  *my_sernum;		/* from nx823.c */
 
 /*-----------------------------------------------------------------------
@@ -63,13 +63,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -82,18 +82,18 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    CFG_FLASH_BASE,
-			    CFG_FLASH_BASE+monitor_flash_len-1,
+			    CONFIG_SYS_FLASH_BASE,
+			    CONFIG_SYS_FLASH_BASE+monitor_flash_len-1,
 			    &flash_info[0]);
 
 	flash_info[0].size = size_b0;
@@ -220,10 +220,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW)0x00FF00FF;      /* restore read mode */
@@ -294,7 +294,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW)0x00B000B0; /* suspend erase	  */
 					*addr = (FPW)0x00FF00FF; /* reset to read mode */
@@ -343,9 +343,9 @@
 #endif
 
 	/* save sernum if needed */
-	if (addr >= CFG_FLASH_SN_SECTOR && addr < CFG_FLASH_SN_BASE)
+	if (addr >= CONFIG_SYS_FLASH_SN_SECTOR && addr < CONFIG_SYS_FLASH_SN_BASE)
 	{
-		u_long dest = CFG_FLASH_SN_BASE;
+		u_long dest = CONFIG_SYS_FLASH_SN_BASE;
 		u_short *sn = (u_short *)my_sernum;
 
 		printf("(saving sernum)");
@@ -452,7 +452,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & (FPW)0x00800080) != (FPW)0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW)0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/nx823/nx823.c b/board/nx823/nx823.c
index 18840ff..df9aaab 100644
--- a/board/nx823/nx823.c
+++ b/board/nx823/nx823.c
@@ -159,7 +159,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0, size_b1, size8, size9;
 
@@ -170,22 +170,22 @@
 	 * Up to 2 Banks of 64Mbit x 2 devices
 	 * Initial builds only have 1
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller SDRAM bank 0
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 	udelay (200);
 
 	/*
 	 * Map controller SDRAM bank 1
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
 	/*
 	 * Perform SDRAM initializsation sequence
@@ -209,7 +209,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -219,7 +219,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE1_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -227,7 +227,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE1_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns     */
@@ -235,7 +235,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {		/* back to 8 columns                    */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -258,7 +258,7 @@
 	 */
 	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
@@ -268,9 +268,9 @@
 	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
 
 		memctl->memc_or2 =
-			((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br2 =
-			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b0 > 0) {
 			/*
@@ -278,9 +278,9 @@
 			 */
 			memctl->memc_or1 =
 				((-size_b0) & 0xFFFF0000) |
-				CFG_OR_TIMING_SDRAM;
+				CONFIG_SYS_OR_TIMING_SDRAM;
 			memctl->memc_br1 =
-				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
 				 BR_V)
 				+ size_b1;
 		} else {
@@ -295,16 +295,16 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 
 	} else {		/* SDRAM Bank 0 is bigger - map first   */
 
 		memctl->memc_or1 =
-			((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+			((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br1 =
-			(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+			(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b1 > 0) {
 			/*
@@ -312,9 +312,9 @@
 			 */
 			memctl->memc_or2 =
 				((-size_b1) & 0xFFFF0000) |
-				CFG_OR_TIMING_SDRAM;
+				CONFIG_SYS_OR_TIMING_SDRAM;
 			memctl->memc_br2 =
-				((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
+				((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA |
 				 BR_V)
 				+ size_b0;
 		} else {
@@ -329,7 +329,7 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 	}
@@ -352,7 +352,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -387,7 +387,7 @@
 	bd_t *bd = gd->bd;
 
 	for (i = 0; i < 8; i++) {
-		bd->bi_sernum[i] = *(u_char *) (CFG_FLASH_SN_BASE + i);
+		bd->bi_sernum[i] = *(u_char *) (CONFIG_SYS_FLASH_SN_BASE + i);
 	}
 	bd->bi_enetaddr[0] = 0x10;
 	bd->bi_enetaddr[1] = 0x20;
diff --git a/board/o2dnt/flash.c b/board/o2dnt/flash.c
index 1cf78c7..9f30880 100644
--- a/board/o2dnt/flash.c
+++ b/board/o2dnt/flash.c
@@ -55,7 +55,7 @@
 #define FLASH_CYCLE1	0x0555
 #define FLASH_CYCLE2	0x02aa
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -82,25 +82,25 @@
 	flash_preinit();
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		memset(&flash_info[i], 0, sizeof(flash_info_t));
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Query flash chip */
 	flash_info[0].size =
-		flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+		flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 	size += flash_info[0].size;
 
 	/* get the h/w and s/w protection status in sync */
 	flash_sync_real_protect(&flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+monitor_flash_len-1,
-			flash_get_info(CFG_MONITOR_BASE));
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+			flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -135,7 +135,7 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->size &&
 				info->start[0] <= base &&
@@ -143,7 +143,7 @@
 			break;
 	}
 
-	return (i == CFG_MAX_FLASH_BANKS ? 0 : info);
+	return (i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info);
 }
 
 /*-----------------------------------------------------------------------
@@ -328,7 +328,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				*addr = (FPW) INTEL_SUSPEND;/* suspend erase */
 				flash_reset(info);	/* reset to read mode */
@@ -337,7 +337,7 @@
 			}
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) { /* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) { /* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
@@ -425,7 +425,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) INTEL_RESET;	/* restore read mode */
 			return (1);
 		}
@@ -464,7 +464,7 @@
 	start = get_timer (0);
 
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf ("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -494,7 +494,7 @@
 				while ((*addr & INTEL_FINISHED) !=
 				       INTEL_FINISHED) {
 					if (get_timer (start) >
-					    CFG_FLASH_UNLOCK_TOUT) {
+					    CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 						printf ("Flash lock bit operation timed out\n");
 						rc = 1;
 						break;
@@ -550,7 +550,7 @@
 	/*
 	 * first, wait for the WSM to be finished. The rationale for
 	 * waiting for the WSM to become idle for at most
-	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
 	 * because of: (1) erase, (2) program or (3) lock bit
 	 * configuration. So we just wait for the longest timeout of
 	 * the (1)-(3), i.e. the erase timeout.
@@ -563,7 +563,7 @@
 
 	start = get_timer (0);
 	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			*addr = (FPW) INTEL_RESET; /* restore read mode */
 			printf("WSM busy too long, can't get prot status\n");
 			return 1;
diff --git a/board/o2dnt/o2dnt.c b/board/o2dnt/o2dnt.c
index 19faf52..c72a741 100644
--- a/board/o2dnt/o2dnt.c
+++ b/board/o2dnt/o2dnt.c
@@ -65,7 +65,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 phys_size_t initdram (int board_type)
@@ -86,9 +86,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -114,11 +114,11 @@
 	if (!dramsize)
 		sdram_start(0);
 
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 
 	if (test1 > test2) {
@@ -164,10 +164,10 @@
 {
 	if (size == 0x800000) { /* adjust mapping */
 		*(vu_long *)MPC5XXX_BOOTCS_START = *(vu_long *)MPC5XXX_CS0_START =
-			START_REG(CFG_BOOTCS_START | size);
+			START_REG(CONFIG_SYS_BOOTCS_START | size);
 
 		*(vu_long *)MPC5XXX_BOOTCS_STOP = *(vu_long *)MPC5XXX_CS0_STOP =
-			STOP_REG(CFG_BOOTCS_START | size, size);
+			STOP_REG(CONFIG_SYS_BOOTCS_START | size, size);
 	}
 }
 
diff --git a/board/omap1610inn/flash.c b/board/omap1610inn/flash.c
index d88a981..36200ad 100644
--- a/board/omap1610inn/flash.c
+++ b/board/omap1610inn/flash.c
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips	   */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -90,11 +90,11 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
-			flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[i]);
-			flash_get_offsets (CFG_FLASH_BASE, &flash_info[i]);
+			flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[i]);
+			flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[i]);
 			/* to reset the lock bit */
 			flash_unlock(&flash_info[i]);
 			break;
@@ -108,8 +108,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
 			CONFIG_ENV_ADDR,
@@ -123,7 +123,7 @@
 void flash_unlock(flash_info_t * info)
 {
 	int j;
-	for (j=2;j<CFG_MAX_FLASH_SECT;j++){
+	for (j=2;j<CONFIG_SYS_MAX_FLASH_SECT;j++){
 	FPWV *addr = (FPWV *) (info->start[j]);
 	flash_unprotect_sectors (addr);
 	*addr = (FPW) 0x00500050;/* clear status register */
@@ -244,10 +244,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -339,7 +339,7 @@
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
 					if (get_timer_masked () >
-					CFG_FLASH_ERASE_TOUT) {
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
 					*addr = (FPW) 0x00B000B0;
@@ -474,7 +474,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/omap2420h4/mem.c b/board/omap2420h4/mem.c
index a3295fd..c8b4186 100644
--- a/board/omap2420h4/mem.c
+++ b/board/omap2420h4/mem.c
@@ -327,7 +327,7 @@
 	__raw_writel(0x10, GPMC_SYSCONFIG);	/* smart idle */
 	__raw_writel(0x0, GPMC_IRQENABLE);	/* isr's sources masked */
 	__raw_writel(tval, GPMC_TIMEOUT_CONTROL);/* timeout disable */
-#ifdef CFG_NAND_BOOT
+#ifdef CONFIG_SYS_NAND_BOOT
 	__raw_writel(0x001, GPMC_CONFIG);	/* set nWP, disable limited addr */
 #else
 	__raw_writel(0x111, GPMC_CONFIG);	/* set nWP, disable limited addr */
@@ -343,7 +343,7 @@
 	__raw_writel(0x0, GPMC_CONFIG7_0);	/* disable current map */
 	sdelay(1000);
 
-#ifdef CFG_NAND_BOOT
+#ifdef CONFIG_SYS_NAND_BOOT
 	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mtype|mwidth, GPMC_CONFIG1_0);
 #else
 	__raw_writel(H4_24XX_GPMC_CONFIG1_0|mux|mtype|mwidth, GPMC_CONFIG1_0);
diff --git a/board/omap2420h4/omap2420h4.c b/board/omap2420h4/omap2420h4.c
index 09b070d..0fe9380 100644
--- a/board/omap2420h4/omap2420h4.c
+++ b/board/omap2420h4/omap2420h4.c
@@ -33,7 +33,7 @@
 #include <asm/mach-types.h>
 #if defined(CONFIG_CMD_NAND)
 #include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -201,7 +201,7 @@
 	u8 vmode_on = 0x8C;
 	#define NOT_EARLY 0
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE); /* need this a bit early */
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); /* need this a bit early */
 
 	btype = get_board_type();
 	mtype = get_mem_type();
@@ -267,7 +267,7 @@
 	__raw_writel(v, CM_CLKSEL2_CORE);
 	__raw_writel(0x1, CM_CLKSEL_WKUP);
 
-#ifdef CFG_NS16550
+#ifdef CONFIG_SYS_NS16550
 	/* Enable UART1 clock */
 	func_clks |= BIT21;
 	if_clks |= BIT21;
@@ -852,16 +852,16 @@
 {
     extern flash_info_t flash_info[];
 
-    nand_probe(CFG_NAND_ADDR);
+    nand_probe(CONFIG_SYS_NAND_ADDR);
     if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN) {
 		print_size(nand_dev_desc[0].totlen, "\n");
     }
 
-#ifdef CFG_JFFS2_MEM_NAND
-    flash_info[CFG_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
-    flash_info[CFG_JFFS2_FIRST_BANK].size = 1024*1024*2;      /* only read kernel single meg partition */
-	flash_info[CFG_JFFS2_FIRST_BANK].sector_count = 1024;   /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
-    flash_info[CFG_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
+#ifdef CONFIG_SYS_JFFS2_MEM_NAND
+    flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].flash_id = nand_dev_desc[0].id;
+    flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].size = 1024*1024*2;      /* only read kernel single meg partition */
+	flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].sector_count = 1024;   /* 1024 blocks in 16meg chip (use less for raw/copied partition) */
+    flash_info[CONFIG_SYS_JFFS2_FIRST_BANK].start[0] = 0x80200000; /* ?, ram for now, open question, copy to RAM or adapt for NAND */
 #endif
 }
 #endif
diff --git a/board/omap730p2/flash.c b/board/omap730p2/flash.c
index 2b62bef..5b56b98 100644
--- a/board/omap730p2/flash.c
+++ b/board/omap730p2/flash.c
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #undef FLASH_PORT_WIDTH32
@@ -88,7 +88,7 @@
 {
 	int i;
 	ulong size = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -104,8 +104,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
 			CONFIG_ENV_ADDR,
@@ -227,10 +227,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -322,7 +322,7 @@
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
 					if (get_timer_masked () >
-					CFG_FLASH_ERASE_TOUT) {
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
 					*addr = (FPW) 0x00B000B0;
@@ -458,7 +458,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/oxc/flash.c b/board/oxc/flash.c
index 94d2660..36e0fca 100644
--- a/board/oxc/flash.c
+++ b/board/oxc/flash.c
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -49,7 +49,7 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
@@ -59,17 +59,17 @@
      * and the size of flash using 0xFF800000 as the base address,
      * and then call flash_get_size() again to fill flash_info.
      */
-    size = flash_get_size((vu_char *)CFG_FLASH_PRELIMBASE, &flash_info[0]);
+    size = flash_get_size((vu_char *)CONFIG_SYS_FLASH_PRELIMBASE, &flash_info[0]);
     if (size)
     {
 	flash_get_size((vu_char *)(-size), &flash_info[0]);
     }
 
-#if (CFG_MONITOR_BASE >= CFG_FLASH_PRELIMBASE)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_PRELIMBASE)
     /* monitor protection ON by default */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 
@@ -286,7 +286,7 @@
     last  = start;
     addr = (vu_char *)(info->start[l_sect]);
     while ((addr[0] & 0x80) != 0x80) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -361,7 +361,7 @@
     /* data polling for D7 */
     start = get_timer (0);
     while ((*((vu_char *)dest) & 0x80) != (data & 0x80)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    return (1);
 	}
     }
diff --git a/board/oxc/oxc.c b/board/oxc/oxc.c
index eb7eeb8..1a2bdf4 100644
--- a/board/oxc/oxc.c
+++ b/board/oxc/oxc.c
@@ -37,13 +37,13 @@
 
 phys_size_t initdram (int board_type)
 {
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long size;
 	long new_bank0_end;
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -92,14 +92,14 @@
 
 int board_early_init_f (void)
 {
-	*(volatile unsigned char *)(CFG_CPLD_RESET) = 0x89;
+	*(volatile unsigned char *)(CONFIG_SYS_CPLD_RESET) = 0x89;
 	return 0;
 }
 
 #ifdef CONFIG_WATCHDOG
 void oxc_wdt_reset(void)
 {
-	*(volatile unsigned char *)(CFG_CPLD_WATCHDOG) = 0xff;
+	*(volatile unsigned char *)(CONFIG_SYS_CPLD_WATCHDOG) = 0xff;
 }
 
 void watchdog_reset(void)
@@ -135,7 +135,7 @@
 
 void board_show_activity (ulong timestamp)
 {
-	if ((timestamp % (CFG_HZ / 10)) == 0)
+	if ((timestamp % (CONFIG_SYS_HZ / 10)) == 0)
 		oxc_toggle_activeled ();
 }
 
@@ -148,9 +148,9 @@
 
 	if ((ledtoggle > (2 * arg)) && ledstatus) {
 		led ^= 0x80;
-		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
 		udelay(200);
-		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, (val & 0x7F) | led);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, (val & 0x7F) | led);
 		ledtoggle = 0;
 	}
 }
@@ -165,13 +165,13 @@
 
 	if (arg > 0 && ledstatus) {
 		ledstatus = 0;
-		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
 		udelay(200);
-		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val | 0x80);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val | 0x80);
 	} else if (arg < 0) {
-		oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val);
+		oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val);
 		udelay(200);
-		oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, val & 0x7F);
+		oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, val & 0x7F);
 		ledstatus = 1;
 	}
 }
@@ -180,21 +180,21 @@
 int misc_init_r (void)
 {
 	/* check whether the i2c expander #0 is accessible */
-	if (!oxc_set_expander(CFG_I2C_EXPANDER0_ADDR, 0x7F)) {
+	if (!oxc_set_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, 0x7F)) {
 		udelay(200);
 		expander0alive = 1;
 	}
 
-#ifdef CFG_OXC_GENERATE_IP
+#ifdef CONFIG_SYS_OXC_GENERATE_IP
 	{
 		char str[32];
-		unsigned long ip = CFG_OXC_IPMASK;
+		unsigned long ip = CONFIG_SYS_OXC_IPMASK;
 		bd_t *bd = gd->bd;
 
 		if (expander0alive) {
 			unsigned char val;
 
-			if (!oxc_get_expander(CFG_I2C_EXPANDER0_ADDR, &val)) {
+			if (!oxc_get_expander(CONFIG_SYS_I2C_EXPANDER0_ADDR, &val)) {
 				ip = (ip & 0xffffff00) | ((val & 0x7c) >> 2);
 			}
 		}
diff --git a/board/pb1x00/flash.c b/board/pb1x00/flash.c
index 3cf29e8..a2fed1d 100644
--- a/board/pb1x00/flash.c
+++ b/board/pb1x00/flash.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*-----------------------------------------------------------------------
  * flash_init()
diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c
index 82e2613..773e446 100644
--- a/board/pb1x00/pb1x00.c
+++ b/board/pb1x00/pb1x00.c
@@ -100,19 +100,19 @@
 	/* We dont need theese unless we run whole pcmcia package */
 	write_one_tlb(20,                 /* index */
 		      0x01ffe000,         /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_IO_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_IO_BASE, /* Hi */
 		      0x3C000017,         /* Lo0 */
 		      0x3C200017);        /* Lo1 */
 
 	write_one_tlb(21,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_ATTR_BASE, /* Hi */
+		      CONFIG_SYS_PCMCIA_ATTR_BASE, /* Hi */
 		      0x3D000017,           /* Lo0 */
 		      0x3D200017);          /* Lo1 */
 #endif	/* 0 */
 	write_one_tlb(22,                   /* index */
 		      0x01ffe000,           /* Pagemask, 16 MB pages */
-		      CFG_PCMCIA_MEM_ADDR,  /* Hi */
+		      CONFIG_SYS_PCMCIA_MEM_ADDR,  /* Hi */
 		      0x3E000017,           /* Lo0 */
 		      0x3E200017);          /* Lo1 */
 #endif	/* CONFIG_IDE_PCMCIA */
diff --git a/board/pcippc2/cpc710_init_ram.c b/board/pcippc2/cpc710_init_ram.c
index 171f06c..8945351 100644
--- a/board/pcippc2/cpc710_init_ram.c
+++ b/board/pcippc2/cpc710_init_ram.c
@@ -81,7 +81,7 @@
 	unsigned long bank_size;
 	u32 mcer;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* Clear memory banks
 	 */
 	out32 (REG (SDRAM0, MCER0), 0);
@@ -107,14 +107,14 @@
 		hang ();
 	}
 	memsize += bank_size;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* Enable bank, zero start
 	 */
 	out32 (REG (SDRAM0, MCER0), mcer | 0x80000000);
 	iobarrier_rw ();
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* Enable memory
 	 */
 	out32 (REG (SDRAM0, MCCR), in32 (REG (SDRAM0, MCCR)) | 0x80000000);
diff --git a/board/pcippc2/flash.c b/board/pcippc2/flash.c
index a915fbe..ec604e0 100644
--- a/board/pcippc2/flash.c
+++ b/board/pcippc2/flash.c
@@ -39,7 +39,7 @@
 #endif
 /*---------------------------------------------------------------------*/
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static ulong flash_get_size (ulong addr, flash_info_t *info);
 static int flash_get_offsets (ulong base, flash_info_t *info);
@@ -52,25 +52,25 @@
 	unsigned long flash_size = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = 0;
 		flash_info[i].size = 0;
 	}
 
-	DEBUGF("\n## Get flash size @ 0x%08x\n", CFG_FLASH_BASE);
+	DEBUGF("\n## Get flash size @ 0x%08x\n", CONFIG_SYS_FLASH_BASE);
 
-	flash_size = flash_get_size (CFG_FLASH_BASE, flash_info);
+	flash_size = flash_get_size (CONFIG_SYS_FLASH_BASE, flash_info);
 
 	DEBUGF("## Flash bank size: %08lx\n", flash_size);
 
 	if (flash_size) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE && \
-    CFG_MONITOR_BASE < CFG_FLASH_BASE + CFG_FLASH_MAX_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE && \
+    CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_MAX_SIZE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE + monitor_flash_len - 1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			      &flash_info[0]);
 #endif
 
@@ -231,10 +231,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	if (! flash_get_offsets (addr, info)) {
@@ -356,10 +356,10 @@
 	last  = start;
 	addr = info->start[l_sect];
 
-	DEBUGF ("Start erase timeout: %d\n", CFG_FLASH_ERASE_TOUT);
+	DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
 
 	while ((in8(addr) & 0x80) != 0x80) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			flash_reset (info->start[0]);
 			return 1;
@@ -488,7 +488,7 @@
 		/* data polling for D7 */
 		start = get_timer (0);
 		while ((in8(dest+i) & 0x80) != (data_ch[i] & 0x80)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				flash_reset (addr);
 				return (1);
 			}
diff --git a/board/pcippc2/i2c.c b/board/pcippc2/i2c.c
index 36b1d0f..ab52562 100644
--- a/board/pcippc2/i2c.c
+++ b/board/pcippc2/i2c.c
@@ -85,7 +85,7 @@
 {
   int			v;
 
-  asm volatile("mtdec %0" : : "r" (time * ((CFG_BUS_CLK / 4) / 1000000)));
+  asm volatile("mtdec %0" : : "r" (time * ((CONFIG_SYS_BUS_CLK / 4) / 1000000)));
 
   do
   {
diff --git a/board/pcippc2/sconsole.c b/board/pcippc2/sconsole.c
index 3b19069..6ef38f4 100644
--- a/board/pcippc2/sconsole.c
+++ b/board/pcippc2/sconsole.c
@@ -41,7 +41,7 @@
 	sb->pos  = 0;
 	sb->size = 0;
 	sb->baud = gd->baudrate;
-	sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+	sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
 
 	return (0);
 }
diff --git a/board/pcippc2/sconsole.h b/board/pcippc2/sconsole.h
index 5d850a5..ff0ccab 100644
--- a/board/pcippc2/sconsole.h
+++ b/board/pcippc2/sconsole.h
@@ -34,7 +34,7 @@
 	char data[1];
 } sconsole_buffer_t;
 
-#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
 
 extern void	(* sconsole_putc)	(char);
 extern void	(* sconsole_puts)	(const char *);
diff --git a/board/pcs440ep/config.mk b/board/pcs440ep/config.mk
index 4d942eb..0844e98 100644
--- a/board/pcs440ep/config.mk
+++ b/board/pcs440ep/config.mk
@@ -43,5 +43,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/pcs440ep/flash.c b/board/pcs440ep/flash.c
index c5a62e2..f90a221 100644
--- a/board/pcs440ep/flash.c
+++ b/board/pcs440ep/flash.c
@@ -24,13 +24,13 @@
 #include <common.h>
 #include <asm/processor.h>
 
-#ifndef CFG_FLASH_READ0
-#define CFG_FLASH_READ0		0x0000	/* 0 is standard			*/
-#define CFG_FLASH_READ1		0x0001	/* 1 is standard			*/
-#define CFG_FLASH_READ2		0x0002	/* 2 is standard			*/
+#ifndef CONFIG_SYS_FLASH_READ0
+#define CONFIG_SYS_FLASH_READ0		0x0000	/* 0 is standard			*/
+#define CONFIG_SYS_FLASH_READ1		0x0001	/* 1 is standard			*/
+#define CONFIG_SYS_FLASH_READ2		0x0002	/* 2 is standard			*/
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*
  * Functions
@@ -45,7 +45,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -130,7 +130,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		/*
 		 * Check if whole sector is erased
 		 */
@@ -175,34 +175,34 @@
 {
 	short i;
 	short n;
-	volatile CFG_FLASH_WORD_SIZE value;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (volatile CFG_FLASH_WORD_SIZE *)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
 
-	value = addr2[CFG_FLASH_READ0];
+	value = addr2[CONFIG_SYS_FLASH_READ0];
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
-	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
 		info->flash_id = FLASH_MAN_EXCEL;
 		break;
-	case (CFG_FLASH_WORD_SIZE)MX_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)MX_MANUFACT:
 		info->flash_id = FLASH_MAN_MX;
 		break;
 	default:
@@ -212,99 +212,99 @@
 		return (0);			/* no or unknown flash	*/
 	}
 
-	value = addr2[CFG_FLASH_READ1];		/* device ID	*/
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID	*/
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000;		/* => 0.5 MB	*/
 		break;
-	case (CFG_FLASH_WORD_SIZE)STM_ID_M29W040B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_ID_M29W040B:
 		info->flash_id += FLASH_AM040;
 		info->sector_count = 8;
 		info->size = 0x0080000; /* => 0,5 MB */
 		break;
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
 		info->flash_id += FLASH_AMDL322T;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
 		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
 		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
 		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;
 		break;				/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
 		info->flash_id += FLASH_SST020;
 		info->sector_count = 64;
 		info->size = 0x00040000;
 		break;				/* => 256 kB	*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
 		info->flash_id += FLASH_SST040;
 		info->sector_count = 128;
 		info->size = 0x00080000;
@@ -381,19 +381,19 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
 			info->protect[i] = 0;
 		else
-			info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+			info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
 	}
 
 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 	}
 
 	return (info->size);
@@ -402,8 +402,8 @@
 
 int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 
@@ -438,14 +438,14 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 
 				/* re-enable interrupts if necessary */
 				if (flag) {
@@ -455,20 +455,20 @@
 
 				/* data polling for D7 */
 				start = get_timer (0);
-				while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-				       (CFG_FLASH_WORD_SIZE)0x00800080) {
-					if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+				       (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 						return (1);
 				}
 			} else {
 				if (sect == s_first) {
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
 				}
-				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 			}
 			l_sect = sect;
 		}
@@ -489,9 +489,9 @@
 
 	start = get_timer (0);
 	last  = start;
-	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -504,8 +504,8 @@
 
 DONE:
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -585,9 +585,9 @@
  */
 static int write_word(flash_info_t *info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
 	int i;
@@ -599,10 +599,10 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
 
-	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -612,9 +612,9 @@
 
 		/* data polling for D7 */
 		start = get_timer (0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 	}
diff --git a/board/pcs440ep/init.S b/board/pcs440ep/init.S
index 36a40c9..25e7f4f 100644
--- a/board/pcs440ep/init.S
+++ b/board/pcs440ep/init.S
@@ -93,10 +93,10 @@
 	 * BOOT_CS (FLASH) must be first. Before relocation SA_I can be off to use the
 	 * speed up boot process. It is patched after relocation to enable SA_I
 	 */
-	tlbentry( CFG_BOOT_BASE_ADDR, SZ_256M, CFG_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
+	tlbentry( CONFIG_SYS_BOOT_BASE_ADDR, SZ_256M, CONFIG_SYS_BOOT_BASE_ADDR, 0, AC_R|AC_W|AC_X|SA_G/*|SA_I*/)
 
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 
 	/*
 	 * TLB entries for SDRAM are not needed on this platform.
@@ -104,15 +104,15 @@
 	 * routine.
 	 */
 
-	tlbentry( CFG_PCI_BASE, SZ_256M, CFG_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, CONFIG_SYS_PCI_BASE, 0, AC_R|AC_W|SA_G|SA_I )
 
 	/* PCI */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE3, SZ_256M, CFG_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE3, SZ_256M, CONFIG_SYS_PCI_MEMBASE3, 0, AC_R|AC_W|SA_G|SA_I )
 
 	/* USB 2.0 Device */
-	tlbentry( CFG_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_USB_DEVICE, SZ_1K, 0x50000000, 0, AC_R|AC_W|SA_G|SA_I )
 
 	tlbtab_end
diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c
index 2140582..271005f 100644
--- a/board/pcs440ep/pcs440ep.c
+++ b/board/pcs440ep/pcs440ep.c
@@ -34,7 +34,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 unsigned char	sha1_checksum[SHA1_SUM_LEN];
 
@@ -193,7 +193,7 @@
 	/* read the MACs from EEprom */
 	status_led_set (0, STATUS_LED_ON);
 	status_led_set (1, STATUS_LED_ON);
-	ret = eeprom_read (CFG_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
+	ret = eeprom_read (CONFIG_SYS_I2C_EEPROM_ADDR, 0, (uchar *)buf, EEPROM_LEN);
 	if (ret == 0) {
 		checksumcrc16 = cyg_crc16 ((uchar *)buf, EEPROM_LEN - 2);
 		/* check, if the EEprom is programmed:
@@ -379,8 +379,8 @@
 	unsigned char org[20];
 	int	i, len = CONFIG_SHA1_LEN;
 
-	memcpy ((char *)CFG_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
-	data = (unsigned char *)CFG_LOAD_ADDR;
+	memcpy ((char *)CONFIG_SYS_LOAD_ADDR, (char *)CONFIG_SHA1_START, len);
+	data = (unsigned char *)CONFIG_SYS_LOAD_ADDR;
 	ptroff = &data[len + SHA1_SUM_POS];
 
 	for (i = 0; i < SHA1_SUM_LEN; i++) {
@@ -485,7 +485,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[1]);
 
@@ -616,7 +616,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -630,14 +630,14 @@
 	  | Make this region non-prefetchable.
 	  +--------------------------------------------------------------------------*/
 	out32r(PCIX0_PMM0MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM0LA, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM0PCILA, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM0LA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM0PCILA, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM0PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM0MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
 	out32r(PCIX0_PMM1MA, 0x00000000);	/* PMM0 Mask/Attribute - disabled b4 setting */
-	out32r(PCIX0_PMM1LA, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
-	out32r(PCIX0_PMM1PCILA, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_PMM1LA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_PMM1PCILA, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_PMM1PCIHA, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_PMM1MA, 0xE0000001);	/* 512M + No prefetching, and enable region */
 
@@ -652,8 +652,8 @@
 
 	/* Program the board's subsystem id/vendor id */
 	pci_write_config_word(0, PCI_SUBSYSTEM_VENDOR_ID,
-			      CFG_PCI_SUBSYS_VENDORID);
-	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CFG_PCI_SUBSYS_ID);
+			      CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	pci_write_config_word(0, PCI_SUBSYSTEM_ID, CONFIG_SYS_PCI_SUBSYS_ID);
 
 	/* Configure command register as bus master */
 	pci_write_config_word(0, PCI_COMMAND, PCI_COMMAND_MASTER);
@@ -667,13 +667,13 @@
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -688,7 +688,7 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
diff --git a/board/pleb2/flash.c b/board/pleb2/flash.c
index 3f01921..abaf0b4 100644
--- a/board/pleb2/flash.c
+++ b/board/pleb2/flash.c
@@ -28,7 +28,7 @@
  */
 #include <environment.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -59,7 +59,7 @@
 static int write_word_amd (flash_info_t * info, FPWV * dest, FPW data);
 static void flash_get_offsets (ulong base, flash_info_t * info);
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 static void flash_sync_real_protect (flash_info_t * info);
 #endif
 
@@ -74,11 +74,11 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b;
 
@@ -90,20 +90,20 @@
 	/* Do this again (was done already in flast_get_size), just
 	 * in case we move it when remap the FLASH.
 	 */
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 	/* read the hardware protection status (if any) into the
 	 * protection array in flash_info.
 	 */
 	flash_sync_real_protect (&flash_info[0]);
 #endif
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 #endif
 
@@ -418,7 +418,7 @@
 	return (info->size);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 
@@ -559,7 +559,7 @@
 
 		while ((*addr & (FPW) 0x00800080) != (FPW) 0x00800080) {
 			if ((now =
-			     get_timer_masked ()) > CFG_FLASH_ERASE_TOUT) {
+			     get_timer_masked ()) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -573,7 +573,7 @@
 			}
 
 			/* show that we're waiting */
-			if ((now - last) > 1 * CFG_HZ) {	/* every second */
+			if ((now - last) > 1 * CONFIG_SYS_HZ) {	/* every second */
 				putc ('.');
 				last = now;
 			}
@@ -609,7 +609,7 @@
 		/* combine source and destination data so can program
 		 * an entire word of 16 or 32 bits
 		 */
-#ifdef CFG_LITTLE_ENDIAN
+#ifdef CONFIG_SYS_LITTLE_ENDIAN
 		for (i = 0; i < sizeof (data); i++) {
 			data >>= 8;
 			if (i < bytes || i - bytes >= left)
@@ -688,7 +688,7 @@
 	/* data polling for D7 */
 	while (res == 0
 	       && (*dest & (FPW) 0x00800080) != (data & (FPW) 0x00800080)) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00F000F0;	/* reset bank */
 			res = 1;
 		}
@@ -733,7 +733,7 @@
 	reset_timer_masked ();
 
 	while (res == 0 && (*dest & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*dest = (FPW) 0x00B000B0;	/* Suspend program      */
 			res = 1;
 		}
@@ -748,7 +748,7 @@
 	return (res);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 int flash_real_protect (flash_info_t * info, long sector, int prot)
diff --git a/board/pleb2/lowlevel_init.S b/board/pleb2/lowlevel_init.S
index add2c53..b95ff9c 100644
--- a/board/pleb2/lowlevel_init.S
+++ b/board/pleb2/lowlevel_init.S
@@ -24,7 +24,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 	.macro CPWAIT reg
@@ -41,92 +41,92 @@
 	/* Set up GPIO pins first */
 
 	ldr	r0,   =GPSR0
-	ldr	r1,   =CFG_GPSR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPSR1
-	ldr	r1,   =CFG_GPSR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPSR2
-	ldr	r1,   =CFG_GPSR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR0
-	ldr	r1,   =CFG_GPCR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR1
-	ldr	r1,   =CFG_GPCR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR2
-	ldr	r1,   =CFG_GPCR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER0
-	ldr	r1,   =CFG_GRER0_VAL
+	ldr	r1,   =CONFIG_SYS_GRER0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER1
-	ldr	r1,   =CFG_GRER1_VAL
+	ldr	r1,   =CONFIG_SYS_GRER1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER2
-	ldr	r1,   =CFG_GRER2_VAL
+	ldr	r1,   =CONFIG_SYS_GRER2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER0
-	ldr	r1,   =CFG_GFER0_VAL
+	ldr	r1,   =CONFIG_SYS_GFER0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER1
-	ldr	r1,   =CFG_GFER1_VAL
+	ldr	r1,   =CONFIG_SYS_GFER1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER2
-	ldr	r1,   =CFG_GFER2_VAL
+	ldr	r1,   =CONFIG_SYS_GFER2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR0
-	ldr	r1,   =CFG_GPDR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR1
-	ldr	r1,   =CFG_GPDR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR2
-	ldr	r1,   =CFG_GPDR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CFG_GAFR0_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CFG_GAFR0_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CFG_GAFR1_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CFG_GAFR1_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CFG_GAFR2_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CFG_GAFR2_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
 	str	r1,   [r0]
 
 	/* enable GPIO pins */
 	ldr	r0,   =PSSR
-	ldr	r1,   =CFG_PSSR_VAL
+	ldr	r1,   =CONFIG_SYS_PSSR_VAL
 	str	r1,   [r0]
 
 
@@ -161,61 +161,61 @@
 	@ Step 2a
 	@ write msc0, read back to ensure data latches
 	@
-	ldr	r2,   =CFG_MSC0_VAL
+	ldr	r2,   =CONFIG_SYS_MSC0_VAL
 	str	r2,   [r1, #MSC0_OFFSET]
 	ldr	r2,   [r1, #MSC0_OFFSET]
 
 	@ write msc1
-	ldr	r2,  =CFG_MSC1_VAL
+	ldr	r2,  =CONFIG_SYS_MSC1_VAL
 	str	r2,  [r1, #MSC1_OFFSET]
 	ldr	r2,  [r1, #MSC1_OFFSET]
 
 	@ write msc2
-	ldr	r2,  =CFG_MSC2_VAL
+	ldr	r2,  =CONFIG_SYS_MSC2_VAL
 	str	r2,  [r1, #MSC2_OFFSET]
 	ldr	r2,  [r1, #MSC2_OFFSET]
 
 
 @ Step 2b
 	@ write mecr
-	ldr	r2,  =CFG_MECR_VAL
+	ldr	r2,  =CONFIG_SYS_MECR_VAL
 	str	r2,  [r1, #MECR_OFFSET]
 
 	@ write mcmem0
-	ldr	r2,  =CFG_MCMEM0_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
 	str	r2,  [r1, #MCMEM0_OFFSET]
 
 	@ write mcmem1
-	ldr	r2,  =CFG_MCMEM1_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
 	str	r2,  [r1, #MCMEM1_OFFSET]
 
 	@ write mcatt0
-	ldr	r2,  =CFG_MCATT0_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
 	str	r2,  [r1, #MCATT0_OFFSET]
 
 	@ write mcatt1
-	ldr	r2,  =CFG_MCATT1_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
 	str	r2,  [r1, #MCATT1_OFFSET]
 
 	@ write mcio0
-	ldr	r2,  =CFG_MCIO0_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
 	str	r2,  [r1, #MCIO0_OFFSET]
 
 	@ write mcio1
-	ldr	r2,  =CFG_MCIO1_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
 	str	r2,  [r1, #MCIO1_OFFSET]
 
 @ Step 2c
 	@ fly-by-dma is defeatured on this part
 	@ write flycnfg
-	@ldr	r2,  =CFG_FLYCNFG_VAL
+	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
 	@str	r2,  [r1, #FLYCNFG_OFFSET]
 
 /* FIXME Does this sequence really make sense */
 #ifdef REDBOOT_WAY
 	@ Step 2d
 	@ get the mdrefr settings
-	ldr	r3,  =CFG_MDREFR_VAL
+	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
 
 	@ extract DRI field (we need a valid DRI field)
 	@
@@ -296,7 +296,7 @@
 #else
 	@ Step 2d
 	@ get the mdrefr settings
-	ldr	r3,  =CFG_MDREFR_VAL
+	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
 
 	@ write back mdrefr
 	@
@@ -340,7 +340,7 @@
 	@ Step 4d
 	@ fetch platform value of mdcnfg
 	@
-	ldr	r2,  =CFG_MDCNFG_VAL
+	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
 
 	@ disable all sdram banks
 	@
@@ -375,7 +375,7 @@
 	@ Access memory *not yet enabled* for CBR refresh cycles (8)
 	@ - CBR is generated for all banks
 
-	ldr	r2, =CFG_DRAM_BASE
+	ldr	r2, =CONFIG_SYS_DRAM_BASE
 	str	r2, [r2]
 	str	r2, [r2]
 	str	r2, [r2]
@@ -405,7 +405,7 @@
 	@ Step 4h
 	@ write mdmrs
 	@
-	ldr	r2,  =CFG_MDMRS_VAL
+	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
 	str	r2,  [r1, #MDMRS_OFFSET]
 
 	@ Done Memory Init
@@ -424,7 +424,7 @@
 
 	@ Set interrupt mask register
 	@
-	ldr	r1,  =CFG_ICMR_VAL
+	ldr	r1,  =CONFIG_SYS_ICMR_VAL
 	ldr	r2,  =ICMR
 	str	r1,  [r2]
 
@@ -440,7 +440,7 @@
 
 	@ set core clocks
 	@
-	ldr	r2,  =CFG_CCCR_VAL
+	ldr	r2,  =CONFIG_SYS_CCCR_VAL
 	ldr	r1,  =CCCR
 	str	r2,  [r1]
 
@@ -463,7 +463,7 @@
 	@ Turn on needed clocks
 	@
 	ldr	r1,  =CKEN
-	ldr	r2,  =CFG_CKEN_VAL
+	ldr	r2,  =CONFIG_SYS_CKEN_VAL
 	str	r2,  [r1]
 
 	/*SET_LED 7 */
diff --git a/board/pm520/flash.c b/board/pm520/flash.c
index 9ec843e..64c8624 100644
--- a/board/pm520/flash.c
+++ b/board/pm520/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -87,11 +87,11 @@
 	ulong size = 0;
 	extern void flash_preinit(void);
 	extern void flash_afterinit(ulong, ulong);
-	ulong flashbase = CFG_FLASH_BASE;
+	ulong flashbase = CONFIG_SYS_FLASH_BASE;
 
 	flash_preinit();
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			memset(&flash_info[i], 0, sizeof(flash_info_t));
@@ -110,11 +110,11 @@
 
 	/* Protect monitor and environment sectors
 	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 #ifndef CONFIG_BOOT_ROM
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 #endif
 #endif
@@ -245,28 +245,28 @@
 		/* In U-Boot we support only 32 MB (no bank-switching) */
 		info->sector_count = 256 / 2;
 		info->size =  0x04000000 / 2;
-		info->start[0] = CFG_FLASH_BASE + 0x02000000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
 		break;				/* => 32 MB     */
 
 	case (FPW) INTEL_ID_28F128J3A:
 		info->flash_id += FLASH_28F128J3A;
 		info->sector_count = 128;
 		info->size = 0x02000000;
-		info->start[0] = CFG_FLASH_BASE + 0x02000000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x02000000;
 		break;				/* => 32 MB     */
 
 	case (FPW) INTEL_ID_28F640J3A:
 		info->flash_id += FLASH_28F640J3A;
 		info->sector_count = 64;
 		info->size = 0x01000000;
-		info->start[0] = CFG_FLASH_BASE + 0x03000000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03000000;
 		break;				/* => 16 MB     */
 
 	case (FPW) INTEL_ID_28F320J3A:
 		info->flash_id += FLASH_28F320J3A;
 		info->sector_count = 32;
 		info->size = 0x800000;
-		info->start[0] = CFG_FLASH_BASE + 0x03800000;
+		info->start[0] = CONFIG_SYS_FLASH_BASE + 0x03800000;
 		break;				/* => 8 MB     */
 
 	default:
@@ -274,10 +274,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -328,7 +328,7 @@
 	/*
 	 * first, wait for the WSM to be finished. The rationale for
 	 * waiting for the WSM to become idle for at most
-	 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
+	 * CONFIG_SYS_FLASH_ERASE_TOUT is as follows. The WSM can be busy
 	 * because of: (1) erase, (2) program or (3) lock bit
 	 * configuration. So we just wait for the longest timeout of
 	 * the (1)-(3), i.e. the erase timeout.
@@ -341,7 +341,7 @@
 
 	start = get_timer (0);
 	while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
-		if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			*addr = (FPW) INTEL_RESET; /* restore read mode */
 			printf("WSM busy too long, can't get prot status\n");
 			return 1;
@@ -425,7 +425,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer(start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -560,7 +560,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -606,7 +606,7 @@
 	start = get_timer(0);
 
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -643,7 +643,7 @@
 				*addr = INTEL_PROTECT;	/* set */
 				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
 				{
-					if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT)
+					if (get_timer(start) > CONFIG_SYS_FLASH_UNLOCK_TOUT)
 					{
 						printf("Flash lock bit operation timed out\n");
 						rc = 1;
diff --git a/board/pm520/pm520.c b/board/pm520/pm520.c
index 6db93fb..9da1041 100644
--- a/board/pm520/pm520.c
+++ b/board/pm520/pm520.c
@@ -37,7 +37,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -80,7 +80,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -89,7 +89,7 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -110,9 +110,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -138,10 +138,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -163,7 +163,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -181,7 +181,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize + dramsize2;
 }
@@ -191,7 +191,7 @@
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup and enable SDRAM chip selects */
@@ -210,9 +210,9 @@
 
 	/* find RAM size */
 	sdram_start(0);
-	test1 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((ulong *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -223,12 +223,12 @@
 	/* set SDRAM end address according to size */
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* Retrieve amount of SDRAM available */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
@@ -318,7 +318,7 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/pm826/flash.c b/board/pm826/flash.c
index bd6d7d9..010f59a 100644
--- a/board/pm826/flash.c
+++ b/board/pm826/flash.c
@@ -28,7 +28,7 @@
 #include <mpc8xx.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -116,13 +116,13 @@
 
 	/* Init: no FLASHes known
 	 */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				size_b0, size_b0 >> 20);
@@ -132,14 +132,14 @@
 	 */
 
 #ifndef CONFIG_BOOT_ROM
-	/* If U-Boot is  booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
+	/* If U-Boot is  booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
 	 * but we shouldn't protect it.
 	 */
 
-# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 # endif
 #endif	/* CONFIG_BOOT_ROM */
@@ -267,7 +267,7 @@
 			last = start;
 			while ((addr[0] & 0x00800080) != 0x00800080 ||
 				   (addr[1] & 0x00800080) != 0x00800080) {
-				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (erase suspended!)\n");
 					/* Suspend erase
 					 */
@@ -362,7 +362,7 @@
 
 	start = get_timer (0);
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			/* Suspend program
 			 */
 			*addr = 0x00B000B0;
diff --git a/board/pm826/pm826.c b/board/pm826/pm826.c
index 2304420..19e7a00 100644
--- a/board/pm826/pm826.c
+++ b/board/pm826/pm826.c
@@ -256,7 +256,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -267,7 +267,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -282,29 +282,29 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9;
 #endif
 	ulong psize = 32 * 1024 * 1024;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-					  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-					  (uchar *) CFG_SDRAM_BASE);
+#ifndef CONFIG_SYS_RAMBOOT
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL) ");
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-						  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	}
 #endif
@@ -314,7 +314,7 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/pm828/flash.c b/board/pm828/flash.c
index 2e92c11..4958a95 100644
--- a/board/pm828/flash.c
+++ b/board/pm828/flash.c
@@ -28,7 +28,7 @@
 #include <mpc8xx.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -116,13 +116,13 @@
 
 	/* Init: no FLASHes known
 	 */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_get_size ((ulong *) CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((ulong *) CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				size_b0, size_b0 >> 20);
@@ -132,14 +132,14 @@
 	 */
 
 #ifndef CONFIG_BOOT_ROM
-	/* If U-Boot is  booted from ROM the CFG_MONITOR_BASE > CFG_FLASH0_BASE
+	/* If U-Boot is  booted from ROM the CONFIG_SYS_MONITOR_BASE > CONFIG_SYS_FLASH0_BASE
 	 * but we shouldn't protect it.
 	 */
 
-# if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]
 	);
 # endif
 #endif	/* CONFIG_BOOT_ROM */
@@ -267,7 +267,7 @@
 			last = start;
 			while ((addr[0] & 0x00800080) != 0x00800080 ||
 				   (addr[1] & 0x00800080) != 0x00800080) {
-				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout (erase suspended!)\n");
 					/* Suspend erase
 					 */
@@ -362,7 +362,7 @@
 
 	start = get_timer (0);
 	while ((*addr & 0x00800080) != 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			/* Suspend program
 			 */
 			*addr = 0x00B000B0;
diff --git a/board/pm828/pm828.c b/board/pm828/pm828.c
index 296a199..4a3b2fd 100644
--- a/board/pm828/pm828.c
+++ b/board/pm828/pm828.c
@@ -259,7 +259,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -270,7 +270,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -315,29 +315,29 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong size8, size9;
 #endif
 	ulong psize = 32 * 1024 * 1024;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-					  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR2_9COL,
-					  (uchar *) CFG_SDRAM_BASE);
+#ifndef CONFIG_SYS_RAMBOOT
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR2_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL) ");
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR2_8COL,
-						  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR2_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL) ");
 	}
 #endif
@@ -347,7 +347,7 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	doc_probe (CFG_DOC_BASE);
+	doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
 
diff --git a/board/pm854/law.c b/board/pm854/law.c
index d74d17a..39e8dbb 100644
--- a/board/pm854/law.c
+++ b/board/pm854/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c
index 90523bd..db855df 100644
--- a/board/pm854/pm854.c
+++ b/board/pm854/pm854.c
@@ -46,7 +46,7 @@
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -83,7 +83,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -133,8 +133,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -154,10 +154,10 @@
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
 	} else {
 		/*
@@ -172,7 +172,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 		udelay(200);
 
 		/*
@@ -186,11 +186,11 @@
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
@@ -227,15 +227,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -244,14 +244,14 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
   #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c
index a7f3813..5e74e2d 100644
--- a/board/pm854/tlb.c
+++ b/board/pm854/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -87,7 +87,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -95,7 +95,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -108,7 +108,7 @@
 	 * Likely it needs to be increased by two for these entries.
 	 */
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 #endif
diff --git a/board/pm856/law.c b/board/pm856/law.c
index d74d17a..39e8dbb 100644
--- a/board/pm856/law.c
+++ b/board/pm856/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c
index ee33286..50c4281 100644
--- a/board/pm856/pm856.c
+++ b/board/pm856/pm856.c
@@ -238,7 +238,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-	    volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	    volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 	    int i,x;
 
 	    x = 10;
@@ -289,8 +289,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -310,10 +310,10 @@
 	lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
 
 	if (lbc_hz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | 0x80000000;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | 0x80000000;	/* DLL Bypass */
 
 	} else if (lbc_hz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000); /* DLL Enabled */
 
 	} else {
 		/*
@@ -328,7 +328,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~0x80000000);/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~0x80000000);/* DLL Enabled */
 		udelay(200);
 
 		/*
@@ -341,11 +341,11 @@
 	}
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
@@ -382,15 +382,15 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-  #ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
     #if defined (CONFIG_DDR_ECC)
 	ddr->err_disable = 0x0000000D;
 	ddr->err_sbe = 0x00ff0000;
@@ -399,14 +399,14 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
   #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c
index a7f3813..5e74e2d 100644
--- a/board/pm856/tlb.c
+++ b/board/pm856/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -87,7 +87,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -95,7 +95,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -108,7 +108,7 @@
 	 * Likely it needs to be increased by two for these entries.
 	 */
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 #endif
diff --git a/board/pn62/pn62.c b/board/pn62/pn62.c
index 60fc431..1b545bf 100644
--- a/board/pn62/pn62.c
+++ b/board/pn62/pn62.c
@@ -85,7 +85,7 @@
 
 	show_startup_phase (2);
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg (MEAR1);
diff --git a/board/ppmc7xx/flash.c b/board/ppmc7xx/flash.c
index 1722a35..e724227 100644
--- a/board/ppmc7xx/flash.c
+++ b/board/ppmc7xx/flash.c
@@ -19,7 +19,7 @@
 static int	write_dword (flash_info_t* info, ulong dest, unsigned char *pdata);
 static void	write_via_fpu (volatile DWORD* addr, DWORD* data);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
@@ -177,12 +177,12 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
-	size_b0 = flash_get_size (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				size_b0, size_b0 >> 20);
@@ -191,10 +191,10 @@
 	/*
 	 * protect monitor and environment sectors
 	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
@@ -359,7 +359,7 @@
 	while ((*(volatile DWORD*)info->start[l_sect] & 0x0080008000800080LL )
 				!= 0x0080008000800080LL )
 	{
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -477,7 +477,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while (*(volatile DWORD*)dest != data ) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/ppmc7xx/pci.c b/board/ppmc7xx/pci.c
index 5b115ea..bf133b7 100644
--- a/board/ppmc7xx/pci.c
+++ b/board/ppmc7xx/pci.c
@@ -42,37 +42,37 @@
     hose->last_busno = 0xff;
 
     pci_set_region(hose->regions + 0,
-	CFG_PCI_MEMORY_BUS,
-	CFG_PCI_MEMORY_PHYS,
-	CFG_PCI_MEMORY_SIZE,
+	CONFIG_SYS_PCI_MEMORY_BUS,
+	CONFIG_SYS_PCI_MEMORY_PHYS,
+	CONFIG_SYS_PCI_MEMORY_SIZE,
 	PCI_REGION_MEM | PCI_REGION_MEMORY);
 
     /* PCI memory space */
     pci_set_region(hose->regions + 1,
-	CFG_PCI_MEM_BUS,
-	CFG_PCI_MEM_PHYS,
-	CFG_PCI_MEM_SIZE,
+	CONFIG_SYS_PCI_MEM_BUS,
+	CONFIG_SYS_PCI_MEM_PHYS,
+	CONFIG_SYS_PCI_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* ISA/PCI memory space */
     pci_set_region(hose->regions + 2,
-	CFG_ISA_MEM_BUS,
-	CFG_ISA_MEM_PHYS,
-	CFG_ISA_MEM_SIZE,
+	CONFIG_SYS_ISA_MEM_BUS,
+	CONFIG_SYS_ISA_MEM_PHYS,
+	CONFIG_SYS_ISA_MEM_SIZE,
 	PCI_REGION_MEM);
 
     /* PCI I/O space */
     pci_set_region(hose->regions + 3,
-	CFG_PCI_IO_BUS,
-	CFG_PCI_IO_PHYS,
-	CFG_PCI_IO_SIZE,
+	CONFIG_SYS_PCI_IO_BUS,
+	CONFIG_SYS_PCI_IO_PHYS,
+	CONFIG_SYS_PCI_IO_SIZE,
 	PCI_REGION_IO);
 
     /* ISA/PCI I/O space */
     pci_set_region(hose->regions + 4,
-	CFG_ISA_IO_BUS,
-	CFG_ISA_IO_PHYS,
-	CFG_ISA_IO_SIZE,
+	CONFIG_SYS_ISA_IO_BUS,
+	CONFIG_SYS_ISA_IO_PHYS,
+	CONFIG_SYS_ISA_IO_SIZE,
 	PCI_REGION_IO);
 
     hose->region_count = 5;
diff --git a/board/ppmc7xx/ppmc7xx.c b/board/ppmc7xx/ppmc7xx.c
index 9c87c10..944cd4d 100644
--- a/board/ppmc7xx/ppmc7xx.c
+++ b/board/ppmc7xx/ppmc7xx.c
@@ -32,7 +32,7 @@
  */
 phys_size_t initdram( int board_type )
 {
-    return CFG_SDRAM_SIZE;
+    return CONFIG_SYS_SDRAM_SIZE;
 }
 
 
diff --git a/board/ppmc8260/ppmc8260.c b/board/ppmc8260/ppmc8260.c
index f3c8509..1808abd 100644
--- a/board/ppmc8260/ppmc8260.c
+++ b/board/ppmc8260/ppmc8260.c
@@ -201,14 +201,14 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	volatile uchar c = 0xff;
-	volatile uchar *ramaddr0 = (uchar *) (CFG_SDRAM0_BASE);
-	volatile uchar *ramaddr1 = (uchar *) (CFG_SDRAM1_BASE);
-	ulong psdmr = CFG_PSDMR;
-	volatile uchar *ramaddr2 = (uchar *) (CFG_SDRAM2_BASE);
-	ulong lsdmr = CFG_LSDMR;
+	volatile uchar *ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE);
+	volatile uchar *ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE);
+	ulong psdmr = CONFIG_SYS_PSDMR;
+	volatile uchar *ramaddr2 = (uchar *) (CONFIG_SYS_SDRAM2_BASE);
+	ulong lsdmr = CONFIG_SYS_LSDMR;
 	int i;
 
 	/*
@@ -228,13 +228,13 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr0++ = c;
 	*ramaddr1++ = c;
@@ -246,8 +246,8 @@
 	}
 
 	memctl->memc_psdmr = psdmr | PSDMR_OP_MRW;
-	ramaddr0 = (uchar *) (CFG_SDRAM0_BASE + 0x110);
-	ramaddr1 = (uchar *) (CFG_SDRAM1_BASE + 0x110);
+	ramaddr0 = (uchar *) (CONFIG_SYS_SDRAM0_BASE + 0x110);
+	ramaddr1 = (uchar *) (CONFIG_SYS_SDRAM1_BASE + 0x110);
 	*ramaddr0 = c;
 	*ramaddr1 = c;
 
@@ -271,15 +271,15 @@
 #endif
 
 	/* return total ram size */
-	return ((CFG_SDRAM0_SIZE + CFG_SDRAM1_SIZE) * 1024 * 1024);
+	return ((CONFIG_SYS_SDRAM0_SIZE + CONFIG_SYS_SDRAM1_SIZE) * 1024 * 1024);
 }
 
 #ifdef CONFIG_MISC_INIT_R
 /* ------------------------------------------------------------------------- */
 int misc_init_r (void)
 {
-#ifdef CFG_LED_BASE
-	uchar ds = *(unsigned char *) (CFG_LED_BASE + 1);
+#ifdef CONFIG_SYS_LED_BASE
+	uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
 	uchar ss;
 	uchar tmp[64];
 	int res;
@@ -298,10 +298,10 @@
 			tmp[17] = '\0';
 			setenv ("ethaddr", (char *)tmp);
 			/* set the led to show the address */
-			*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
+			*((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
 		}
 	}
-#endif /* CFG_LED_BASE */
+#endif /* CONFIG_SYS_LED_BASE */
 	return (0);
 }
 #endif /* CONFIG_MISC_INIT_R */
diff --git a/board/ppmc8260/strataflash.c b/board/ppmc8260/strataflash.c
index f9abfac..cc91627 100644
--- a/board/ppmc8260/strataflash.c
+++ b/board/ppmc8260/strataflash.c
@@ -104,7 +104,7 @@
 
 #define NUM_ERASE_REGIONS 4
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 
 /*-----------------------------------------------------------------------
@@ -121,7 +121,7 @@
 static ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
 static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 /*-----------------------------------------------------------------------
@@ -181,15 +181,15 @@
 	 *
 	 */
 
-	address = CFG_FLASH_BASE;
+	address = CONFIG_SYS_FLASH_BASE;
 	size = 0;
 
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		size += flash_info[i].size = flash_get_size(address, i);
-		address += CFG_FLASH_INCREMENT;
+		address += CONFIG_SYS_FLASH_INCREMENT;
 		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
 				flash_info[0].size, flash_info[i].size<<20);
@@ -197,8 +197,8 @@
 	}
 
 	/* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+monitor_flash_len-1; i++)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1; i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
 
@@ -319,7 +319,7 @@
 		wp = cp;
 	}
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while(cnt >= info->portwidth) {
 		i = info->buffer_size > cnt? cnt: info->buffer_size;
 		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
@@ -340,7 +340,7 @@
 		wp += info->portwidth;
 		cnt -= info->portwidth;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 	if (cnt == 0) {
 		return (0);
 	}
@@ -679,7 +679,7 @@
 	return flash_full_status_check(info, 0, info->write_tout, "write");
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* loop through the sectors from the highest address
  * when the passed address is greater or equal to the sector address
@@ -749,4 +749,4 @@
 	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c
index cc491d0..dc34319 100644
--- a/board/prodrive/alpr/alpr.c
+++ b/board/prodrive/alpr/alpr.c
@@ -92,8 +92,8 @@
 	mtdcr (uic0vr, 0x00000001); /* */
 
 	/* Setup shutdown/SSD empty interrupt as inputs */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
-	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_SHUTDOWN | CFG_GPIO_SSD_EMPTY));
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_SHUTDOWN | CONFIG_SYS_GPIO_SSD_EMPTY));
 
 	/* Setup GPIO/IRQ multiplexing */
 	mtsdr(sdr_pfc0, 0x01a33e00);
@@ -124,8 +124,8 @@
 static int board_rev(void)
 {
 	/* Setup as input */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
-	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CFG_GPIO_REV0 | CFG_GPIO_REV1));
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
+	out32(GPIO0_ODR, in32(GPIO0_ODR) & ~(CONFIG_SYS_GPIO_REV0 | CONFIG_SYS_GPIO_REV1));
 
 	return (in32(GPIO0_IR) >> 16) & 0x3;
 }
@@ -186,7 +186,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*--------------------------------------------------------------------------+
@@ -201,7 +201,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -210,12 +210,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -239,11 +239,11 @@
 	/*
 	 * Configure EREADY as input
 	 */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_GPIO_EREADY);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_GPIO_EREADY);
 	udelay(1000);
 
 	for (;;) {
-		if (in32(GPIO0_IR) & CFG_GPIO_EREADY)
+		if (in32(GPIO0_IR) & CONFIG_SYS_GPIO_EREADY)
 			return;
 	}
 
@@ -260,7 +260,7 @@
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -274,19 +274,19 @@
 	out32r( PCIX0_POM1SA, 0 ); /* disable */
 	out32r( PCIX0_POM2SA, 0 ); /* disable */
 
-	out32r(PCIX0_POM0LAL, CFG_PCI_MEMBASE);	/* PMM0 Local Address */
+	out32r(PCIX0_POM0LAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 Local Address */
 	out32r(PCIX0_POM0LAH, 0x00000003);	/* PMM0 Local Address */
-	out32r(PCIX0_POM0PCIAL, CFG_PCI_MEMBASE);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_POM0PCIAL, CONFIG_SYS_PCI_MEMBASE);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_POM0PCIAH, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_POM0SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
 
-	out32r(PCIX0_POM1LAL, CFG_PCI_MEMBASE2);	/* PMM0 Local Address */
+	out32r(PCIX0_POM1LAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 Local Address */
 	out32r(PCIX0_POM1LAH, 0x00000003);	/* PMM0 Local Address */
-	out32r(PCIX0_POM1PCIAL, CFG_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
+	out32r(PCIX0_POM1PCIAL, CONFIG_SYS_PCI_MEMBASE2);	/* PMM0 PCI Low Address */
 	out32r(PCIX0_POM1PCIAH, 0x00000000);	/* PMM0 PCI High Address */
 	out32r(PCIX0_POM1SA, ~(0x10000000 - 1) | 1);	/* 256MB + enable region */
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_MASTER_INIT) */
 
 #ifdef CONFIG_POST
 /*
diff --git a/board/prodrive/alpr/config.mk b/board/prodrive/alpr/config.mk
index 9e18335..b62e776 100644
--- a/board/prodrive/alpr/config.mk
+++ b/board/prodrive/alpr/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c
index e94360f..0ecebc9 100644
--- a/board/prodrive/alpr/fpga.c
+++ b/board/prodrive/alpr/fpga.c
@@ -61,10 +61,10 @@
 #define	SET_GPIO_0(bit)		SET_GPIO_REG_0(GPIO0_OR, bit)
 #define	SET_GPIO_1(bit)		SET_GPIO_REG_1(GPIO0_OR, bit)
 
-#define FPGA_PRG		(0x80000000 >> CFG_GPIO_PROG_EN)
-#define FPGA_CONFIG		(0x80000000 >> CFG_GPIO_CONFIG)
-#define FPGA_DATA		(0x80000000 >> CFG_GPIO_DATA)
-#define FPGA_CLK		(0x80000000 >> CFG_GPIO_CLK)
+#define FPGA_PRG		(0x80000000 >> CONFIG_SYS_GPIO_PROG_EN)
+#define FPGA_CONFIG		(0x80000000 >> CONFIG_SYS_GPIO_CONFIG)
+#define FPGA_DATA		(0x80000000 >> CONFIG_SYS_GPIO_DATA)
+#define FPGA_CLK		(0x80000000 >> CONFIG_SYS_GPIO_CLK)
 #define OLD_VAL			(FPGA_PRG | FPGA_CONFIG)
 
 #define SET_FPGA(data)		out32(GPIO0_OR, data)
@@ -87,43 +87,43 @@
 
 	reg = in32(GPIO0_IR);
 	/* Enable the FPGA Chain */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_PROG_EN);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_PROG_EN);
-	SET_GPIO_1(CFG_GPIO_PROG_EN);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_SEL_DPR);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_SEL_DPR);
-	SET_GPIO_0((CFG_GPIO_SEL_DPR));
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_1(CONFIG_SYS_GPIO_PROG_EN);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_SEL_DPR);
+	SET_GPIO_0((CONFIG_SYS_GPIO_SEL_DPR));
 
 	/* initialize the GPIO Pins */
 	/* output */
-	SET_GPIO_0(CFG_GPIO_CLK);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CLK);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CLK);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CLK);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CLK);
 
 	/* output */
-	SET_GPIO_0(CFG_GPIO_DATA);
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_DATA);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_DATA);
+	SET_GPIO_0(CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_DATA);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_DATA);
 
 	/* First we set STATUS to 0 then as an input */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
-	SET_GPIO_0(CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_STATUS);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_STATUS);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_0(CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_STATUS);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_STATUS);
 
 	/* output */
-	SET_GPIO_REG_1(GPIO0_TCR, CFG_GPIO_CONFIG);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CONFIG);
-	SET_GPIO_0(CFG_GPIO_CONFIG);
+	SET_GPIO_REG_1(GPIO0_TCR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CONFIG);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 
 	/* input */
-	SET_GPIO_0(CFG_GPIO_CON_DON);
-	SET_GPIO_REG_0(GPIO0_TCR, CFG_GPIO_CON_DON);
-	SET_GPIO_REG_0(GPIO0_ODR, CFG_GPIO_CON_DON);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_TCR, CONFIG_SYS_GPIO_CON_DON);
+	SET_GPIO_REG_0(GPIO0_ODR, CONFIG_SYS_GPIO_CON_DON);
 
 	/* CONFIG = 0 STATUS = 0 -> FPGA in reset state */
-	SET_GPIO_0(CFG_GPIO_CONFIG);
+	SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 	return FPGA_SUCCESS;
 }
 
@@ -131,9 +131,9 @@
 int fpga_config_fn (int assert_config, int flush, int cookie)
 {
 	if (assert_config) {
-		SET_GPIO_1(CFG_GPIO_CONFIG);
+		SET_GPIO_1(CONFIG_SYS_GPIO_CONFIG);
 	} else {
-		SET_GPIO_0(CFG_GPIO_CONFIG);
+		SET_GPIO_0(CONFIG_SYS_GPIO_CONFIG);
 	}
 	return FPGA_SUCCESS;
 }
@@ -144,7 +144,7 @@
 	unsigned long	reg;
 
 	reg = in32(GPIO0_IR);
-	if (reg &= (0x80000000 >> CFG_GPIO_STATUS)) {
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_STATUS)) {
 		PRINTF("STATUS = HIGH\n");
 		return FPGA_FAIL;
 	}
@@ -157,7 +157,7 @@
 {
 	unsigned long	reg;
 	reg = in32(GPIO0_IR);
-	if (reg &= (0x80000000 >> CFG_GPIO_CON_DON)) {
+	if (reg &= (0x80000000 >> CONFIG_SYS_GPIO_CON_DON)) {
 		PRINTF("CONF_DON = HIGH\n");
 		return FPGA_FAIL;
 	}
@@ -189,10 +189,10 @@
 			i --;
 		} while (i > 0);
 
-#ifdef CFG_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		if (bytecount % len_40 == 0) {
 			putc ('.');		/* let them know we are alive */
-#ifdef CFG_FPGA_CHECK_CTRLC
+#ifdef CONFIG_SYS_FPGA_CHECK_CTRLC
 			if (ctrlc ())
 				return FPGA_FAIL;
 #endif
@@ -205,7 +205,7 @@
 /* called, when programming is aborted */
 int fpga_abort_fn (int cookie)
 {
-	SET_GPIO_1((CFG_GPIO_SEL_DPR));
+	SET_GPIO_1((CONFIG_SYS_GPIO_SEL_DPR));
 	return FPGA_SUCCESS;
 }
 
diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S
index 76164ce..4af7d13 100644
--- a/board/prodrive/alpr/init.S
+++ b/board/prodrive/alpr/init.S
@@ -87,26 +87,26 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xff000000, SZ_16M, 0xff000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-	tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+	tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
 #ifdef CONFIG_4xx_DCACHE
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G)
 #else
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
 #endif
 
-#ifdef CFG_INIT_RAM_DCACHE
+#ifdef CONFIG_SYS_INIT_RAM_DCACHE
 	/* TLB-entry for init-ram in dcache (SA_I must be turned off!) */
-	tlbentry( CFG_INIT_RAM_ADDR, SZ_64K, CFG_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
+	tlbentry( CONFIG_SYS_INIT_RAM_ADDR, SZ_64K, CONFIG_SYS_INIT_RAM_ADDR, 0, AC_R|AC_W|AC_X|SA_G )
 #endif
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
 
 	/* PCI */
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, CFG_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE1, SZ_256M, CFG_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE2, SZ_256M, CFG_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, CONFIG_SYS_PCI_MEMBASE, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE1, SZ_256M, CONFIG_SYS_PCI_MEMBASE1, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE2, SZ_256M, CONFIG_SYS_PCI_MEMBASE2, 3, AC_R|AC_W|SA_G|SA_I )
 
 	/* NAND */
-	tlbentry( CFG_NAND_BASE, SZ_4K, CFG_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_NAND_BASE, SZ_4K, CONFIG_SYS_NAND_BASE, 1, AC_R|AC_W|AC_X|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/prodrive/alpr/nand.c b/board/prodrive/alpr/nand.c
index 99f5737..b18c96b 100644
--- a/board/prodrive/alpr/nand.c
+++ b/board/prodrive/alpr/nand.c
@@ -137,7 +137,7 @@
 
 int board_nand_init(struct nand_chip *nand)
 {
-	alpr_ndfc = (struct alpr_ndfc_regs *)CFG_NAND_BASE;
+	alpr_ndfc = (struct alpr_ndfc_regs *)CONFIG_SYS_NAND_BASE;
 
 	nand->ecc.mode = NAND_ECC_SOFT;
 
diff --git a/board/prodrive/common/flash.c b/board/prodrive/common/flash.c
index 363631f..c42fa83 100644
--- a/board/prodrive/common/flash.c
+++ b/board/prodrive/common/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/processor.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*
  * Functions
@@ -91,7 +91,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		/*
 		 * Check if whole sector is erased
 		 */
@@ -136,31 +136,31 @@
 {
 	short i;
 	short n;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong)addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00900090;
 
-	value = addr2[CFG_FLASH_READ0];
+	value = addr2[CONFIG_SYS_FLASH_READ0];
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_MANUFACT:
 		info->flash_id = FLASH_MAN_AMD;
 		break;
-	case (CFG_FLASH_WORD_SIZE)FUJ_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)FUJ_MANUFACT:
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
-	case (CFG_FLASH_WORD_SIZE)SST_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_MANUFACT:
 		info->flash_id = FLASH_MAN_SST;
 		break;
-	case (CFG_FLASH_WORD_SIZE)STM_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)STM_MANUFACT:
 		info->flash_id = FLASH_MAN_STM;
 		break;
-	case (CFG_FLASH_WORD_SIZE)EXCEL_MANUFACT:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)EXCEL_MANUFACT:
 		info->flash_id = FLASH_MAN_EXCEL;
 		break;
 	default:
@@ -170,82 +170,82 @@
 		return (0);			/* no or unknown flash	*/
 	}
 
-	value = addr2[CFG_FLASH_READ1];		/* device ID		*/
+	value = addr2[CONFIG_SYS_FLASH_READ1];		/* device ID		*/
 
 	switch (value) {
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400T:
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV400B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00080000;
 		break;				/* => 0.5 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV800B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00100000;
 		break;				/* => 1 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV160B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
 		break;				/* => 2 MB		*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322T:
 		info->flash_id += FLASH_AMDL322T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL322B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL322B:
 		info->flash_id += FLASH_AMDL322B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323T:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323T:
 		info->flash_id += FLASH_AMDL323T;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)AMD_ID_DL323B:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_DL323B:
 		info->flash_id += FLASH_AMDL323B;
 		info->sector_count = 71;
 		info->size = 0x00400000;  break;	/* => 4 MB	*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF020:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF020:
 		info->flash_id += FLASH_SST020;
 		info->sector_count = 64;
 		info->size = 0x00040000;
 		break;				/* => 256 kB		*/
 
-	case (CFG_FLASH_WORD_SIZE)SST_ID_xF040:
+	case (CONFIG_SYS_FLASH_WORD_SIZE)SST_ID_xF040:
 		info->flash_id += FLASH_SST040;
 		info->sector_count = 128;
 		info->size = 0x00080000;
@@ -318,19 +318,19 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 		if ((info->flash_id & FLASH_VENDMASK) != FLASH_MAN_AMD)
 			info->protect[i] = 0;
 		else
-			info->protect[i] = addr2[CFG_FLASH_READ2] & 1;
+			info->protect[i] = addr2[CONFIG_SYS_FLASH_READ2] & 1;
 	}
 
 	/*
 	 * Prevent writes to uninitialized FLASH.
 	 */
 	if (info->flash_id != FLASH_UNKNOWN) {
-		addr2 = (CFG_FLASH_WORD_SIZE *)info->start[0];
-		*addr2 = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+		addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+		*addr2 = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 	}
 
 	return (info->size);
@@ -339,8 +339,8 @@
 
 int flash_erase(flash_info_t *info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 	ulong start, now, last;
 
@@ -375,14 +375,14 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect<=s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[sect]);
 			if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) {
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-				addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-				addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+				addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+				addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 
 				/* re-enable interrupts if necessary */
 				if (flag) {
@@ -392,20 +392,20 @@
 
 				/* data polling for D7 */
 				start = get_timer (0);
-				while ((addr2[0] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-				       (CFG_FLASH_WORD_SIZE)0x00800080) {
-					if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+				while ((addr2[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+				       (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+					if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 						return (1);
 				}
 			} else {
 				if (sect == s_first) {
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00800080;
-					addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-					addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080;
+					addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+					addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
 				}
-				addr2[0] = (CFG_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
+				addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00300030;  /* sector erase */
 			}
 			l_sect = sect;
 		}
@@ -426,9 +426,9 @@
 
 	start = get_timer (0);
 	last  = start;
-	addr = (CFG_FLASH_WORD_SIZE *)(info->start[l_sect]);
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE)0x00800080) != (CFG_FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[l_sect]);
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) != (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -441,8 +441,8 @@
 
 DONE:
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *)info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *)info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00F000F0;	/* reset bank */
 
 	printf (" done\n");
 	return 0;
@@ -522,9 +522,9 @@
  */
 static int write_word(flash_info_t *info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *)(info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *)dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *)&data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *)dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *)&data;
 	ulong start;
 	int flag;
 	int i;
@@ -536,10 +536,10 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
 
-	for (i=0; i<4/sizeof(CFG_FLASH_WORD_SIZE); i++) {
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE)0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE)0x00A000A0;
+	for (i=0; i<4/sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE)0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -549,9 +549,9 @@
 
 		/* data polling for D7 */
 		start = get_timer (0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE)0x00800080) !=
-		       (data2[i] & (CFG_FLASH_WORD_SIZE)0x00800080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080) !=
+		       (data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE)0x00800080)) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 	}
diff --git a/board/prodrive/common/fpga.c b/board/prodrive/common/fpga.c
index f9412a2..14bff07 100644
--- a/board/prodrive/common/fpga.c
+++ b/board/prodrive/common/fpga.c
@@ -37,11 +37,11 @@
 #define DBG(x...)
 #endif /* DEBUG */
 
-#define FPGA_PRG		CFG_FPGA_PRG /* FPGA program pin (cpu output)*/
-#define FPGA_CLK		CFG_FPGA_CLK /* FPGA clk pin (cpu output)    */
-#define FPGA_DATA		CFG_FPGA_DATA /* FPGA data pin (cpu output)  */
-#define FPGA_DONE		CFG_FPGA_DONE /* FPGA done pin (cpu input)   */
-#define FPGA_INIT		CFG_FPGA_INIT /* FPGA init pin (cpu input)   */
+#define FPGA_PRG		CONFIG_SYS_FPGA_PRG /* FPGA program pin (cpu output)*/
+#define FPGA_CLK		CONFIG_SYS_FPGA_CLK /* FPGA clk pin (cpu output)    */
+#define FPGA_DATA		CONFIG_SYS_FPGA_DATA /* FPGA data pin (cpu output)  */
+#define FPGA_DONE		CONFIG_SYS_FPGA_DONE /* FPGA done pin (cpu input)   */
+#define FPGA_INIT		CONFIG_SYS_FPGA_INIT /* FPGA init pin (cpu input)   */
 
 #define ERROR_FPGA_PRG_INIT_LOW  -1        /* Timeout after PRG* asserted   */
 #define ERROR_FPGA_PRG_INIT_HIGH -2        /* Timeout after PRG* deasserted */
diff --git a/board/prodrive/p3mx/misc.S b/board/prodrive/p3mx/misc.S
index 160b1d3..233fd83 100644
--- a/board/prodrive/p3mx/misc.S
+++ b/board/prodrive/p3mx/misc.S
@@ -16,7 +16,7 @@
 board_relocate_rom:
 	mflr	r7
 	/* update the location of the GT registers */
-	lis	r11, CFG_GT_REGS@h
+	lis	r11, CONFIG_SYS_GT_REGS@h
 	/* if we're using ECC, we must use the DMA engine to copy ourselves */
 	bl	start_idma_transfer_0
 	bl	wait_for_idma_0
@@ -29,12 +29,12 @@
 board_init_ecc:
 	mflr	r7
 	/* NOTE: r10 still contains the location we've been relocated to
-	 * which happens to be TOP_OF_RAM - CFG_MONITOR_LEN */
+	 * which happens to be TOP_OF_RAM - CONFIG_SYS_MONITOR_LEN */
 
 	/* now that we're running from ram, init the rest of main memory
 	 * for ECC use */
-	lis	r8, CFG_MONITOR_LEN@h
-	ori	r8, r8, CFG_MONITOR_LEN@l
+	lis	r8, CONFIG_SYS_MONITOR_LEN@h
+	ori	r8, r8, CONFIG_SYS_MONITOR_LEN@l
 
 	divw	r3, r10, r8
 
@@ -120,15 +120,15 @@
 	blr
 #endif
 
-#ifdef CFG_BOARD_ASM_INIT
+#ifdef CONFIG_SYS_BOARD_ASM_INIT
 	/* NOTE: trashes r3-r7 */
 	.globl board_asm_init
 board_asm_init:
 	/* just move the GT registers to where they belong */
-	lis	r3, CFG_DFL_GT_REGS@h
-	ori	r3, r3, CFG_DFL_GT_REGS@l
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r3, CONFIG_SYS_DFL_GT_REGS@h
+	ori	r3, r3, CONFIG_SYS_DFL_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTERNAL_SPACE_DECODE
 
 	/* test to see if we've already moved */
@@ -153,11 +153,11 @@
 	cmp	cr0, r7, r6
 	bne	1b
 
-	lis	r3, CFG_INT_SRAM_BASE@h
-	ori	r3, r3, CFG_INT_SRAM_BASE@l
+	lis	r3, CONFIG_SYS_INT_SRAM_BASE@h
+	ori	r3, r3, CONFIG_SYS_INT_SRAM_BASE@l
 	rlwinm  r3, r3, 16, 16, 31
-	lis	r4, CFG_GT_REGS@h
-	ori	r4, r4, CFG_GT_REGS@l
+	lis	r4, CONFIG_SYS_GT_REGS@h
+	ori	r4, r4, CONFIG_SYS_GT_REGS@l
 	li	r5, INTEGRATED_SRAM_BASE_ADDR
 	stwbrx  r3, r5, r4
 
diff --git a/board/prodrive/p3mx/mpsc.c b/board/prodrive/p3mx/mpsc.c
index 2494ec6..cc05b45 100644
--- a/board/prodrive/p3mx/mpsc.c
+++ b/board/prodrive/p3mx/mpsc.c
@@ -422,7 +422,7 @@
 			  (MV64460_CUNIT_BASE_ADDR_WIN_0_BIT * 2)));
 
 	/* Setup MPSC internal address space base address	*/
-	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CFG_GT_REGS);
+	GT_REG_WRITE (CUNIT_INTERNAL_SPACE_BASE_ADDR_REG, CONFIG_SYS_GT_REGS);
 
 	/* no high address remap*/
 	GT_REG_WRITE (CUNIT_HIGH_ADDR_REMAP_REG0, 0x00);
@@ -512,9 +512,9 @@
 
 #ifdef ZUMA_NTL
 	/* from tclk */
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #else
-	clock = (CFG_TCLK / (16 * rate)) - 1;
+	clock = (CONFIG_SYS_TCLK / (16 * rate)) - 1;
 #endif
 
 	galbrg_set_CDV (channel, clock);	/* set timer Reg. for BRG */
diff --git a/board/prodrive/p3mx/p3mx.c b/board/prodrive/p3mx/p3mx.c
index 69d7c9b..0247bb8 100644
--- a/board/prodrive/p3mx/p3mx.c
+++ b/board/prodrive/p3mx/p3mx.c
@@ -67,7 +67,7 @@
 /* ------------------------------------------------------------------------- */
 
 /* this is the current GT register space location */
-/* it starts at CFG_DFL_GT_REGS but moves later to CFG_GT_REGS */
+/* it starts at CONFIG_SYS_DFL_GT_REGS but moves later to CONFIG_SYS_GT_REGS */
 
 /* Unfortunately, we cant change it while we are in flash, so we initialize it
  * to the "final" value. This means that any debug_led calls before
@@ -76,7 +76,7 @@
  */
 
 void board_prebootm_init (void);
-unsigned int INTERNAL_REG_BASE_ADDR = CFG_GT_REGS;
+unsigned int INTERNAL_REG_BASE_ADDR = CONFIG_SYS_GT_REGS;
 int display_mem_map (void);
 void set_led(int);
 
@@ -129,7 +129,7 @@
 
 		GT_REG_WRITE (PCI_0_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_0_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 
 	}
 	if ((GTREGREAD (PCI_1_MODE) & (BIT4 | BIT5)) != 0) {	/* if  PCI-X */
@@ -138,7 +138,7 @@
 
 		GT_REG_WRITE (PCI_1_CONFIG_ADDR, BIT31 | val);
 		GT_REG_WRITE (PCI_1_CONFIG_DATA_VIRTUAL_REG,
-			      (stat & 0xffff0000) | CFG_PCI_IDSEL);
+			      (stat & 0xffff0000) | CONFIG_SYS_PCI_IDSEL);
 	}
 
 	/* Enable master */
@@ -157,21 +157,21 @@
 	 * in 64360 when writing to pci base go and overide remap automaticaly,
 	 * in 64460 it doesn't
 	 */
-	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CFG_PCI0_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CFG_PCI0_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_0_IO_SIZE, (CFG_PCI0_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_IO_BASE_ADDR, CONFIG_SYS_PCI0_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_0I_O_ADDRESS_REMAP, CONFIG_SYS_PCI0_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_0_IO_SIZE, (CONFIG_SYS_PCI0_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CFG_PCI0_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CFG_PCI0_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI0_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_0_MEMORY0_SIZE, (CONFIG_SYS_PCI0_MEM_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CFG_PCI1_IO_SPACE >> 16);
-	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CFG_PCI1_IO_SPACE_PCI >> 16);
-	GT_REG_WRITE (PCI_1_IO_SIZE, (CFG_PCI1_IO_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_IO_BASE_ADDR, CONFIG_SYS_PCI1_IO_SPACE >> 16);
+	GT_REG_WRITE (PCI_1I_O_ADDRESS_REMAP, CONFIG_SYS_PCI1_IO_SPACE_PCI >> 16);
+	GT_REG_WRITE (PCI_1_IO_SIZE, (CONFIG_SYS_PCI1_IO_SIZE - 1) >> 16);
 
-	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CFG_PCI1_MEM_BASE >> 16);
-	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CFG_PCI1_MEM_SIZE - 1) >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_BASE_ADDR, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1MEMORY0_ADDRESS_REMAP, CONFIG_SYS_PCI1_MEM_BASE >> 16);
+	GT_REG_WRITE (PCI_1_MEMORY0_SIZE, (CONFIG_SYS_PCI1_MEM_SIZE - 1) >> 16);
 
 	/* PCI interface settings */
 	/* Timeout set to retry forever */
@@ -189,7 +189,7 @@
 	for (stat = 0; stat <= PCI_HOST1; stat++)
 		pciWriteConfigReg (stat,
 				   PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS,
-				   SELF, CFG_GT_REGS);
+				   SELF, CONFIG_SYS_GT_REGS);
 #endif
 
 }
@@ -204,7 +204,7 @@
 	/* cpu configuration register */
 	tmp = GTREGREAD (CPU_CONFIGURATION);
 	/* set the SINGLE_CPU bit  see MV64460 */
-#ifndef CFG_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
+#ifndef CONFIG_SYS_GT_DUAL_CPU		/* SINGLE_CPU seems to cause JTAG problems */
 	tmp |= CPU_CONF_SINGLE_CPU;
 #endif
 	tmp &= ~CPU_CONF_AACK_DELAY_2;
@@ -246,7 +246,7 @@
 	 * that if it's not at the power-on location, it's where we put
 	 * it last time. (huber)
 	 */
-	my_remap_gt_regs (CFG_DFL_GT_REGS, CFG_GT_REGS);
+	my_remap_gt_regs (CONFIG_SYS_DFL_GT_REGS, CONFIG_SYS_GT_REGS);
 
 #ifdef CONFIG_PCI
 	gt_pci_config ();
@@ -274,17 +274,17 @@
 	memoryMapDeviceSpace(DEVICE3, 0, 0);
 	GT_REG_WRITE(DEVICE_BANK3PARAMETERS, 0);
 
-	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CFG_BOOT_PAR);
+	GT_REG_WRITE(DEVICE_BOOT_BANK_PARAMETERS, CONFIG_SYS_BOOT_PAR);
 
 	gt_cpu_config();
 
 	/* MPP setup */
-	GT_REG_WRITE (MPP_CONTROL0, CFG_MPP_CONTROL_0);
-	GT_REG_WRITE (MPP_CONTROL1, CFG_MPP_CONTROL_1);
-	GT_REG_WRITE (MPP_CONTROL2, CFG_MPP_CONTROL_2);
-	GT_REG_WRITE (MPP_CONTROL3, CFG_MPP_CONTROL_3);
+	GT_REG_WRITE (MPP_CONTROL0, CONFIG_SYS_MPP_CONTROL_0);
+	GT_REG_WRITE (MPP_CONTROL1, CONFIG_SYS_MPP_CONTROL_1);
+	GT_REG_WRITE (MPP_CONTROL2, CONFIG_SYS_MPP_CONTROL_2);
+	GT_REG_WRITE (MPP_CONTROL3, CONFIG_SYS_MPP_CONTROL_3);
 
-	GT_REG_WRITE (GPP_LEVEL_CONTROL, CFG_GPP_LEVEL_CONTROL);
+	GT_REG_WRITE (GPP_LEVEL_CONTROL, CONFIG_SYS_GPP_LEVEL_CONTROL);
 
 	set_led(LED_RED);
 
@@ -298,7 +298,7 @@
 	u8 val;
 
 	icache_enable ();
-#ifdef CFG_L2
+#ifdef CONFIG_SYS_L2
 	l2cache_enable ();
 #endif
 #ifdef CONFIG_MPSC
@@ -311,7 +311,7 @@
 	 * No diode, 250 ohm series resistor
 	 */
 	val = 0xa5;
-	i2c_write(CFG_I2C_RTC_ADDR, 8, 1, &val, 1);
+	i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 8, 1, &val, 1);
 
 	return 0;
 }
@@ -328,7 +328,7 @@
 
 void after_reloc (ulong dest_addr, gd_t * gd)
 {
-	memoryMapDeviceSpace (BOOT_DEVICE, CFG_BOOT_SPACE, CFG_BOOT_SIZE);
+	memoryMapDeviceSpace (BOOT_DEVICE, CONFIG_SYS_BOOT_SPACE, CONFIG_SYS_BOOT_SIZE);
 
 /*	display_mem_map(); */
 
@@ -347,7 +347,7 @@
 {
 	char *s = getenv("serial#");
 
-	printf("Board: %s", CFG_BOARD_NAME);
+	printf("Board: %s", CONFIG_SYS_BOARD_NAME);
 
 	if (s != NULL) {
 		puts(", serial# ");
@@ -458,7 +458,7 @@
 
 /* DRAM check routines copied from gw8260 */
 
-#if defined (CFG_DRAM_TEST)
+#if defined (CONFIG_SYS_DRAM_TEST)
 
 /*********************************************************************/
 /* NAME:  move64() -  moves a double word (64-bit)		     */
@@ -489,7 +489,7 @@
 }
 
 
-#if defined (CFG_DRAM_TEST_DATA)
+#if defined (CONFIG_SYS_DRAM_TEST_DATA)
 
 unsigned long long pattern[] = {
 	0xaaaaaaaaaaaaaaaaULL,
@@ -552,7 +552,7 @@
 /*********************************************************************/
 int mem_test_data (void)
 {
-	unsigned long long *pmem = (unsigned long long *) CFG_MEMTEST_START;
+	unsigned long long *pmem = (unsigned long long *) CONFIG_SYS_MEMTEST_START;
 	unsigned long long temp64 = 0;
 	int num_patterns = sizeof (pattern) / sizeof (pattern[0]);
 	int i;
@@ -579,9 +579,9 @@
 
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_DATA */
+#endif /* CONFIG_SYS_DRAM_TEST_DATA */
 
-#if defined (CFG_DRAM_TEST_ADDRESS)
+#if defined (CONFIG_SYS_DRAM_TEST_ADDRESS)
 /*********************************************************************/
 /* NAME:  mem_test_address() -	test address lines		     */
 /*								     */
@@ -606,8 +606,8 @@
 int mem_test_address (void)
 {
 	volatile unsigned int *pmem =
-		(volatile unsigned int *) CFG_MEMTEST_START;
-	const unsigned int size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 4;
+		(volatile unsigned int *) CONFIG_SYS_MEMTEST_START;
+	const unsigned int size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 4;
 	unsigned int i;
 
 	/* write address to each location */
@@ -623,9 +623,9 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_ADDRESS */
+#endif /* CONFIG_SYS_DRAM_TEST_ADDRESS */
 
-#if defined (CFG_DRAM_TEST_WALK)
+#if defined (CONFIG_SYS_DRAM_TEST_WALK)
 /*********************************************************************/
 /* NAME:   mem_march() -  memory march				     */
 /*								     */
@@ -683,7 +683,7 @@
 	}
 	return 0;
 }
-#endif /* CFG_DRAM_TEST_WALK */
+#endif /* CONFIG_SYS_DRAM_TEST_WALK */
 
 /*********************************************************************/
 /* NAME:   mem_test_walk() -  a simple walking ones test	     */
@@ -715,8 +715,8 @@
 {
 	unsigned long long mask;
 	volatile unsigned long long *pmem =
-		(volatile unsigned long long *) CFG_MEMTEST_START;
-	const unsigned long size = (CFG_MEMTEST_END - CFG_MEMTEST_START) / 8;
+		(volatile unsigned long long *) CONFIG_SYS_MEMTEST_START;
+	const unsigned long size = (CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START) / 8;
 
 	unsigned int i;
 
@@ -782,15 +782,15 @@
 	int runaddress = 0;
 	int runwalk    = 0;
 
-#ifdef CFG_DRAM_TEST_DATA
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	s = getenv ("testdramdata");
 	rundata = (s && (*s == 'y')) ? 1 : 0;
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	s = getenv ("testdramaddress");
 	runaddress = (s && (*s == 'y')) ? 1 : 0;
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	s = getenv ("testdramwalk");
 	runwalk = (s && (*s == 'y')) ? 1 : 0;
 #endif
@@ -798,8 +798,8 @@
 	if ((rundata == 1) || (runaddress == 1) || (runwalk == 1))
 		printf ("Testing RAM from 0x%08x to 0x%08x ...  "
 			"(don't panic... that will take a moment !!!!)\n",
-			CFG_MEMTEST_START, CFG_MEMTEST_END);
-#ifdef CFG_DRAM_TEST_DATA
+			CONFIG_SYS_MEMTEST_START, CONFIG_SYS_MEMTEST_END);
+#ifdef CONFIG_SYS_DRAM_TEST_DATA
 	if (rundata == 1) {
 		printf ("Test DATA ...  ");
 		if (mem_test_data () == 1) {
@@ -809,7 +809,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_ADDRESS
+#ifdef CONFIG_SYS_DRAM_TEST_ADDRESS
 	if (runaddress == 1) {
 		printf ("Test ADDRESS ...  ");
 		if (mem_test_address () == 1) {
@@ -819,7 +819,7 @@
 			printf ("ok \n");
 	}
 #endif
-#ifdef CFG_DRAM_TEST_WALK
+#ifdef CONFIG_SYS_DRAM_TEST_WALK
 	if (runwalk == 1) {
 		printf ("Test WALKING ONEs ...  ");
 		if (mem_test_walk () == 1) {
@@ -834,7 +834,7 @@
 	return 0;
 
 }
-#endif /* CFG_DRAM_TEST */
+#endif /* CONFIG_SYS_DRAM_TEST */
 
 /* ronen - the below functions are used by the bootm function           */
 /*  - we map the base register to fbe00000 (same mapping as in the LSP) */
diff --git a/board/prodrive/p3mx/pci.c b/board/prodrive/p3mx/pci.c
index 137739b..85f7caa 100644
--- a/board/prodrive/p3mx/pci.c
+++ b/board/prodrive/p3mx/pci.c
@@ -932,14 +932,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci0_hose.regions + 0,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_0_MEM_SPACE,
-			CFG_PCI0_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_0_MEM_SPACE,
+			CONFIG_SYS_PCI0_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci0_hose.regions + 1,
-			CFG_PCI0_IO_SPACE_PCI,
-			CFG_PCI0_IO_SPACE, CFG_PCI0_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI0_IO_SPACE_PCI,
+			CONFIG_SYS_PCI0_IO_SPACE, CONFIG_SYS_PCI0_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci0_hose,
 		     pci_hose_read_config_byte_via_dword,
@@ -981,14 +981,14 @@
 
 	/* PCI memory space */
 	pci_set_region (pci1_hose.regions + 0,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_0_MEM_SPACE,
-			CFG_PCI1_MEM_SIZE, PCI_REGION_MEM);
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_0_MEM_SPACE,
+			CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
 
 	/* PCI I/O space */
 	pci_set_region (pci1_hose.regions + 1,
-			CFG_PCI1_IO_SPACE_PCI,
-			CFG_PCI1_IO_SPACE, CFG_PCI1_IO_SIZE, PCI_REGION_IO);
+			CONFIG_SYS_PCI1_IO_SPACE_PCI,
+			CONFIG_SYS_PCI1_IO_SPACE, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO);
 
 	pci_set_ops (&pci1_hose,
 		     pci_hose_read_config_byte_via_dword,
diff --git a/board/prodrive/p3mx/sdram_init.c b/board/prodrive/p3mx/sdram_init.c
index d881d38..bac6c12 100644
--- a/board/prodrive/p3mx/sdram_init.c
+++ b/board/prodrive/p3mx/sdram_init.c
@@ -243,9 +243,9 @@
 	udelay(2);  /* FIXME  make this dynamic for the system clock */
 
 	/* SDRAM init done */
-	memory_map_bank(0, CFG_SDRAM_BASE,  (256 << 20));
-#ifdef CFG_SDRAM1_BASE
-	memory_map_bank(1, CFG_SDRAM1_BASE, (256 << 20));
+	memory_map_bank(0, CONFIG_SYS_SDRAM_BASE,  (256 << 20));
+#ifdef CONFIG_SYS_SDRAM1_BASE
+	memory_map_bank(1, CONFIG_SYS_SDRAM1_BASE, (256 << 20));
 #endif
 
 	/* DUNIT_MMASK: enable SnoopHitEn bit to avoid errata CPU-#4
diff --git a/board/prodrive/p3p440/config.mk b/board/prodrive/p3p440/config.mk
index e5722dd..60d3bf4 100644
--- a/board/prodrive/p3p440/config.mk
+++ b/board/prodrive/p3p440/config.mk
@@ -40,5 +40,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S
index ee6b706..8c1a79c 100644
--- a/board/prodrive/p3p440/init.S
+++ b/board/prodrive/p3p440/init.S
@@ -90,10 +90,10 @@
 tlbtab:
     tlbtab_start
     tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-    tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-    tlbentry( CFG_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
-    tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-    tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-    tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+    tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_4K, 0x80000000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CONFIG_SYS_ISRAM_BASE + 0x1000, SZ_4K, 0x80001000, 0, AC_R|AC_W|AC_X )
+    tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+    tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
     tlbtab_end
diff --git a/board/prodrive/p3p440/p3p440.c b/board/prodrive/p3p440/p3p440.c
index 1a8aacb..1a0486f 100644
--- a/board/prodrive/p3p440/p3p440.c
+++ b/board/prodrive/p3p440/p3p440.c
@@ -35,29 +35,29 @@
 {
 	switch (color) {
 	case LED_OFF:
-		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_LED_GREEN & ~CFG_LED_RED);
+		out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_LED_GREEN & ~CONFIG_SYS_LED_RED);
 		break;
 
 	case LED_GREEN:
-		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_GREEN) & ~CFG_LED_RED);
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN) & ~CONFIG_SYS_LED_RED);
 		break;
 
 	case LED_RED:
-		out32(GPIO0_OR,  (in32(GPIO0_OR) | CFG_LED_RED) & ~CFG_LED_GREEN);
+		out32(GPIO0_OR,  (in32(GPIO0_OR) | CONFIG_SYS_LED_RED) & ~CONFIG_SYS_LED_GREEN);
 		break;
 
 	case LED_ORANGE:
-		out32(GPIO0_OR,  in32(GPIO0_OR) | CFG_LED_GREEN | CFG_LED_RED);
+		out32(GPIO0_OR,  in32(GPIO0_OR) | CONFIG_SYS_LED_GREEN | CONFIG_SYS_LED_RED);
 		break;
 	}
 }
 
 static int is_monarch(void)
 {
-	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CFG_GPIO_RDY);
+	out32(GPIO0_OR,  in32(GPIO0_OR) & ~CONFIG_SYS_GPIO_RDY);
 	udelay(1000);
 
-	if (in32(GPIO0_IR) & CFG_MONARCH_IO)
+	if (in32(GPIO0_IR) & CONFIG_SYS_MONARCH_IO)
 		return 0;
 	else
 		return 1;
@@ -68,11 +68,11 @@
 	/*
 	 * Configure EREADY_IO as input
 	 */
-	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CFG_EREADY_IO);
+	out32(GPIO0_TCR, in32(GPIO0_TCR) & ~CONFIG_SYS_EREADY_IO);
 	udelay(1000);
 
 	for (;;) {
-		if (in32(GPIO0_IR) & CFG_EREADY_IO)
+		if (in32(GPIO0_IR) & CONFIG_SYS_EREADY_IO)
 			return;
 	}
 
@@ -95,8 +95,8 @@
 	mtdcr(cpc0_gpio, 0x03F01F80);
 
 	out32(GPIO0_ODR, 0x00000000);	/* no open drain pins      */
-	out32(GPIO0_TCR, CFG_GPIO_RDY | CFG_EREADY_IO | CFG_LED_RED | CFG_LED_GREEN);
-	out32(GPIO0_OR,  CFG_GPIO_RDY);
+	out32(GPIO0_TCR, CONFIG_SYS_GPIO_RDY | CONFIG_SYS_EREADY_IO | CONFIG_SYS_LED_RED | CONFIG_SYS_LED_GREEN);
+	out32(GPIO0_OR,  CONFIG_SYS_GPIO_RDY);
 
 	/*--------------------------------------------------------------------
 	 * Setup the interrupt controller polarities, triggers, etc.
@@ -152,7 +152,7 @@
 	/*
 	 * Check if only one FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
 		mtebc(pb1cr, 0);			/* disable cs */
 		mtebc(pb1ap, 0);
 		mtebc(pb2cr, 0);			/* disable cs */
@@ -203,7 +203,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*--------------------------------------------------------------------------+
@@ -218,7 +218,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r(PCIX0_PIM0LAL, CFG_SDRAM_BASE);
+	out32r(PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE);
 	out32r(PCIX0_PIM0LAH, 0);
 	out32r(PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1);
 
@@ -227,12 +227,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r(PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID);
-	out16r(PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID);
+	out16r(PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID);
+	out16r(PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID);
 
 	out16r(PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY);
 }
-#endif				/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif				/* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  is_pci_host
diff --git a/board/prodrive/p3p440/p3p440.h b/board/prodrive/p3p440/p3p440.h
index e4e87d1..47e9018 100644
--- a/board/prodrive/p3p440/p3p440.h
+++ b/board/prodrive/p3p440/p3p440.h
@@ -24,11 +24,11 @@
 #ifndef __P3P440_H__
 #define __P3P440_H__
 
-#define CFG_GPIO_RDY	(0x80000000 >> 11)
-#define CFG_MONARCH_IO	(0x80000000 >> 18)
-#define CFG_EREADY_IO	(0x80000000 >> 20)
-#define CFG_LED_GREEN	(0x80000000 >> 21)
-#define CFG_LED_RED	(0x80000000 >> 22)
+#define CONFIG_SYS_GPIO_RDY	(0x80000000 >> 11)
+#define CONFIG_SYS_MONARCH_IO	(0x80000000 >> 18)
+#define CONFIG_SYS_EREADY_IO	(0x80000000 >> 20)
+#define CONFIG_SYS_LED_GREEN	(0x80000000 >> 21)
+#define CONFIG_SYS_LED_RED	(0x80000000 >> 22)
 
 #define LED_OFF		1
 #define LED_GREEN	2
diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c
index 5738c5b..351aed1 100644
--- a/board/prodrive/pdnb3/flash.c
+++ b/board/prodrive/pdnb3/flash.c
@@ -52,7 +52,7 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; i++)
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++)
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]);
@@ -66,20 +66,20 @@
 
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Environment protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_ENV_ADDR,
 		      CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Redundant environment protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
 		      CONFIG_ENV_ADDR_REDUND,
 		      CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-		      &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		      &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	flash_info[0].size = size;
 
diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c
index 1ce3c8c..2efe027 100644
--- a/board/prodrive/pdnb3/nand.c
+++ b/board/prodrive/pdnb3/nand.c
@@ -136,7 +136,7 @@
 
 int board_nand_init(struct nand_chip *nand)
 {
-	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CFG_NAND_BASE;
+	pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE;
 
 	nand->ecc.mode = NAND_ECC_SOFT;
 
diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c
index 3445a3a..3773ba1 100644
--- a/board/prodrive/pdnb3/pdnb3.c
+++ b/board/prodrive/pdnb3/pdnb3.c
@@ -34,8 +34,8 @@
 
 /* predefine these here for FPGA programming (before including fpga.c) */
 #define SET_FPGA(data)	*IXP425_GPIO_GPOUTR = (data)
-#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_DONE)
-#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CFG_FPGA_INIT)
+#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE)
+#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT)
 #define OLD_VAL		old_val
 
 static unsigned long old_val = 0;
@@ -56,46 +56,46 @@
 	/* adress of boot parameters */
 	gd->bd->bi_boot_params = 0x00000100;
 
-	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET);
 
-	GPIO_OUTPUT_SET(CFG_GPIO_SYS_RUNNING);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING);
 
 	/*
 	 * Setup GPIO's for FPGA programming
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_PRG);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK);
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_DATA);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_INIT);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_DONE);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE);
 
 	/*
 	 * Setup GPIO's for interrupts
 	 */
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTA);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTA);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI_INTB);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI_INTB);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTORE_INT);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTORE_INT);
-	GPIO_OUTPUT_DISABLE(CFG_GPIO_RESTART_INT);
-	GPIO_INT_ACT_LOW_SET(CFG_GPIO_RESTART_INT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT);
+	GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT);
+	GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT);
 
 	/*
 	 * Setup GPIO's for 33MHz clock output
 	 */
 	*IXP425_GPIO_GPCLKR = 0x01FF0000;
-	GPIO_OUTPUT_ENABLE(CFG_GPIO_CLK_33M);
+	GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M);
 
 	/*
 	 * Setup other chip select's
 	 */
-	*IXP425_EXP_CS1 = CFG_EXP_CS1;
+	*IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1;
 
 	return 0;
 }
@@ -132,14 +132,14 @@
 	int status;
 	int index;
 	int i;
-	ulong len = CFG_MALLOC_LEN;
+	ulong len = CONFIG_SYS_MALLOC_LEN;
 
 	/*
 	 * Setup GPIO's for FPGA programming
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_PRG);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_CLK);
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_DATA);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA);
 
 	/*
 	 * Save value so no readback is required upon programming
@@ -149,8 +149,8 @@
 	/*
 	 * First try to decompress fpga image (gzip compressed?)
 	 */
-	dst = malloc(CFG_FPGA_MAX_SIZE);
-	if (gunzip(dst, CFG_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
+	dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE);
+	if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) {
 		printf("Error: Image has to be gzipp'ed!\n");
 		return -1;
 	}
@@ -204,9 +204,9 @@
 	/*
 	 * Reset FPGA
 	 */
-	GPIO_OUTPUT_CLEAR(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET);
 	udelay(10);
-	GPIO_OUTPUT_SET(CFG_GPIO_FPGA_RESET);
+	GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET);
 
 	return (0);
 }
diff --git a/board/psyent/common/AMDLV065D.c b/board/psyent/common/AMDLV065D.c
index 8a7b14e..0fcf354 100644
--- a/board/psyent/common/AMDLV065D.c
+++ b/board/psyent/common/AMDLV065D.c
@@ -30,7 +30,7 @@
 #endif
 
 #define SECTSZ		(64 * 1024)
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*----------------------------------------------------------------------*/
 unsigned long flash_init (void)
@@ -39,18 +39,18 @@
 	unsigned long addr;
 	flash_info_t *fli = &flash_info[0];
 
-	fli->size = CFG_FLASH_SIZE;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->size = CONFIG_SYS_FLASH_SIZE;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	fli->flash_id = FLASH_MAN_AMD + FLASH_AMDLV065D;
 
-	addr = CFG_FLASH_BASE;
+	addr = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < fli->sector_count; ++i) {
 		fli->start[i] = addr;
 		addr += SECTSZ;
 		fli->protect[i] = 1;
 	}
 
-	return (CFG_FLASH_SIZE);
+	return (CONFIG_SYS_FLASH_SIZE);
 }
 /*--------------------------------------------------------------------*/
 void flash_print_info (flash_info_t * info)
@@ -135,7 +135,7 @@
 			while ( readb (addr2) != 0xff) {
 				udelay (1000 * 1000);
 				putc ('.');
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("timeout\n");
 					return 1;
 				}
@@ -177,7 +177,7 @@
 		/* Verify write */
 		start = get_timer (0);
 		while (readb (dst) != b) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return 1;
 			}
 		}
diff --git a/board/psyent/pk1c20/led.c b/board/psyent/pk1c20/led.c
index c75fe8c..e5e7705 100644
--- a/board/psyent/pk1c20/led.c
+++ b/board/psyent/pk1c20/led.c
@@ -33,7 +33,7 @@
 
 void __led_init (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
@@ -44,7 +44,7 @@
 
 void __led_set (led_id_t mask, int state)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	if (state == STATUS_LED_ON)
 		val &= ~mask;
@@ -55,7 +55,7 @@
 
 void __led_toggle (led_id_t mask)
 {
-	nios_pio_t *pio = (nios_pio_t *)CFG_LEDPIO_ADDR;
+	nios_pio_t *pio = (nios_pio_t *)CONFIG_SYS_LEDPIO_ADDR;
 
 	val ^= mask;
 	writel (&pio->data, val);
diff --git a/board/purple/flash.c b/board/purple/flash.c
index 640bc29..37c7bec 100644
--- a/board/purple/flash.c
+++ b/board/purple/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <asm/inca-ip.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 typedef unsigned long FLASH_PORT_WIDTH;
 typedef volatile unsigned long FLASH_PORT_WIDTHV;
@@ -207,7 +207,7 @@
 	load_cmd(IN_RAM_CMD_READ);
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		ulong flashbase = PHYS_FLASH_1;
 		ulong * buscon = (ulong *) INCA_IP_EBU_EBU_BUSCON0;
 
@@ -229,12 +229,12 @@
 		size += flash_info[i].size;
 	}
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
-		      flash_get_info(CFG_MONITOR_BASE));
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
+		      flash_get_info(CONFIG_SYS_MONITOR_BASE));
 #endif
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -282,13 +282,13 @@
 	int i;
 	flash_info_t * info;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i ++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i ++) {
 		info = & flash_info[i];
 		if (info->start[0] <= base && base < info->start[0] + info->size)
 			break;
 	}
 
-	return i == CFG_MAX_FLASH_BANKS ? 0 : info;
+	return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info;
 }
 
 /*-----------------------------------------------------------------------
@@ -507,10 +507,10 @@
 
 		start = get_timer(0);
 
-		while ((now = get_timer(start)) <= CFG_FLASH_ERASE_TOUT) {
+		while ((now = get_timer(start)) <= CONFIG_SYS_FLASH_ERASE_TOUT) {
 
 			/* show that we're waiting */
-			if ((get_timer(last)) > CFG_HZ) {/* every second */
+			if ((get_timer(last)) > CONFIG_SYS_HZ) {/* every second */
 				putc ('.');
 				last = get_timer(0);
 			}
diff --git a/board/purple/purple.c b/board/purple/purple.c
index 900e66f..54bef65 100644
--- a/board/purple/purple.c
+++ b/board/purple/purple.c
@@ -129,14 +129,14 @@
 {
 	/* The only supported number of SDRAM banks is 4.
 	 */
-#define CFG_NB	4
+#define CONFIG_SYS_NB	4
 
 	ulong	cfgpb0	= *INCA_IP_SDRAM_MC_CFGPB0;
 	ulong	cfgdw	= *INCA_IP_SDRAM_MC_CFGDW;
 	int	cols	= cfgpb0 & 0xF;
 	int	rows	= (cfgpb0 & 0xF0) >> 4;
 	int	dw	= cfgdw & 0xF;
-	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CFG_NB;
+	ulong	size	= (1 << (rows + cols)) * (1 << (dw - 1)) * CONFIG_SYS_NB;
 	void (*  sdram_init) (ulong);
 
 	sdram_init = (void (*)(ulong)) CKSEG0ADDR(&sdram_timing_init);
@@ -253,26 +253,26 @@
 
 	/* copy u-boot code
 	 */
-	copyLongs((ulong *)CFG_MONITOR_BASE,
+	copyLongs((ulong *)CONFIG_SYS_MONITOR_BASE,
 		  (ulong *)dest_addr,
-		  ((ulong)&uboot_end_data - CFG_MONITOR_BASE + 3) / 4);
+		  ((ulong)&uboot_end_data - CONFIG_SYS_MONITOR_BASE + 3) / 4);
 
 
 	/* flush caches
 	 */
 
 	start = CKSEG0;
-	end = start + CFG_DCACHE_SIZE;
+	end = start + CONFIG_SYS_DCACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Writeback_Inv_D);
-		start += CFG_CACHELINE_SIZE;
+		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 
 	start = CKSEG0;
-	end = start + CFG_ICACHE_SIZE;
+	end = start + CONFIG_SYS_ICACHE_SIZE;
 	while(start < end) {
 		cache_unroll(start,Index_Invalidate_I);
-		start += CFG_CACHELINE_SIZE;
+		start += CONFIG_SYS_CACHELINE_SIZE;
 	}
 }
 
diff --git a/board/purple/sconsole.c b/board/purple/sconsole.c
index f52d50d..cd9d871 100644
--- a/board/purple/sconsole.c
+++ b/board/purple/sconsole.c
@@ -38,7 +38,7 @@
 
 	sb->pos  = 0;
 	sb->size = 0;
-	sb->max_size = CFG_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
+	sb->max_size = CONFIG_SYS_SCONSOLE_SIZE - sizeof (sconsole_buffer_t);
 
 	return (0);
 }
diff --git a/board/purple/sconsole.h b/board/purple/sconsole.h
index e130ad4..baed5fb 100644
--- a/board/purple/sconsole.h
+++ b/board/purple/sconsole.h
@@ -33,7 +33,7 @@
 	char data[1];
 } sconsole_buffer_t;
 
-#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CFG_SCONSOLE_ADDR)
+#define SCONSOLE_BUFFER		((sconsole_buffer_t *) CONFIG_SYS_SCONSOLE_ADDR)
 
 extern void	(* sconsole_putc)	(char);
 extern void	(* sconsole_puts)	(const char *);
diff --git a/board/pxa255_idp/lowlevel_init.S b/board/pxa255_idp/lowlevel_init.S
index 80b5182..a50760f 100644
--- a/board/pxa255_idp/lowlevel_init.S
+++ b/board/pxa255_idp/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 	.macro CPWAIT reg
@@ -53,67 +53,67 @@
 
 	/* Set up GPIO pins first ----------------------------------------- */
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr	r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 #ifdef DEBUG_BLINK_ENABLE
@@ -156,17 +156,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,   =CFG_MSC0_VAL
+	ldr     r2,   =CONFIG_SYS_MSC0_VAL
 	str     r2,   [r1, #MSC0_OFFSET]
 	ldr     r2,   [r1, #MSC0_OFFSET]	/* read back to ensure      */
 						/* that data latches        */
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,  =CFG_MSC1_VAL
+	ldr     r2,  =CONFIG_SYS_MSC1_VAL
 	str     r2,  [r1, #MSC1_OFFSET]
 	ldr     r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,  =CFG_MSC2_VAL
+	ldr     r2,  =CONFIG_SYS_MSC2_VAL
 	str     r2,  [r1, #MSC2_OFFSET]
 	ldr     r2,  [r1, #MSC2_OFFSET]
 
@@ -175,37 +175,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,  =CFG_MECR_VAL
+	ldr     r2,  =CONFIG_SYS_MECR_VAL
 	str     r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,  =CFG_MCMEM0_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM0_VAL
 	str     r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,  =CFG_MCMEM1_VAL
+	ldr     r2,  =CONFIG_SYS_MCMEM1_VAL
 	str     r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,  =CFG_MCATT0_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT0_VAL
 	str     r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,  =CFG_MCATT1_VAL
+	ldr     r2,  =CONFIG_SYS_MCATT1_VAL
 	str     r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,  =CFG_MCIO0_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO0_VAL
 	str     r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,  =CFG_MCIO1_VAL
+	ldr     r2,  =CONFIG_SYS_MCIO1_VAL
 	str     r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
@@ -225,7 +225,7 @@
 	/* Before accessing MDREFR we need a valid DRI field, so we set     */
 	/* this to power on defaults + DRI field.                           */
 
-	ldr     r3,     =CFG_MDREFR_VAL
+	ldr     r3,     =CONFIG_SYS_MDREFR_VAL
 	ldr     r2,     =0xFFF
 	and     r3,     r3,  r2
 	ldr	r4,	=0x03ca4000
@@ -253,7 +253,7 @@
 
 	/* set MDREFR according to user define with exception of a few bits */
 
-	ldr     r4,     =CFG_MDREFR_VAL
+	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
 	orr	r4,	r4,	#(MDREFR_SLFRSH)
 	bic	r4,	r4,	#(MDREFR_E1PIN|MDREFR_E0PIN)
 	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
@@ -267,7 +267,7 @@
 
 	/* Step 4c: assert MDREFR:E1PIN and E0PIO as desired                */
 
-	ldr     r4,     =CFG_MDREFR_VAL
+	ldr     r4,     =CONFIG_SYS_MDREFR_VAL
 	str     r4,     [r1, #MDREFR_OFFSET]    /* write back MDREFR        */
 	ldr     r4,     [r1, #MDREFR_OFFSET]
 
@@ -275,7 +275,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*          configure but not enable each SDRAM partition pair.     */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 
 	str     r4,     [r1, #MDCNFG_OFFSET]	/* write back MDCNFG        */
@@ -300,7 +300,7 @@
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
@@ -319,7 +319,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,  =CFG_MDMRS_VAL
+	ldr     r2,  =CONFIG_SYS_MDMRS_VAL
 	str     r2,  [r1, #MDMRS_OFFSET]
 
 	/* We are finished with Intel's memory controller initialisation    */
diff --git a/board/pxa255_idp/pxa_idp.c b/board/pxa255_idp/pxa_idp.c
index 5765c55..b0aa8dd 100644
--- a/board/pxa255_idp/pxa_idp.c
+++ b/board/pxa255_idp/pxa_idp.c
@@ -127,7 +127,7 @@
 	return 0;
 }
 
-U_BOOT_CMD(idpcmd, CFG_MAXARGS, 0, do_idpcmd,
+U_BOOT_CMD(idpcmd, CONFIG_SYS_MAXARGS, 0, do_idpcmd,
 	   "idpcmd    - custom IDP command\n",
 	   "no args at this time\n"
 );
diff --git a/board/pxa255_idp/pxa_reg_calcs.out b/board/pxa255_idp/pxa_reg_calcs.out
index bda9946..39295fb 100644
--- a/board/pxa255_idp/pxa_reg_calcs.out
+++ b/board/pxa255_idp/pxa_reg_calcs.out
@@ -15,21 +15,21 @@
 gpsr2: 0x1c000
 
 
-#define CFG_GAFR0_L_VAL	0x80001005
-#define CFG_GAFR0_U_VAL	0xa5128012
-#define CFG_GAFR1_L_VAL	0x699a9558
-#define CFG_GAFR1_U_VAL	0xaaa5aa6a
-#define CFG_GAFR2_L_VAL	0xaaaaaaaa
-#define CFG_GAFR2_U_VAL	0x2
-#define CFG_GPCR0_VAL	0x1800400
-#define CFG_GPCR1_VAL	0x0
-#define CFG_GPCR2_VAL	0x0
-#define CFG_GPDR0_VAL	0xc1818440
-#define CFG_GPDR1_VAL	0xfcffab82
-#define CFG_GPDR2_VAL	0x1ffff
-#define CFG_GPSR0_VAL	0x8000
-#define CFG_GPSR1_VAL	0x3f0002
-#define CFG_GPSR2_VAL	0x1c000
+#define CONFIG_SYS_GAFR0_L_VAL	0x80001005
+#define CONFIG_SYS_GAFR0_U_VAL	0xa5128012
+#define CONFIG_SYS_GAFR1_L_VAL	0x699a9558
+#define CONFIG_SYS_GAFR1_U_VAL	0xaaa5aa6a
+#define CONFIG_SYS_GAFR2_L_VAL	0xaaaaaaaa
+#define CONFIG_SYS_GAFR2_U_VAL	0x2
+#define CONFIG_SYS_GPCR0_VAL	0x1800400
+#define CONFIG_SYS_GPCR1_VAL	0x0
+#define CONFIG_SYS_GPCR2_VAL	0x0
+#define CONFIG_SYS_GPDR0_VAL	0xc1818440
+#define CONFIG_SYS_GPDR1_VAL	0xfcffab82
+#define CONFIG_SYS_GPDR2_VAL	0x1ffff
+#define CONFIG_SYS_GPSR0_VAL	0x8000
+#define CONFIG_SYS_GPSR1_VAL	0x3f0002
+#define CONFIG_SYS_GPSR2_VAL	0x1c000
 
 
 GPIO: 0, dir=0, set=0, clr=0, alt=none, desc=USER_RESET#
diff --git a/board/pxa255_idp/pxa_reg_calcs.py b/board/pxa255_idp/pxa_reg_calcs.py
index c4bcb4b..2f89e31 100644
--- a/board/pxa255_idp/pxa_reg_calcs.py
+++ b/board/pxa255_idp/pxa_reg_calcs.py
@@ -246,12 +246,12 @@
 
 # U-boot define names
 uboot_reg_names = {
-	'gpdr0':'CFG_GPDR0_VAL', 'gpdr1':'CFG_GPDR1_VAL', 'gpdr2':'CFG_GPDR2_VAL',
-	'gpsr0':'CFG_GPSR0_VAL', 'gpsr1':'CFG_GPSR1_VAL', 'gpsr2':'CFG_GPSR2_VAL',
-	'gpcr0':'CFG_GPCR0_VAL', 'gpcr1':'CFG_GPCR1_VAL', 'gpcr2':'CFG_GPCR2_VAL',
-	'gafr0_l':'CFG_GAFR0_L_VAL', 'gafr0_u':'CFG_GAFR0_U_VAL',
-	'gafr1_l':'CFG_GAFR1_L_VAL', 'gafr1_u':'CFG_GAFR1_U_VAL',
-	'gafr2_l':'CFG_GAFR2_L_VAL', 'gafr2_u':'CFG_GAFR2_U_VAL',
+	'gpdr0':'CONFIG_SYS_GPDR0_VAL', 'gpdr1':'CONFIG_SYS_GPDR1_VAL', 'gpdr2':'CONFIG_SYS_GPDR2_VAL',
+	'gpsr0':'CONFIG_SYS_GPSR0_VAL', 'gpsr1':'CONFIG_SYS_GPSR1_VAL', 'gpsr2':'CONFIG_SYS_GPSR2_VAL',
+	'gpcr0':'CONFIG_SYS_GPCR0_VAL', 'gpcr1':'CONFIG_SYS_GPCR1_VAL', 'gpcr2':'CONFIG_SYS_GPCR2_VAL',
+	'gafr0_l':'CONFIG_SYS_GAFR0_L_VAL', 'gafr0_u':'CONFIG_SYS_GAFR0_U_VAL',
+	'gafr1_l':'CONFIG_SYS_GAFR1_L_VAL', 'gafr1_u':'CONFIG_SYS_GAFR1_U_VAL',
+	'gafr2_l':'CONFIG_SYS_GAFR2_L_VAL', 'gafr2_u':'CONFIG_SYS_GAFR2_U_VAL',
 }
 
 # bit mappings
diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c
index 766ee95..35525bc 100644
--- a/board/quad100hd/nand.c
+++ b/board/quad100hd/nand.c
@@ -37,9 +37,9 @@
 	struct nand_chip *this = mtd->priv;
 
 	if (ctrl & NAND_CTRL_CHANGE) {
-		gpio_write_bit(CFG_NAND_CLE, !!(ctrl & NAND_CLE));
-		gpio_write_bit(CFG_NAND_ALE, !!(ctrl & NAND_ALE));
-		gpio_write_bit(CFG_NAND_CE, !(ctrl & NAND_NCE));
+		gpio_write_bit(CONFIG_SYS_NAND_CLE, !!(ctrl & NAND_CLE));
+		gpio_write_bit(CONFIG_SYS_NAND_ALE, !!(ctrl & NAND_ALE));
+		gpio_write_bit(CONFIG_SYS_NAND_CE, !(ctrl & NAND_NCE));
 	}
 
 	if (cmd != NAND_CMD_NONE)
@@ -48,7 +48,7 @@
 
 static int quad100hd_nand_ready(struct mtd_info *mtd)
 {
-	return gpio_read_in_bit(CFG_NAND_RDY);
+	return gpio_read_in_bit(CONFIG_SYS_NAND_RDY);
 }
 
 /*
diff --git a/board/quantum/fpga.c b/board/quantum/fpga.c
index 75c2658..092aaab 100644
--- a/board/quantum/fpga.c
+++ b/board/quantum/fpga.c
@@ -62,11 +62,11 @@
 
 int fpga_boot (unsigned char *fpgadata, int size)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	int i, index, len;
 	int count;
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	int j;
 	unsigned char data;
 #else
@@ -89,7 +89,7 @@
 
 	index = 0;
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/* search for preamble 0xFFFFFFFF */
 	while (1) {
 		if ((fpgadata[index] == 0xff) && (fpgadata[index + 1] == 0xff)
@@ -159,12 +159,12 @@
 	debug ("write configuration data into fpga\n");
 	/* write configuration-data into fpga... */
 
-#ifdef CFG_FPGA_SPARTAN2
+#ifdef CONFIG_SYS_FPGA_SPARTAN2
 	/*
 	 * Load uncompressed image into fpga
 	 */
 	for (i = index; i < size; i++) {
-#ifdef CFG_FPGA_PROG_FEEDBACK
+#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK
 		if ((i % 1024) == 0)
 			printf ("%6d out of %6d\r", i, size);	/* let them know we are alive */
 #endif
diff --git a/board/quantum/quantum.c b/board/quantum/quantum.c
index 345f127..d94b5d7 100644
--- a/board/quantum/quantum.c
+++ b/board/quantum/quantum.c
@@ -104,7 +104,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size9;
 
@@ -112,15 +112,15 @@
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000088;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -136,12 +136,12 @@
 	/* Check Bank 0 Memory Size,
 	 * 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
 			   SDRAM_MAX_SIZE);
 	/*
 	 * Final mapping:
 	 */
-	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 	udelay (1000);
 
 	return (size9);
@@ -160,7 +160,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile ulong *addr;
 	ulong cnt, val, size;
@@ -224,14 +224,14 @@
 	void *fpga_data;
 	int fpga_size;
 	int status;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	int flash_size;
 
 	/* Remap FLASH according to real size */
 	flash_size = flash_init ();
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-flash_size & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	if (fpga_data_str && fpga_size_str) {
 		fpga_data = (void *) simple_strtoul (fpga_data_str, NULL, 16);
diff --git a/board/r2dplus/r2dplus.c b/board/r2dplus/r2dplus.c
index 4e0c66a..0c08d68 100644
--- a/board/r2dplus/r2dplus.c
+++ b/board/r2dplus/r2dplus.c
@@ -43,9 +43,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/r360mpi/flash.c b/board/r360mpi/flash.c
index 8145437..45cccf7 100644
--- a/board/r360mpi/flash.c
+++ b/board/r360mpi/flash.c
@@ -29,11 +29,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -76,13 +76,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -95,19 +95,19 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size ((FPW *) CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size ((FPW *) CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	(void) flash_protect (FLAG_PROTECT_SET,
-				CFG_FLASH_BASE,
-				CFG_FLASH_BASE + monitor_flash_len - 1,
+				CONFIG_SYS_FLASH_BASE,
+				CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 				&flash_info[0]);
 #endif
 
@@ -261,10 +261,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -335,7 +335,7 @@
 			udelay (1000);
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-			    if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			    if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 				*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -472,7 +472,7 @@
 	start = get_timer (0);
 
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/r360mpi/pcmcia.c b/board/r360mpi/pcmcia.c
index 4fd9d12..85da41b 100644
--- a/board/r360mpi/pcmcia.c
+++ b/board/r360mpi/pcmcia.c
@@ -28,10 +28,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/*
 	* Configure SIUMCR to enable PCMCIA port B
@@ -132,8 +132,8 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* remove all power */
 	immap->im_ioport.iop_pcdat |= 0x0400;
@@ -164,8 +164,8 @@
 			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
 	* and assert RESET signal
diff --git a/board/r360mpi/r360mpi.c b/board/r360mpi/r360mpi.c
index c51e412..b502e4d 100644
--- a/board/r360mpi/r360mpi.c
+++ b/board/r360mpi/r360mpi.c
@@ -105,7 +105,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9;
 	long int size_b0 = 0;
@@ -120,7 +120,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -129,10 +129,10 @@
 	 * preliminary address - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -152,7 +152,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	udelay (1000);
@@ -160,7 +160,7 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
@@ -168,7 +168,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -181,7 +181,7 @@
 	 */
 	if ((size_b0 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
@@ -189,20 +189,20 @@
 	 * Final mapping
 	 */
 
-	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	/* adjust refresh rate depending on SDRAM type, one bank */
 	reg = memctl->memc_mptpr;
-	reg >>= 1;		/* reduce to CFG_MPTPR_1BK_8K / _4K */
+	reg >>= 1;		/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 	memctl->memc_mptpr = reg;
 
 	udelay (10000);
 
 #ifdef CONFIG_CAN_DRIVER
 	/* Initialize OR3 / BR3 */
-	memctl->memc_or3 = CFG_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
-	memctl->memc_br3 = CFG_BR3_CAN;
+	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;		/* switch GPLB_5 to GPLA_5 */
+	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 
 	/* Initialize MBMR */
 	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 works as UPWAITB */
@@ -256,7 +256,7 @@
 static long int dram_size (long int mamr_value,
 			   long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -268,7 +268,7 @@
 
 void r360_i2c_lcd_write (uchar data0, uchar data1)
 {
-	if (i2c_write (CFG_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
+	if (i2c_write (CONFIG_SYS_I2C_LCD_ADDR, data0, 1, &data1, 1)) {
 		printf("Can't write lcd data 0x%02X 0x%02X.\n", data0, data1);
 	}
 }
@@ -292,9 +292,9 @@
 	char *str;
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
-	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
+	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, (uchar *)kbd_data, KEYBD_DATALEN);
 
 	for (i = 0; i < KEYBD_DATALEN; ++i) {
 		sprintf (keybd_env + i + i, "%02X", kbd_data[i]);
@@ -397,10 +397,10 @@
 	uchar keybd_env[2 * KEYBD_DATALEN + 1];
 	int i;
 
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read keys */
-	i2c_read (CFG_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
+	i2c_read (CONFIG_SYS_I2C_KEY_ADDR, 0, 0, kbd_data, KEYBD_DATALEN);
 
 	puts ("Keys:");
 	for (i = 0; i < KEYBD_DATALEN; ++i) {
diff --git a/board/r7780mp/r7780mp.c b/board/r7780mp/r7780mp.c
index efbeec9..396e4b6 100644
--- a/board/r7780mp/r7780mp.c
+++ b/board/r7780mp/r7780mp.c
@@ -48,9 +48,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/rattler/rattler.c b/board/rattler/rattler.c
index ad75c21..80f57dc 100644
--- a/board/rattler/rattler.c
+++ b/board/rattler/rattler.c
@@ -35,31 +35,31 @@
  * according to the five values podr/pdir/ppar/psor/pdat for that entry
  */
 
-#define CFG_FCC1 (CONFIG_ETHER_INDEX == 1)
-#define CFG_FCC2 (CONFIG_ETHER_INDEX == 2)
+#define CONFIG_SYS_FCC1 (CONFIG_ETHER_INDEX == 1)
+#define CONFIG_SYS_FCC2 (CONFIG_ETHER_INDEX == 2)
 
 const iop_conf_t iop_conf_tab[4][32] = {
 
     /* Port A */
     {	/*	      conf      ppar psor pdir podr pdat */
-	/* PA31 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
-	/* PA30 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
-	/* PA29 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
-	/* PA28 */ { CFG_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
-	/* PA27 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
-	/* PA26 */ { CFG_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
+	/* PA31 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII COL    */
+	/* PA30 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII CRS    */
+	/* PA29 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_ER  */
+	/* PA28 */ { CONFIG_SYS_FCC1,   1,   1,   1,   0,   0 }, /* FCC1 MII TX_EN  */
+	/* PA27 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_DV  */
+	/* PA26 */ { CONFIG_SYS_FCC1,   1,   1,   0,   0,   0 }, /* FCC1 MII RX_ER  */
 	/* PA25 */ { 0,          0,   0,   0,   0,   0 }, /* PA25            */
 	/* PA24 */ { 0,          0,   0,   0,   0,   0 }, /* PA24            */
 	/* PA23 */ { 0,          0,   0,   0,   0,   0 }, /* PA23            */
 	/* PA22 */ { 1,          0,   0,   1,   0,   1 }, /* Eth PHYs reset  */
-	/* PA21 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
-	/* PA20 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
-	/* PA19 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
-	/* PA18 */ { CFG_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
-	/* PA17 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
-	/* PA16 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
-	/* PA15 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
-	/* PA14 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
+	/* PA21 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[3] */
+	/* PA20 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[2] */
+	/* PA19 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[1] */
+	/* PA18 */ { CONFIG_SYS_FCC1,   1,   0,   1,   0,   0 }, /* FCC1 MII TxD[0] */
+	/* PA17 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[0] */
+	/* PA16 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[1] */
+	/* PA15 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[2] */
+	/* PA14 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 MII RxD[3] */
 	/* PA13 */ { 0,          0,   0,   0,   0,   0 }, /* PA13            */
 	/* PA12 */ { 0,          0,   0,   0,   0,   0 }, /* PA12            */
 	/* PA11 */ { 0,          0,   0,   0,   0,   0 }, /* PA11            */
@@ -78,20 +78,20 @@
 
     /* Port B */
     {   /*	      conf      ppar psor pdir podr pdat */
-	/* PB31 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
-	/* PB30 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
-	/* PB29 */ { CFG_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
-	/* PB28 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
-	/* PB27 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
-	/* PB26 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
-	/* PB25 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
-	/* PB24 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
-	/* PB23 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
-	/* PB22 */ { CFG_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
-	/* PB21 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
-	/* PB20 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
-	/* PB19 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
-	/* PB18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
+	/* PB31 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TX_ER  */
+	/* PB30 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_DV  */
+	/* PB29 */ { CONFIG_SYS_FCC2,   1,   1,   1,   0,   0 }, /* FCC2 MII TX_EN  */
+	/* PB28 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RX_ER  */
+	/* PB27 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII COL    */
+	/* PB26 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII CRS    */
+	/* PB25 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[3] */
+	/* PB24 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[2] */
+	/* PB23 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[1] */
+	/* PB22 */ { CONFIG_SYS_FCC2,   1,   0,   1,   0,   0 }, /* FCC2 MII TxD[0] */
+	/* PB21 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[0] */
+	/* PB20 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[1] */
+	/* PB19 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[2] */
+	/* PB18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 MII RxD[3] */
 	/* PB17 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 	/* PB16 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
 	/* PB15 */ { 0,          0,   0,   0,   0,   0 }, /* non-existent    */
@@ -123,12 +123,12 @@
 	/* PC25 */ { 0,          0,   0,   0,   0,   0 }, /* PC25            */
 	/* PC24 */ { 0,          0,   0,   0,   0,   0 }, /* PC24            */
 	/* PC23 */ { 0,          0,   0,   0,   0,   0 }, /* PC23            */
-	/* PC22 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
-	/* PC21 */ { CFG_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
+	/* PC22 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 TxClk (CLK10) */
+	/* PC21 */ { CONFIG_SYS_FCC1,   1,   0,   0,   0,   0 }, /* FCC1 RxClk (CLK11) */
 	/* PC20 */ { 0,          0,   0,   0,   0,   0 }, /* PC20            */
 	/* PC19 */ { 0,          0,   0,   0,   0,   0 }, /* PC19            */
-	/* PC18 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
-	/* PC17 */ { CFG_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
+	/* PC18 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 TxClk (CLK14) */
+	/* PC17 */ { CONFIG_SYS_FCC2,   1,   0,   0,   0,   0 }, /* FCC2 RxClk (CLK15) */
 	/* PC16 */ { 0,          0,   0,   0,   0,   0 }, /* PC16            */
 	/* PC15 */ { 0,          0,   0,   0,   0,   0 }, /* PC15            */
 	/* PC14 */ { 0,          0,   0,   0,   0,   0 }, /* PC14            */
@@ -187,26 +187,26 @@
 
 phys_size_t initdram(int board_type)
 {
-	long int msize = CFG_SDRAM_SIZE;
+	long int msize = CONFIG_SYS_SDRAM_SIZE;
 
-#ifndef CFG_RAMBOOT
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+#ifndef CONFIG_SYS_RAMBOOT
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	vu_char *ramaddr = (vu_char *)CFG_SDRAM_BASE;
+	vu_char *ramaddr = (vu_char *)CONFIG_SYS_SDRAM_BASE;
 	uchar c = 0xFF;
-	uint psdmr = CFG_PSDMR;
+	uint psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	immap->im_siu_conf.sc_ppc_acr  = 0x02;
 	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or1  = CFG_SDRAM_OR;
-	memctl->memc_br1  = CFG_SDRAM_BR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or1  = CONFIG_SYS_SDRAM_OR;
+	memctl->memc_br1  = CONFIG_SYS_SDRAM_BR;
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA; /* Precharge all banks */
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | PSDMR_OP_CBRR; /* CBR refresh */
@@ -216,7 +216,7 @@
 	*ramaddr = c;
 	memctl->memc_psdmr = psdmr | PSDMR_RFEN;    /* Refresh enable */
 	*ramaddr = c;
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 	/* Return total 60x bus SDRAM size */
 	return msize * 1024 * 1024;
@@ -224,7 +224,7 @@
 
 int checkboard(void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	printf("Board: Rattler Rev. %c\n", bcsr[0x20] + 0x40);
 	return 0;
diff --git a/board/rbc823/flash.c b/board/rbc823/flash.c
index 26ebcae..cb1e089 100644
--- a/board/rbc823/flash.c
+++ b/board/rbc823/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -42,20 +42,20 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i)
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i)
 	    flash_info[i].flash_id = FLASH_UNKNOWN;
 
 	/* Detect size */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* Setup offsets */
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* Monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -322,7 +322,7 @@
 
 	while ((addr[0] & 0xFF) != 0xFF)
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -454,7 +454,7 @@
 	    start = get_timer (0);
 	    while ((*cdest ^ *cdata) & 0x80)
 	    {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	    }
diff --git a/board/rbc823/kbd.c b/board/rbc823/kbd.c
index 6d530f6..1d48f6d 100644
--- a/board/rbc823/kbd.c
+++ b/board/rbc823/kbd.c
@@ -48,7 +48,7 @@
 
 void smc1_setbrg (void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	volatile cpm8xx_t *cp = &(im->im_cpm);
 
 	/* Set up the baud rate generator.
@@ -65,7 +65,7 @@
 
 int smc1_init (void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	volatile smc_t *sp;
 	volatile smc_uart_t *up;
 	volatile cbd_t *tbdf, *rbdf;
@@ -86,15 +86,15 @@
 	im->im_siu_conf.sc_sdcr = 1;
 
 	/* clear error conditions */
-#ifdef	CFG_SDSR
-	im->im_sdma.sdma_sdsr = CFG_SDSR;
+#ifdef	CONFIG_SYS_SDSR
+	im->im_sdma.sdma_sdsr = CONFIG_SYS_SDSR;
 #else
 	im->im_sdma.sdma_sdsr = 0x83;
 #endif
 
 	/* clear SDMA interrupt mask */
-#ifdef	CFG_SDMR
-	im->im_sdma.sdma_sdmr = CFG_SDMR;
+#ifdef	CONFIG_SYS_SDMR
+	im->im_sdma.sdma_sdmr = CONFIG_SYS_SDMR;
 #else
 	im->im_sdma.sdma_sdmr = 0x00;
 #endif
@@ -109,7 +109,7 @@
 	 * the buffer descriptors.
 	 */
 
-#ifdef CFG_ALLOC_DPRAM
+#ifdef CONFIG_SYS_ALLOC_DPRAM
 	dpaddr = dpram_alloc_align (sizeof(cbd_t)*2 + 2, 8) ;
 #else
 	dpaddr = CPM_KEYBOARD_BASE ;
@@ -182,7 +182,7 @@
 	volatile cbd_t		*tbdf;
 	volatile char		*buf;
 	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 
 	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
@@ -210,7 +210,7 @@
 	volatile cbd_t		*rbdf;
 	volatile unsigned char	*buf;
 	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 	unsigned char		c;
 
@@ -235,7 +235,7 @@
 {
 	volatile cbd_t		*rbdf;
 	volatile smc_uart_t	*up;
-	volatile immap_t	*im = (immap_t *)CFG_IMMR;
+	volatile immap_t	*im = (immap_t *)CONFIG_SYS_IMMR;
 	volatile cpm8xx_t	*cpmp = &(im->im_cpm);
 
 	up = (smc_uart_t *)&cpmp->cp_dparam[PROFF_SMC];
diff --git a/board/rbc823/rbc823.c b/board/rbc823/rbc823.c
index 5b62af6..b294906 100644
--- a/board/rbc823/rbc823.c
+++ b/board/rbc823/rbc823.c
@@ -144,7 +144,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0, size8, size9;
 
@@ -154,15 +154,15 @@
 	/*
 	 * 1 Bank of 64Mbit x 2 devices
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_1BK_4K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_4K;
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller SDRAM bank 0
 	 */
-	memctl->memc_or4 = CFG_OR4_PRELIM;
-	memctl->memc_br4 = CFG_BR4_PRELIM;
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 	udelay (200);
 
 	/*
@@ -170,11 +170,11 @@
 	 */
 	memctl->memc_mcr = 0x80008105;	/* SDRAM bank 0 */
 	udelay (1);
-	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_8X;
 	udelay (200);
 	memctl->memc_mcr = 0x80008130;	/* SDRAM bank 0 - execute twice */
 	udelay (1);
-	memctl->memc_mamr = (CFG_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
+	memctl->memc_mamr = (CONFIG_SYS_MAMR_8COL & ~(MAMR_TLFA_MSK)) | MAMR_TLFA_4X;
 	udelay (200);
 
 	memctl->memc_mamr |= MAMR_PTAE;	/* enable refresh */
@@ -186,21 +186,21 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;	/* 16: but should be: CFG_MPTPR_1BK_4K */
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;	/* 16: but should be: CONFIG_SYS_MPTPR_1BK_4K */
 
 	/*
 	 * Check Bank 0 Memory Size for re-configuration
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, (long *) SDRAM_BASE4_PRELIM,
 			   SDRAM_MAX_SIZE);
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE4_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {	/* leave configuration at 9 columns     */
@@ -208,7 +208,7 @@
 /*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {		/* back to 8 columns                    */
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 /*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
@@ -221,14 +221,14 @@
 	 */
 	if ((size_b0 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
 	/* SDRAM Bank 0 is bigger - map first       */
 
-	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-	memctl->memc_br4 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_or4 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+	memctl->memc_br4 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 	udelay (10000);
 
@@ -248,7 +248,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -258,7 +258,7 @@
 
 void doc_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	upmconfig (UPMB, (uint *) static_table,
diff --git a/board/rmu/flash.c b/board/rmu/flash.c
index 7c248a7..a3ab851 100644
--- a/board/rmu/flash.c
+++ b/board/rmu/flash.c
@@ -26,7 +26,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -40,13 +40,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0 ;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -64,21 +64,21 @@
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Re-do sizing to get full correct info */
 
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -406,7 +406,7 @@
 	last  = start;
 	addr = (vu_long *)(info->start[l_sect]);
 	while ((addr[0] & 0x80808080) != 0x80808080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -529,7 +529,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/rmu/rmu.c b/board/rmu/rmu.c
index e22dc52..cd02b9c 100644
--- a/board/rmu/rmu.c
+++ b/board/rmu/rmu.c
@@ -94,7 +94,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size9;
 
@@ -102,15 +102,15 @@
 		   sizeof (sdram_table) / sizeof (uint));
 
 	/* Refresh clock prescalar */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000088;
 
 	/* Map controller banks 1 to the SDRAM bank */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_9COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -127,14 +127,14 @@
 	 * 9 column mode
 	 */
 
-	size9 = dram_size (CFG_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, (long *) SDRAM_BASE_PRELIM,
 			   SDRAM_MAX_SIZE);
 
 	/*
 	 * Final mapping:
 	 */
 
-	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+	memctl->memc_or1 = ((-size9) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 	udelay (1000);
 
 	return (size9);
@@ -153,7 +153,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/rpxsuper/flash.c b/board/rpxsuper/flash.c
index 5f444bf..be29b65 100644
--- a/board/rpxsuper/flash.c
+++ b/board/rpxsuper/flash.c
@@ -33,7 +33,7 @@
 #include <mpc8xx.h>
 #include <asm/io.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define RD_SWP32(x) in_le32((volatile u32*)x)
 
@@ -53,21 +53,21 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
     /* for now, only support the 4 MB Flash SIMM */
-    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 
     /*
      * protect monitor and environment sectors
      */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 
@@ -81,7 +81,7 @@
 		  &flash_info[0]);
 #endif
 
-    return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024);
+    return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
 }
 
 /*-----------------------------------------------------------------------
@@ -292,7 +292,7 @@
     addr = (vu_long*)(info->start[l_sect]);
     while (	(addr[0] & 0x80808080) != 0x80808080 ||
 		(addr[1] & 0x80808080) != 0x80808080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -423,7 +423,7 @@
     /* data polling for D7 */
     start = get_timer (0);
     while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    return (1);
 	}
     }
diff --git a/board/rpxsuper/mii_phy.c b/board/rpxsuper/mii_phy.c
index ef99aff..12e23f4 100644
--- a/board/rpxsuper/mii_phy.c
+++ b/board/rpxsuper/mii_phy.c
@@ -54,7 +54,7 @@
 {
     int i;
     unsigned short tmp, val = 0, adr = 0;
-    t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
 
     tmp = 0x6002 | (adr << 7) | (reg << 2);
     regs->bcsr4 = 0xC3;
@@ -83,7 +83,7 @@
 {
     int i;
     unsigned short tmp, adr = 0;
-    t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
 
     tmp = 0x5002 | (adr << 7) | (reg << 2);
     regs->bcsr4 = 0xC3;
diff --git a/board/rpxsuper/rpxsuper.c b/board/rpxsuper/rpxsuper.c
index f633c5c..aa59803 100644
--- a/board/rpxsuper/rpxsuper.c
+++ b/board/rpxsuper/rpxsuper.c
@@ -193,11 +193,11 @@
 */
 int board_early_init_f (void)
 {
-    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8260_t *memctl = &immap->im_memctl;
-    memctl->memc_br4 = CFG_BR4_PRELIM;
-    memctl->memc_or4 = CFG_OR4_PRELIM;
+    memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
+    memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
     regs->bcsr1 = 0x70; /* to enable terminal no SMC1 */
     regs->bcsr2 = 0x20;	/* mut be written to enable writing FLASH */
     return 0;
@@ -206,7 +206,7 @@
 void
 reset_phy(void)
 {
-    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
     regs->bcsr4 = 0xC3;
 }
 
@@ -216,7 +216,7 @@
 
 int checkboard(void)
 {
-    volatile t_rpx_regs *regs = (t_rpx_regs*)CFG_REGS_BASE;
+    volatile t_rpx_regs *regs = (t_rpx_regs*)CONFIG_SYS_REGS_BASE;
     printf ("Board: Embedded Planet RPX Super, Revision %d\n",
 	regs->bcsr0 >> 4);
 
@@ -227,15 +227,15 @@
 
 phys_size_t initdram(int board_type)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8260_t *memctl = &immap->im_memctl;
     volatile uchar c = 0, *ramaddr;
     ulong psdmr, lsdmr, bcr;
     long size = 0;
     int i;
 
-    psdmr = CFG_PSDMR;
-    lsdmr = CFG_LSDMR;
+    psdmr = CONFIG_SYS_PSDMR;
+    lsdmr = CONFIG_SYS_LSDMR;
 
     /*
      * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35):
@@ -254,17 +254,17 @@
      *  accessing the SDRAM with a single-byte transaction."
      *
      * The appropriate BRx/ORx registers have already been set when we
-     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
      */
 
-    size = CFG_SDRAM0_SIZE;
+    size = CONFIG_SYS_SDRAM0_SIZE;
     bcr = immap->im_siu_conf.sc_bcr;
     immap->im_siu_conf.sc_bcr = (bcr & ~BCR_EBM);
 
-    memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-    ramaddr = (uchar *)(CFG_SDRAM0_BASE);
-    memctl->memc_psrt = CFG_PSRT;
+    ramaddr = (uchar *)(CONFIG_SYS_SDRAM0_BASE);
+    memctl->memc_psrt = CONFIG_SYS_PSRT;
 
     memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
     *ramaddr = c;
@@ -281,10 +281,10 @@
 
     immap->im_siu_conf.sc_bcr = bcr;
 
-#ifndef CFG_RAMBOOT
-/*    size += CFG_SDRAM1_SIZE; */
-    ramaddr = (uchar *)(CFG_SDRAM1_BASE);
-    memctl->memc_lsrt = CFG_LSRT;
+#ifndef CONFIG_SYS_RAMBOOT
+/*    size += CONFIG_SYS_SDRAM1_SIZE; */
+    ramaddr = (uchar *)(CONFIG_SYS_SDRAM1_BASE);
+    memctl->memc_lsrt = CONFIG_SYS_LSRT;
 
     memctl->memc_lsdmr = lsdmr | PSDMR_OP_PREA;
     *ramaddr = c;
diff --git a/board/rsdproto/flash.c b/board/rsdproto/flash.c
index 312b400..e99c2a6 100644
--- a/board/rsdproto/flash.c
+++ b/board/rsdproto/flash.c
@@ -41,7 +41,7 @@
  */
 #undef WITH_AUTOSELECT
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if 1
 #define D(x)
@@ -94,7 +94,7 @@
 #endif
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
@@ -120,14 +120,14 @@
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= PHYS_FLASH
+#if CONFIG_SYS_MONITOR_BASE >= PHYS_FLASH
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[1]);
 #endif
 
@@ -259,7 +259,7 @@
 	start = get_timer (0);
 	do
 	{
-		if (get_timer(start) > CFG_FLASH_ERASE_TOUT)
+		if (get_timer(start) > CONFIG_SYS_FLASH_ERASE_TOUT)
 		{	/* write reset command, command address is unimportant */
 			/* this command turns the flash back to read mode     */
 			f_addr =
@@ -387,7 +387,7 @@
 	start = get_timer (0);
 	do
 	{
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 		{
 			/* write reset command, command address is unimportant */
 			/* this command turns the flash back to read mode     */
diff --git a/board/rsdproto/rsdproto.c b/board/rsdproto/rsdproto.c
index eeec3b4..26edb2e 100644
--- a/board/rsdproto/rsdproto.c
+++ b/board/rsdproto/rsdproto.c
@@ -253,7 +253,7 @@
 	puts ("Board: Rohde & Schwarz 8260 Protocol Board\n");
 
 	/* initialise i2c */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	read_RS5C372_time (&timedate);
 	printf ("  Time:  %02d:%02d:%02d\n",
@@ -284,7 +284,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
 #ifdef INIT_LOCAL_BUS_SDRAM
@@ -317,7 +317,7 @@
 		 *
 		 * The appropriate BRx/ORx registers have already
 		 * been set when we get here (see cpu_init_f). The
-		 * SDRAM can be accessed at the address CFG_SDRAM_BASE.
+		 * SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 		 */
 		memctl->memc_mptpr = 0x2000;
 		memctl->memc_mar = 0x0200;
@@ -330,7 +330,7 @@
 		memctl->memc_lsrt = 0x0b;
 		memctl->memc_lurt = 0x00;
 		ramaddr = (uchar *) PHYS_SDRAM_LOCAL;
-		sdmr = CFG_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		sdmr = CONFIG_SYS_LSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 		memctl->memc_lsdmr = sdmr | PSDMR_OP_PREA;
 		*ramaddr = 0xff;
 		for (i = 0; i < 8; i++) {
@@ -339,13 +339,13 @@
 		}
 		memctl->memc_lsdmr = sdmr | PSDMR_OP_MRW;
 		*ramaddr = 0xff;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_NORM;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_NORM;
 #endif
 		/* initialise 60x bus ram */
 		memctl->memc_psrt = 0x0b;
 		memctl->memc_purt = 0x08;
 		ramaddr32 = (ulong *) PHYS_SDRAM_60X;
-		sdmr = CFG_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
+		sdmr = CONFIG_SYS_PSDMR & ~(PSDMR_OP_MSK | PSDMR_RFEN | PSDMR_PBI);
 		memctl->memc_psdmr = sdmr | PSDMR_OP_PREA;
 		ramaddr32[0] = 0x00ff00ff;
 		ramaddr32[1] = 0x00ff00ff;
diff --git a/board/rsk7203/rsk7203.c b/board/rsk7203/rsk7203.c
index 2d74359..2cbd45e 100644
--- a/board/rsk7203/rsk7203.c
+++ b/board/rsk7203/rsk7203.c
@@ -39,9 +39,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/sacsng/clkinit.c b/board/sacsng/clkinit.c
index edb775d..4a7f362 100644
--- a/board/sacsng/clkinit.c
+++ b/board/sacsng/clkinit.c
@@ -37,7 +37,7 @@
 
 void Daq_BRG_Reset(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      volatile uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -53,7 +53,7 @@
 
 void Daq_BRG_Disable(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      volatile uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -68,7 +68,7 @@
 
 void Daq_BRG_Enable(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      volatile uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -82,7 +82,7 @@
 
 uint Daq_BRG_Get_Div16(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -104,7 +104,7 @@
 
 void Daq_BRG_Set_Div16(uint brg, uint div16)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -126,7 +126,7 @@
 
 uint Daq_BRG_Get_Count(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
      uint brg_cnt;
 
@@ -153,7 +153,7 @@
 
 void Daq_BRG_Set_Count(uint brg, uint brg_cnt)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -183,7 +183,7 @@
 
 uint Daq_BRG_Get_ExtClk(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -243,7 +243,7 @@
 
 void Daq_BRG_Set_ExtClk(uint brg, uint extc)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
 
      brg_ptr = (uint *)&immr->im_brgc1;
@@ -259,7 +259,7 @@
 
 uint Daq_BRG_Rate(uint brg)
 {
-     volatile immap_t *immr = (immap_t *)CFG_IMMR;
+     volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
      uint *brg_ptr;
      uint brg_cnt;
      uint brg_freq = 0;
@@ -296,7 +296,7 @@
 
 void Daq_Init_Clocks(int sample_rate, int sample_64x)
 {
-    volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
     uint mclk_divisor; /* MCLK divisor */
     int  flag;         /* Interrupt state */
 
@@ -378,7 +378,7 @@
 
 {
 #ifdef TIGHTEN_UP_BRG_TIMING
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
     register uint mclk_brg;       /* MCLK  BRG value */
     register uint sclk_brg;       /* SCLK  BRG value */
     register uint lrclk_brg;      /* LRCLK BRG value */
@@ -663,7 +663,7 @@
 
 {
 #ifdef TIGHTEN_UP_BRG_TIMING
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 
     register uint mclk_brg;       /* MCLK  BRG value */
     register uint sclk_brg;       /* SCLK  BRG value */
@@ -914,7 +914,7 @@
 void Daq_Display_Clocks(void)
 
 {
-    volatile immap_t *immr = (immap_t *)CFG_IMMR;
+    volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
     uint mclk_divisor; /* Detected MCLK divisor */
     uint sclk_divisor; /* Detected SCLK divisor */
 
diff --git a/board/sacsng/flash.c b/board/sacsng/flash.c
index 8fecf95..8b30f50 100644
--- a/board/sacsng/flash.c
+++ b/board/sacsng/flash.c
@@ -28,14 +28,14 @@
 #undef  DEBUG
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 #ifndef CONFIG_ENV_SIZE
 #define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
 #endif
 
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -52,24 +52,24 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b0 = flash_get_size((vu_short *)CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_short *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 			size_b0, size_b0<<20);
 	}
 
-	size_b1 = flash_get_size((vu_short *)CFG_FLASH1_BASE, &flash_info[1]);
+	size_b1 = flash_get_size((vu_short *)CONFIG_SYS_FLASH1_BASE, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -82,11 +82,11 @@
 #endif
 
 	if (size_b1) {
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -247,7 +247,7 @@
 	} else {
 #ifdef DEBUG
 		printf("Unknown flash type 0x%04X\n", value);
-		info->size = CFG_FLASH_SIZE;
+		info->size = CONFIG_SYS_FLASH_SIZE;
 #else
 		info->flash_id = FLASH_UNKNOWN;
 		return (0);			/* => no or unknown flash */
@@ -374,7 +374,7 @@
 	last  = start;
 	addr = (vu_short*)(info->start[l_sect]);
 	while ((addr[0] & 0x0080) != 0x0080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			addr[0] = 0xF0F0;	/* reset bank */
 			__asm__ __volatile__(" sync\n ");
@@ -509,7 +509,7 @@
 		/* data polling for D7 */
 		start = get_timer (0);
 		while (*(vu_short *)dest != (ushort)data) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/sacsng/sacsng.c b/board/sacsng/sacsng.c
index c00f14e..2513937 100644
--- a/board/sacsng/sacsng.c
+++ b/board/sacsng/sacsng.c
@@ -161,16 +161,16 @@
 
 phys_size_t initdram(int board_type)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8260_t *memctl = &immap->im_memctl;
     volatile uchar c = 0;
-    volatile uchar *ramaddr = (uchar *)(CFG_SDRAM_BASE + 0x8);
-    uint  psdmr = CFG_PSDMR;
+    volatile uchar *ramaddr = (uchar *)(CONFIG_SYS_SDRAM_BASE + 0x8);
+    uint  psdmr = CONFIG_SYS_PSDMR;
     int   i;
     uint   psrt = 14;					/* for no SPD */
     uint   chipselects = 1;				/* for no SPD */
-    uint   sdram_size = CFG_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
-    uint   or = CFG_OR2_PRELIM;				/* for no SPD */
+    uint   sdram_size = CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024;	/* for no SPD */
+    uint   or = CONFIG_SYS_OR2_PRELIM;				/* for no SPD */
 #ifdef SDRAM_SPD_ADDR
     uint   data_width;
     uint   rows;
@@ -383,10 +383,10 @@
      *  accessing the SDRAM with a single-byte transaction."
      *
      * The appropriate BRx/ORx registers have already been set when we
-     * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+     * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
      */
 
-    memctl->memc_mptpr = CFG_MPTPR;
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR;
     memctl->memc_psrt  = psrt;
 
     memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
@@ -409,7 +409,7 @@
     if(chipselects > 1) {
 	ramaddr += sdram_size;
 
-	memctl->memc_br3 = CFG_BR3_PRELIM + sdram_size;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM + sdram_size;
 	memctl->memc_or3 = or;
 
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
@@ -446,8 +446,8 @@
     /*
      * Note: iop is used by the I2C macros, and iopa by the ADC/DAC initialization.
      */
-    volatile ioport_t *iopa = ioport_addr((immap_t *)CFG_IMMR, 0 /* port A */);
-    volatile ioport_t *iop  = ioport_addr((immap_t *)CFG_IMMR, I2C_PORT);
+    volatile ioport_t *iopa = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 0 /* port A */);
+    volatile ioport_t *iop  = ioport_addr((immap_t *)CONFIG_SYS_IMMR, I2C_PORT);
 
     int  reg;          /* I2C register value */
     char *ep;          /* Environment pointer */
@@ -854,14 +854,14 @@
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
 
     iopd->pdat &= ~cs_mask[slave->cs];
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-    volatile ioport_t *iopd = ioport_addr((immap_t *)CFG_IMMR, 3 /* port D */);
+    volatile ioport_t *iopd = ioport_addr((immap_t *)CONFIG_SYS_IMMR, 3 /* port D */);
 
     iopd->pdat |= cs_mask[slave->cs];
 }
diff --git a/board/samsung/smdk6400/smdk6400.c b/board/samsung/smdk6400/smdk6400.c
index 77fd2c8..bd2e45a 100644
--- a/board/samsung/smdk6400/smdk6400.c
+++ b/board/samsung/smdk6400/smdk6400.c
@@ -107,12 +107,12 @@
 }
 #endif
 
-#if defined(CONFIG_CMD_NAND) && defined(CFG_NAND_LEGACY)
+#if defined(CONFIG_CMD_NAND) && defined(CONFIG_SYS_NAND_LEGACY)
 #include <linux/mtd/nand.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 void nand_init(void)
 {
-	nand_probe(CFG_NAND_BASE);
+	nand_probe(CONFIG_SYS_NAND_BASE);
 	if (nand_dev_desc[0].ChipID != NAND_ChipID_UNKNOWN)
 		print_size(nand_dev_desc[0].totlen, "\n");
 }
diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c
index 762fb73..dd712e3 100644
--- a/board/sandburst/common/flash.c
+++ b/board/sandburst/common/flash.c
@@ -41,9 +41,9 @@
 #endif /* DEBUG */
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xfff80000}	/* Boot Flash */
 };
 
@@ -65,7 +65,7 @@
 unsigned long flash_init (void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 
@@ -74,7 +74,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -284,7 +284,7 @@
 	start = get_timer (0);
 	last  = start;
 	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return -1;
 		}
@@ -502,7 +502,7 @@
 		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c
index 1e3dffb..9af6b8d 100644
--- a/board/sandburst/common/ppc440gx_i2c.c
+++ b/board/sandburst/common/ppc440gx_i2c.c
@@ -43,8 +43,8 @@
 #define IIC_NOK_TOUT	6		/* Transfer timeout */
 
 #define IIC_TIMEOUT 1			/* 1 second */
-#if defined(CFG_I2C_NOPROBES)
-static uchar i2c_no_probes[] = CFG_I2C_NOPROBES;
+#if defined(CONFIG_SYS_I2C_NOPROBES)
+static uchar i2c_no_probes[] = CONFIG_SYS_I2C_NOPROBES;
 #endif
 
 static void _i2c_bus1_reset (void)
@@ -105,7 +105,7 @@
 	unsigned long freqOPB;
 	int val, divisor;
 
-#ifdef CFG_I2C_INIT_BOARD
+#ifdef CONFIG_SYS_I2C_INIT_BOARD
 	/* call board specific i2c bus reset routine before accessing the   */
 	/* environment, which might be in a chip on that bus. For details   */
 	/* about this problem see doc/I2C_Edge_Conditions.                  */
@@ -384,7 +384,7 @@
 	}
 
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -397,7 +397,7 @@
 	 * hidden in the chip address.
 	 */
 	if( alen > 0 )
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 	if( (ret = i2c_transfer1( 1, chip<<1, &xaddr[4-alen], alen, buffer, len )) != 0) {
 		printf( "I2c read: failed %d\n", ret);
@@ -422,7 +422,7 @@
 		xaddr[3] = addr & 0xFF;
 	}
 
-#ifdef CFG_I2C_EEPROM_ADDR_OVERFLOW
+#ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW
 	/*
 	 * EEPROM chips that implement "address overflow" are ones
 	 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of
@@ -435,7 +435,7 @@
 	 * hidden in the chip address.
 	 */
 	if( alen > 0 )
-		chip |= ((addr >> (alen * 8)) & CFG_I2C_EEPROM_ADDR_OVERFLOW);
+		chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW);
 #endif
 
 	return (i2c_transfer1( 0, chip<<1, &xaddr[4-alen], alen, buffer, len ) != 0);
@@ -465,13 +465,13 @@
 int do_i2c1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
 	int j;
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
 	int k, skip;
 #endif
 
 	puts ("Valid chip addresses:");
 	for(j = 0; j < 128; j++) {
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
 		skip = 0;
 		for (k = 0; k < sizeof(i2c_no_probes); k++){
 			if (j == i2c_no_probes[k]){
@@ -488,7 +488,7 @@
 	}
 	putc ('\n');
 
-#if defined(CFG_I2C_NOPROBES)
+#if defined(CONFIG_SYS_I2C_NOPROBES)
 	puts ("Excluded chip addresses:");
 	for( k = 0; k < sizeof(i2c_no_probes); k++ )
 		printf(" %02X", i2c_no_probes[k] );
diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h
index 10000f5..328abd6 100644
--- a/board/sandburst/common/ppc440gx_i2c.h
+++ b/board/sandburst/common/ppc440gx_i2c.h
@@ -32,7 +32,7 @@
 
 #ifdef CONFIG_HARD_I2C
 
-#define I2C_BUS1_BASE_ADDR (CFG_PERIPHERAL_BASE + 0x00000500)
+#define I2C_BUS1_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500)
 #define	   I2C_REGISTERS_BUS1_BASE_ADDRESS I2C_BUS1_BASE_ADDR
 #define    IIC_MDBUF1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICMDBUF)
 #define    IIC_SDBUF1	(I2C_REGISTERS_BUS1_BASE_ADDRESS+IICSDBUF)
diff --git a/board/sandburst/common/sb_common.c b/board/sandburst/common/sb_common.c
index 51b1c75..f6ea16f 100644
--- a/board/sandburst/common/sb_common.c
+++ b/board/sandburst/common/sb_common.c
@@ -43,7 +43,7 @@
 {
 	ppc440_gpio_regs_t *gpio_regs;
 
-	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
 
 	if (gpio_regs->in & SBCOMMON_GPIO_PRI_N) {
 		return 0;
@@ -63,7 +63,7 @@
 {
 	ppc440_gpio_regs_t *gpio_regs;
 
-	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
 
 	if (gpio_regs->in & SBCOMMON_GPIO_SEC_PRES)
 		return 0;
@@ -84,7 +84,7 @@
 
 	/* Get the board serial number from eeprom */
 	/* Initialize I2C */
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read 256 bytes in EEPROM */
 	i2c_read (0x50, 0, 1, buff, 0x100);
@@ -218,11 +218,11 @@
  *
  *
  ************************************************************************/
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("Testing SDRAM: ");
@@ -340,7 +340,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*--------------------------------------------------------------------------+
@@ -355,7 +355,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -364,12 +364,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 
 /*************************************************************************
@@ -405,7 +405,7 @@
 	if (0 == macaddr_idx) {
 
 		/* Initialize I2C */
-		i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+		i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 		/* Read 256 bytes in EEPROM */
 		i2c_read (0x50, 0, 1, buff, 0x100);
diff --git a/board/sandburst/karef/config.mk b/board/sandburst/karef/config.mk
index 65c1e48..f2f94c5 100644
--- a/board/sandburst/karef/config.mk
+++ b/board/sandburst/karef/config.mk
@@ -39,5 +39,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S
index b1d47a4..3198dfd 100644
--- a/board/sandburst/karef/init.S
+++ b/board/sandburst/karef/init.S
@@ -90,12 +90,12 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/sandburst/karef/karef.c b/board/sandburst/karef/karef.c
index 72ce976..7909d34 100644
--- a/board/sandburst/karef/karef.c
+++ b/board/sandburst/karef/karef.c
@@ -65,7 +65,7 @@
 	mtsdr(sdr_pfc0, 0x00103E00);
 
 	/* Setup access for LEDs, and system topology info */
-	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
 	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
 	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
 
@@ -93,7 +93,7 @@
 	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 	      EBC_BXAP_PEN_DISABLED);
 
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 	/*--------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -259,8 +259,8 @@
 	KAREF_FPGA_REGS_ST *karef_ps;
 	OFEM_FPGA_REGS_ST *ofem_ps;
 
-	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
-	ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+	ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 
 	scan_id = (unsigned char)((karef_ps->revision_ul &
 				   SAND_HAL_KA_SC_SCAN_REVISION_IDENTIFICATION_MASK)
@@ -319,7 +319,7 @@
 
 	/* Fix the ack in the bme 32 */
 	udelay(5000);
-	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 	asm("eieio");
 
 
@@ -335,7 +335,7 @@
 {
 	/* Turn on i2c bus 1 */
 	puts ("I2C1:  ");
-	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	puts ("ready\n");
 
 	/* Turn on fans 3 & 4 */
@@ -397,8 +397,8 @@
 	}
 
 	if( getenv("fakeled")) {
-		karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
-		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 		ofem_ps->control_ul &= ~SAND_HAL_KA_SC_SCAN_CNTL_FAULT_LED_MASK;
 		karef_ps->control_ul &= ~SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_MASK;
 		setenv("bootdelay", "-1");
@@ -417,7 +417,7 @@
 {
 	KAREF_FPGA_REGS_ST *karef_ps;
 	/* TODO: ide reset */
-	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 
 	if (on) {
 		karef_ps->reset_ul &= ~SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK;
@@ -440,7 +440,7 @@
 	/* Ensure we have power all around */
 	udelay(500);
 
-	karef_ps = (KAREF_FPGA_REGS_ST *)CFG_KAREF_FPGA_BASE;
+	karef_ps = (KAREF_FPGA_REGS_ST *)CONFIG_SYS_KAREF_FPGA_BASE;
 	tmp =
 		SAND_HAL_KA_SC_SCAN_RESET_CF_RESET_N_MASK |
 		SAND_HAL_KA_SC_SCAN_RESET_BME_RESET_N_MASK |
@@ -470,7 +470,7 @@
 			SAND_HAL_KA_OF_OFEM_RESET_LOCH0_RESET_N_MASK |
 			SAND_HAL_KA_OF_OFEM_RESET_MAC0_RESET_N_MASK;
 
-		ofem_ps = (OFEM_FPGA_REGS_ST *)CFG_OFEM_FPGA_BASE;
+		ofem_ps = (OFEM_FPGA_REGS_ST *)CONFIG_SYS_OFEM_FPGA_BASE;
 		ofem_ps->reset_ul = tmp;
 
 		ofem_ps->control_ul |= 1 < SAND_HAL_KA_OF_OFEM_CNTL_FAULT_LED_SHIFT;
diff --git a/board/sandburst/metrobox/config.mk b/board/sandburst/metrobox/config.mk
index 91aee2f..565e826 100644
--- a/board/sandburst/metrobox/config.mk
+++ b/board/sandburst/metrobox/config.mk
@@ -34,5 +34,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S
index e398f00..ccdec46 100644
--- a/board/sandburst/metrobox/init.S
+++ b/board/sandburst/metrobox/init.S
@@ -88,12 +88,12 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x20000000, SZ_256M, 0x20000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x30000000, SZ_256M, 0x30000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/sandburst/metrobox/metrobox.c b/board/sandburst/metrobox/metrobox.c
index c38850d..c3c4459 100644
--- a/board/sandburst/metrobox/metrobox.c
+++ b/board/sandburst/metrobox/metrobox.c
@@ -55,7 +55,7 @@
 	mtsdr(sdr_pfc0, 0x00103E00);
 
 	/* Setup access for LEDs, and system topology info */
-	gpio_regs = (ppc440_gpio_regs_t *)CFG_GPIO_BASE;
+	gpio_regs = (ppc440_gpio_regs_t *)CONFIG_SYS_GPIO_BASE;
 	gpio_regs->open_drain = SBCOMMON_GPIO_SYS_LEDS;
 	gpio_regs->tri_state  = SBCOMMON_GPIO_DBGLEDS;
 
@@ -83,7 +83,7 @@
 	      EBC_BXAP_RE_DISABLED  | EBC_BXAP_BEM_WRITEONLY |
 	      EBC_BXAP_PEN_DISABLED);
 
-	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) |
+	mtebc(pb0cr, EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |
 	      EBC_BXCR_BS_1MB | EBC_BXCR_BU_RW | EBC_BXCR_BW_8BIT);
 	/*--------------------------------------------------------------------+
 	  | 8KB NVRAM/RTC. Initialize bank 1 with default values.
@@ -246,7 +246,7 @@
 	unsigned char opto_rev, opto_id;
 	OPTO_FPGA_REGS_ST *opto_ps;
 
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	opto_rev = (unsigned char)((opto_ps->revision_ul &
 				    SAND_HAL_XC_XCVR_CNTL_REVISION_REVISION_MASK)
@@ -286,7 +286,7 @@
 
 	/* Fix the ack in the bme 32 */
 	udelay(5000);
-	out32(CFG_BME32_BASE + 0x0000000C, 0x00000001);
+	out32(CONFIG_SYS_BME32_BASE + 0x0000000C, 0x00000001);
 	asm("eieio");
 
 
@@ -302,7 +302,7 @@
 {
 	/* Turn on i2c bus 1 */
 	puts ("I2C1:  ");
-	i2c1_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c1_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 	puts ("ready\n");
 
 	/* Turn on fans */
@@ -323,7 +323,7 @@
 	unsigned char opto_rev;
 	OPTO_FPGA_REGS_ST *opto_ps;
 
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	if(NULL != getenv("secondserial")) {
 	    puts("secondserial is set, switching to second serial port\n");
@@ -387,7 +387,7 @@
 void ide_set_reset(int on)
 {
 	OPTO_FPGA_REGS_ST *opto_ps;
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	if (on) {		/* assert RESET */
 	    opto_ps->reset_ul &= ~SAND_HAL_XC_XCVR_CNTL_RESET_CF_RESET_N_MASK;
@@ -412,7 +412,7 @@
 	/*
 	 * Take appropriate hw bits out of reset
 	 */
-	opto_ps = (OPTO_FPGA_REGS_ST *)CFG_FPGA_BASE;
+	opto_ps = (OPTO_FPGA_REGS_ST *)CONFIG_SYS_FPGA_BASE;
 
 	tmp =
 	    SAND_HAL_XC_XCVR_CNTL_RESET_MAC1_RESET_N_MASK |
diff --git a/board/sandpoint/early_init.S b/board/sandpoint/early_init.S
index 07dafb7..531dcdf 100644
--- a/board/sandpoint/early_init.S
+++ b/board/sandpoint/early_init.S
@@ -32,68 +32,68 @@
 
 #if defined(USE_DINK32)
   /* We are running from RAM, so do not clear the MCCR1_MEMGO bit! */
-  #define MCCR1VAL ((CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
+  #define MCCR1VAL ((CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT) | MCCR1_MEMGO)
 #else
-  #define MCCR1VAL (CFG_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CFG_ROMFAL << MCCR1_ROMFAL_SHIFT)
+  #define MCCR1VAL (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) | (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT)
 #endif
 
 	.text
 
 	/* Values to program into memory controller registers */
 tbl:	.long	MCCR1, MCCR1VAL
-	.long	MCCR2, CFG_REFINT << MCCR2_REFINT_SHIFT
+	.long	MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT
 	.long	MCCR3
-	.long	(((CFG_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
-		(CFG_REFREC << MCCR3_REFREC_SHIFT) | \
-		(CFG_RDLAT  << MCCR3_RDLAT_SHIFT)
+	.long	(((CONFIG_SYS_BSTOPRE & 0x000000f0) >> 4) << MCCR3_BSTOPRE2TO5_SHIFT) | \
+		(CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) | \
+		(CONFIG_SYS_RDLAT  << MCCR3_RDLAT_SHIFT)
 	.long	MCCR4
-	.long	(CFG_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CFG_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
-		(CFG_REGISTERD_TYPE_BUFFER << 20) | \
-		(((CFG_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
-		((CFG_SDMODE_CAS_LAT << 4) | (CFG_SDMODE_WRAP << 3) | \
-		(CFG_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
-		(CFG_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
-		((CFG_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
+	.long	(CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) | (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) | \
+		(CONFIG_SYS_REGISTERD_TYPE_BUFFER << 20) | \
+		(((CONFIG_SYS_BSTOPRE & 0x00000300) >> 8) << MCCR4_BSTOPRE0TO1_SHIFT ) | \
+		((CONFIG_SYS_SDMODE_CAS_LAT << 4) | (CONFIG_SYS_SDMODE_WRAP << 3) | \
+		(CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) | \
+		(CONFIG_SYS_ACTTORW << MCCR4_ACTTORW_SHIFT) | \
+		((CONFIG_SYS_BSTOPRE & 0x0000000f) << MCCR4_BSTOPRE6TO9_SHIFT )
 	.long	MSAR1
-	.long	(((CFG_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR1
-	.long	(((CFG_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MSAR2
-	.long	(((CFG_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMSAR2
-	.long	(((CFG_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR1
-	.long	(((CFG_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR1
-	.long	(((CFG_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	MEAR2
-	.long	(((CFG_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24)
 	.long	EMEAR2
-	.long	(((CFG_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
-		(((CFG_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
-		(((CFG_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
-		(((CFG_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
+	.long	(((CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  0) | \
+		(((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) <<  8) | \
+		(((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) | \
+		(((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24)
 	.long	0
 
 
@@ -123,7 +123,7 @@
 	/* set bank enable bits */
 	lis	r0, MBER@h
 	ori	r0, 0, MBER@l
-	li	r1, CFG_BANK_ENABLE
+	li	r1, CONFIG_SYS_BANK_ENABLE
 	stwbrx	r0, 0, r3
 	eieio
 	stb	r1, 0(r4)
@@ -145,8 +145,8 @@
 	eieio
 
 	/* set up stack pointer */
-	lis	r1, CFG_INIT_SP_OFFSET@h
-	ori	r1, r1, CFG_INIT_SP_OFFSET@l
+	lis	r1, CONFIG_SYS_INIT_SP_OFFSET@h
+	ori	r1, r1, CONFIG_SYS_INIT_SP_OFFSET@l
 
 	mtlr	r10
 	blr
diff --git a/board/sandpoint/flash.c b/board/sandpoint/flash.c
index 0f3eca2..e366cc6 100644
--- a/board/sandpoint/flash.c
+++ b/board/sandpoint/flash.c
@@ -30,11 +30,11 @@
 #define ROM_CS0_START	0xFF800000
 #define ROM_CS1_START	0xFF000000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR  (CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR  (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE  CONFIG_ENV_SECT_SIZE
@@ -140,10 +140,10 @@
 {
   unsigned long i;
   unsigned char j;
-  static const ulong flash_banks[] = CFG_FLASH_BANKS;
+  static const ulong flash_banks[] = CONFIG_SYS_FLASH_BANKS;
 
   /* Init: no FLASHes known */
-  for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+  for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
   {
     flash_info_t * const pflinfo = &flash_info[i];
     pflinfo->flash_id = FLASH_UNKNOWN;
@@ -154,9 +154,9 @@
   /* Enable writes to Sandpoint flash */
   {
     register unsigned char temp;
-    CONFIG_READ_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+    CONFIG_READ_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
     temp &= ~0x20; /* clear BIOSWP bit */
-    CONFIG_WRITE_BYTE(CFG_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
+    CONFIG_WRITE_BYTE(CONFIG_SYS_WINBOND_ISA_CFG_ADDR + WINBOND_CSCR, temp);
   }
 
   for(i = 0; i < sizeof flash_banks / sizeof flash_banks[0]; i++)
@@ -223,10 +223,10 @@
     }
     /* Protect monitor and environment sectors
      */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
     flash_protect(FLAG_PROTECT_SET,
-		CFG_MONITOR_BASE,
-		CFG_MONITOR_BASE + monitor_flash_len - 1,
+		CONFIG_SYS_MONITOR_BASE,
+		CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 		&flash_info[0]);
 #endif
 
@@ -612,7 +612,7 @@
     addr = (FLASH_WORD_SIZE *)(info->start[0] + (
 			(info->start[l_sect] - info->start[0]) << sh8b));
     while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -751,7 +751,7 @@
 	    start = get_timer (0);
 	    while ((dest2[i << sh8b] & (FLASH_WORD_SIZE)0x00800080) !=
 		   (data2[i] & (FLASH_WORD_SIZE)0x00800080)) {
-	      if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	      if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 		return (1);
 	      }
 	    }
diff --git a/board/sandpoint/sandpoint.c b/board/sandpoint/sandpoint.c
index 832baa2..bb01d73 100644
--- a/board/sandpoint/sandpoint.c
+++ b/board/sandpoint/sandpoint.c
@@ -58,7 +58,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
diff --git a/board/sbc2410x/flash.c b/board/sbc2410x/flash.c
index fa3996d..abb0935 100644
--- a/board/sbc2410x/flash.c
+++ b/board/sbc2410x/flash.c
@@ -29,7 +29,7 @@
 #define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
 #define MAIN_SECT_SIZE  0x10000	/* 64 KB */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 #define CMD_READ_ARRAY		0x000000F0
 #define CMD_UNLOCK1		0x000000AA
@@ -39,8 +39,8 @@
 #define CMD_PROGRAM		0x000000A0
 #define CMD_UNLOCK_BYPASS	0x00000020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
 
 #define BIT_ERASE_DONE		0x00000080
 #define BIT_RDY_MASK		0x00000080
@@ -59,7 +59,7 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
@@ -73,8 +73,8 @@
 #error "Unknown flash configured"
 #endif
 			flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -109,8 +109,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -234,7 +234,7 @@
 
 				/* check timeout */
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip = TMO;
 					break;
@@ -330,7 +330,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip = ERR | TMO;
 			break;
 		}
diff --git a/board/sbc405/strataflash.c b/board/sbc405/strataflash.c
index d21d885..e5863d6 100644
--- a/board/sbc405/strataflash.c
+++ b/board/sbc405/strataflash.c
@@ -103,7 +103,7 @@
 
 #define NUM_ERASE_REGIONS 4
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 
 /*-----------------------------------------------------------------------
@@ -120,7 +120,7 @@
 static ulong flash_get_size (ulong base, int banknum);
 static int flash_write_cfiword (flash_info_t *info, ulong dest, cfiword_t cword);
 static int flash_full_status_check(flash_info_t * info, ulong sector, ulong tout, char * prompt);
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 static int flash_write_cfibuffer(flash_info_t * info, ulong dest, uchar * cp, int len);
 #endif
 /*-----------------------------------------------------------------------
@@ -180,14 +180,14 @@
 	 *
 	 */
 
-	address = CFG_FLASH_BASE;
+	address = CONFIG_SYS_FLASH_BASE;
 	size = 0;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		size += flash_info[i].size = flash_get_size(address, i);
-		address += CFG_FLASH_INCREMENT;
+		address += CONFIG_SYS_FLASH_INCREMENT;
 		if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 			printf ("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n",i,
 				flash_info[0].size, flash_info[i].size<<20);
@@ -196,14 +196,14 @@
 
 #if 0 /* test-only */
 	/* Monitor protection ON by default */
-#if (CFG_MONITOR_BASE >= CFG_FLASH_BASE)
-	for(i=0; flash_info[0].start[i] < CFG_MONITOR_BASE+CFG_MONITOR_LEN-1; i++)
+#if (CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE)
+	for(i=0; flash_info[0].start[i] < CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1; i++)
 		(void)flash_real_protect(&flash_info[0], i, 1);
 #endif
 #else
 	/* monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-		       - CFG_MONITOR_LEN,
+		       - CONFIG_SYS_MONITOR_LEN,
 		       - 1, &flash_info[1]);
 #endif
 
@@ -277,7 +277,7 @@
 
 	printf ("  Sector Start Addresses:");
 	for (i=0; i<info->sector_count; ++i) {
-#ifdef CFG_FLASH_EMPTY_INFO
+#ifdef CONFIG_SYS_FLASH_EMPTY_INFO
 		int k;
 		int size;
 		int erased;
@@ -357,7 +357,7 @@
 		wp = cp;
 	}
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 	while(cnt >= info->portwidth) {
 		i = info->buffer_size > cnt? cnt: info->buffer_size;
 		if((rc = flash_write_cfibuffer(info, wp, src,i)) != ERR_OK)
@@ -378,7 +378,7 @@
 		wp += info->portwidth;
 		cnt -= info->portwidth;
 	}
-#endif /* CFG_FLASH_USE_BUFFER_WRITE */
+#endif /* CONFIG_SYS_FLASH_USE_BUFFER_WRITE */
 	if (cnt == 0) {
 		return (0);
 	}
@@ -720,7 +720,7 @@
 	return flash_full_status_check(info, 0, info->write_tout, "write");
 }
 
-#ifdef CFG_FLASH_USE_BUFFER_WRITE
+#ifdef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 
 /* loop through the sectors from the highest address
  * when the passed address is greater or equal to the sector address
@@ -790,4 +790,4 @@
 	flash_write_cmd(info, sector, 0, FLASH_CMD_CLEAR_STATUS);
 	return retcode;
 }
-#endif /* CFG_USE_FLASH_BUFFER_WRITE */
+#endif /* CONFIG_SYS_USE_FLASH_BUFFER_WRITE */
diff --git a/board/sbc8240/flash.c b/board/sbc8240/flash.c
index dec6156..a095753 100644
--- a/board/sbc8240/flash.c
+++ b/board/sbc8240/flash.c
@@ -32,10 +32,10 @@
 #include <mpc824x.h>
 #include <asm/processor.h>
 
-#if CFG_MAX_FLASH_BANKS != 1
-#error "CFG_MAX_FLASH_BANKS must be 1"
+#if CONFIG_SYS_MAX_FLASH_BANKS != 1
+#error "CONFIG_SYS_MAX_FLASH_BANKS must be 1"
 #endif
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -399,7 +399,7 @@
 	last = start;
 	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
 	       (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return -1;
 		}
@@ -628,7 +628,7 @@
 		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/sbc8240/sbc8240.c b/board/sbc8240/sbc8240.c
index 075e377..01abe26 100644
--- a/board/sbc8240/sbc8240.c
+++ b/board/sbc8240/sbc8240.c
@@ -53,7 +53,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -97,9 +97,9 @@
 /* ------------------------------------------------------------------------- */
 int misc_init_r (void)
 {
-#ifdef CFG_LED_BASE
-	*((unsigned char *) (CFG_LED_BASE)) = 0xFF;
-#endif /* CFG_LED_BASE */
+#ifdef CONFIG_SYS_LED_BASE
+	*((unsigned char *) (CONFIG_SYS_LED_BASE)) = 0xFF;
+#endif /* CONFIG_SYS_LED_BASE */
 
 	return (0);
 }
diff --git a/board/sbc8260/flash.c b/board/sbc8260/flash.c
index d3b1f31..645c67f 100644
--- a/board/sbc8260/flash.c
+++ b/board/sbc8260/flash.c
@@ -31,7 +31,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -49,21 +49,21 @@
     int i;
 
     /* Init: no FLASHes known */
-    for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+    for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
     /* for now, only support the 4 MB Flash SIMM */
-    size = flash_get_size((vu_long *)CFG_FLASH0_BASE, &flash_info[0]);
+    size = flash_get_size((vu_long *)CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 
     /*
      * protect monitor and environment sectors
      */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_MONITOR_BASE,
-		  CFG_MONITOR_BASE+monitor_flash_len-1,
+		  CONFIG_SYS_MONITOR_BASE,
+		  CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		  &flash_info[0]);
 #endif
 
@@ -77,7 +77,7 @@
 		  &flash_info[0]);
 #endif
 
-    return /*size*/ (CFG_FLASH0_SIZE * 1024 * 1024);
+    return /*size*/ (CONFIG_SYS_FLASH0_SIZE * 1024 * 1024);
 }
 
 /*-----------------------------------------------------------------------
@@ -258,7 +258,7 @@
     last  = start;
     addr = (vu_long*)(info->start[l_sect]);
     while ((addr[0] & 0x80808080) != 0x80808080) {
-	if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 	    printf ("Timeout\n");
 	    return 1;
 	}
@@ -381,7 +381,7 @@
     /* data polling for D7 */
     start = get_timer (0);
     while ((*((vu_long *)dest) & 0x80808080) != (data & 0x80808080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    return (1);
 	}
     }
diff --git a/board/sbc8260/sbc8260.c b/board/sbc8260/sbc8260.c
index 5781f62..f5f23be 100644
--- a/board/sbc8260/sbc8260.c
+++ b/board/sbc8260/sbc8260.c
@@ -210,10 +210,10 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
-	volatile uchar c = 0, *ramaddr = (uchar *) (CFG_SDRAM_BASE + 0x8);
-	ulong psdmr = CFG_PSDMR;
+	volatile uchar c = 0, *ramaddr = (uchar *) (CONFIG_SYS_SDRAM_BASE + 0x8);
+	ulong psdmr = CONFIG_SYS_PSDMR;
 	int i;
 
 	/*
@@ -233,11 +233,11 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_psdmr = psdmr | PSDMR_OP_PREA;
 	*ramaddr = c;
@@ -253,15 +253,15 @@
 	*ramaddr = c;
 
 	/* return total ram size */
-	return (CFG_SDRAM0_SIZE * 1024 * 1024);
+	return (CONFIG_SYS_SDRAM0_SIZE * 1024 * 1024);
 }
 
 #ifdef CONFIG_MISC_INIT_R
 /* ------------------------------------------------------------------------- */
 int misc_init_r (void)
 {
-#ifdef CFG_LED_BASE
-	uchar ds = *(unsigned char *) (CFG_LED_BASE + 1);
+#ifdef CONFIG_SYS_LED_BASE
+	uchar ds = *(unsigned char *) (CONFIG_SYS_LED_BASE + 1);
 	uchar ss;
 	uchar tmp[64];
 	int res;
@@ -280,10 +280,10 @@
 			tmp[17] = '\0';
 			setenv ("ethaddr", tmp);
 			/* set the led to show the address */
-			*((unsigned char *) (CFG_LED_BASE + 1)) = ds;
+			*((unsigned char *) (CONFIG_SYS_LED_BASE + 1)) = ds;
 		}
 	}
-#endif /* CFG_LED_BASE */
+#endif /* CONFIG_SYS_LED_BASE */
 	return (0);
 }
 #endif /* CONFIG_MISC_INIT_R */
diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c
index 527f7e4..9022c55 100644
--- a/board/sbc8349/pci.c
+++ b/board/sbc8349/pci.c
@@ -40,8 +40,8 @@
 #ifdef CONFIG_PCI
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 
 #ifndef CONFIG_PCI_PNP
 static struct pci_config_table pci_mpc8349emds_config_table[] = {
@@ -90,7 +90,7 @@
 	u32 dev;
 	struct	pci_controller * hose;
 
-	immr = (immap_t *)CFG_IMMR;
+	immr = (immap_t *)CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *)&immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
@@ -132,10 +132,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
 
 	/*
@@ -143,18 +143,18 @@
 	 */
 
 	/* PCI1 mem space - prefetch */
-	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI1 IO space */
-	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 
 	/* PCI1 mmio - non-prefetch mem space */
-	pci_pot[2].potar = (CFG_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[2].pobar = (CFG_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[2].potar = (CONFIG_SYS_PCI1_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[2].pobar = (CONFIG_SYS_PCI1_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[2].pocmr = POCMR_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/*
@@ -173,23 +173,23 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI1_MEM_BASE,
-		       CFG_PCI1_MEM_PHYS,
-		       CFG_PCI1_MEM_SIZE,
+		       CONFIG_SYS_PCI1_MEM_BASE,
+		       CONFIG_SYS_PCI1_MEM_PHYS,
+		       CONFIG_SYS_PCI1_MEM_SIZE,
 		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI1_MMIO_BASE,
-		       CFG_PCI1_MMIO_PHYS,
-		       CFG_PCI1_MMIO_SIZE,
+		       CONFIG_SYS_PCI1_MMIO_BASE,
+		       CONFIG_SYS_PCI1_MMIO_PHYS,
+		       CONFIG_SYS_PCI1_MMIO_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI1_IO_BASE,
-		       CFG_PCI1_IO_PHYS,
-		       CFG_PCI1_IO_SIZE,
+		       CONFIG_SYS_PCI1_IO_BASE,
+		       CONFIG_SYS_PCI1_IO_PHYS,
+		       CONFIG_SYS_PCI1_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -202,8 +202,8 @@
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR+0x8300),
-			   (CFG_IMMR+0x8304));
+			   (CONFIG_SYS_IMMR+0x8300),
+			   (CONFIG_SYS_IMMR+0x8304));
 
 	pci_register_hose(hose);
 
@@ -239,18 +239,18 @@
 	 */
 
 	/* PCI2 mem space - prefetch */
-	pci_pot[3].potar = (CFG_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[3].pobar = (CFG_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[3].potar = (CONFIG_SYS_PCI2_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[3].pobar = (CONFIG_SYS_PCI2_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[3].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_PREFETCH_EN | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/* PCI2 IO space */
-	pci_pot[4].potar = (CFG_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[4].pobar = (CFG_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[4].potar = (CONFIG_SYS_PCI2_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[4].pobar = (CONFIG_SYS_PCI2_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[4].pocmr = POCMR_EN | POCMR_PCI2 | POCMR_IO | (POCMR_CM_1M & POCMR_CM_MASK);
 
 	/* PCI2 mmio - non-prefetch mem space */
-	pci_pot[5].potar = (CFG_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[5].pobar = (CFG_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[5].potar = (CONFIG_SYS_PCI2_MMIO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[5].pobar = (CONFIG_SYS_PCI2_MMIO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[5].pocmr = POCMR_EN | POCMR_PCI2 | (POCMR_CM_256M & POCMR_CM_MASK);
 
 	/*
@@ -269,23 +269,23 @@
 
 	/* PCI memory prefetch space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI2_MEM_BASE,
-		       CFG_PCI2_MEM_PHYS,
-		       CFG_PCI2_MEM_SIZE,
+		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_PHYS,
+		       CONFIG_SYS_PCI2_MEM_SIZE,
 		       PCI_REGION_MEM|PCI_REGION_PREFETCH);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI2_MMIO_BASE,
-		       CFG_PCI2_MMIO_PHYS,
-		       CFG_PCI2_MMIO_SIZE,
+		       CONFIG_SYS_PCI2_MMIO_BASE,
+		       CONFIG_SYS_PCI2_MMIO_PHYS,
+		       CONFIG_SYS_PCI2_MMIO_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI2_IO_BASE,
-		       CFG_PCI2_IO_PHYS,
-		       CFG_PCI2_IO_SIZE,
+		       CONFIG_SYS_PCI2_IO_BASE,
+		       CONFIG_SYS_PCI2_IO_PHYS,
+		       CONFIG_SYS_PCI2_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -298,8 +298,8 @@
 	hose->region_count = 4;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR+0x8380),
-			   (CFG_IMMR+0x8384));
+			   (CONFIG_SYS_IMMR+0x8380),
+			   (CONFIG_SYS_IMMR+0x8384));
 
 	pci_register_hose(hose);
 
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 93ada0b..4154f29 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -54,14 +54,14 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
 	/* DDR SDRAM - Main SODIMM */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
 	msize = spd_sdram();
 #else
@@ -88,12 +88,12 @@
  ************************************************************************/
 int fixed_sdram(void)
 {
-	volatile immap_t *im = (immap_t *)CFG_IMMR;
+	volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 	u32 msize = 0;
 	u32 ddr_size;
 	u32 ddr_size_log2;
 
-	msize = CFG_DDR_SIZE;
+	msize = CONFIG_SYS_DDR_SIZE;
 	for (ddr_size = msize << 20, ddr_size_log2 = 0;
 	     (ddr_size > 1);
 	     ddr_size = ddr_size>>1, ddr_size_log2++) {
@@ -101,22 +101,22 @@
 			return -1;
 		}
 	}
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE & 0xfffff000;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
 	im->sysconf.ddrlaw[0].ar = LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
 
-#if (CFG_DDR_SIZE != 256)
+#if (CONFIG_SYS_DDR_SIZE != 256)
 #warning Currently any ddr size other than 256 is not supported
 #endif
 	im->ddr.csbnds[2].csbnds = 0x0000000f;
-	im->ddr.cs_config[2] = CFG_DDR_CONFIG;
+	im->ddr.cs_config[2] = CONFIG_SYS_DDR_CONFIG;
 
 	/* currently we use only one CS, so disable the other banks */
 	im->ddr.cs_config[0] = 0;
 	im->ddr.cs_config[1] = 0;
 	im->ddr.cs_config[3] = 0;
 
-	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
-	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
+	im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
 
 	im->ddr.sdram_cfg =
 		SDRAM_CFG_SREN
@@ -128,16 +128,16 @@
 	/* for 32-bit mode burst length is 8 */
 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
 #endif
-	im->ddr.sdram_mode = CFG_DDR_MODE;
+	im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
 
-	im->ddr.sdram_interval = CFG_DDR_INTERVAL;
+	im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 	udelay(200);
 
 	/* enable DDR controller */
 	im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
 	return msize;
 }
-#endif/*!CFG_SPD_EEPROM*/
+#endif/*!CONFIG_SYS_SPD_EEPROM*/
 
 
 int checkboard (void)
@@ -149,44 +149,44 @@
 /*
  * if board is fitted with SDRAM
  */
-#if defined(CFG_BR2_PRELIM)  \
-	&& defined(CFG_OR2_PRELIM) \
-	&& defined(CFG_LBLAWBAR2_PRELIM) \
-	&& defined(CFG_LBLAWAR2_PRELIM)
+#if defined(CONFIG_SYS_BR2_PRELIM)  \
+	&& defined(CONFIG_SYS_OR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWBAR2_PRELIM) \
+	&& defined(CONFIG_SYS_LBLAWAR2_PRELIM)
 /*
  * Initialize SDRAM memory on the Local Bus.
  */
 
 void sdram_init(void)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile lbus83xx_t *lbc= &immap->lbus;
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 
 	puts("\n   SDRAM on Local Bus: ");
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
 
 	/* setup mtrpt, lsrt and lbcr for LB bus */
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->mrtpr = CFG_LBC_MRTPR;
-	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	asm("sync");
 
 	/*
 	 * Configure the SDRAM controller Machine Mode Register.
 	 */
-	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 
-	lbc->lsdmr = CFG_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* 0x68636733; precharge all the banks */
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_2; /* 0x48636733; auto refresh */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; /* 0x48636733; auto refresh */
 	asm("sync");
 	/*1 times*/
 	*sdram_addr = 0xff;
@@ -214,12 +214,12 @@
 	udelay(100);
 
 	/* 0x58636733; mode register write operation */
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
 
-	lbc->lsdmr = CFG_LBC_LSDMR_5; /* 0x40636733; normal operation */
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* 0x40636733; normal operation */
 	asm("sync");
 	*sdram_addr = 0xff;
 	udelay(100);
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c
index ab54260..e8c7ae2 100644
--- a/board/sbc8548/law.c
+++ b/board/sbc8548/law.c
@@ -46,12 +46,12 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 	/* LBC window - maps 256M 0xf0000000 -> 0xffffffff */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c
index f31d7d6..21f82f2 100644
--- a/board/sbc8548/sbc8548.c
+++ b/board/sbc8548/sbc8548.c
@@ -53,9 +53,9 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
-	volatile u_char *rev= (void *)CFG_BD_REV;
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
+	volatile u_char *rev= (void *)CONFIG_SYS_BD_REV;
 
 	printf ("Board: Wind River SBC8548 Rev. 0x%01x\n",
 			(*rev) >> 4);
@@ -98,7 +98,7 @@
 		 *    Override DLL = 1, Course Adj = 1, Tap Select = 0
 		 */
 
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 		gur->ddrdllcr = 0x81000000;
 		asm("sync;isync;msync");
@@ -135,8 +135,8 @@
 void
 local_bus_init(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	uint clkdiv;
 	uint lbc_hz;
@@ -169,44 +169,44 @@
 void
 sdram_init(void)
 {
-#if defined(CFG_OR3_PRELIM) && defined(CFG_BR3_PRELIM)
+#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
 
 	uint idx;
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	uint *sdram_addr = (uint *)CONFIG_SYS_LBC_SDRAM_BASE;
 	uint lsdmr_common;
 
 	puts("    SDRAM: ");
 
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
+	print_size (CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 
 	/*
 	 * Setup SDRAM Base and Option Registers
 	 */
-	lbc->or3 = CFG_OR3_PRELIM;
+	lbc->or3 = CONFIG_SYS_OR3_PRELIM;
 	asm("msync");
 
-	lbc->br3 = CFG_BR3_PRELIM;
+	lbc->br3 = CONFIG_SYS_BR3_PRELIM;
 	asm("msync");
 
-	lbc->lbcr = CFG_LBC_LBCR;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
 	asm("msync");
 
 
-	lbc->lsrt = CFG_LBC_LSRT;
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("msync");
 
 	/*
 	 * MPC8548 uses "new" 15-16 style addressing.
 	 */
-	lsdmr_common = CFG_LBC_LSDMR_COMMON;
-	lsdmr_common |= CFG_LBC_LSDMR_BSMA1516;
+	lsdmr_common = CONFIG_SYS_LBC_LSDMR_COMMON;
+	lsdmr_common |= CONFIG_SYS_LBC_LSDMR_BSMA1516;
 
 	/*
 	 * Issue PRECHARGE ALL command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_PCHALL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_PCHALL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -216,7 +216,7 @@
 	 * Issue 8 AUTO REFRESH commands.
 	 */
 	for (idx = 0; idx < 8; idx++) {
-		lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_ARFRSH;
+		lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH;
 		asm("sync;msync");
 		*sdram_addr = 0xff;
 		ppcDcbf((unsigned long) sdram_addr);
@@ -226,7 +226,7 @@
 	/*
 	 * Issue 8 MODE-set command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_MRW;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_MRW;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -235,7 +235,7 @@
 	/*
 	 * Issue NORMAL OP command.
 	 */
-	lbc->lsdmr = lsdmr_common | CFG_LBC_LSDMR_OP_NORMAL;
+	lbc->lsdmr = lsdmr_common | CONFIG_SYS_LBC_LSDMR_OP_NORMAL;
 	asm("sync;msync");
 	*sdram_addr = 0xff;
 	ppcDcbf((unsigned long) sdram_addr);
@@ -244,17 +244,17 @@
 #endif	/* enable SDRAM init */
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int
 testdram(void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("Testing DRAM from 0x%08x to 0x%08x\n",
-	       CFG_MEMTEST_START,
-	       CFG_MEMTEST_END);
+	       CONFIG_SYS_MEMTEST_START,
+	       CONFIG_SYS_MEMTEST_END);
 
 	printf("DRAM test phase 1:\n");
 	for (p = pstart; p < pend; p++)
@@ -290,9 +290,9 @@
  ************************************************************************/
 long int fixed_sdram (void)
 {
-    #define CFG_DDR_CONTROL 0xc300c000
+    #define CONFIG_SYS_DDR_CONTROL 0xc300c000
 
-	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
 	ddr->cs0_bnds		= 0x0000007f;
 	ddr->cs1_bnds		= 0x008000ff;
@@ -319,12 +319,12 @@
 
 	#if defined (CONFIG_DDR_ECC)
 	  /* Enable ECC checking */
-	  ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	  ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
 	#else
-	  ddr->sdram_cfg = CFG_DDR_CONTROL;
+	  ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 	#endif
 
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif
 
@@ -367,11 +367,11 @@
 void
 pci_init_board(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 	struct pci_config_table *table;
@@ -397,24 +397,24 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 		hose->region_count = 3;
 
@@ -466,7 +466,7 @@
 
 #ifdef CONFIG_PCIE1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) || (host_agent == 3);
@@ -486,23 +486,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCIE1_MEM_BASE,
-			       CFG_PCIE1_MEM_PHYS,
-			       CFG_PCIE1_MEM_SIZE,
+			       CONFIG_SYS_PCIE1_MEM_BASE,
+			       CONFIG_SYS_PCIE1_MEM_PHYS,
+			       CONFIG_SYS_PCIE1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCIE1_IO_BASE,
-			       CFG_PCIE1_IO_PHYS,
-			       CFG_PCIE1_IO_SIZE,
+			       CONFIG_SYS_PCIE1_IO_BASE,
+			       CONFIG_SYS_PCIE1_IO_PHYS,
+			       CONFIG_SYS_PCIE1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c
index 6314005..18d11f6 100644
--- a/board/sbc8548/tlb.c
+++ b/board/sbc8548/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff800000	16M	TLB for 8MB FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -71,7 +71,7 @@
 	 * 0x0		256M DDR SDRAM
 	 */
 	#if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 	#endif
@@ -81,7 +81,7 @@
 	 * 0xe0000000	1M	CCSRBAR
 	 * 0xe2000000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_64M, 1),
 
@@ -89,7 +89,7 @@
 	 * TLB 5:	64M	Cacheable, non-guarded
 	 * 0xf0000000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -100,7 +100,7 @@
 	 * 0xf8300000	1M	Board revision
 	 * 0xf8b00000	1M	EEPROM
 	 */
-	SET_TLB_ENTRY(1, CFG_EPLD_BASE, CFG_EPLD_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_16M, 1),
 };
diff --git a/board/sbc8560/law.c b/board/sbc8560/law.c
index 10dedb4..4e6baed 100644
--- a/board/sbc8560/law.c
+++ b/board/sbc8560/law.c
@@ -51,10 +51,10 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c
index dc66170..413926d 100644
--- a/board/sbc8560/sbc8560.c
+++ b/board/sbc8560/sbc8560.c
@@ -197,7 +197,7 @@
 int board_early_init_f (void)
 {
 #if defined(CONFIG_PCI)
-    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -207,7 +207,7 @@
 void reset_phy (void)
 {
 #if defined(CONFIG_ETHER_ON_FCC) /* avoid compile warnings for now */
-	volatile unsigned char *bcsr = (unsigned char *) CFG_BCSR;
+	volatile unsigned char *bcsr = (unsigned char *) CONFIG_SYS_BCSR;
 #endif
 	/* reset Giga bit Ethernet port if needed here */
 
@@ -249,9 +249,9 @@
 	printf ("\tCPU: %lu MHz\n", sysinfo.freqProcessor / 1000000);
 	printf ("\tCCB: %lu MHz\n", sysinfo.freqSystemBus / 1000000);
 	printf ("\tDDR: %lu MHz\n", sysinfo.freqSystemBus / 2000000);
-	if((CFG_LBC_LCRR & 0x0f) == 2 || (CFG_LBC_LCRR & 0x0f) == 4 \
-		|| (CFG_LBC_LCRR & 0x0f) == 8) {
-		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CFG_LBC_LCRR & 0x0f));
+	if((CONFIG_SYS_LBC_LCRR & 0x0f) == 2 || (CONFIG_SYS_LBC_LCRR & 0x0f) == 4 \
+		|| (CONFIG_SYS_LBC_LCRR & 0x0f) == 8) {
+		printf ("\tLBC: %lu MHz\n", sysinfo.freqSystemBus / 1000000 /(CONFIG_SYS_LBC_LCRR & 0x0f));
 	} else {
 		printf("\tLBC: unknown\n");
 	}
@@ -267,13 +267,13 @@
 
 #if 0
 #if !defined(CONFIG_RAM_AS_FLASH)
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	sys_info_t sysinfo;
 	uint temp_lbcdll = 0;
 #endif
 #endif /* 0 */
 #if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL)
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_DDR_DLL)
 	uint temp_ddrdll = 0;
@@ -296,38 +296,38 @@
 #if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */
 	get_sys_info(&sysinfo);
 	/* if localbus freq is less than 66Mhz,we use bypass mode,otherwise use DLL */
-	if(sysinfo.freqSystemBus/(CFG_LBC_LCRR & 0x0f) < 66000000) {
-		lbc->lcrr = (CFG_LBC_LCRR & 0x0fffffff)| 0x80000000;
+	if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) {
+		lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000;
 	} else {
 #if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */
 		lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */
 #endif
-		lbc->lcrr = CFG_LBC_LCRR & 0x7fffffff;
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff;
 		udelay(200);
 		temp_lbcdll = gur->lbcdllcr;
 		gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000;
 		asm("sync;isync;msync");
 	}
-	lbc->or2 = CFG_OR2_PRELIM; /* 64MB SDRAM */
-	lbc->br2 = CFG_BR2_PRELIM;
-	lbc->lbcr = CFG_LBC_LBCR;
-	lbc->lsdmr = CFG_LBC_LSDMR_1;
+	lbc->or2 = CONFIG_SYS_OR2_PRELIM; /* 64MB SDRAM */
+	lbc->br2 = CONFIG_SYS_BR2_PRELIM;
+	lbc->lbcr = CONFIG_SYS_LBC_LBCR;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1;
 	asm("sync");
 	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_2;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
 	asm("sync");
 	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_3;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3;
 	asm("sync");
 	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_4;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
 	asm("sync");
 	(unsigned int) * (ulong *)0 = 0x000000ff;
-	lbc->lsdmr = CFG_LBC_LSDMR_5;
+	lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5;
 	asm("sync");
-	lbc->lsrt = CFG_LBC_LSRT;
+	lbc->lsrt = CONFIG_SYS_LBC_LSRT;
 	asm("sync");
-	lbc->mrtpr = CFG_LBC_MRTPR;
+	lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
 	asm("sync");
 #endif
 #endif
@@ -338,7 +338,7 @@
 		 * enable errors */
 		uint *p = 0;
 		uint i = 0;
-		volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+		volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 		dma_init();
 		for (*p = 0; p < (uint *)(8 * 1024); p++) {
 			if (((unsigned int)p & 0x1f) == 0) { dcbz(p); }
@@ -381,11 +381,11 @@
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
@@ -422,12 +422,12 @@
 long int fixed_sdram (void)
 {
 
-#define CFG_DDR_CONTROL 0xc2000000
+#define CONFIG_SYS_DDR_CONTROL 0xc2000000
 
-  #ifndef CFG_RAMBOOT
-	volatile ccsr_ddr_t *ddr= (void *)(CFG_MPC85xx_DDR_ADDR);
+  #ifndef CONFIG_SYS_RAMBOOT
+	volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
-#if (CFG_SDRAM_SIZE == 512)
+#if (CONFIG_SYS_SDRAM_SIZE == 512)
 	ddr->cs0_bnds		= 0x0000000f;
 #else
 	ddr->cs0_bnds		= 0x00000007;
@@ -452,14 +452,14 @@
 	udelay(500);
     #if defined (CONFIG_DDR_ECC)
 	/* Enable ECC checking */
-	ddr->sdram_cfg = (CFG_DDR_CONTROL | 0x20000000);
+	ddr->sdram_cfg = (CONFIG_SYS_DDR_CONTROL | 0x20000000);
     #else
-	ddr->sdram_cfg = CFG_DDR_CONTROL;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
     #endif
 	asm("sync; isync; msync");
 	udelay(500);
   #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif	/* !defined(CONFIG_SPD_EEPROM) */
 
diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c
index d073399..fe0ac76 100644
--- a/board/sbc8560/tlb.c
+++ b/board/sbc8560/tlb.c
@@ -28,7 +28,7 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 /* TLB for CCSRBAR (IMMR) */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_1M, 1),
 
@@ -44,20 +44,20 @@
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
 #if !defined(CONFIG_SPD_EEPROM)
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 5, BOOKE_PAGESZ_256M, 1),
 #endif
 
-	SET_TLB_ENTRY(1, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(1, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_16K, 1),
 
-	SET_TLB_ENTRY(1, CFG_PCI_MEM_PHYS, CFG_PCI_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI_MEM_PHYS, CONFIG_SYS_PCI_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 };
diff --git a/board/sbc8641d/law.c b/board/sbc8641d/law.c
index 801c5b7..de47fcd 100644
--- a/board/sbc8641d/law.c
+++ b/board/sbc8641d/law.c
@@ -44,15 +44,15 @@
 
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
-	SET_LAW(CFG_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_1),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xf8000000, LAW_SIZE_2M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	SET_LAW(0xfe000000, LAW_SIZE_32M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
-	SET_LAW(CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR_2),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO)
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/sbc8641d/sbc8641d.c b/board/sbc8641d/sbc8641d.c
index 62b48c8..06d1d2a 100644
--- a/board/sbc8641d/sbc8641d.c
+++ b/board/sbc8641d/sbc8641d.c
@@ -66,7 +66,7 @@
 	dram_size = fixed_sdram ();
 #endif
 
-#if defined(CFG_RAMBOOT)
+#if defined(CONFIG_SYS_RAMBOOT)
 	puts ("    DDR: ");
 	return dram_size;
 #endif
@@ -82,11 +82,11 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	puts ("SDRAM test phase 1:\n");
@@ -122,72 +122,72 @@
  */
 long int fixed_sdram (void)
 {
-#if !defined(CFG_RAMBOOT)
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+#if !defined(CONFIG_SYS_RAMBOOT)
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs1_bnds = CFG_DDR_CS1_BNDS;
-	ddr->cs2_bnds = CFG_DDR_CS2_BNDS;
-	ddr->cs3_bnds = CFG_DDR_CS3_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->cs1_config = CFG_DDR_CS1_CONFIG;
-	ddr->cs2_config = CFG_DDR_CS2_CONFIG;
-	ddr->cs3_config = CFG_DDR_CS3_CONFIG;
-	ddr->timing_cfg_3 = CFG_DDR_TIMING_3;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_cfg_1 = CFG_DDR_CFG_1A;
-	ddr->sdram_cfg_2 = CFG_DDR_CFG_2;
-	ddr->sdram_mode_1 = CFG_DDR_MODE_1;
-	ddr->sdram_mode_2 = CFG_DDR_MODE_2;
-	ddr->sdram_mode_cntl = CFG_DDR_MODE_CTL;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
-	ddr->sdram_data_init = CFG_DDR_DATA_INIT;
-	ddr->sdram_clk_cntl = CFG_DDR_CLK_CTRL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CFG_2;
+	ddr->sdram_mode_1 = CONFIG_SYS_DDR_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
+	ddr->sdram_mode_cntl = CONFIG_SYS_DDR_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 
 	asm ("sync;isync");
 
 	udelay (500);
 
-	ddr->sdram_cfg_1 = CFG_DDR_CFG_1B;
+	ddr->sdram_cfg_1 = CONFIG_SYS_DDR_CFG_1B;
 	asm ("sync; isync");
 
 	udelay (500);
 	ddr = &immap->im_ddr2;
 
-	ddr->cs0_bnds = CFG_DDR2_CS0_BNDS;
-	ddr->cs1_bnds = CFG_DDR2_CS1_BNDS;
-	ddr->cs2_bnds = CFG_DDR2_CS2_BNDS;
-	ddr->cs3_bnds = CFG_DDR2_CS3_BNDS;
-	ddr->cs0_config = CFG_DDR2_CS0_CONFIG;
-	ddr->cs1_config = CFG_DDR2_CS1_CONFIG;
-	ddr->cs2_config = CFG_DDR2_CS2_CONFIG;
-	ddr->cs3_config = CFG_DDR2_CS3_CONFIG;
-	ddr->timing_cfg_3 = CFG_DDR2_EXT_REFRESH;
-	ddr->timing_cfg_0 = CFG_DDR2_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR2_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR2_TIMING_2;
-	ddr->sdram_cfg_1 = CFG_DDR2_CFG_1A;
-	ddr->sdram_cfg_2 = CFG_DDR2_CFG_2;
-	ddr->sdram_mode_1 = CFG_DDR2_MODE_1;
-	ddr->sdram_mode_2 = CFG_DDR2_MODE_2;
-	ddr->sdram_mode_cntl = CFG_DDR2_MODE_CTL;
-	ddr->sdram_interval = CFG_DDR2_INTERVAL;
-	ddr->sdram_data_init = CFG_DDR2_DATA_INIT;
-	ddr->sdram_clk_cntl = CFG_DDR2_CLK_CTRL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR2_CS0_BNDS;
+	ddr->cs1_bnds = CONFIG_SYS_DDR2_CS1_BNDS;
+	ddr->cs2_bnds = CONFIG_SYS_DDR2_CS2_BNDS;
+	ddr->cs3_bnds = CONFIG_SYS_DDR2_CS3_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR2_CS0_CONFIG;
+	ddr->cs1_config = CONFIG_SYS_DDR2_CS1_CONFIG;
+	ddr->cs2_config = CONFIG_SYS_DDR2_CS2_CONFIG;
+	ddr->cs3_config = CONFIG_SYS_DDR2_CS3_CONFIG;
+	ddr->timing_cfg_3 = CONFIG_SYS_DDR2_EXT_REFRESH;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR2_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR2_TIMING_2;
+	ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1A;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR2_CFG_2;
+	ddr->sdram_mode_1 = CONFIG_SYS_DDR2_MODE_1;
+	ddr->sdram_mode_2 = CONFIG_SYS_DDR2_MODE_2;
+	ddr->sdram_mode_cntl = CONFIG_SYS_DDR2_MODE_CTL;
+	ddr->sdram_interval = CONFIG_SYS_DDR2_INTERVAL;
+	ddr->sdram_data_init = CONFIG_SYS_DDR2_DATA_INIT;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR2_CLK_CTRL;
 
 	asm ("sync;isync");
 
 	udelay (500);
 
-	ddr->sdram_cfg_1 = CFG_DDR2_CFG_1B;
+	ddr->sdram_cfg_1 = CONFIG_SYS_DDR2_CFG_1B;
 	asm ("sync; isync");
 
 	udelay (500);
 #endif
-	return CFG_SDRAM_SIZE * 1024 * 1024;
+	return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
 }
 #endif				/* !defined(CONFIG_SPD_EEPROM) */
 
@@ -222,7 +222,7 @@
 
 void pci_init_board(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_CCSRBAR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
 	volatile ccsr_gur_t *gur = &immap->im_gur;
 	uint devdisr = gur->devdisr;
 	uint io_sel = (gur->pordevsr & MPC8641_PORDEVSR_IO_SEL)
@@ -230,7 +230,7 @@
 
 #ifdef CONFIG_PCI1
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 #ifdef DEBUG
@@ -252,23 +252,23 @@
 
 		/* inbound */
 		pci_set_region(hose->regions + 0,
-			       CFG_PCI_MEMORY_BUS,
-			       CFG_PCI_MEMORY_PHYS,
-			       CFG_PCI_MEMORY_SIZE,
+			       CONFIG_SYS_PCI_MEMORY_BUS,
+			       CONFIG_SYS_PCI_MEMORY_PHYS,
+			       CONFIG_SYS_PCI_MEMORY_SIZE,
 			       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region(hose->regions + 1,
-			       CFG_PCI1_MEM_BASE,
-			       CFG_PCI1_MEM_PHYS,
-			       CFG_PCI1_MEM_SIZE,
+			       CONFIG_SYS_PCI1_MEM_BASE,
+			       CONFIG_SYS_PCI1_MEM_PHYS,
+			       CONFIG_SYS_PCI1_MEM_SIZE,
 			       PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region(hose->regions + 2,
-			       CFG_PCI1_IO_BASE,
-			       CFG_PCI1_IO_PHYS,
-			       CFG_PCI1_IO_SIZE,
+			       CONFIG_SYS_PCI1_IO_BASE,
+			       CONFIG_SYS_PCI1_IO_PHYS,
+			       CONFIG_SYS_PCI1_IO_SIZE,
 			       PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -292,30 +292,30 @@
 
 #ifdef CONFIG_PCI2
 {
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI2_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI2_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci2_hose;
 
 
 	/* inbound */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI_MEMORY_BUS,
-		       CFG_PCI_MEMORY_PHYS,
-		       CFG_PCI_MEMORY_SIZE,
+		       CONFIG_SYS_PCI_MEMORY_BUS,
+		       CONFIG_SYS_PCI_MEMORY_PHYS,
+		       CONFIG_SYS_PCI_MEMORY_SIZE,
 		       PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 	/* outbound memory */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI2_MEM_BASE,
-		       CFG_PCI2_MEM_PHYS,
-		       CFG_PCI2_MEM_SIZE,
+		       CONFIG_SYS_PCI2_MEM_BASE,
+		       CONFIG_SYS_PCI2_MEM_PHYS,
+		       CONFIG_SYS_PCI2_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* outbound io */
 	pci_set_region(hose->regions + 2,
-		       CFG_PCI2_IO_BASE,
-		       CFG_PCI2_IO_PHYS,
-		       CFG_PCI2_IO_SIZE,
+		       CONFIG_SYS_PCI2_IO_BASE,
+		       CONFIG_SYS_PCI2_IO_PHYS,
+		       CONFIG_SYS_PCI2_IO_SIZE,
 		       PCI_REGION_IO);
 
 	hose->region_count = 3;
diff --git a/board/sc3/sc3nand.c b/board/sc3/sc3nand.c
index 45eff28..62b40f1 100644
--- a/board/sc3/sc3nand.c
+++ b/board/sc3/sc3nand.c
@@ -77,7 +77,7 @@
 {
 	nand->ecc.mode = NAND_ECC_SOFT;
 
-	sc3_io_base = (void *) CFG_NAND_BASE;
+	sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
 	/* Set address of NAND IO lines (Using Linear Data Access Region) */
 	nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
 	nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c
index 493d51a..dcb8c57 100644
--- a/board/sc520_cdp/flash.c
+++ b/board/sc520_cdp/flash.c
@@ -222,7 +222,7 @@
 		ulong flashbase = 0;
 		int sectsize = 0;
 
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		switch (i) {
 		case 0:
 			flashbase = SC520_FLASH_BANK0_BASE;
@@ -370,7 +370,7 @@
 	while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
 
 		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+		if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			*(volatile u32*)(addr) = 0xf0f0f0f0;
 			return 1;
 		}
@@ -493,7 +493,7 @@
 	/* data polling for D7 */
 	while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
 		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-		if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+		if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			addr2[0] = 0xf0f0f0f0;
 			return 1;
 		}
diff --git a/board/sc520_cdp/flash_old.c b/board/sc520_cdp/flash_old.c
index b68626e..9491ca2 100644
--- a/board/sc520_cdp/flash_old.c
+++ b/board/sc520_cdp/flash_old.c
@@ -89,7 +89,7 @@
 			flash_info[i].sector_count = 0;
 			sectsize=0;
 		}
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		switch (i) {
 		case 0:
 			flashbase = SC520_FLASH_BANK0_BASE;
@@ -240,7 +240,7 @@
 				result = readl(addr);
 
 				/* check timeout */
-				if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer(0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					writel(CMD_READ_ARRAY, addr + 1);
 					chip1 = TMO;
 					break;
@@ -342,7 +342,7 @@
 		result = readl(addr);
 
 		/* check timeout */
-		if (get_timer(0) > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer(0) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip1 = ERR | TMO;
 			break;
 		}
diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 99debde..779f957 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c
@@ -87,7 +87,7 @@
 	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
 	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
 
-	if (CFG_USE_SIO_UART) {
+	if (CONFIG_SYS_USE_SIO_UART) {
 		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
 		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
 		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
@@ -122,10 +122,10 @@
 	 * when we need one (a board with more pci interrupt pins
 	 * would use a larger table */
 	static int irq_list[] = {
-		CFG_FIRST_PCI_IRQ,
-		CFG_SECOND_PCI_IRQ,
-		CFG_THIRD_PCI_IRQ,
-		CFG_FORTH_PCI_IRQ
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
 	};
 	static int next_irq_index=0;
 
@@ -279,7 +279,7 @@
 
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
-	if (CFG_USE_SIO_UART) {
+	if (CONFIG_SYS_USE_SIO_UART) {
 		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
 		setup_ali_sio(1);
 	} else {
diff --git a/board/sc520_spunk/flash.c b/board/sc520_spunk/flash.c
index 609cc42..d702046 100644
--- a/board/sc520_spunk/flash.c
+++ b/board/sc520_spunk/flash.c
@@ -228,7 +228,7 @@
 		ulong flashbase = 0;
 		int sectsize = 0;
 
-		memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		switch (i) {
 		case 0:
 			flashbase = SC520_FLASH_BANK0_BASE;
@@ -419,7 +419,7 @@
 	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
 
 		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+		if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			*(volatile u16*)(addr) = 0x00f0;
 			return 1;
 		}
@@ -467,7 +467,7 @@
 	elapsed = 0;
 	while (((*(volatile u16*)(addr + sector)) & 0x0080) != 0x0080) {
 		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-		if (elapsed > ((CFG_FLASH_ERASE_TOUT/CFG_HZ) * 1000)) {
+		if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			*(volatile u16*)(addr + sector) = 0x00B0;  /* suspend erase      */
 			*(volatile u16*)(addr + sector) = 0x00FF;  /* reset to read mode */
 			return 1;
@@ -602,7 +602,7 @@
 		/* data polling for D7 */
 		while ((dest2[i] & 0x0080) != (data2[i] & 0x0080)) {
 			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+			if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 				addr2[i] = 0x00f0;
 				return 1;
 			}
@@ -639,7 +639,7 @@
 		/* data polling for D7 */
 		while ((*(volatile u16*)dest & 0x0080) != 0x0080) {
 			elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
-			if (elapsed > ((CFG_FLASH_WRITE_TOUT/CFG_HZ) * 1000)) {
+			if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 				*(volatile u16*)dest = 0x00ff;
 				return 1;
 			}
diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index 0b11caa..d3bd869 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c
@@ -105,10 +105,10 @@
 	 * when we need one (a board with more pci interrupt pins
 	 * would use a larger table */
 	static int irq_list[] = {
-		CFG_FIRST_PCI_IRQ,
-		CFG_SECOND_PCI_IRQ,
-		CFG_THIRD_PCI_IRQ,
-		CFG_FORTH_PCI_IRQ
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
 	};
 	static int next_irq_index=0;
 
diff --git a/board/scb9328/flash.c b/board/scb9328/flash.c
index 536725a..c6f94ae 100644
--- a/board/scb9328/flash.c
+++ b/board/scb9328/flash.c
@@ -82,7 +82,7 @@
 #endif
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static FLASH_BUS_RET flash_status_reg (void)
 {
@@ -109,7 +109,7 @@
 	return ok;
 }
 
-#if ( CFG_MAX_FLASH_BANKS != 1 )
+#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
 #  error "SCB9328 platform has only one flash bank!"
 #endif
 
@@ -120,11 +120,11 @@
 	unsigned long address = SCB9328_FLASH_BASE;
 
 	flash_info[0].size = SCB9328_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
-	for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
 		flash_info[0].start[i] = address;
 #ifdef SCB9328_FLASH_UNLOCK
 		/* Some devices are hw locked after start. */
@@ -137,8 +137,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-				   CFG_FLASH_BASE,
-				   CFG_FLASH_BASE + monitor_flash_len - 1,
+				   CONFIG_SYS_FLASH_BASE,
+				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 				   &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -209,7 +209,7 @@
 
 		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
 		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
 			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
 			printf ("ok.\n");
 		} else {
@@ -257,7 +257,7 @@
 	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
 	*address = data;
 
-	if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
 		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
 		rc = ERR_TIMOUT;
 		printf ("timeout! Aborting...\n");
diff --git a/board/scb9328/lowlevel_init.S b/board/scb9328/lowlevel_init.S
index ba3b6d2..8e6a49e 100644
--- a/board/scb9328/lowlevel_init.S
+++ b/board/scb9328/lowlevel_init.S
@@ -29,13 +29,13 @@
 
 /* Change PERCLK1DIV to 14 ie 14+1 */
 	ldr		r0,	=PCDR
-	ldr		r1,	=CFG_PCDR_VAL
+	ldr		r1,	=CONFIG_SYS_PCDR_VAL
 	str		r1,   [r0]
 
 /* set MCU PLL Control Register 0 */
 
 	ldr		r0,	=MPCTL0
-	ldr		r1,	=CFG_MPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_MPCTL0_VAL
 	str		r1,   [r0]
 
 /* set mpll restart bit */
@@ -57,7 +57,7 @@
 /* set System PLL Control Register 0 */
 
 	ldr		r0,	=SPCTL0
-	ldr		r1,	=CFG_SPCTL0_VAL
+	ldr		r1,	=CONFIG_SYS_SPCTL0_VAL
 	str		r1,   [r0]
 
 /* set spll restart bit */
@@ -77,7 +77,7 @@
 	bne		1b
 
 	ldr		r0,   =CSCR
-	ldr		r1,   =CFG_CSCR_VAL
+	ldr		r1,   =CONFIG_SYS_CSCR_VAL
 	str		r1,   [r0]
 
 /* I have now read the ARM920 DataSheet back-to-Back, and have stumbled upon
@@ -102,65 +102,65 @@
 	MCR p15,0,r0,c1,c0,0
 
 	ldr		r0,	=GPR(0)
-	ldr		r1,	=CFG_GPR_A_VAL
+	ldr		r1,	=CONFIG_SYS_GPR_A_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GIUS(0)
-	ldr		r1,	=CFG_GIUS_A_VAL
+	ldr		r1,	=CONFIG_SYS_GIUS_A_VAL
 	str		r1,   [r0]
 
 /* CS3 becomes CS3 by clearing reset default bit 1 in FMCR */
 
 	ldr		r0,	=FMCR
-	ldr		r1,	=CFG_FMCR_VAL
+	ldr		r1,	=CONFIG_SYS_FMCR_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0U
-	ldr		r1,	=CFG_CS0U_VAL
+	ldr		r1,	=CONFIG_SYS_CS0U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS0L
-	ldr		r1,	=CFG_CS0L_VAL
+	ldr		r1,	=CONFIG_SYS_CS0L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1U
-	ldr		r1,	=CFG_CS1U_VAL
+	ldr		r1,	=CONFIG_SYS_CS1U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS1L
-	ldr		r1,	=CFG_CS1L_VAL
+	ldr		r1,	=CONFIG_SYS_CS1L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS2U
-	ldr		r1,	=CFG_CS2U_VAL
+	ldr		r1,	=CONFIG_SYS_CS2U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS2L
-	ldr		r1,	=CFG_CS2L_VAL
+	ldr		r1,	=CONFIG_SYS_CS2L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS3U
-	ldr		r1,	=CFG_CS3U_VAL
+	ldr		r1,	=CONFIG_SYS_CS3U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS3L
-	ldr		r1,	=CFG_CS3L_VAL
+	ldr		r1,	=CONFIG_SYS_CS3L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4U
-	ldr		r1,	=CFG_CS4U_VAL
+	ldr		r1,	=CONFIG_SYS_CS4U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS4L
-	ldr		r1,	=CFG_CS4L_VAL
+	ldr		r1,	=CONFIG_SYS_CS4L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5U
-	ldr		r1,	=CFG_CS5U_VAL
+	ldr		r1,	=CONFIG_SYS_CS5U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=CS5L
-	ldr		r1,	=CFG_CS5L_VAL
+	ldr		r1,	=CONFIG_SYS_CS5L_VAL
 	str		r1,   [r0]
 
 /* SDRAM Setup */
diff --git a/board/sh7763rdp/sh7763rdp.c b/board/sh7763rdp/sh7763rdp.c
index 92ac7b7..88bab70 100644
--- a/board/sh7763rdp/sh7763rdp.c
+++ b/board/sh7763rdp/sh7763rdp.c
@@ -66,9 +66,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/sh7785lcr/sh7785lcr.c b/board/sh7785lcr/sh7785lcr.c
index 66b21f8..786c758 100644
--- a/board/sh7785lcr/sh7785lcr.c
+++ b/board/sh7785lcr/sh7785lcr.c
@@ -38,9 +38,9 @@
 {
 	DECLARE_GLOBAL_DATA_PTR;
 
-	gd->bd->bi_memstart = CFG_SDRAM_BASE;
-	gd->bd->bi_memsize = CFG_SDRAM_SIZE;
-	printf("DRAM:  %dMB\n", CFG_SDRAM_SIZE / (1024 * 1024));
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	printf("DRAM:  %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024));
 	return 0;
 }
 
diff --git a/board/shannon/flash.c b/board/shannon/flash.c
index 7d6eca8..0455afa 100644
--- a/board/shannon/flash.c
+++ b/board/shannon/flash.c
@@ -30,7 +30,7 @@
 #define FLASH_BANK_SIZE 0x400000	/* 4 MB */
 #define MAIN_SECT_SIZE  0x20000		/* 128 KB */
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x00F000F0
@@ -41,8 +41,8 @@
 #define CMD_PROGRAM		0x00A000A0
 #define CMD_UNLOCK_BYPASS	0x00200020
 
-#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
-#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2)))
 
 #define BIT_ERASE_DONE		0x00800080
 #define BIT_RDY_MASK		0x00800080
@@ -61,15 +61,15 @@
     int i, j;
     ulong size = 0;
 
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; i++)
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++)
     {
 	ulong flashbase = 0;
 	flash_info[i].flash_id =
 	  (AMD_MANUFACT & FLASH_VENDMASK) |
 	  (AMD_ID_LV160B & FLASH_TYPEMASK);
 	flash_info[i].size = FLASH_BANK_SIZE;
-	flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-	memset(flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+	flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+	memset(flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 	if (i == 0)
 	  flashbase = PHYS_FLASH_1;
 	else
@@ -112,19 +112,19 @@
 #ifdef CONFIG_INFERNO
     /* first one, 0x00000 to 0x07fff */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE + 0x00000,
-		  CFG_FLASH_BASE + 0x08000 - 1,
+		  CONFIG_SYS_FLASH_BASE + 0x00000,
+		  CONFIG_SYS_FLASH_BASE + 0x08000 - 1,
 		  &flash_info[0]);
 
     /* third to 10th, 0x0c000 - 0xdffff */
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE + 0x0c000,
-		  CFG_FLASH_BASE + 0xe0000 - 1,
+		  CONFIG_SYS_FLASH_BASE + 0x0c000,
+		  CONFIG_SYS_FLASH_BASE + 0xe0000 - 1,
 		  &flash_info[0]);
 #else
     flash_protect(FLAG_PROTECT_SET,
-		  CFG_FLASH_BASE,
-		  CFG_FLASH_BASE + monitor_flash_len - 1,
+		  CONFIG_SYS_FLASH_BASE,
+		  CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		  &flash_info[0]);
 
     flash_protect(FLAG_PROTECT_SET,
@@ -253,7 +253,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+		if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
 		{
 		    MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 		    chip1 = TMO;
@@ -358,7 +358,7 @@
 	result = *addr;
 
 	/* check timeout */
-	if (get_timer_masked() > CFG_FLASH_ERASE_TOUT)
+	if (get_timer_masked() > CONFIG_SYS_FLASH_ERASE_TOUT)
 	{
 	    chip1 = ERR | TMO;
 	    break;
diff --git a/board/siemens/CCM/ccm.c b/board/siemens/CCM/ccm.c
index d653763..8053da4 100644
--- a/board/siemens/CCM/ccm.c
+++ b/board/siemens/CCM/ccm.c
@@ -133,7 +133,7 @@
 int power_on_reset(void)
 {
     /* Test Reset Status Register */
-    return ((volatile immap_t *)CFG_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
+    return ((volatile immap_t *)CONFIG_SYS_IMMR)->im_clkrst.car_rsr & RSR_CSRS ? 0:1;
 }
 
 #define PB_LED_GREEN	0x10000		/* red LED is on PB.15 */
@@ -142,7 +142,7 @@
 
 static void init_leds (void)
 {
-    volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
 
     immap->im_cpm.cp_pbpar &= ~PB_LEDS;
     immap->im_cpm.cp_pbodr &= ~PB_LEDS;
@@ -157,7 +157,7 @@
 
 phys_size_t initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
     long int size8, size9;
     long int size = 0;
@@ -171,7 +171,7 @@
      * with two SDRAM banks or four cycles every 31.2 us with one
      * bank. It will be adjusted after memory sizing.
      */
-    memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+    memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
     memctl->memc_mar  = 0x00000088;
 
@@ -180,10 +180,10 @@
      * preliminary addresses - these have to be modified after the
      * SDRAM size has been determined.
      */
-    memctl->memc_or2 = CFG_OR2_PRELIM;
-    memctl->memc_br2 = CFG_BR2_PRELIM;
+    memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+    memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-    memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
+    memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE)); /* no refresh yet */
 
     udelay(200);
 
@@ -203,21 +203,21 @@
      *
      * try 8 column mode
      */
-    size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+    size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 
     udelay (1000);
 
     /*
      * try 9 column mode
      */
-    size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+    size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 
     if (size8 < size9) {		/* leave configuration at 9 columns	*/
 	size = size9;
 /*	debug ("SDRAM in 9 column mode: %ld MB\n", size >> 20);	*/
     } else {				/* back to 8 columns			*/
 	size = size8;
-	memctl->memc_mamr = CFG_MAMR_8COL;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 	udelay(500);
 /*	debug ("SDRAM in 8 column mode: %ld MB\n", size >> 20);	*/
     }
@@ -230,7 +230,7 @@
      */
     if (size < 0x02000000) {
 	/* reduce to 15.6 us (62.4 us / quad) */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 	udelay(1000);
     }
 
@@ -238,13 +238,13 @@
      * Final mapping
      */
 
-    memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-    memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+    memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+    memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 
     /* adjust refresh rate depending on SDRAM type, one bank */
     reg = memctl->memc_mptpr;
-    reg >>= 1;	/* reduce to CFG_MPTPR_1BK_8K / _4K */
+    reg >>= 1;	/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
     memctl->memc_mptpr = reg;
 
     can_driver_enable ();
@@ -263,7 +263,7 @@
  */
 void can_driver_enable (void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Initialize MBMR */
@@ -302,13 +302,13 @@
     memctl->memc_mcr = 0x011C | UPMB;
 
     /* Initialize OR3 / BR3 for CAN Bus Controller */
-    memctl->memc_or3 = CFG_OR3_CAN;
-    memctl->memc_br3 = CFG_BR3_CAN;
+    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 }
 
 void can_driver_disable (void)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     /* Reset OR3 / BR3 to disable  CAN Bus Controller */
@@ -331,7 +331,7 @@
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
 
     memctl->memc_mamr = mamr_value;
@@ -341,24 +341,24 @@
 
 /* ------------------------------------------------------------------------- */
 
-#define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
 
-#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN)
+#define ETH_ALL_BITS	(ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN)
 
 void	reset_phy(void)
 {
-	immap_t *immr = (immap_t *)CFG_IMMR;
+	immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	ulong value;
 
 	/* Configure all needed port pins for GPIO */
-#ifdef CFG_ETH_MDDIS_VALUE
-	immr->im_ioport.iop_padat |=   CFG_PA_ETH_MDDIS;
+#ifdef CONFIG_SYS_ETH_MDDIS_VALUE
+	immr->im_ioport.iop_padat |=   CONFIG_SYS_PA_ETH_MDDIS;
 #else
-	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* Set low */
+	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET);	/* Set low */
 #endif
-	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* GPIO */
-	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET);	/* active output */
-	immr->im_ioport.iop_padir |=   CFG_PA_ETH_MDDIS | CFG_PA_ETH_RESET;	/* output */
+	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET);	/* GPIO */
+	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET);	/* active output */
+	immr->im_ioport.iop_padir |=   CONFIG_SYS_PA_ETH_MDDIS | CONFIG_SYS_PA_ETH_RESET;	/* output */
 
 	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
 	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */
@@ -366,23 +366,23 @@
 	value  = immr->im_cpm.cp_pbdat;
 
 	/* Assert Powerdown and Reset signals */
-	value |=  CFG_PB_ETH_POWERDOWN;
+	value |=  CONFIG_SYS_PB_ETH_POWERDOWN;
 
 	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
-#ifdef CFG_ETH_CFG1_VALUE
-	value |=   CFG_PB_ETH_CFG1;
+#ifdef CONFIG_SYS_ETH_CFG1_VALUE
+	value |=   CONFIG_SYS_PB_ETH_CFG1;
 #else
-	value &= ~(CFG_PB_ETH_CFG1);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG1);
 #endif
-#ifdef CFG_ETH_CFG2_VALUE
-	value |=   CFG_PB_ETH_CFG2;
+#ifdef CONFIG_SYS_ETH_CFG2_VALUE
+	value |=   CONFIG_SYS_PB_ETH_CFG2;
 #else
-	value &= ~(CFG_PB_ETH_CFG2);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG2);
 #endif
-#ifdef CFG_ETH_CFG3_VALUE
-	value |=   CFG_PB_ETH_CFG3;
+#ifdef CONFIG_SYS_ETH_CFG3_VALUE
+	value |=   CONFIG_SYS_PB_ETH_CFG3;
 #else
-	value &= ~(CFG_PB_ETH_CFG3);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG3);
 #endif
 
 	/* Drive output signals to initial state */
@@ -391,11 +391,11 @@
 	udelay (10000);
 
 	/* De-assert Ethernet Powerdown */
-	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN); /* Enable PHY power */
+	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN); /* Enable PHY power */
 	udelay (10000);
 
 	/* de-assert RESET signal of PHY */
-	immr->im_ioport.iop_padat |= CFG_PA_ETH_RESET;
+	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_RESET;
 	udelay (1000);
 }
 
diff --git a/board/siemens/CCM/flash.c b/board/siemens/CCM/flash.c
index 9c32785..ad1ed79 100644
--- a/board/siemens/CCM/flash.c
+++ b/board/siemens/CCM/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -75,38 +75,38 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V;
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 	} else {
@@ -419,7 +419,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -542,7 +542,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/siemens/CCM/fpga_ccm.c b/board/siemens/CCM/fpga_ccm.c
index 11b97bc..50b08ab 100644
--- a/board/siemens/CCM/fpga_ccm.c
+++ b/board/siemens/CCM/fpga_ccm.c
@@ -31,7 +31,7 @@
 
 fpga_t fpga_list[] = {
     { "PUMA" , PUMA_CONF_BASE ,
-      CFG_PC_PUMA_INIT , CFG_PC_PUMA_PROG , CFG_PC_PUMA_DONE  }
+      CONFIG_SYS_PC_PUMA_INIT , CONFIG_SYS_PC_PUMA_PROG , CONFIG_SYS_PC_PUMA_DONE  }
 };
 int fpga_count = sizeof(fpga_list) / sizeof(fpga_t);
 
@@ -90,7 +90,7 @@
 
 ulong fpga_control (fpga_t* fpga, int cmd)
 {
-    volatile immap_t     *immr  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immr  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immr->im_memctl;
 
     switch (cmd) {
diff --git a/board/siemens/IAD210/IAD210.c b/board/siemens/IAD210/IAD210.c
index 9c0ff02..e9e7f84 100644
--- a/board/siemens/IAD210/IAD210.c
+++ b/board/siemens/IAD210/IAD210.c
@@ -102,7 +102,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile iop8xx_t *iop = &immap->im_ioport;
 	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
@@ -117,7 +117,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	memctl->memc_mar = 0x00000088;
 
@@ -126,10 +126,10 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -155,20 +155,20 @@
 	 * Check Bank 0 Memory Size for re-configuration
 	 *
 	 */
-	size = dram_size (CFG_MAMR, (long *) SDRAM_BASE_PRELIM,
+	size = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE_PRELIM,
 			  SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
 
-	memctl->memc_mamr = CFG_MAMR;
+	memctl->memc_mamr = CONFIG_SYS_MAMR;
 	udelay (1000);
 
 	/*
 	 * Final mapping
 	 */
-	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CFG_OR2_PRELIM;
-	memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
+	memctl->memc_or2 = ((-size) & 0xFFFF0000) | CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V);
 
 	udelay (10000);
 
@@ -195,7 +195,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -219,7 +219,7 @@
 
 void board_ether_init (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *iop = &immap->im_ioport;
 	volatile fec_t *fecp = &immap->im_cpm.cp_fec;
 
@@ -230,7 +230,7 @@
 
 int board_early_init_f (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	volatile iop8xx_t *iop = &immap->im_ioport;
@@ -261,7 +261,7 @@
 void board_get_enetaddr (uchar * addr)
 {
 	int i;
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	unsigned int rccrtmp;
 
diff --git a/board/siemens/IAD210/atm.c b/board/siemens/IAD210/atm.c
index 1b27f33..d1b75bc 100644
--- a/board/siemens/IAD210/atm.c
+++ b/board/siemens/IAD210/atm.c
@@ -57,7 +57,7 @@
  ****************************************************************************/
 int atmLoad()
 {
-  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
   volatile iop8xx_t      *iop    = &immap->im_ioport;
 
@@ -91,7 +91,7 @@
  ****************************************************************************/
 void atmUnload()
 {
-  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile cpmtimer8xx_t *timers = &immap->im_cpmtimer;
   volatile iop8xx_t      *iop    = &immap->im_ioport;
 
@@ -141,11 +141,11 @@
 int atmMemInit()
 {
   int i;
-  unsigned immr = CFG_IMMR;
+  unsigned immr = CONFIG_SYS_IMMR;
   int total_num_rbd = 0;
   int total_num_tbd = 0;
 
-  memset((char *)CFG_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
+  memset((char *)CONFIG_SYS_IMMR + 0x2000 + ATM_DPRAM_BEGIN, 0x00, ATM_DPRAM_SIZE);
 
   g_atm.csram_size = NUM_INT_ENTRIES * SIZE_OF_INT_ENTRY;
 
@@ -226,11 +226,11 @@
 void atmApcInit()
 {
   int i;
-  /* unsigned immr = CFG_IMMR; */
-  uint16 * mphypt_ptr = MPHYPT_PTR(CFG_IMMR);
-  struct apc_params_t * apcp_ptr = APCP_PTR(CFG_IMMR);
-  uint16 * apct_prio1_ptr = APCT1_PTR(CFG_IMMR);
-  uint16 * tq_ptr = TQ_PTR(CFG_IMMR);
+  /* unsigned immr = CONFIG_SYS_IMMR; */
+  uint16 * mphypt_ptr = MPHYPT_PTR(CONFIG_SYS_IMMR);
+  struct apc_params_t * apcp_ptr = APCP_PTR(CONFIG_SYS_IMMR);
+  uint16 * apct_prio1_ptr = APCT1_PTR(CONFIG_SYS_IMMR);
+  uint16 * tq_ptr = TQ_PTR(CONFIG_SYS_IMMR);
   /***************************************************/
   /* Initialize MPHY Pointing Table (only one entry) */
   /***************************************************/
@@ -290,7 +290,7 @@
  ****************************************************************************/
 void atmAmtInit()
 {
-  unsigned immr = CFG_IMMR;
+  unsigned immr = CONFIG_SYS_IMMR;
 
   g_atm.am_top = AM_PTR(immr);
   g_atm.ap_top = AP_PTR(immr);
@@ -315,7 +315,7 @@
  ****************************************************************************/
 void atmCpmInit()
 {
-  unsigned immr = CFG_IMMR;
+  unsigned immr = CONFIG_SYS_IMMR;
 
   memset((char *)immr + 0x3F00, 0x00, 0xC0);
 
@@ -551,7 +551,7 @@
  ****************************************************************************/
 void atmUtpInit()
 {
-  volatile immap_t       *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t       *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile iop8xx_t      *iop    = &immap->im_ioport;
   volatile car8xx_t	 *car    = &immap->im_clkrst;
   volatile cpm8xx_t	 *cpm    = &immap->im_cpm;
diff --git a/board/siemens/IAD210/atm.h b/board/siemens/IAD210/atm.h
index 71b0497..cd5b45e 100644
--- a/board/siemens/IAD210/atm.h
+++ b/board/siemens/IAD210/atm.h
@@ -6,9 +6,9 @@
 typedef volatile unsigned int vuint32;
 
 
-#define DPRAM_ATM CFG_IMMR + 0x3000
+#define DPRAM_ATM CONFIG_SYS_IMMR + 0x3000
 
-#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CFG_IMMR - 0x2000)
+#define ATM_DPRAM_BEGIN  (DPRAM_ATM - CONFIG_SYS_IMMR - 0x2000)
 #define NUM_CONNECTIONS  1
 #define SAR_RXB_SIZE     1584
 #define AM_HMASK         0x0FFFFFF0
diff --git a/board/siemens/IAD210/flash.c b/board/siemens/IAD210/flash.c
index 110858d..c262e0f 100644
--- a/board/siemens/IAD210/flash.c
+++ b/board/siemens/IAD210/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -38,13 +38,13 @@
 
 unsigned long flash_init (void)
 {
-  volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+  volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
   volatile memctl8xx_t *memctl = &immap->im_memctl;
   unsigned long size;
   int i;
 
   /* Init: no FLASHes known */
-  for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+  for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
     flash_info[i].flash_id = FLASH_UNKNOWN;
   }
 
@@ -59,13 +59,13 @@
 
 
   /* Remap FLASH according to real size */
-  memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size & 0xFFFF8000);
-  memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+  memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size & 0xFFFF8000);
+  memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
   /* Re-do sizing to get full correct info */
-  size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+  size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-  flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+  flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
   flash_info[0].size = size;
 
@@ -368,7 +368,7 @@
   last  = start;
   addr = (vu_long*)(info->start[l_sect]);
   while ((addr[0] & 0x00800080) != 0x00800080) {
-    if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+    if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
       printf ("Timeout\n");
       return 1;
     }
@@ -491,7 +491,7 @@
   /* data polling for D7 */
   start = get_timer (0);
   while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-    if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+    if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
       return (1);
     }
   }
diff --git a/board/siemens/SCM/config.mk b/board/siemens/SCM/config.mk
index 855ae38..5d0898b 100644
--- a/board/siemens/SCM/config.mk
+++ b/board/siemens/SCM/config.mk
@@ -25,7 +25,7 @@
 # Siemens SCM boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_SCM.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_SCM.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/siemens/SCM/flash.c b/board/siemens/SCM/flash.c
index 500af92..4a6d538 100644
--- a/board/siemens/SCM/flash.c
+++ b/board/siemens/SCM/flash.c
@@ -31,7 +31,7 @@
 #define V_BYTE(a)	(*(volatile unsigned char *)( a ))
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -185,13 +185,13 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				size_b0, size_b0 >> 20);
@@ -201,10 +201,10 @@
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
@@ -364,7 +364,7 @@
 	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
 	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
 	{
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -480,7 +480,7 @@
 	start = get_timer (0);
 	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
 		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/siemens/SCM/fpga_scm.c b/board/siemens/SCM/fpga_scm.c
index 661bf66..acd9c15 100644
--- a/board/siemens/SCM/fpga_scm.c
+++ b/board/siemens/SCM/fpga_scm.c
@@ -28,18 +28,18 @@
 #include "../common/fpga.h"
 
 fpga_t fpga_list[] = {
-	{"FIOX", CFG_FIOX_BASE,
-	 CFG_PD_FIOX_INIT, CFG_PD_FIOX_PROG, CFG_PD_FIOX_DONE}
+	{"FIOX", CONFIG_SYS_FIOX_BASE,
+	 CONFIG_SYS_PD_FIOX_INIT, CONFIG_SYS_PD_FIOX_PROG, CONFIG_SYS_PD_FIOX_DONE}
 	,
-	{"FDOHM", CFG_FDOHM_BASE,
-	 CFG_PD_FDOHM_INIT, CFG_PD_FDOHM_PROG, CFG_PD_FDOHM_DONE}
+	{"FDOHM", CONFIG_SYS_FDOHM_BASE,
+	 CONFIG_SYS_PD_FDOHM_INIT, CONFIG_SYS_PD_FDOHM_PROG, CONFIG_SYS_PD_FDOHM_DONE}
 };
 int fpga_count = sizeof (fpga_list) / sizeof (fpga_t);
 
 
 ulong fpga_control (fpga_t * fpga, int cmd)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	switch (cmd) {
 	case FPGA_INIT_IS_HIGH:
@@ -74,11 +74,11 @@
 		break;
 
 	case FPGA_GET_ID:
-		if (fpga->conf_base == CFG_FIOX_BASE) {
+		if (fpga->conf_base == CONFIG_SYS_FIOX_BASE) {
 			ulong ver =
 				*(volatile ulong *) (fpga->conf_base + 0x10);
 			return ((ver >> 10) & 0xf) + ((ver >> 2) & 0xf0);
-		} else if (fpga->conf_base == CFG_FDOHM_BASE) {
+		} else if (fpga->conf_base == CONFIG_SYS_FDOHM_BASE) {
 			return (*(volatile ushort *) fpga->conf_base) & 0xff;
 		} else {
 			return *(volatile ulong *) fpga->conf_base;
diff --git a/board/siemens/SCM/scm.c b/board/siemens/SCM/scm.c
index 6a9dd25..e0611fe 100644
--- a/board/siemens/SCM/scm.c
+++ b/board/siemens/SCM/scm.c
@@ -249,7 +249,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
@@ -274,7 +274,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -285,7 +285,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -308,10 +308,10 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long size8, size9;
 #endif
 	long psize, lsize;
@@ -319,8 +319,8 @@
 	psize = 16 * 1024 * 1024;
 	lsize = 0;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 #if 0							/* Just for debugging */
 #define	prt_br_or(brX,orX) do {				\
@@ -338,37 +338,37 @@
 	prt_br_or (br3, or3);
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-					  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
-					  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL - %ld MB, ", psize >> 20);
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-						  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL - %ld MB, ", psize >> 20);
 	}
 
 	/* Local SDRAM setup:
 	 */
-#ifdef CFG_INIT_LOCAL_SDRAM
-	memctl->memc_lsrt = CFG_LSRT;
-	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
 					  (uchar *) SDRAM_BASE2_PRELIM);
-	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
 					  (uchar *) SDRAM_BASE2_PRELIM);
 
 	if (size8 < size9) {
 		lsize = size9;
 		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
 	} else {
-		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
 						  (uchar *) SDRAM_BASE2_PRELIM);
 		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
 	}
@@ -377,11 +377,11 @@
 	/* Set up BR2 so that the local SDRAM goes
 	 * right after the 60x SDRAM
 	 */
-	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
-			(CFG_SDRAM_BASE + psize);
+	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CONFIG_SYS_SDRAM_BASE + psize);
 #endif
-#endif /* CFG_INIT_LOCAL_SDRAM */
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -394,17 +394,17 @@
 
 static void config_scoh_cs (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immr->im_memctl;
-	volatile can_reg_t *can = (volatile can_reg_t *) CFG_CAN0_BASE;
+	volatile can_reg_t *can = (volatile can_reg_t *) CONFIG_SYS_CAN0_BASE;
 	volatile uint tmp, i;
 
 	/* Initialize OR3 / BR3 for CAN Bus Controller 0 */
-	memctl->memc_or3 = CFG_CAN0_OR3;
-	memctl->memc_br3 = CFG_CAN0_BR3;
+	memctl->memc_or3 = CONFIG_SYS_CAN0_OR3;
+	memctl->memc_br3 = CONFIG_SYS_CAN0_BR3;
 	/* Initialize OR4 / BR4 for CAN Bus Controller 1 */
-	memctl->memc_or4 = CFG_CAN1_OR4;
-	memctl->memc_br4 = CFG_CAN1_BR4;
+	memctl->memc_or4 = CONFIG_SYS_CAN1_OR4;
+	memctl->memc_br4 = CONFIG_SYS_CAN1_BR4;
 
 	/* Initialize MAMR to write in the array at address 0x0 */
 	memctl->memc_mamr = 0x00 | MxMR_OP_WARR | MxMR_GPL_x4DIS;
@@ -487,19 +487,19 @@
 
 
 	/* Initialize OR5 / BR5 for the extended EEPROM Bank0 */
-	memctl->memc_or5 = CFG_EXTPROM_OR5;
-	memctl->memc_br5 = CFG_EXTPROM_BR5;
+	memctl->memc_or5 = CONFIG_SYS_EXTPROM_OR5;
+	memctl->memc_br5 = CONFIG_SYS_EXTPROM_BR5;
 	/* Initialize OR6 / BR6 for the extended EEPROM Bank1 */
-	memctl->memc_or6 = CFG_EXTPROM_OR6;
-	memctl->memc_br6 = CFG_EXTPROM_BR6;
+	memctl->memc_or6 = CONFIG_SYS_EXTPROM_OR6;
+	memctl->memc_br6 = CONFIG_SYS_EXTPROM_BR6;
 
 	/* Initialize OR7 / BR7 for the Glue Logic */
-	memctl->memc_or7 = CFG_FIOX_OR7;
-	memctl->memc_br7 = CFG_FIOX_BR7;
+	memctl->memc_or7 = CONFIG_SYS_FIOX_OR7;
+	memctl->memc_br7 = CONFIG_SYS_FIOX_BR7;
 
 	/* Initialize OR8 / BR8 for the DOH Logic */
-	memctl->memc_or8 = CFG_FDOHM_OR8;
-	memctl->memc_br8 = CFG_FDOHM_BR8;
+	memctl->memc_or8 = CONFIG_SYS_FDOHM_OR8;
+	memctl->memc_br8 = CONFIG_SYS_FDOHM_BR8;
 
 	DEBUGF ("OR0 %08x   BR0 %08x\n", memctl->memc_or0, memctl->memc_br0);
 	DEBUGF ("OR1 %08x   BR1 %08x\n", memctl->memc_or1, memctl->memc_br1);
diff --git a/board/siemens/SMN42/flash.c b/board/siemens/SMN42/flash.c
index ae64096..8cf17b8 100644
--- a/board/siemens/SMN42/flash.c
+++ b/board/siemens/SMN42/flash.c
@@ -25,8 +25,8 @@
 #include <asm/byteorder.h>
 #include <asm/arch/hardware.h>
 
-static unsigned long flash_addr_table[CFG_MAX_FLASH_BANKS] = CFG_FLASH_BANKS_LIST;
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+static unsigned long flash_addr_table[CONFIG_SYS_MAX_FLASH_BANKS] = CONFIG_SYS_FLASH_BANKS_LIST;
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 extern int lpc2292_copy_buffer_to_flash(flash_info_t *, ulong);
 extern int lpc2292_flash_erase(flash_info_t *, int, int);
@@ -172,19 +172,19 @@
  * From here on is code for the external S29GL128N taken from cam5200_flash.c
  */
 
-#define CFG_FLASH_WORD_SIZE unsigned short
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
 
 static int wait_for_DQ7_32(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-			(CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -199,8 +199,8 @@
 
 int ext_flash_erase(flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect, ret;
 
 	ret = 0;
@@ -236,14 +236,14 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 
 			l_sect = sect;
 			/*
@@ -269,8 +269,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	if (ret)
 		printf(" error\n");
@@ -282,20 +282,20 @@
 static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 			info->flash_id = FLASH_MAN_AMD;
 			break;
 		default:
@@ -308,12 +308,12 @@
 	value = addr2[1];	/* device ID            */
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE)AMD_ID_MIRROR:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_MIRROR:
 			value = addr2[14];
 			switch(value) {
-				case (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_2:
+				case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_2:
 					value = addr2[15];
-					if (value != (CFG_FLASH_WORD_SIZE)AMD_ID_GL128N_3) {
+					if (value != (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_GL128N_3) {
 						info->flash_id = FLASH_UNKNOWN;
 					} else {
 						info->flash_id += FLASH_S29GL128N;
@@ -340,13 +340,13 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		info->protect[i] = addr2[2] & 1;
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -354,11 +354,11 @@
 static unsigned long ext_flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 1; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 1; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -384,9 +384,9 @@
 
 static int write_word(flash_info_t * info, ulong dest, ushort data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) &data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) &data;
 	ulong start;
 	int flag;
 
@@ -398,9 +398,9 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts();
 
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 	*dest2 = *data2;
 
 	/* re-enable interrupts if necessary */
@@ -409,10 +409,10 @@
 
 	/* data polling for D7 */
 	start = get_timer(0);
-	while ((*dest2 & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-			(*data2 & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+	while ((*dest2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(*data2 & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			printf("WRITE_TOUT\n");
 			return (1);
 		}
diff --git a/board/siemens/pcu_e/flash.c b/board/siemens/pcu_e/flash.c
index 97b511e..3ce7bb3 100644
--- a/board/siemens/pcu_e/flash.c
+++ b/board/siemens/pcu_e/flash.c
@@ -26,7 +26,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -47,7 +47,7 @@
 /*---------------------------------------------------------------------*/
 
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -68,20 +68,20 @@
  */
 
 #define PCU_MONITOR_BASE   ( (flash_info[0].start[0] + flash_info[0].size - 1) \
-			   - (0xFFFFFFFF - CFG_MONITOR_BASE) )
+			   - (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE) )
 
 /*-----------------------------------------------------------------------
  */
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long base, size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -131,7 +131,7 @@
 
 	/* Remap FLASH according to real size */
 	base = 0 - size_b0;
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & 0xFFFF8000);
 	memctl->memc_br0 = (base & BR_BA_MSK) | BR_PS_16 | BR_MS_GPCM | BR_V;
 
 	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
@@ -162,7 +162,7 @@
 	if (size_b1) {
 		flash_info_t tmp_info;
 
-		memctl->memc_or6 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_or6 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
 		memctl->memc_br6 = ((base - size_b1) & BR_BA_MSK) |
 				    BR_PS_16 | BR_MS_GPCM | BR_V;
 
@@ -437,10 +437,10 @@
 #endif
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	saddr = (vu_short *)info->start[0];
@@ -526,7 +526,7 @@
 	last  = start;
 	addr = (vu_short*)(info->start[l_sect]);
 	while ((addr[0] & 0x0080) != 0x0080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -660,7 +660,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 
-	for (passed=0; passed < CFG_FLASH_WRITE_TOUT; passed=get_timer(start)) {
+	for (passed=0; passed < CONFIG_SYS_FLASH_WRITE_TOUT; passed=get_timer(start)) {
 
 		sval = *sdest;
 
@@ -683,7 +683,7 @@
 		 dest, sval, sdata);
 	}
 
-	if (passed >= CFG_FLASH_WRITE_TOUT) {
+	if (passed >= CONFIG_SYS_FLASH_WRITE_TOUT) {
 		DEBUGF ("Timeout @ addr 0x%08lX: val %04X data %04X\n",
 			dest, sval, sdata);
 		rc = 1;
diff --git a/board/siemens/pcu_e/pcu_e.c b/board/siemens/pcu_e/pcu_e.c
index 5647f7a..a60c825 100644
--- a/board/siemens/pcu_e/pcu_e.c
+++ b/board/siemens/pcu_e/pcu_e.c
@@ -158,7 +158,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 	long int size_b0, reg;
 	int i;
@@ -169,7 +169,7 @@
 	upmconfig (UPMA, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* burst length=4, burst type=sequential, CAS latency=2 */
 	memctl->memc_mar = 0x00000088;
@@ -178,15 +178,15 @@
 	 * Map controller bank 2 to the SDRAM bank at preliminary address.
 	 */
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-	memctl->memc_or5 = CFG_OR5_PRELIM;
-	memctl->memc_br5 = CFG_BR5_PRELIM;
+	memctl->memc_or5 = CONFIG_SYS_OR5_PRELIM;
+	memctl->memc_br5 = CONFIG_SYS_BR5_PRELIM;
 #else  /* XXX */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 #endif /* XXX */
 
 	/* initialize memory address register */
-	memctl->memc_mamr = CFG_MAMR;	/* refresh not enabled yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR;	/* refresh not enabled yet */
 
 	/* mode initialization (offset 5) */
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
@@ -241,12 +241,12 @@
 	 * Check Bank 0 Memory Size for re-configuration
 	 */
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-	size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
+	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE5_PRELIM, SDRAM_MAX_SIZE);
 #else  /* XXX */
-	size_b0 = dram_size (CFG_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size_b0 = dram_size (CONFIG_SYS_MAMR, (long *) SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 #endif /* XXX */
 
-	memctl->memc_mamr = CFG_MAMR | MAMR_PTAE;
+	memctl->memc_mamr = CONFIG_SYS_MAMR | MAMR_PTAE;
 
 	/*
 	 * Final mapping:
@@ -254,10 +254,10 @@
 
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
 	memctl->memc_or5 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
-	memctl->memc_br5 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br5 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 #else  /* XXX */
 	memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | SDRAM_TIMING;
-	memctl->memc_br2 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+	memctl->memc_br2 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 #endif /* XXX */
 	udelay (1000);
 
@@ -283,7 +283,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -294,29 +294,29 @@
 /* ------------------------------------------------------------------------- */
 
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-#define	ETH_CFG_BITS	(CFG_PB_ETH_CFG1 | CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_CFG1 | CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
 #else  /* XXX */
-#define	ETH_CFG_BITS	(CFG_PB_ETH_MDDIS | CFG_PB_ETH_CFG1 | \
-			 CFG_PB_ETH_CFG2  | CFG_PB_ETH_CFG3 )
+#define	ETH_CFG_BITS	(CONFIG_SYS_PB_ETH_MDDIS | CONFIG_SYS_PB_ETH_CFG1 | \
+			 CONFIG_SYS_PB_ETH_CFG2  | CONFIG_SYS_PB_ETH_CFG3 )
 #endif /* XXX */
 
-#define ETH_ALL_BITS	(ETH_CFG_BITS | CFG_PB_ETH_POWERDOWN | CFG_PB_ETH_RESET)
+#define ETH_ALL_BITS	(ETH_CFG_BITS | CONFIG_SYS_PB_ETH_POWERDOWN | CONFIG_SYS_PB_ETH_RESET)
 
 void reset_phy (void)
 {
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	ulong value;
 
 	/* Configure all needed port pins for GPIO */
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-# ifdef CFG_ETH_MDDIS_VALUE
-	immr->im_ioport.iop_padat |= CFG_PA_ETH_MDDIS;
+# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
+	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_ETH_MDDIS;
 # else
-	immr->im_ioport.iop_padat &= ~(CFG_PA_ETH_MDDIS);	/* Set low */
+	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* Set low */
 # endif
-	immr->im_ioport.iop_papar &= ~(CFG_PA_ETH_MDDIS);	/* GPIO */
-	immr->im_ioport.iop_paodr &= ~(CFG_PA_ETH_MDDIS);	/* active output */
-	immr->im_ioport.iop_padir |= CFG_PA_ETH_MDDIS;	/* output */
+	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* GPIO */
+	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_ETH_MDDIS);	/* active output */
+	immr->im_ioport.iop_padir |= CONFIG_SYS_PA_ETH_MDDIS;	/* output */
 #endif /* XXX */
 	immr->im_cpm.cp_pbpar &= ~(ETH_ALL_BITS);	/* GPIO */
 	immr->im_cpm.cp_pbodr &= ~(ETH_ALL_BITS);	/* active output */
@@ -324,31 +324,31 @@
 	value = immr->im_cpm.cp_pbdat;
 
 	/* Assert Powerdown and Reset signals */
-	value |= CFG_PB_ETH_POWERDOWN;
-	value &= ~(CFG_PB_ETH_RESET);
+	value |= CONFIG_SYS_PB_ETH_POWERDOWN;
+	value &= ~(CONFIG_SYS_PB_ETH_RESET);
 
 	/* PHY configuration includes MDDIS and CFG1 ... CFG3 */
 #if !PCU_E_WITH_SWAPPED_CS
-# ifdef CFG_ETH_MDDIS_VALUE
-	value |= CFG_PB_ETH_MDDIS;
+# ifdef CONFIG_SYS_ETH_MDDIS_VALUE
+	value |= CONFIG_SYS_PB_ETH_MDDIS;
 # else
-	value &= ~(CFG_PB_ETH_MDDIS);
+	value &= ~(CONFIG_SYS_PB_ETH_MDDIS);
 # endif
 #endif
-#ifdef CFG_ETH_CFG1_VALUE
-	value |= CFG_PB_ETH_CFG1;
+#ifdef CONFIG_SYS_ETH_CFG1_VALUE
+	value |= CONFIG_SYS_PB_ETH_CFG1;
 #else
-	value &= ~(CFG_PB_ETH_CFG1);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG1);
 #endif
-#ifdef CFG_ETH_CFG2_VALUE
-	value |= CFG_PB_ETH_CFG2;
+#ifdef CONFIG_SYS_ETH_CFG2_VALUE
+	value |= CONFIG_SYS_PB_ETH_CFG2;
 #else
-	value &= ~(CFG_PB_ETH_CFG2);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG2);
 #endif
-#ifdef CFG_ETH_CFG3_VALUE
-	value |= CFG_PB_ETH_CFG3;
+#ifdef CONFIG_SYS_ETH_CFG3_VALUE
+	value |= CONFIG_SYS_PB_ETH_CFG3;
 #else
-	value &= ~(CFG_PB_ETH_CFG3);
+	value &= ~(CONFIG_SYS_PB_ETH_CFG3);
 #endif
 
 	/* Drive output signals to initial state */
@@ -357,11 +357,11 @@
 	udelay (10000);
 
 	/* De-assert Ethernet Powerdown */
-	immr->im_cpm.cp_pbdat &= ~(CFG_PB_ETH_POWERDOWN);	/* Enable PHY power */
+	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_ETH_POWERDOWN);	/* Enable PHY power */
 	udelay (10000);
 
 	/* de-assert RESET signal of PHY */
-	immr->im_cpm.cp_pbdat |= CFG_PB_ETH_RESET;
+	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_ETH_RESET;
 	udelay (1000);
 }
 
@@ -414,7 +414,7 @@
 
 static void puma_set_mode (int mode)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
 
 	/* disable PUMA in memory controller */
@@ -452,7 +452,7 @@
 
 static void puma_load (ulong addr, ulong len)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile uchar *fpga_addr = (volatile uchar *) PUMA_CONF_BASE;	/* XXX ??? */
 	uchar *data = (uchar *) addr;
 	int i;
@@ -462,33 +462,33 @@
 		++len;
 
 	/* Reset FPGA */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_INIT);	/* make input */
-	immr->im_ioport.iop_pcso  &= ~(CFG_PC_PUMA_INIT);
-	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_INIT);
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_INIT);	/* make input */
+	immr->im_ioport.iop_pcso  &= ~(CONFIG_SYS_PC_PUMA_INIT);
+	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_INIT);
 
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-	immr->im_cpm.cp_pbpar &= ~(CFG_PB_PUMA_PROG);		/* GPIO */
-	immr->im_cpm.cp_pbodr &= ~(CFG_PB_PUMA_PROG);		/* active output */
-	immr->im_cpm.cp_pbdat &= ~(CFG_PB_PUMA_PROG);		/* Set low */
-	immr->im_cpm.cp_pbdir |=   CFG_PB_PUMA_PROG;		/* output */
+	immr->im_cpm.cp_pbpar &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* GPIO */
+	immr->im_cpm.cp_pbodr &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* active output */
+	immr->im_cpm.cp_pbdat &= ~(CONFIG_SYS_PB_PUMA_PROG);		/* Set low */
+	immr->im_cpm.cp_pbdir |=   CONFIG_SYS_PB_PUMA_PROG;		/* output */
 #else
-	immr->im_ioport.iop_papar &= ~(CFG_PA_PUMA_PROG);	/* GPIO */
-	immr->im_ioport.iop_padat &= ~(CFG_PA_PUMA_PROG);	/* Set low */
-	immr->im_ioport.iop_paodr &= ~(CFG_PA_PUMA_PROG);	/* active output */
-	immr->im_ioport.iop_padir |=   CFG_PA_PUMA_PROG;	/* output */
+	immr->im_ioport.iop_papar &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* GPIO */
+	immr->im_ioport.iop_padat &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* Set low */
+	immr->im_ioport.iop_paodr &= ~(CONFIG_SYS_PA_PUMA_PROG);	/* active output */
+	immr->im_ioport.iop_padir |=   CONFIG_SYS_PA_PUMA_PROG;	/* output */
 #endif /* XXX */
 	udelay (100);
 
 #if PCU_E_WITH_SWAPPED_CS	/* XXX */
-	immr->im_cpm.cp_pbdat |= CFG_PB_PUMA_PROG;	/* release reset */
+	immr->im_cpm.cp_pbdat |= CONFIG_SYS_PB_PUMA_PROG;	/* release reset */
 #else
-	immr->im_ioport.iop_padat |= CFG_PA_PUMA_PROG;	/* release reset */
+	immr->im_ioport.iop_padat |= CONFIG_SYS_PA_PUMA_PROG;	/* release reset */
 #endif /* XXX */
 
 	/* wait until INIT indicates completion of reset */
 	for (i = 0; i < PUMA_INIT_TIMEOUT; ++i) {
 		udelay (1000);
-		if (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_INIT)
+		if (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_INIT)
 			break;
 	}
 	if (i == PUMA_INIT_TIMEOUT) {
@@ -519,14 +519,14 @@
 
 static int puma_init_done (void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* make sure pin is GPIO input */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_PUMA_DONE);
-	immr->im_ioport.iop_pcso &= ~(CFG_PC_PUMA_DONE);
-	immr->im_ioport.iop_pcdir &= ~(CFG_PC_PUMA_DONE);
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_PUMA_DONE);
+	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_PUMA_DONE);
+	immr->im_ioport.iop_pcdir &= ~(CONFIG_SYS_PC_PUMA_DONE);
 
-	return (immr->im_ioport.iop_pcdat & CFG_PC_PUMA_DONE) ? 1 : 0;
+	return (immr->im_ioport.iop_pcdat & CONFIG_SYS_PC_PUMA_DONE) ? 1 : 0;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/sixnet/flash.c b/board/sixnet/flash.c
index 3f23299..a8dfca8 100644
--- a/board/sixnet/flash.c
+++ b/board/sixnet/flash.c
@@ -28,7 +28,7 @@
  */
 #include <environment.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /* NOTE - CONFIG_FLASH_16BIT means the CPU interface is 16-bit, it
  *        has nothing to do with the flash chip being 8-bit or 16-bit.
@@ -56,7 +56,7 @@
 static int write_word_intel(flash_info_t *info, FPWV *dest, FPW data);
 static int write_word_amd(flash_info_t *info, FPWV *dest, FPW data);
 static void flash_get_offsets(ulong base, flash_info_t *info);
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 static void flash_sync_real_protect(flash_info_t *info);
 #endif
 
@@ -67,17 +67,17 @@
  */
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
-	size_b = flash_get_size((FPW *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b = flash_get_size((FPW *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b;
 
@@ -91,20 +91,20 @@
 	/* Do this again (was done already in flast_get_size), just
 	 * in case we move it when remap the FLASH.
 	 */
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 	/* read the hardware protection status (if any) into the
 	 * protection array in flash_info.
 	 */
 	flash_sync_real_protect(&flash_info[0]);
 #endif
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -405,7 +405,7 @@
 	return (info->size);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 
@@ -544,7 +544,7 @@
 		udelay (1000);
 
 		while ((*addr & (FPW)0x00800080) != (FPW)0x00800080) {
-			if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 
 				if (intel) {
@@ -663,7 +663,7 @@
 
     /* data polling for D7 */
     while (res == 0 && (*dest & (FPW)0x00800080) != (data & (FPW)0x00800080)) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00F000F0;	/* reset bank */
 	    res = 1;
 	}
@@ -709,7 +709,7 @@
     start = get_timer (0);
 
     while (res == 0 && (*dest & (FPW)0x00800080) != (FPW)0x00800080) {
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *dest = (FPW)0x00B000B0;	/* Suspend program	*/
 	    res = 1;
 	}
@@ -724,7 +724,7 @@
     return (res);
 }
 
-#ifdef CFG_FLASH_PROTECTION
+#ifdef CONFIG_SYS_FLASH_PROTECTION
 /*-----------------------------------------------------------------------
  */
 int flash_real_protect (flash_info_t * info, long sector, int prot)
diff --git a/board/sixnet/sixnet.c b/board/sixnet/sixnet.c
index dcd3472..3ed581e 100644
--- a/board/sixnet/sixnet.c
+++ b/board/sixnet/sixnet.c
@@ -35,7 +35,7 @@
 
 #if defined(CONFIG_CMD_NAND)
 #include <linux/mtd/nand_legacy.h>
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -133,7 +133,7 @@
 #define FPGA_DONE	0x0080	/* PA8, input, high when FPGA load complete */
 #define FPGA_PROGRAM_L	0x0040	/* PA9, output, low to reset, high to start */
 #define FPGA_INIT_L	0x0020	/* PA10, input, low indicates not ready	*/
-#define fpga (*(volatile unsigned char *)(CFG_FPGA_PROG))	/* FPGA port */
+#define fpga (*(volatile unsigned char *)(CONFIG_SYS_FPGA_PROG))	/* FPGA port */
 
 int board_postclk_init (void)
 {
@@ -143,7 +143,7 @@
 # include "fpgadata.c"
 	};
 
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 #define porta (immap->im_ioport.iop_padat)
 	const unsigned char* pdata;
@@ -247,10 +247,10 @@
 /* ------------------------------------------------------------------------- */
 
 /* base address for SRAM, assume 32-bit port,  valid */
-#define NVRAM_BR_VALUE   (CFG_SRAM_BASE | BR_PS_32 | BR_V)
+#define NVRAM_BR_VALUE   (CONFIG_SYS_SRAM_BASE | BR_PS_32 | BR_V)
 
 /*  up to 64MB - will be adjusted for actual size */
-#define NVRAM_OR_PRELIM  (ORMASK(CFG_SRAM_SIZE) \
+#define NVRAM_OR_PRELIM  (ORMASK(CONFIG_SYS_SRAM_SIZE) \
 	| OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_5_CLK | OR_EHTR)
 /*
  * Miscellaneous platform dependent initializations after running in RAM.
@@ -258,7 +258,7 @@
 
 int misc_init_r (void)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	char* s;
 	char* e;
@@ -271,7 +271,7 @@
 	/* Is there any SRAM? Is it 16 or 32 bits wide? */
 
 	/* First look for 32-bit SRAM */
-	bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+	bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
 
 	if (bd->bi_sramsize == 0) {
 	    /* no 32-bit SRAM, but there could be 16-bit SRAM since
@@ -279,7 +279,7 @@
 	     * Try again with a 16-bit bus.
 	     */
 	    memctl->memc_br2 |= BR_PS_16;
-	    bd->bi_sramsize = ram_size((ulong*)CFG_SRAM_BASE, CFG_SRAM_SIZE);
+	    bd->bi_sramsize = ram_size((ulong*)CONFIG_SYS_SRAM_BASE, CONFIG_SYS_SRAM_SIZE);
 	}
 
 	if (bd->bi_sramsize == 0) {
@@ -288,7 +288,7 @@
 	else {
 	    /* adjust or2 for actual size of SRAM */
 	    memctl->memc_or2 |= ORMASK(bd->bi_sramsize);
-	    bd->bi_sramstart = CFG_SRAM_BASE;
+	    bd->bi_sramstart = CONFIG_SYS_SRAM_BASE;
 	    printf("SRAM:  %lu KB\n", bd->bi_sramsize >> 10);
 	}
 
@@ -330,7 +330,7 @@
 #if defined(CONFIG_CMD_NAND)
 void nand_init(void)
 {
-	unsigned long totlen = nand_probe(CFG_DFLASH_BASE);
+	unsigned long totlen = nand_probe(CONFIG_SYS_DFLASH_BASE);
 
 	printf ("%4lu MB\n", totlen >> 20);
 }
@@ -498,7 +498,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	uint size_sdram = 0;
 	uint size_sdram9 = 0;
diff --git a/board/sl8245/flash.c b/board/sl8245/flash.c
index c787bfb..4455b63 100644
--- a/board/sl8245/flash.c
+++ b/board/sl8245/flash.c
@@ -27,7 +27,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -43,7 +43,7 @@
 #define PARAM_SECT23_SIZE 0x8000
 #define PARAM_SECT4_SIZE 0x10000
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static int write_data (flash_info_t *info, ulong dest, ulong *data);
 static void write_via_fpu(vu_long *addr, ulong *data);
@@ -79,8 +79,8 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		vu_long *addr = (vu_long *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		vu_long *addr = (vu_long *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
 
 		write_via_fpu (&addr[0xaaa], precmd0);
 		write_via_fpu (&addr[0x554], precmd1);
@@ -108,10 +108,10 @@
 		write_via_fpu (addr, cmdres);
 
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		for (j = 0; j < 32; j++) {
-			flash_info[i].start[j] = CFG_FLASH_BASE +
+			flash_info[i].start[j] = CONFIG_SYS_FLASH_BASE +
 					i * FLASH_BANK_SIZE + j * MAIN_SECT_SIZE;
 		}
 		flash_info[i].start[32] =
@@ -125,22 +125,22 @@
 
 	/* Protect monitor and environment sectors
 	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			&flash_info[1]);
 #else
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 #endif
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
-#if CONFIG_ENV_ADDR >= CFG_FLASH_BASE + FLASH_BANK_SIZE
+#if CONFIG_ENV_ADDR >= CONFIG_SYS_FLASH_BASE + FLASH_BANK_SIZE
 	flash_protect ( FLAG_PROTECT_SET,
 			CONFIG_ENV_ADDR,
 			CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[1]);
@@ -267,7 +267,7 @@
 
 			while (((addr[0] & 0x00800080) != 0x00800080) ||
 				   ((addr[1] & 0x00800080) != 0x00800080)) {
-				if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					write_via_fpu (addr, cmdersusp);
 					write_via_fpu (addr, cmdres);
@@ -452,7 +452,7 @@
 
 	while (((addr[0] & 0x00800080) != (data[0] & 0x00800080)) ||
 	       ((addr[1] & 0x00800080) != (data[1] & 0x00800080))) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			write_via_fpu (chip, cmdres);
 			return (1);
 		}
diff --git a/board/sl8245/sl8245.c b/board/sl8245/sl8245.c
index 25adc28..e849e01 100644
--- a/board/sl8245/sl8245.c
+++ b/board/sl8245/sl8245.c
@@ -37,13 +37,13 @@
 
 phys_size_t initdram (int board_type)
 {
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long size;
 	long new_bank0_end;
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size - 1;
 	mear1 = mpc824x_mpc107_getreg(MEAR1);
@@ -57,7 +57,7 @@
 
 	return (size);
 #else
-	return CFG_MAX_RAM_SIZE;
+	return CONFIG_SYS_MAX_RAM_SIZE;
 #endif
 }
 
diff --git a/board/smdk2400/flash.c b/board/smdk2400/flash.c
index af46bf6..9eee60d 100644
--- a/board/smdk2400/flash.c
+++ b/board/smdk2400/flash.c
@@ -33,7 +33,7 @@
 #define FLASH_BANK_SIZE 0x1000000	/* 2 x   8 MB */
 #define MAIN_SECT_SIZE  0x40000		/* 2 x 128 kB */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x00FF00FF
@@ -66,17 +66,17 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
 			(INTEL_MANUFACT     & FLASH_VENDMASK) |
 			(INTEL_ID_28F640J3A & FLASH_TYPEMASK);
 		flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
-			flashbase = CFG_FLASH_BASE;
+			flashbase = CONFIG_SYS_FLASH_BASE;
 		else
 			panic ("configured too many flash banks!\n");
 		for (j = 0; j < flash_info[i].sector_count; j++) {
@@ -92,8 +92,8 @@
 	 * Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -299,7 +299,7 @@
 			/* wait until flash is ready */
 			do {
 				/* check timeout */
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					*addr = CMD_STATUS_RESET;
 					result = BIT_TIMEOUT;
 					break;
@@ -394,7 +394,7 @@
 	/* wait until flash is ready */
 	do {
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			*addr = CMD_SUSPEND;
 			result = BIT_TIMEOUT;
 			break;
diff --git a/board/smdk2410/flash.c b/board/smdk2410/flash.c
index 32ae80d..132d752 100644
--- a/board/smdk2410/flash.c
+++ b/board/smdk2410/flash.c
@@ -30,7 +30,7 @@
 #define FLASH_BANK_SIZE	PHYS_FLASH_SIZE
 #define MAIN_SECT_SIZE  0x10000	/* 64 KB */
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x000000F0
@@ -41,8 +41,8 @@
 #define CMD_PROGRAM		0x000000A0
 #define CMD_UNLOCK_BYPASS	0x00000020
 
-#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CFG_FLASH_BASE + (0x00000555 << 1)))
-#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CFG_FLASH_BASE + (0x000002AA << 1)))
+#define MEM_FLASH_ADDR1		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1)))
+#define MEM_FLASH_ADDR2		(*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1)))
 
 #define BIT_ERASE_DONE		0x00000080
 #define BIT_RDY_MASK		0x00000080
@@ -61,7 +61,7 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		ulong flashbase = 0;
 
 		flash_info[i].flash_id =
@@ -75,8 +75,8 @@
 #error "Unknown flash configured"
 #endif
 			flash_info[i].size = FLASH_BANK_SIZE;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 		if (i == 0)
 			flashbase = PHYS_FLASH_1;
 		else
@@ -111,8 +111,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_FLASH_BASE,
-		       CFG_FLASH_BASE + monitor_flash_len - 1,
+		       CONFIG_SYS_FLASH_BASE,
+		       CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 		       &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -236,7 +236,7 @@
 
 				/* check timeout */
 				if (get_timer_masked () >
-				    CFG_FLASH_ERASE_TOUT) {
+				    CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip = TMO;
 					break;
@@ -332,7 +332,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			chip = ERR | TMO;
 			break;
 		}
diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c
index d2f169b..9e276a1 100644
--- a/board/snmc/qs850/flash.c
+++ b/board/snmc/qs850/flash.c
@@ -29,7 +29,7 @@
 #include <asm/u-boot.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 
 #define FLASH_WORD_SIZE unsigned long
@@ -57,7 +57,7 @@
 	volatile FLASH_WORD_SIZE* flash_base;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -87,13 +87,13 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
 		flash_get_offsets ((ulong)flash_base, &flash_info[0]);
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
 		size_b1 = 0 ;
 		flash_info[0].size = size_b0;
 		return(size_b0);
@@ -125,8 +125,8 @@
 	flash_get_offsets (base_b0, &flash_info[0]);
 
 	/* monitor protection ON by default */
-	(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-		CFG_MONITOR_BASE+CFG_MONITOR_LEN-1, &flash_info[0]);
+	(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+		CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1, &flash_info[0]);
 
 	if (size_b1) {
 		/* Re-do sizing to get full correct info */
@@ -134,11 +134,11 @@
 		flash_get_offsets (base_b1, &flash_info[1]);
 
 		/* monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CFG_MONITOR_LEN,
+		(void)flash_protect(FLAG_PROTECT_SET, base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
 			base_b1+size_b1-1, &flash_info[1]);
 
 		/* monitor protection OFF by default (one is enough) */
-		(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CFG_MONITOR_LEN,
+		(void)flash_protect(FLAG_PROTECT_CLEAR, base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
 			base_b0+size_b0-1, &flash_info[0]);
 	} else {
 		flash_info[1].flash_id = FLASH_UNKNOWN;
@@ -480,7 +480,7 @@
 	while ((addr[0] & (0x00800080&FLASH_ID_MASK)) !=
 			(0x00800080&FLASH_ID_MASK)  )
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -607,7 +607,7 @@
 	start = get_timer(0);
 
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/snmc/qs850/qs850.c b/board/snmc/qs850/qs850.c
index 2fbe8ae..cc8eaad 100644
--- a/board/snmc/qs850/qs850.c
+++ b/board/snmc/qs850/qs850.c
@@ -146,7 +146,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -155,17 +155,17 @@
 	/*
 	* Prescaler for refresh
 	*/
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/*
 	* Map controller bank 1 to the SDRAM address
 	*/
-	memctl->memc_or1 = CFG_OR1;
-	memctl->memc_br1 = CFG_BR1;
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
 	udelay(1000);
 
 	/* perform SDRAM initialization sequence */
-	memctl->memc_mamr = CFG_16M_MAMR;
+	memctl->memc_mamr = CONFIG_SYS_16M_MAMR;
 	udelay(100);
 
 	/* Program the SDRAM's Mode Register */
@@ -192,7 +192,7 @@
 	/*
 	* Check for 32M SDRAM Memory Size
 	*/
-	size = dram_size(CFG_32M_MAMR|MAMR_PTAE,
+	size = dram_size(CONFIG_SYS_32M_MAMR|MAMR_PTAE,
 	(long *)SDRAM_BASE, SDRAM_32M_MAX_SIZE);
 	udelay (1000);
 
@@ -200,7 +200,7 @@
 	* Check for 16M SDRAM Memory Size
 	*/
 	if (size != SDRAM_32M_MAX_SIZE) {
-	size = dram_size(CFG_16M_MAMR|MAMR_PTAE,
+	size = dram_size(CONFIG_SYS_16M_MAMR|MAMR_PTAE,
 	(long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
 	udelay (1000);
 	}
@@ -221,7 +221,7 @@
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c
index aa2e856..2cb8dcb 100644
--- a/board/snmc/qs860t/flash.c
+++ b/board/snmc/qs860t/flash.c
@@ -29,10 +29,10 @@
 #include <asm/u-boot.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 
-#ifdef CFG_FLASH_16BIT
+#ifdef CONFIG_SYS_FLASH_16BIT
 #define FLASH_WORD_SIZE	unsigned short
 #define FLASH_ID_MASK	0xFFFF
 #else
@@ -46,7 +46,7 @@
 /* stolen from esteem192e/flash.c */
 ulong flash_get_size (volatile FLASH_WORD_SIZE *addr, flash_info_t *info);
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t *info, ulong dest, ulong data);
 #else
 static int write_short (flash_info_t *info, ulong dest, ushort data);
@@ -65,7 +65,7 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -79,20 +79,20 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
 		flash_get_offsets (FLASH_BASE1_PRELIM, &flash_info[0]);
 
 		/* Monitor protection ON by default */
 #if 0	/* sand: */
 		(void)flash_protect(FLAG_PROTECT_SET,
-			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
 			FLASH_BASE1_PRELIM-1+size_b0,
 			&flash_info[0]);
 #else
 		(void)flash_protect(FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 			&flash_info[0]);
 #endif
 		size_b1 = 0 ;
@@ -126,13 +126,13 @@
 		/* monitor protection ON by default */
 #if 0	/* sand: */
 		(void)flash_protect(FLAG_PROTECT_SET,
-			FLASH_BASE1_PRELIM-CFG_MONITOR_LEN+size_b0,
+			FLASH_BASE1_PRELIM-CONFIG_SYS_MONITOR_LEN+size_b0,
 			FLASH_BASE1_PRELIM-1+size_b0,
 			&flash_info[0]);
 #else
 		(void)flash_protect(FLAG_PROTECT_SET,
-			CFG_MONITOR_BASE,
-			CFG_MONITOR_BASE+CFG_MONITOR_LEN-1,
+			CONFIG_SYS_MONITOR_BASE,
+			CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN-1,
 			&flash_info[0]);
 #endif
 
@@ -144,12 +144,12 @@
 
 			/* monitor protection ON by default */
 			(void)flash_protect(FLAG_PROTECT_SET,
-				base_b1+size_b1-CFG_MONITOR_LEN,
+				base_b1+size_b1-CONFIG_SYS_MONITOR_LEN,
 				base_b1+size_b1-1,
 				&flash_info[1]);
 			/* monitor protection OFF by default (one is enough) */
 			(void)flash_protect(FLAG_PROTECT_CLEAR,
-				base_b0+size_b0-CFG_MONITOR_LEN,
+				base_b0+size_b0-CONFIG_SYS_MONITOR_LEN,
 				base_b0+size_b0-1,
 				&flash_info[0]);
 		} else {
@@ -182,7 +182,7 @@
 	else if (info->flash_id & FLASH_BTYPE) {
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			/* set sector offsets for bottom boot block type */
 			info->start[0] = base + 0x00000000;
 			info->start[1] = base + 0x00004000;
@@ -234,7 +234,7 @@
 		i = info->sector_count - 1;
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00008000;
 			info->start[i--] = base + info->size - 0x0000C000;
@@ -393,7 +393,7 @@
 	/* Write auto select command: read Manufacturer ID */
 
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 	/*
 	 * Note: if it is an AMD flash and the word at addr[0000]
@@ -650,7 +650,7 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 	if (info->flash_id < FLASH_AMD_COMP) {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 		addr[0x0555] = 0x00AA00AA;
 		addr[0x02AA] = 0x00550055;
 		addr[0x0555] = 0x00800080;
@@ -690,7 +690,7 @@
 		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
 		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
 		       (0x00800080 & FLASH_ID_MASK)) {
-			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -711,7 +711,7 @@
 		for (sect = s_first; sect <= s_last; sect++) {
 			if (info->protect[sect] == 0) {	/* not protected */
 				barf = 0;
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 				addr = (vu_long *) (info->start[sect]);
 				addr[0] = 0x00200020;
 				addr[0] = 0x00D000D0;
@@ -766,7 +766,7 @@
 	flash_info_t *info;
 	int i;
 
-	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
 		if ((addr >= info->start[0]) &&
 		    (addr < (info->start[0] + info->size)) ) {
 			return (info);
@@ -843,7 +843,7 @@
 
 int write_buff (flash_info_t *info, uchar *src, ulong addr, ulong cnt)
 {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 	ulong cp, wp, data;
 	int l;
 #else
@@ -852,7 +852,7 @@
 #endif
 	int i, rc;
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 
 	wp = (addr & ~3);	/* get lower word aligned address */
@@ -979,7 +979,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t *info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long*)(info->start[0]);
@@ -1015,13 +1015,13 @@
 
 	if(info->flash_id > FLASH_AMD_COMP) {
 		while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
 	} else {
 		while(!(addr[0] & 0x00800080)) {	/* wait for error or finish */
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 
@@ -1081,7 +1081,7 @@
 	if(info->flash_id < FLASH_AMD_COMP) {
 		/* AMD stuff */
 		while ((*((vu_short *)dest) & 0x0080) != (data & 0x0080)) {
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1089,7 +1089,7 @@
 	} else {
 		/* intel stuff */
 		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
 		}
 
 		if( addr[0] & 0x003A) {	/* check for error */
@@ -1103,7 +1103,7 @@
 		*addr = 0x00B0;
 		*addr = 0x0070;
 		while(!(addr[0] & 0x0080)){	/* wait for error or finish */
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) return (1);
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) return (1);
 		}
 		*addr = 0x00FF;
 	}
diff --git a/board/snmc/qs860t/qs860t.c b/board/snmc/qs860t/qs860t.c
index 17c9356..b272d80 100644
--- a/board/snmc/qs860t/qs860t.c
+++ b/board/snmc/qs860t/qs860t.c
@@ -117,7 +117,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 
@@ -131,12 +131,12 @@
 	/*
 	* Map controller bank 2 to the SDRAM address
 	*/
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 	udelay(200);
 
 	/* perform SDRAM initialization sequence */
-	memctl->memc_mbmr = CFG_16M_MBMR;
+	memctl->memc_mbmr = CONFIG_SYS_16M_MBMR;
 	udelay(100);
 
 	memctl->memc_mar  = 0x00000088;
@@ -155,7 +155,7 @@
 	/*
 	* Check for 64M SDRAM Memory Size
 	*/
-	size = dram_size (CFG_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
+	size = dram_size (CONFIG_SYS_64M_MBMR, (ulong *)SDRAM_BASE, SDRAM_64M_MAX_SIZE);
 	udelay (1000);
 
 	/*
@@ -163,7 +163,7 @@
 	*/
 	if (size != SDRAM_64M_MAX_SIZE) {
 #endif
-	size = dram_size (CFG_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
+	size = dram_size (CONFIG_SYS_16M_MBMR, (long *)SDRAM_BASE, SDRAM_16M_MAX_SIZE);
 	udelay (1000);
 #if 0
 	}
@@ -184,31 +184,31 @@
 	/*
 	* Map the 8M Intel Flash device to chip select 1
 	*/
-	memctl->memc_or1 = CFG_OR1;
-	memctl->memc_br1 = CFG_BR1;
+	memctl->memc_or1 = CONFIG_SYS_OR1;
+	memctl->memc_br1 = CONFIG_SYS_BR1;
 
 
 	/*
 	* Map 64K NVRAM, Sipex Device, NAND Ctl Reg, and LED Ctl Reg
 	* to chip select 3
 	*/
-	memctl->memc_or3 = CFG_OR3;
-	memctl->memc_br3 = CFG_BR3;
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
 
 	/*
 	* Map chip selects 4, 5, 6, & 7 for external expansion connector
 	*/
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 
-	memctl->memc_or5 = CFG_OR5;
-	memctl->memc_br5 = CFG_BR5;
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
 
-	memctl->memc_or6 = CFG_OR6;
-	memctl->memc_br6 = CFG_BR6;
+	memctl->memc_or6 = CONFIG_SYS_OR6;
+	memctl->memc_br6 = CONFIG_SYS_BR6;
 
-	memctl->memc_or7 = CFG_OR7;
-	memctl->memc_br7 = CFG_BR7;
+	memctl->memc_or7 = CONFIG_SYS_OR7;
+	memctl->memc_br7 = CONFIG_SYS_BR7;
 
 #endif
 
@@ -227,7 +227,7 @@
 
 static long int dram_size (long int mbmr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mbmr = mbmr_value;
diff --git a/board/socrates/law.c b/board/socrates/law.c
index 89b446f..71cff8c 100644
--- a/board/socrates/law.c
+++ b/board/socrates/law.c
@@ -47,14 +47,14 @@
  */
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-#if defined(CFG_FPGA_BASE)
-	SET_LAW(CFG_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+#if defined(CONFIG_SYS_FPGA_BASE)
+	SET_LAW(CONFIG_SYS_FPGA_BASE, LAWAR_SIZE_1M, LAW_TRGT_IF_LBC),
 #endif
-	SET_LAW(CFG_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LIME_BASE, LAWAR_SIZE_64M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/socrates/nand.c b/board/socrates/nand.c
index 6ec53f8..7d76f42 100644
--- a/board/socrates/nand.c
+++ b/board/socrates/nand.c
@@ -23,7 +23,7 @@
 
 #include <common.h>
 
-#if defined(CFG_NAND_BASE)
+#if defined(CONFIG_SYS_NAND_BASE)
 #include <nand.h>
 #include <asm/errno.h>
 #include <asm/io.h>
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index 12d1b8a..029ba02 100644
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -41,7 +41,7 @@
  */
 long int sdram_setup(int casl)
 {
-	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 
 	/*
 	 * Disable memory controller.
@@ -49,28 +49,28 @@
 	ddr->cs0_config = 0;
 	ddr->sdram_cfg = 0;
 
-	ddr->cs0_bnds = CFG_DDR_CS0_BNDS;
-	ddr->cs0_config = CFG_DDR_CS0_CONFIG;
-	ddr->timing_cfg_0 = CFG_DDR_TIMING_0;
-	ddr->timing_cfg_1 = CFG_DDR_TIMING_1;
-	ddr->timing_cfg_2 = CFG_DDR_TIMING_2;
-	ddr->sdram_mode = CFG_DDR_MODE;
-	ddr->sdram_interval = CFG_DDR_INTERVAL;
-	ddr->sdram_cfg_2 = CFG_DDR_CONFIG_2;
-	ddr->sdram_clk_cntl = CFG_DDR_CLK_CONTROL;
+	ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
+	ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
+	ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
+	ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
+	ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
+	ddr->sdram_mode = CONFIG_SYS_DDR_MODE;
+	ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
+	ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONFIG_2;
+	ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CONTROL;
 
 	asm ("sync;isync;msync");
 	udelay(1000);
 
-	ddr->sdram_cfg = CFG_DDR_CONFIG;
+	ddr->sdram_cfg = CONFIG_SYS_DDR_CONFIG;
 	asm ("sync; isync; msync");
 	udelay(1000);
 
-	if (get_ram_size(0, CFG_SDRAM_SIZE<<20) == CFG_SDRAM_SIZE<<20) {
+	if (get_ram_size(0, CONFIG_SYS_SDRAM_SIZE<<20) == CONFIG_SYS_SDRAM_SIZE<<20) {
 		/*
 		 * OK, size detected -> all done
 		 */
-		return CFG_SDRAM_SIZE<<20;
+		return CONFIG_SYS_SDRAM_SIZE<<20;
 	}
 
 	return 0;				/* nothing found !		*/
@@ -90,11 +90,11 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf ("SDRAM test phase 1:\n");
diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c
index 0991177..d83dc7d 100644
--- a/board/socrates/socrates.c
+++ b/board/socrates/socrates.c
@@ -51,7 +51,7 @@
 
 int checkboard (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	char *src;
 	int f;
@@ -87,7 +87,7 @@
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -98,20 +98,20 @@
 	/*
 	 * Check if boot FLASH isn't max size
 	 */
-	if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) {
-		memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff);
-		memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);
+	if (gd->bd->bi_flashsize < (0 - CONFIG_SYS_FLASH0)) {
+		memctl->or0 = gd->bd->bi_flashstart | (CONFIG_SYS_OR0_PRELIM & 0x00007fff);
+		memctl->br0 = gd->bd->bi_flashstart | (CONFIG_SYS_BR0_PRELIM & 0x00007fff);
 
 		/*
 		 * Re-check to get correct base address
 		 */
-		flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1);
+		flash_get_size(gd->bd->bi_flashstart, CONFIG_SYS_MAX_FLASH_BANKS - 1);
 	}
 
 	/*
 	 * Check if only one FLASH bank is available
 	 */
-	if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) {
+	if (gd->bd->bi_flashsize != CONFIG_SYS_MAX_FLASH_BANKS * (0 - CONFIG_SYS_FLASH0)) {
 		memctl->or1 = 0;
 		memctl->br1 = 0;
 
@@ -120,24 +120,24 @@
 		 */
 		flash_protect (FLAG_PROTECT_CLEAR,
 			       gd->bd->bi_flashstart, 0xffffffff,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Monitor protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
-			       CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Environment protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
 			       CONFIG_ENV_ADDR,
 			       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 		/* Redundant environment protection ON by default */
 		flash_protect (FLAG_PROTECT_SET,
 			       CONFIG_ENV_ADDR_REDUND,
 			       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-			       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+			       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 	}
 
 	return 0;
@@ -148,12 +148,12 @@
  */
 void local_bus_init (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
-	volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
+	volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR);
 	sys_info_t sysinfo;
 	uint clkdiv;
 	uint lbc_mhz;
-	uint lcrr = CFG_LBC_LCRR;
+	uint lcrr = CONFIG_SYS_LBC_LCRR;
 
 	get_sys_info (&sysinfo);
 	clkdiv = lbc->lcrr & 0x0f;
@@ -219,7 +219,7 @@
 #ifdef CONFIG_BOARD_EARLY_INIT_R
 int board_early_init_r (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 
 	/* set and reset the GPIO pin 2 which will reset the W83782G chip */
 	out_8((unsigned char*)&gur->gpoutdr, 0x3F );
@@ -246,19 +246,19 @@
 	val[i++] = gd->bd->bi_flashstart;
 	val[i++] = gd->bd->bi_flashsize;
 
-	if (mb862xx.frameAdrs == CFG_LIME_BASE) {
+	if (mb862xx.frameAdrs == CONFIG_SYS_LIME_BASE) {
 		/* Fixup LIME mapping */
 		val[i++] = 2;			/* chip select number */
 		val[i++] = 0;			/* always 0 */
-		val[i++] = CFG_LIME_BASE;
-		val[i++] = CFG_LIME_SIZE;
+		val[i++] = CONFIG_SYS_LIME_BASE;
+		val[i++] = CONFIG_SYS_LIME_SIZE;
 	}
 
 	/* Fixup FPGA mapping */
 	val[i++] = 3;				/* chip select number */
 	val[i++] = 0;				/* always 0 */
-	val[i++] = CFG_FPGA_BASE;
-	val[i++] = CFG_FPGA_SIZE;
+	val[i++] = CONFIG_SYS_FPGA_BASE;
+	val[i++] = CONFIG_SYS_FPGA_SIZE;
 
 	rc = fdt_find_and_setprop(blob, "/localbus", "ranges",
 				  val, i * sizeof(u32), 1);
@@ -268,14 +268,14 @@
 }
 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */
 
-#define CFG_LIME_SRST		((CFG_LIME_BASE) + 0x01FC002C)
-#define CFG_LIME_CCF		((CFG_LIME_BASE) + 0x01FC0038)
-#define CFG_LIME_MMR		((CFG_LIME_BASE) + 0x01FCFFFC)
+#define CONFIG_SYS_LIME_SRST		((CONFIG_SYS_LIME_BASE) + 0x01FC002C)
+#define CONFIG_SYS_LIME_CCF		((CONFIG_SYS_LIME_BASE) + 0x01FC0038)
+#define CONFIG_SYS_LIME_MMR		((CONFIG_SYS_LIME_BASE) + 0x01FCFFFC)
 /* Lime clock frequency */
-#define CFG_LIME_CLK_100MHZ	0x00000
-#define CFG_LIME_CLK_133MHZ	0x10000
+#define CONFIG_SYS_LIME_CLK_100MHZ	0x00000
+#define CONFIG_SYS_LIME_CLK_133MHZ	0x10000
 /* SDRAM parameter */
-#define CFG_LIME_MMR_VALUE	0x4157BA63
+#define CONFIG_SYS_LIME_MMR_VALUE	0x4157BA63
 
 #define DISPLAY_WIDTH		800
 #define DISPLAY_HEIGHT		480
@@ -308,11 +308,11 @@
 	return init_regs;
 }
 
-#define CFG_LIME_CID		((CFG_LIME_BASE) + 0x01FC00F0)
-#define CFG_LIME_REV		((CFG_LIME_BASE) + 0x01FF8084)
+#define CONFIG_SYS_LIME_CID		((CONFIG_SYS_LIME_BASE) + 0x01FC00F0)
+#define CONFIG_SYS_LIME_REV		((CONFIG_SYS_LIME_BASE) + 0x01FF8084)
 int lime_probe(void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint cfg_br2;
 	uint cfg_or2;
 	uint reg;
@@ -323,14 +323,14 @@
 	/* Configure GPCM for CS2 */
 	memctl->br2 = 0;
 	memctl->or2 = 0xfc000410;
-	memctl->br2 = (CFG_LIME_BASE) | 0x00001901;
+	memctl->br2 = (CONFIG_SYS_LIME_BASE) | 0x00001901;
 
 	/* Try to access GDC ID/Revision registers */
-	reg = in_be32((void *)CFG_LIME_CID);
-	reg = in_be32((void *)CFG_LIME_CID);
+	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
+	reg = in_be32((void *)CONFIG_SYS_LIME_CID);
 	if (reg == 0x303) {
-		reg = in_be32((void *)CFG_LIME_REV);
-		reg = in_be32((void *)CFG_LIME_REV);
+		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
+		reg = in_be32((void *)CONFIG_SYS_LIME_REV);
 		reg = ((reg & ~0xff) == 0x20050100) ? 1 : 0;
 	} else
 		reg = 0;
@@ -351,22 +351,22 @@
 	/*
 	 * Reset Lime controller
 	 */
-	out_be32((void *)CFG_LIME_SRST, 0x1);
+	out_be32((void *)CONFIG_SYS_LIME_SRST, 0x1);
 	udelay(200);
 
 	/* Set Lime clock to 133MHz */
-	out_be32((void *)CFG_LIME_CCF, CFG_LIME_CLK_133MHZ);
+	out_be32((void *)CONFIG_SYS_LIME_CCF, CONFIG_SYS_LIME_CLK_133MHZ);
 	/* Delay required */
 	udelay(300);
 	/* Set memory parameters */
-	out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE);
+	out_be32((void *)CONFIG_SYS_LIME_MMR, CONFIG_SYS_LIME_MMR_VALUE);
 
 	mb862xx.winSizeX = DISPLAY_WIDTH;
 	mb862xx.winSizeY = DISPLAY_HEIGHT;
 	mb862xx.gdfIndex = GDF_15BIT_555RGB;
 	mb862xx.gdfBytesPP = 2;
 
-	return CFG_LIME_BASE;
+	return CONFIG_SYS_LIME_BASE;
 }
 
 #define W83782D_REG_CFG		0x40
@@ -381,22 +381,22 @@
 {
 	u8 buf;
 
-	if (i2c_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
+	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 1, &buf, 1))
 		return -1;
 
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG, 0x80);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BANK_SEL, 0);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_ADCCLK, 0x40);
 
-	buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
+	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL,
 		      buf | 0x80);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_BEEP_CTRL2, 0);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_PWMOUT1, 0x47);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_VBAT, 0x01);
 
-	buf = i2c_reg_read(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG);
-	i2c_reg_write(CFG_I2C_W83782G_ADDR, W83782D_REG_CFG,
+	buf = i2c_reg_read(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG);
+	i2c_reg_write(CONFIG_SYS_I2C_W83782G_ADDR, W83782D_REG_CFG,
 		      (buf & 0xf4) | 0x01);
 	return 0;
 }
@@ -408,37 +408,37 @@
 	u8 old_buf;
 
 	/* Select bank 0 */
-	if (i2c_read(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+	if (i2c_read(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
 		goto err;
 	else
 		buf = old_buf & 0xf8;
 
-	if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
+	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &buf, 1))
 		goto err;
 
 	if (br > 0) {
 		/* PWMOUT1 duty cycle ctrl */
 		buf = 255 / (100 / br);
-		if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
 			goto err;
 
 		/* LEDs on */
-		reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
 		if (!(reg & BACKLIGHT_ENABLE));
-			out_be32((void *)(CFG_FPGA_BASE + 0x0c),
+			out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c),
 				 reg | BACKLIGHT_ENABLE);
 	} else {
 		buf = 0;
-		if (i2c_write(CFG_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
+		if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x5b, 1, &buf, 1))
 			goto err;
 
 		/* LEDs off */
-		reg = in_be32((void *)(CFG_FPGA_BASE + 0x0c));
+		reg = in_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c));
 		reg &= ~BACKLIGHT_ENABLE;
-		out_be32((void *)(CFG_FPGA_BASE + 0x0c), reg);
+		out_be32((void *)(CONFIG_SYS_FPGA_BASE + 0x0c), reg);
 	}
 	/* Restore previous bank setting */
-	if (i2c_write(CFG_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
+	if (i2c_write(CONFIG_SYS_I2C_W83782G_ADDR, 0x4e, 1, &old_buf, 1))
 		goto err;
 
 	return;
diff --git a/board/socrates/tlb.c b/board/socrates/tlb.c
index d255cea..b91b1ea 100644
--- a/board/socrates/tlb.c
+++ b/board/socrates/tlb.c
@@ -31,16 +31,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -50,7 +50,7 @@
 	 * 0xfc000000	64M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_64M, 1),
 
@@ -58,7 +58,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -66,16 +66,16 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
-#if defined(CFG_FPGA_BASE)
+#if defined(CONFIG_SYS_FPGA_BASE)
 	/*
 	 * TLB 4:	1M	Non-cacheable, guarded
 	 * 0xc0000000	1M	FPGA and NAND
 	 */
-	SET_TLB_ENTRY(1, CFG_FPGA_BASE, CFG_FPGA_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_1M, 1),
 #endif
@@ -87,7 +87,7 @@
 	 * (0xcbfc0000	256K	LIME GDC MMIO)
 	 * MMIO is relocatable and could be at 0xcbfc0000
 	 */
-	SET_TLB_ENTRY(1, CFG_LIME_BASE, CFG_LIME_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LIME_BASE, CONFIG_SYS_LIME_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -96,7 +96,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -107,11 +107,11 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 8, BOOKE_PAGESZ_256M, 1),
 };
diff --git a/board/sorcery/sorcery.c b/board/sorcery/sorcery.c
index e4fb146..3e1bd6f 100644
--- a/board/sorcery/sorcery.c
+++ b/board/sorcery/sorcery.c
@@ -34,7 +34,7 @@
 
 	size = dramSetup ();
 
-	return get_ram_size(CFG_SDRAM_BASE, size);
+	return get_ram_size(CONFIG_SYS_SDRAM_BASE, size);
 }
 
 int checkboard (void)
diff --git a/board/spc1920/hpi.c b/board/spc1920/hpi.c
index cf21b21..26d0f9c 100644
--- a/board/spc1920/hpi.c
+++ b/board/spc1920/hpi.c
@@ -144,16 +144,16 @@
 /* init the host port interface on UPMA */
 int hpi_init(void)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
-	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
 
 	upmconfig(UPMA, (uint *)dsp_table_slow, sizeof(dsp_table_slow)/sizeof(uint));
 	udelay(100);
 
-	memctl->memc_mamr = CFG_MAMR;
-	memctl->memc_or3 = CFG_OR3;
-	memctl->memc_br3 = CFG_BR3;
+	memctl->memc_mamr = CONFIG_SYS_MAMR;
+	memctl->memc_or3 = CONFIG_SYS_OR3;
+	memctl->memc_br3 = CONFIG_SYS_BR3;
 
 	/* reset dsp */
 	dsp_reset();
@@ -170,7 +170,7 @@
 /* activate the Host Port interface */
 static int hpi_activate(void)
 {
-	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
 
 	/* turn on hpi */
 	pld->dsp_hpi_on = 0x1;
@@ -193,7 +193,7 @@
 /* turn off the host port interface */
 static void hpi_inactivate(void)
 {
-	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
 
 	/* deactivate hpi */
 	pld->dsp_hpi_on = 0x0;
@@ -210,7 +210,7 @@
 /* reset the DSP */
 static void dsp_reset(void)
 {
-	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE;
+	volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE;
 	pld->dsp_reset = 0x1;
 	pld->dsp_hpi_on = 0x0;
 
diff --git a/board/spc1920/spc1920.c b/board/spc1920/spc1920.c
index a32aad0..ee939bf 100644
--- a/board/spc1920/spc1920.c
+++ b/board/spc1920/spc1920.c
@@ -84,9 +84,9 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immr->im_memctl;
-	/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CFG_SPC1920_PLD_BASE; */
+	/* volatile spc1920_pld_t *pld = (spc1920_pld_t *) CONFIG_SYS_SPC1920_PLD_BASE; */
 
 	long int size_b0;
 	long int size8, size9;
@@ -99,19 +99,19 @@
 
 	udelay(100);
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 	/* burst length=4, burst type=sequential, CAS latency=2 */
-	memctl->memc_mar = CFG_MAR;
+	memctl->memc_mar = CONFIG_SYS_MAR;
 
 	/*
 	 * Map controller bank 1 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
 	/* initialize memory address register */
-	memctl->memc_mbmr = CFG_MBMR_8COL; /* refresh not enabled yet */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL; /* refresh not enabled yet */
 
 	/* mode initialization (offset 5) */
 	udelay (200);				/* 0x80006105 */
@@ -132,7 +132,7 @@
 	/* Need at least 10 DRAM accesses to stabilize */
 	for (i = 0; i < 10; ++i) {
 		volatile unsigned long *addr =
-			(volatile unsigned long *) CFG_SDRAM_BASE;
+			(volatile unsigned long *) CONFIG_SYS_SDRAM_BASE;
 		unsigned long val;
 
 		val = *(addr + i);
@@ -144,22 +144,22 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MBMR_8COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
+	size8 = dram_size (CONFIG_SYS_MBMR_8COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
 
 	udelay (1000);
 
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MBMR_9COL, (long *)CFG_SDRAM_BASE, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MBMR_9COL, (long *)CONFIG_SYS_SDRAM_BASE, SDRAM_MAX_SIZE);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-		memctl->memc_mbmr = CFG_MBMR_9COL | MBMR_PTBE;
+		memctl->memc_mbmr = CONFIG_SYS_MBMR_9COL | MBMR_PTBE;
 		udelay (500);
 	} else {			/* back to 8 columns            */
 		size_b0 = size8;
-		memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+		memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 		udelay (500);
 	}
 
@@ -169,15 +169,15 @@
 
 	memctl->memc_or1 = ((-size_b0) & 0xFFFF0000) |
 			OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING;
-	memctl->memc_br1 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
+	memctl->memc_br1 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V;
 	udelay (1000);
 
 	/* initalize the DSP Host Port Interface */
 	hpi_init();
 
 	/* FRAM Setup */
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 	udelay(1000);
 
 	return (size_b0);
@@ -193,7 +193,7 @@
 static long int dram_size (long int mbmr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mbmr = mbmr_value;
@@ -207,7 +207,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* Set Go/NoGo led (PA15) to color red */
 	immap->im_ioport.iop_papar &= ~0x1;
@@ -240,7 +240,7 @@
 	immap->im_ioport.iop_pddat |= 0x0020;
 
 
-#ifdef CFG_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
+#ifdef CONFIG_SYS_SMC1_PLD_CLK4 /* SMC1 uses CLK4 from PLD */
 	immap->im_cpm.cp_simode |= 0x7000;
 	immap->im_cpm.cp_simode &= ~(0x8000);
 #endif
diff --git a/board/spd8xx/flash.c b/board/spd8xx/flash.c
index 8c0bb4f..fb2fb6a 100644
--- a/board/spd8xx/flash.c
+++ b/board/spd8xx/flash.c
@@ -24,7 +24,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*-----------------------------------------------------------------------
  */
diff --git a/board/spd8xx/spd8xx.c b/board/spd8xx/spd8xx.c
index 6387f8a..9e9678d 100644
--- a/board/spd8xx/spd8xx.c
+++ b/board/spd8xx/spd8xx.c
@@ -145,7 +145,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0;
 
@@ -153,23 +153,23 @@
 	/*
 	 * Map controller bank 2 to the SRAM bank at preliminary address.
 	 */
-	memctl->memc_or2 = CFG_OR2;
-	memctl->memc_br2 = CFG_BR2;
+	memctl->memc_or2 = CONFIG_SYS_OR2;
+	memctl->memc_br2 = CONFIG_SYS_BR2;
 #endif
 
 	/*
 	 * Map controller bank 4 to the PER8 bank.
 	 */
-	memctl->memc_or4 = CFG_OR4;
-	memctl->memc_br4 = CFG_BR4;
+	memctl->memc_or4 = CONFIG_SYS_OR4;
+	memctl->memc_br4 = CONFIG_SYS_BR4;
 
 #if 0
 	/* Configure SHARC at UMA */
 	upmconfig (UPMA, (uint *) sharc_table,
 		   sizeof (sharc_table) / sizeof (uint));
 	/* Map controller bank 5 to the SHARC */
-	memctl->memc_or5 = CFG_OR5;
-	memctl->memc_br5 = CFG_BR5;
+	memctl->memc_or5 = CONFIG_SYS_OR5;
+	memctl->memc_br5 = CONFIG_SYS_BR5;
 #endif
 
 	memctl->memc_mamr = 0x00001000;
@@ -178,17 +178,17 @@
 	upmconfig (UPMB, (uint *) sdram_table,
 		   sizeof (sdram_table) / sizeof (uint));
 
-	memctl->memc_mptpr = CFG_MPTPR_1BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_1BK_8K;
 
 	memctl->memc_mar = 0x00000088;
 
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or3 = CFG_OR3_PRELIM;
-	memctl->memc_br3 = CFG_BR3_PRELIM;
+	memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+	memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 
-	memctl->memc_mbmr = CFG_MBMR_8COL;	/* refresh not enabled yet */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL;	/* refresh not enabled yet */
 
 	udelay (200);
 	memctl->memc_mcr = 0x80806105;
@@ -205,10 +205,10 @@
 	 * Check Bank 0 Memory Size for re-configuration
 	 */
 	size_b0 =
-		dram_size (CFG_MBMR_8COL, SDRAM_BASE3_PRELIM,
+		dram_size (CONFIG_SYS_MBMR_8COL, SDRAM_BASE3_PRELIM,
 			   SDRAM_MAX_SIZE);
 
-	memctl->memc_mbmr = CFG_MBMR_8COL | MBMR_PTBE;
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_8COL | MBMR_PTBE;
 
 	return (size_b0);
 }
@@ -226,7 +226,7 @@
 static long int dram_size (long int mamr_value, long int *base,
 			   long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mbmr = mamr_value;
@@ -238,7 +238,7 @@
 
 void reset_phy (void)
 {
-	immap_t *immr = (immap_t *) CFG_IMMR;
+	immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 	ushort sreg;
 
 	/* Configure extra port pins for NS DP83843 PHY */
@@ -274,21 +274,21 @@
 
 void ide_set_reset (int on)
 {
-	volatile immap_t *immr = (immap_t *) CFG_IMMR;
+	volatile immap_t *immr = (immap_t *) CONFIG_SYS_IMMR;
 
 	/*
 	 * Configure PC for IDE Reset Pin
 	 */
 	if (on) {		/* assert RESET */
-		immr->im_ioport.iop_pcdat &= ~(CFG_PC_IDE_RESET);
+		immr->im_ioport.iop_pcdat &= ~(CONFIG_SYS_PC_IDE_RESET);
 	} else {		/* release RESET */
-		immr->im_ioport.iop_pcdat |= CFG_PC_IDE_RESET;
+		immr->im_ioport.iop_pcdat |= CONFIG_SYS_PC_IDE_RESET;
 	}
 
 	/* program port pin as GPIO output */
-	immr->im_ioport.iop_pcpar &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcso &= ~(CFG_PC_IDE_RESET);
-	immr->im_ioport.iop_pcdir |= CFG_PC_IDE_RESET;
+	immr->im_ioport.iop_pcpar &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcso &= ~(CONFIG_SYS_PC_IDE_RESET);
+	immr->im_ioport.iop_pcdir |= CONFIG_SYS_PC_IDE_RESET;
 }
 
 /* ------------------------------------------------------------------------- */
diff --git a/board/ssv/adnpesc1/adnpesc1.c b/board/ssv/adnpesc1/adnpesc1.c
index 71de208..9d32741 100644
--- a/board/ssv/adnpesc1/adnpesc1.c
+++ b/board/ssv/adnpesc1/adnpesc1.c
@@ -76,14 +76,14 @@
 
 void spi_cs_activate(struct spi_slave *slave)
 {
-	nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
+	nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE;
 
 	spi->slaveselect = SPI_RTC_CS_MASK;	/* activate (1) */
 }
 
 void spi_cs_deactivate(struct spi_slave *slave)
 {
-	nios_spi_t *spi = (nios_spi_t *)CFG_NIOS_SPIBASE;
+	nios_spi_t *spi = (nios_spi_t *)CONFIG_SYS_NIOS_SPIBASE;
 
 	spi->slaveselect = 0;			/* deactivate (0) */
 }
diff --git a/board/ssv/adnpesc1/config.mk b/board/ssv/adnpesc1/config.mk
index 7d8eb03..cf05445 100644
--- a/board/ssv/adnpesc1/config.mk
+++ b/board/ssv/adnpesc1/config.mk
@@ -22,7 +22,7 @@
 # MA 02111-1307 USA
 #
 
-TEXT_BASE = 0x02fc0000	# ATTENTION: notice your CFG_MONITOR_LEN setting
+TEXT_BASE = 0x02fc0000	# ATTENTION: notice your CONFIG_SYS_MONITOR_LEN setting
 
 ifeq ($(debug),1)
 PLATFORM_CPPFLAGS += -DDEBUG
diff --git a/board/ssv/adnpesc1/flash.c b/board/ssv/adnpesc1/flash.c
index 2614068..882630c 100644
--- a/board/ssv/adnpesc1/flash.c
+++ b/board/ssv/adnpesc1/flash.c
@@ -36,7 +36,7 @@
 /*---------------------------------------------------------------------*/
 #define	BANKSZ	(8 * 1024 * 1024)
 #define	SECTSZ	(64 * 1024)
-#define	UBOOTSECS ((CFG_MONITOR_LEN + CONFIG_ENV_SIZE) / SECTSZ)
+#define	UBOOTSECS ((CONFIG_SYS_MONITOR_LEN + CONFIG_ENV_SIZE) / SECTSZ)
 #define	UBOOTAREA (UBOOTSECS * 64 * 1024)	/* monitor / env area */
 
 /*---------------------------------------------------------------------*/
@@ -47,16 +47,16 @@
 	flash_info_t *fli = &flash_info[0];
 
 	fli->size = BANKSZ;
-	fli->sector_count = CFG_MAX_FLASH_SECT;
+	fli->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	fli->flash_id = FLASH_MAN_AMD + FLASH_AMLV640U;
 
-	addr = CFG_FLASH_BASE;
+	addr = CONFIG_SYS_FLASH_BASE;
 	for (i = 0; i < fli->sector_count; ++i) {
 		fli->start[i] = addr;
 		addr += SECTSZ;
 
 		/* Protect monitor / environment area */
-		if (addr <= (CFG_FLASH_BASE + UBOOTAREA))
+		if (addr <= (CONFIG_SYS_FLASH_BASE + UBOOTAREA))
 			fli->protect[i] = 1;
 		else
 			fli->protect[i] = 0;
diff --git a/board/ssv/adnpesc1/vectors.S b/board/ssv/adnpesc1/vectors.S
index fb7e17e..8b2da2f 100644
--- a/board/ssv/adnpesc1/vectors.S
+++ b/board/ssv/adnpesc1/vectors.S
@@ -57,12 +57,12 @@
 	.align	4
 _vectors:
 
-#if	defined(CFG_NIOS_CPU_OCI_BASE)
+#if	defined(CONFIG_SYS_NIOS_CPU_OCI_BASE)
 	/* OCI does the reset job */
 	.long	_def_xhandler@h		/* Vector 0  - NMI / Reset */
 #else
 	/* there is no OCI, so we have to do a direct reset jump here */
-	.long	CFG_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
+	.long	CONFIG_SYS_NIOS_CPU_RST_VECT	/* Vector 0  - Reset to GERMS */
 #endif
 	.long	_cwp_lolimit@h		/* Vector 1  - underflow */
 	.long	_cwp_hilimit@h		/* Vector 2  - overflow	*/
@@ -80,7 +80,7 @@
 	.long	_def_xhandler@h		/* Vector 13 - future reserved */
 	.long	_def_xhandler@h		/* Vector 14 - future reserved */
 	.long	_def_xhandler@h		/* Vector 15 - future reserved */
-#if	(CFG_NIOS_TMRIRQ == 16)
+#if	(CONFIG_SYS_NIOS_TMRIRQ == 16)
 	.long	_timebase_int@h		/* Vector 16 - lopri timer*/
 #else
 	.long	_def_xhandler@h		/* Vector 16 */
@@ -118,7 +118,7 @@
 	.long	_def_xhandler@h		/* Vector 47 */
 	.long	_def_xhandler@h		/* Vector 48 */
 	.long	_def_xhandler@h		/* Vector 49 */
-#if	(CFG_NIOS_TMRIRQ == 50)
+#if	(CONFIG_SYS_NIOS_TMRIRQ == 50)
 	.long	_timebase_int@h		/* Vector 50 - lopri timer*/
 #else
 	.long	_def_xhandler@h		/* Vector 50 */
diff --git a/board/ssv/common/flash.c b/board/ssv/common/flash.c
index 70cab7f..70bf9d6 100644
--- a/board/ssv/common/flash.c
+++ b/board/ssv/common/flash.c
@@ -29,7 +29,7 @@
 #include <watchdog.h>
 #include <nios.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 /*--------------------------------------------------------------------*/
 void flash_print_info (flash_info_t * info)
@@ -72,8 +72,8 @@
 
 int flash_erase (flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int prot, sect, wait;
 	unsigned oldpri;
 	ulong start;
@@ -116,7 +116,7 @@
 	 */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 			*addr = 0xf0;
 			*(addr+0xAAA/2) = 0xaa;
 			*(addr+0x554/2) = 0x55;
@@ -135,7 +135,7 @@
 					udelay (125 * 1000);
 				}
 				putc ('.');
-				if (get_timer (start) > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer (start) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("timeout\n");
 					return 1;
 				}
@@ -163,14 +163,14 @@
 int write_buff (flash_info_t * info, uchar * srcbuffer, ulong addr, ulong cnt)
 {
 
-	volatile CFG_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0];
-	volatile CFG_FLASH_WORD_SIZE *dst = (vu_short *) addr;
-	CFG_FLASH_WORD_SIZE *src = (void *) srcbuffer;
-	CFG_FLASH_WORD_SIZE b;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *cmd = (vu_short *) info->start[0];
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dst = (vu_short *) addr;
+	CONFIG_SYS_FLASH_WORD_SIZE *src = (void *) srcbuffer;
+	CONFIG_SYS_FLASH_WORD_SIZE b;
 	unsigned oldpri;
 	ulong start;
 
-	cnt /= sizeof(CFG_FLASH_WORD_SIZE);
+	cnt /= sizeof(CONFIG_SYS_FLASH_WORD_SIZE);
 	while (cnt) {
 		/* Check for sufficient erase */
 		b = *src;
@@ -192,7 +192,7 @@
 		/* Verify write */
 		start = get_timer (0);
 		while (*dst != b) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				*cmd = 0xf0;
 				return 1;
 			}
diff --git a/board/ssv/common/post.c b/board/ssv/common/post.c
index a5f29c1..c7a9ccc 100644
--- a/board/ssv/common/post.c
+++ b/board/ssv/common/post.c
@@ -25,19 +25,19 @@
 
 #if defined(CONFIG_POST) || defined(CONFIG_LOGBUFFER)
 
-#if !defined(CFG_NIOS_POST_WORD_ADDR)
-#error "*** CFG_NIOS_POST_WORD_ADDR not defined ***"
+#if !defined(CONFIG_SYS_NIOS_POST_WORD_ADDR)
+#error "*** CONFIG_SYS_NIOS_POST_WORD_ADDR not defined ***"
 #endif
 
 void post_word_store (ulong a)
 {
-	volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+	volatile void *save_addr = (void *)(CONFIG_SYS_NIOS_POST_WORD_ADDR);
 	*(volatile ulong *) save_addr = a;
 }
 
 ulong post_word_load (void)
 {
-	volatile void *save_addr = (void *)(CFG_NIOS_POST_WORD_ADDR);
+	volatile void *save_addr = (void *)(CONFIG_SYS_NIOS_POST_WORD_ADDR);
 	return *(volatile ulong *) save_addr;
 }
 
diff --git a/board/stxgp3/flash.c b/board/stxgp3/flash.c
index 1433491..61c9602 100644
--- a/board/stxgp3/flash.c
+++ b/board/stxgp3/flash.c
@@ -37,13 +37,13 @@
 
 #include <common.h>
 
-#if !defined(CFG_NO_FLASH)
+#if !defined(CONFIG_SYS_NO_FLASH)
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -72,7 +72,7 @@
 	/* Init: enable write,
 	 * or we cannot even write flash commands
 	 */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 
 		/* set the default sector offset */
@@ -80,7 +80,7 @@
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
@@ -88,15 +88,15 @@
 	}
 
 	/* Re-do sizing to get full correct info */
-	size = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 
 #ifdef	CONFIG_ENV_IS_IN_FLASH
@@ -329,7 +329,7 @@
 					asm("sync");
 					return 1;
 				}
-				if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+				if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = 0xFFFFFFFF;	/* reset bank */
 					asm("sync");
@@ -458,7 +458,7 @@
 	flag  = 0;
 
 	while (((csr = *addr) & 0x00800080) != 0x00800080) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			flag = 1;
 			break;
 		}
@@ -502,7 +502,7 @@
 
 	start = get_timer (0);
 	while((*addr & 0x00800080) != 0x00800080){
-		if ((now=get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now=get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout on clearing Block Lock Bit\n");
 			*addr = 0xFFFFFFFF;	/* reset bank */
 			asm("sync");
@@ -512,4 +512,4 @@
 	return 0;
 }
 
-#endif /* !CFG_NO_FLASH */
+#endif /* !CONFIG_SYS_NO_FLASH */
diff --git a/board/stxgp3/law.c b/board/stxgp3/law.c
index a7e9ceb..ba89f0e 100644
--- a/board/stxgp3/law.c
+++ b/board/stxgp3/law.c
@@ -46,13 +46,13 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
 	/* This is not so much the SDRAM map as it is the whole localbus map. */
-	SET_LAW(CFG_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxgp3/stxgp3.c b/board/stxgp3/stxgp3.c
index c80f1b3..3804fe0 100644
--- a/board/stxgp3/stxgp3.c
+++ b/board/stxgp3/stxgp3.c
@@ -203,7 +203,7 @@
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-    volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+    volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
     pci->peer &= 0xfffffffdf; /* disable master abort */
 #endif
@@ -215,7 +215,7 @@
 {
 	volatile uint *blatch;
 
-	blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
+	blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
 
 	/* reset Giga bit Ethernet port if needed here */
 
@@ -267,7 +267,7 @@
 	if (next_led_update > get_ticks())
 		return;
 
-	blatch = (volatile uint *)CFG_LBC_LCLDEVS_BASE;
+	blatch = (volatile uint *)CONFIG_SYS_LBC_LCLDEVS_BASE;
 
 	led_bit >>= 1;
 	if (led_bit == 0)
@@ -284,7 +284,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */
@@ -308,11 +308,11 @@
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c
index d410416..aa11a5d 100644
--- a/board/stxgp3/tlb.c
+++ b/board/stxgp3/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xff000000	16M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_16M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -87,7 +87,7 @@
 	 * 0xe000_0000	1M	CCSRBAR
 	 * 0xe200_0000	16M	PCI1 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -95,7 +95,7 @@
 	 * TLB 6:	64M	Cacheable, non-guarded
 	 * 0xf000_0000	64M	LBC SDRAM
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_SDRAM_BASE, CFG_LBC_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -103,7 +103,7 @@
 	 * TLB 7:	16K	Non-cacheable, guarded
 	 * 0xfc000000	16K	Configuration Latch register
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_LCLDEVS_BASE, CFG_LBC_LCLDEVS_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_LCLDEVS_BASE, CONFIG_SYS_LBC_LCLDEVS_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_16K, 1),
 
@@ -117,11 +117,11 @@
 	 * Likely it needs to be increased by two for these entries.
 	 */
 #error("Update the number of table entries in tlb1_entry")
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 8, BOOKE_PAGESZ_64M, 1),
 
-	SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x4000000, CFG_DDR_SDRAM_BASE + 0x4000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 9, BOOKE_PAGESZ_64M, 1),
 #endif
diff --git a/board/stxssa/law.c b/board/stxssa/law.c
index 8730cdf..55dde66 100644
--- a/board/stxssa/law.c
+++ b/board/stxssa/law.c
@@ -47,14 +47,14 @@
 
 struct law_entry law_table[] = {
 #ifndef CONFIG_SPD_EEPROM
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_128M, LAW_TRGT_IF_DDR),
 #endif
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
-	SET_LAW(CFG_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI_2),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_1),
+	SET_LAW(CONFIG_SYS_PCI2_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI_2),
 	/* Map the whole localbus, including flash and reset latch. */
-	SET_LAW(CFG_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_LBC_OPTION_BASE, LAWAR_SIZE_256M, LAW_TRGT_IF_LBC),
 };
 
 int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/stxssa/stxssa.c b/board/stxssa/stxssa.c
index 4d4dc06..73dddf3 100644
--- a/board/stxssa/stxssa.c
+++ b/board/stxssa/stxssa.c
@@ -207,7 +207,7 @@
 #if 0
 	int	i;
 #endif
-	blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
 
 	/* reset Giga bit Ethernet port if needed here */
 
@@ -253,7 +253,7 @@
 board_early_init_f(void)
 {
 #if defined(CONFIG_PCI)
-	volatile ccsr_pcix_t *pci = (void *)(CFG_MPC85xx_PCIX_ADDR);
+	volatile ccsr_pcix_t *pci = (void *)(CONFIG_SYS_MPC85xx_PCIX_ADDR);
 
 	pci->peer &= 0xffffffdf; /* disable master abort */
 #endif
@@ -284,7 +284,7 @@
 	if (next_led_update > get_ticks())
 		return;
 
-	blatch = (volatile uint *)CFG_LBC_CFGLATCH_BASE;
+	blatch = (volatile uint *)CONFIG_SYS_LBC_CFGLATCH_BASE;
 
 	led_bit >>= 1;
 	if (led_bit == 0)
@@ -301,7 +301,7 @@
 
 #if defined(CONFIG_DDR_DLL)
 	{
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 		uint temp_ddrdll = 0;
 
 		/* Work around to stabilize DDR DLL */
@@ -325,11 +325,11 @@
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf("SDRAM test phase 1:\n");
diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c
index 86cbd11..0386432 100644
--- a/board/stxssa/tlb.c
+++ b/board/stxssa/tlb.c
@@ -28,16 +28,16 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		      MAS3_SX|MAS3_SW|MAS3_SR, 0,
 		      0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -46,7 +46,7 @@
 	 * 0xfc000000	6M4	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -54,7 +54,7 @@
 	 * TLB 1:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 1, BOOKE_PAGESZ_256M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,7 +70,7 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0xa0000000	256M	PCI2 MEM First half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS, CFG_PCI2_MEM_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS, CONFIG_SYS_PCI2_MEM_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -78,7 +78,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	PCI2 MEM Second half
 	 */
-	SET_TLB_ENTRY(1, CFG_PCI2_MEM_PHYS + 0x10000000, CFG_PCI2_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY(1, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI2_MEM_PHYS + 0x10000000,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,7 +88,7 @@
 	 * 0xe200_0000	16M	PCI1 IO
 	 * 0xe300_0000	16M	PCI2 IO
 	 */
-	SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 5, BOOKE_PAGESZ_64M, 1),
 
@@ -98,7 +98,7 @@
 	 * 0xfb000000		Configuration Latch register (one word)
 	 * 0xfc000000		Up to 64M flash
 	 */
-	SET_TLB_ENTRY(1, CFG_LBC_OPTION_BASE, CFG_LBC_OPTION_BASE,
+	SET_TLB_ENTRY(1, CONFIG_SYS_LBC_OPTION_BASE, CONFIG_SYS_LBC_OPTION_BASE,
 		      MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 		      0, 7, BOOKE_PAGESZ_256M, 1),
 };
diff --git a/board/stxxtc/stxxtc.c b/board/stxxtc/stxxtc.c
index 4bb2d68..a1a36c4 100644
--- a/board/stxxtc/stxxtc.c
+++ b/board/stxxtc/stxxtc.c
@@ -349,7 +349,7 @@
 #define MAR_SDRAM_INIT		((CAS_LATENCY << 6) | 0x00000008LU)
 
 /* 9 */
-#define CFG_MAMR	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+#define CONFIG_SYS_MAMR	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
 			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
 			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
 
@@ -401,7 +401,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size;
 	u32 d1, d2;
@@ -418,10 +418,10 @@
 	/*
 	 * Map controller bank 3 to the SDRAM bank at preliminary address.
 	 */
-	memctl->memc_or4 = CFG_OR4_PRELIM;
-	memctl->memc_br4 = CFG_BR4_PRELIM;
+	memctl->memc_or4 = CONFIG_SYS_OR4_PRELIM;
+	memctl->memc_br4 = CONFIG_SYS_BR4_PRELIM;
 
-	memctl->memc_mamr = CFG_MAMR & ~MAMR_PTAE;	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR & ~MAMR_PTAE;	/* no refresh yet */
 
 	udelay(200);
 
@@ -529,7 +529,7 @@
 
 int board_early_init_f(void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile iop8xx_t *ioport = &immap->im_ioport;
 	volatile cpm8xx_t *cpm = &immap->im_cpm;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
@@ -579,13 +579,13 @@
 #include <linux/mtd/nand_legacy.h>
 
 extern ulong nand_probe(ulong physadr);
-extern struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE];
+extern struct nand_chip nand_dev_desc[CONFIG_SYS_MAX_NAND_DEVICE];
 
 void nand_init(void)
 {
 	unsigned long totlen;
 
-	totlen = nand_probe(CFG_NAND_BASE);
+	totlen = nand_probe(CONFIG_SYS_NAND_BASE);
 	printf ("%4lu MB\n", totlen >> 20);
 }
 #endif
@@ -599,7 +599,7 @@
 
 #endif
 
-#if defined(CFG_CONSOLE_IS_IN_ENV) && defined(CFG_CONSOLE_OVERWRITE_ROUTINE)
+#if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)
 int overwrite_console(void)
 {
 	/* printf("overwrite_console called\n"); */
diff --git a/board/svm_sc8xx/flash.c b/board/svm_sc8xx/flash.c
index 00fed59..db1f21a 100644
--- a/board/svm_sc8xx/flash.c
+++ b/board/svm_sc8xx/flash.c
@@ -24,10 +24,10 @@
 #include <mpc8xx.h>
 
 #ifndef	CONFIG_ENV_ADDR
-#define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 #endif
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -54,7 +54,7 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
@@ -62,16 +62,16 @@
 	size_b0=0;
 	size_b1=0;
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
-#ifdef CFG_DOC_BASE
+#ifdef CONFIG_SYS_DOC_BASE
 #ifndef CONFIG_FEL8xx_AT
-	memctl->memc_or5 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */
-	memctl->memc_br5 = CFG_DOC_BASE | 0x401;
+	memctl->memc_or5 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br5 = CONFIG_SYS_DOC_BASE | 0x401;
 #else
-	memctl->memc_or3 = (0xffff8000 | CFG_OR_TIMING_DOC ); /* 32k bytes */
-	memctl->memc_br3 = CFG_DOC_BASE | 0x401;
+	memctl->memc_or3 = (0xffff8000 | CONFIG_SYS_OR_TIMING_DOC ); /* 32k bytes */
+	memctl->memc_br3 = CONFIG_SYS_DOC_BASE | 0x401;
 #endif
 #endif
 #if defined( CONFIG_BOOT_8B)
@@ -136,19 +136,19 @@
 	}
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -161,21 +161,21 @@
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & 0xFFFF8000);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				    BR_MS_GPCM | BR_V;
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 #endif
 
@@ -561,7 +561,7 @@
 # error CONFIG_BOOT_(size)B missing.
 #endif
 	{
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -710,7 +710,7 @@
 	  start = get_timer (0);
 	last  = start;
 	  while(  ( my_in_8((unsigned char *) (dest+i)) ) != ( data_ch[i]  ) ) {
-		  if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) {
+		  if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
 			  return 1;
 		  }
 	  }
@@ -730,7 +730,7 @@
 	  start = get_timer (0);
 	last  = start;
 	  while(  ( my_in_be16((unsigned short *) (dest+(i*2))) ) != ( data_short[i]  ) ) {
-		  if (get_timer(start) > CFG_FLASH_WRITE_TOUT ) {
+		  if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT ) {
 			  return 1;
 		  }
 	  }
@@ -749,7 +749,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/svm_sc8xx/svm_sc8xx.c b/board/svm_sc8xx/svm_sc8xx.c
index 48e05b8..4390e49 100644
--- a/board/svm_sc8xx/svm_sc8xx.c
+++ b/board/svm_sc8xx/svm_sc8xx.c
@@ -102,15 +102,15 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size_b0 = 0;
 
 	upmconfig(UPMA, (uint *)sdram_table, sizeof(sdram_table)/sizeof(uint));
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 #if defined (CONFIG_SDRAM_16M)
-	memctl->memc_mamr = 0x00802114 | CFG_MxMR_PTx;
+	memctl->memc_mamr = 0x00802114 | CONFIG_SYS_MxMR_PTx;
 	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 	udelay(1);
 	memctl->memc_mcr  = 0x80002830;
@@ -122,7 +122,7 @@
 	memctl->memc_or1 =  0xff000a00;
 	size_b0 = 0x01000000;
 #elif defined (CONFIG_SDRAM_32M)
-	memctl->memc_mamr = 0x00904114 | CFG_MxMR_PTx;
+	memctl->memc_mamr = 0x00904114 | CONFIG_SYS_MxMR_PTx;
 	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 	udelay(1);
 	memctl->memc_mcr  = 0x80002830;
@@ -134,7 +134,7 @@
 	memctl->memc_or1 =  0xfe000a00;
 	size_b0 = 0x02000000;
 #elif defined (CONFIG_SDRAM_64M)
-	memctl->memc_mamr = 0x00a04114 | CFG_MxMR_PTx;
+	memctl->memc_mamr = 0x00a04114 | CONFIG_SYS_MxMR_PTx;
 	memctl->memc_mcr  = 0x80002105;     /* SDRAM bank 0 */
 	udelay(1);
 	memctl->memc_mcr  = 0x80002830;
@@ -156,6 +156,6 @@
 #if defined(CONFIG_CMD_DOC)
 void doc_init (void)
 {
-	        doc_probe (CFG_DOC_BASE);
+	        doc_probe (CONFIG_SYS_DOC_BASE);
 }
 #endif
diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c
index e9f6418..933d5ec 100644
--- a/board/tb0229/flash.c
+++ b/board/tb0229/flash.c
@@ -27,10 +27,10 @@
 #include <ppc4xx.h>
 #include <asm/processor.h>
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips        */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips        */
 
 
-#ifdef CFG_FLASH_16BIT
+#ifdef CONFIG_SYS_FLASH_16BIT
 #define FLASH_WORD_SIZE	unsigned short
 #define	FLASH_ID_MASK	0xFFFF
 #else
@@ -44,7 +44,7 @@
 /* stolen from esteem192e/flash.c */
 ulong flash_get_size (volatile FLASH_WORD_SIZE * addr, flash_info_t * info);
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t * info, ulong dest, ulong data);
 #else
 static int write_short (flash_info_t * info, ulong dest, ushort data);
@@ -63,14 +63,14 @@
 	unsigned long base_b0, base_b1;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here - FIXME XXX */
 
 	size_b0 =
-		flash_get_size ((volatile FLASH_WORD_SIZE *) CFG_FLASH_BASE,
+		flash_get_size ((volatile FLASH_WORD_SIZE *) CONFIG_SYS_FLASH_BASE,
 				&flash_info[0]);
 
 	if (flash_info[0].flash_id == FLASH_UNKNOWN) {
@@ -78,9 +78,9 @@
 	}
 
 	/* Only one bank */
-	if (CFG_MAX_FLASH_BANKS == 1) {
+	if (CONFIG_SYS_MAX_FLASH_BANKS == 1) {
 		/* Setup offsets */
-		flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 		/* Monitor protection ON by default */
 #if 0				/* sand: */
@@ -91,19 +91,19 @@
 				      &flash_info[0]);
 #else
 		(void) flash_protect (FLAG_PROTECT_SET,
-				      CFG_MONITOR_BASE,
-				      CFG_MONITOR_BASE + monitor_flash_len -
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
 				      1, &flash_info[0]);
 #endif
 		size_b1 = 0;
 		flash_info[0].size = size_b0;
 	}
-#ifdef CFG_FLASH_BASE_2
+#ifdef CONFIG_SYS_FLASH_BASE_2
 	/* 2 banks */
 	else {
 		size_b1 =
 			flash_get_size ((volatile FLASH_WORD_SIZE *)
-					CFG_FLASH_BASE_2, &flash_info[1]);
+					CONFIG_SYS_FLASH_BASE_2, &flash_info[1]);
 
 		/* Re-do sizing to get full correct info */
 
@@ -144,8 +144,8 @@
 				      &flash_info[0]);
 #else
 		(void) flash_protect (FLAG_PROTECT_SET,
-				      CFG_MONITOR_BASE,
-				      CFG_MONITOR_BASE + monitor_flash_len -
+				      CONFIG_SYS_MONITOR_BASE,
+				      CONFIG_SYS_MONITOR_BASE + monitor_flash_len -
 				      1, &flash_info[0]);
 #endif
 
@@ -200,7 +200,7 @@
 	} else if (info->flash_id & FLASH_BTYPE) {
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			/* set sector offsets for bottom boot block type        */
 			info->start[0] = base + 0x00000000;
 			info->start[1] = base + 0x00004000;
@@ -256,7 +256,7 @@
 		i = info->sector_count - 1;
 		if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			info->start[i--] = base + info->size - 0x00004000;
 			info->start[i--] = base + info->size - 0x00008000;
 			info->start[i--] = base + info->size - 0x0000C000;
@@ -448,7 +448,7 @@
 	/* Write auto select command: read Manufacturer ID */
 
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 	/*
 	 * Note: if it is an AMD flash and the word at addr[0000]
@@ -699,7 +699,7 @@
 	/* Disable interrupts which might cause a timeout here */
 	flag = disable_interrupts ();
 	if (info->flash_id < FLASH_AMD_COMP) {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 		addr[0x0555] = 0x00AA00AA;
 		addr[0x02AA] = 0x00550055;
 		addr[0x0555] = 0x00800080;
@@ -741,7 +741,7 @@
 		addr = (volatile FLASH_WORD_SIZE *) (info->start[l_sect]);
 		while ((addr[0] & (0x00800080 & FLASH_ID_MASK)) !=
 		       (0x00800080 & FLASH_ID_MASK)) {
-			if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+			if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 				printf ("Timeout\n");
 				return 1;
 			}
@@ -762,7 +762,7 @@
 		for (sect = s_first; sect <= s_last; sect++) {
 			if (info->protect[sect] == 0) {	/* not protected */
 				barf = 0;
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 				addr = (vu_long *) (info->start[sect]);
 				addr[0] = 0x00500050;
 				addr[0] = 0x00200020;
@@ -801,7 +801,7 @@
 				l_sect = sect;
 			}
 			addr = (volatile FLASH_WORD_SIZE *) info->start[0];
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 			addr[0] = (0x00FF00FF & FLASH_ID_MASK);	/* reset bank */
 #else
 			addr[0] = (0x00FF & FLASH_ID_MASK);	/* reset bank */
@@ -821,7 +821,7 @@
 	flash_info_t *info;
 	int i;
 
-	for (i=0, info=&flash_info[0]; i<CFG_MAX_FLASH_BANKS; ++i, ++info) {
+	for (i=0, info=&flash_info[0]; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i, ++info) {
 		if ((addr >= info->start[0]) &&
 		    (addr < (info->start[0] + info->size)) ) {
 			return (info);
@@ -898,7 +898,7 @@
 
 int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt)
 {
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 	ulong cp, wp, data;
 	int l;
 #else
@@ -907,7 +907,7 @@
 #endif
 	int i, rc;
 
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 
 
 	wp = (addr & ~3);	/* get lower word aligned address */
@@ -1034,7 +1034,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifndef CFG_FLASH_16BIT
+#ifndef CONFIG_SYS_FLASH_16BIT
 static int write_word (flash_info_t * info, ulong dest, ulong data)
 {
 	vu_long *addr = (vu_long *) (info->start[0]);
@@ -1076,7 +1076,7 @@
 
 		while ((*((vu_long *) dest) & 0x00800080) !=
 		       (data & 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				printf ("timeout\n");
 				return (1);
 			}
@@ -1085,7 +1085,7 @@
 	} else {
 
 		while (!(addr[0] & 0x00800080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				printf ("timeout\n");
 				return (1);
 			}
@@ -1157,7 +1157,7 @@
 	if (info->flash_id < FLASH_AMD_COMP) {
 		/* AMD stuff */
 		while ((*((vu_short *) dest) & 0x0080) != (data & 0x0080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -1165,7 +1165,7 @@
 	} else {
 		/* intel stuff */
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 
@@ -1184,7 +1184,7 @@
 		*addr = 0x00B0;
 		*addr = 0x0070;
 		while (!(addr[0] & 0x0080)) {	/* wait for error or finish */
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 
diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c
index 2abb4a7..d3f05b2 100644
--- a/board/tb0229/tb0229.c
+++ b/board/tb0229/tb0229.c
@@ -34,7 +34,7 @@
 
 phys_size_t initdram(int board_type)
 {
-	return get_ram_size (CFG_SDRAM_BASE, 0x8000000);
+	return get_ram_size (CONFIG_SYS_SDRAM_BASE, 0x8000000);
 }
 
 int checkboard (void)
diff --git a/board/total5200/sdram.c b/board/total5200/sdram.c
index a1601f2..dc4c6f1 100644
--- a/board/total5200/sdram.c
+++ b/board/total5200/sdram.c
@@ -29,7 +29,7 @@
 
 #include "sdram.h"
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void mpc5xxx_sdram_start (sdram_conf_t *sdram_conf, int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -72,7 +72,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *            use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *            use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *            is something else than 0x00000000.
  */
 
@@ -81,7 +81,7 @@
 {
 	ulong dramsize = 0;
 	ulong dramsize2 = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -102,9 +102,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	mpc5xxx_sdram_start(sdram_conf, 0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	mpc5xxx_sdram_start(sdram_conf, 1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		mpc5xxx_sdram_start(sdram_conf, 0);
 		dramsize = test1;
@@ -129,9 +129,9 @@
 
 	/* find RAM size using SDRAM CS1 only */
 	mpc5xxx_sdram_start(sdram_conf, 0);
-	test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	mpc5xxx_sdram_start(sdram_conf, 1);
-	test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (test1 > test2) {
 		mpc5xxx_sdram_start(sdram_conf, 0);
 		dramsize2 = test1;
@@ -152,7 +152,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -170,7 +170,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize + dramsize2;
 }
@@ -180,7 +180,7 @@
 long int mpc5xxx_sdram_init (sdram_conf_t *sdram_conf)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup and enable SDRAM chip selects */
@@ -199,9 +199,9 @@
 
 	/* find RAM size */
 	mpc5xxx_sdram_start(sdram_conf, 0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	mpc5xxx_sdram_start(sdram_conf, 1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		mpc5xxx_sdram_start(sdram_conf, 0);
 		dramsize = test1;
@@ -212,12 +212,12 @@
 	/* set SDRAM end address according to size */
 	*(vu_long *)MPC5XXX_SDRAM_STOP = ((dramsize - 1) >> 15);
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* Retrieve amount of SDRAM available */
 	dramsize = ((*(vu_long *)MPC5XXX_SDRAM_STOP + 1) << 15);
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	return dramsize;
 }
diff --git a/board/total5200/total5200.c b/board/total5200/total5200.c
index ec00a67..c524d63 100644
--- a/board/total5200/total5200.c
+++ b/board/total5200/total5200.c
@@ -71,15 +71,15 @@
 	/*
 	 * Retrieve FPGA Revision.
 	 */
-	printf ("(FPGA %08lX)\n", *(vu_long *) (CFG_FPGA_BASE + 0x400));
+	printf ("(FPGA %08lX)\n", *(vu_long *) (CONFIG_SYS_FPGA_BASE + 0x400));
 
 	/*
 	 * Take all peripherals in power-up mode.
 	 */
 #if CONFIG_TOTAL5200_REV==2
-	*(vu_char *) (CFG_CPLD_BASE + 0x46) = 0x70;
+	*(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x46) = 0x70;
 #else
-	*(vu_long *) (CFG_CPLD_BASE + 0x400) = 0x70;
+	*(vu_long *) (CONFIG_SYS_CPLD_BASE + 0x400) = 0x70;
 #endif
 
 	return 0;
@@ -284,7 +284,7 @@
 /* Returns  SED13806 base address. First thing called in the driver. */
 unsigned int board_video_init (void)
 {
-	return CFG_LCD_BASE;
+	return CONFIG_SYS_LCD_BASE;
 }
 
 /* Called after initializing the SED13806 and before clearing the screen. */
diff --git a/board/tqc/tqm5200/cam5200_flash.c b/board/tqc/tqm5200/cam5200_flash.c
index 4fc4dc6..124b47d 100644
--- a/board/tqc/tqm5200/cam5200_flash.c
+++ b/board/tqc/tqm5200/cam5200_flash.c
@@ -35,7 +35,7 @@
 
 #define swap16(x) __swab16(x)
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips */
 
 /*
  * CAM5200 is a TQM5200B based board. Additionally it also features
@@ -51,15 +51,15 @@
  * 16 bit flash bank and two sets of routines *_32 and *_16 to handle
  * specifics of both flashes.
  */
-static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = {
-	{CFG_BOOTCS_START, CFG_CS5_START | 1}
+static unsigned long flash_addr_table[][CONFIG_SYS_MAX_FLASH_BANKS] = {
+	{CONFIG_SYS_BOOTCS_START, CONFIG_SYS_CS5_START | 1}
 };
 
 /*-----------------------------------------------------------------------
  * Functions
  */
 static int write_word(flash_info_t * info, ulong dest, ulong data);
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word_32(flash_info_t * info, ulong dest, ulong data);
 static int write_word_16(flash_info_t * info, ulong dest, ulong data);
 static int flash_erase_32(flash_info_t * info, int s_first, int s_last);
@@ -145,7 +145,7 @@
 /*
  * The following code cannot be run from FLASH!
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static ulong flash_get_size(vu_long * addr, flash_info_t * info)
 {
 
@@ -164,23 +164,23 @@
 #endif
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("get_size32: FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00900090;
 	udelay(1000);
 
 	value = addr2[0];
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 			info->flash_id = FLASH_MAN_AMD;
 			break;
 		default:
@@ -228,13 +228,13 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		info->protect[i] = addr2[2] & 1;
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;
 
 	return (info->size);
 }
@@ -242,14 +242,14 @@
 static int wait_for_DQ7_32(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-			(CFG_FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -262,7 +262,7 @@
 	return 0;
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 {
 	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
@@ -277,8 +277,8 @@
 int flash_erase(flash_info_t * info, int s_first, int s_last)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 
 	if ((s_first < 0) || (s_first > s_last)) {
@@ -313,14 +313,14 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00300030;	/* sector erase */
 
 			l_sect = sect;
 			/*
@@ -342,8 +342,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00F000F0;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -423,7 +423,7 @@
  * 1 - write timeout
  * 2 - Flash not erased
  */
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 {
 	if ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) {
@@ -438,9 +438,9 @@
 static int write_word(flash_info_t * info, ulong dest, ulong data)
 #endif
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i, flag;
 
@@ -448,13 +448,13 @@
 	if ((*((vu_long *)dest) & data) != data)
 		return (2);
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00AA00AA;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00550055;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x00A000A0;
 
 		dest2[i] = data2[i];
 
@@ -464,10 +464,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) !=
-				(data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080) !=
+				(data2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT)
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT)
 				return (1);
 		}
 	}
@@ -475,10 +475,10 @@
 	return (0);
 }
 
-#ifdef CFG_FLASH_2ND_16BIT_DEV
+#ifdef CONFIG_SYS_FLASH_2ND_16BIT_DEV
 
-#undef  CFG_FLASH_WORD_SIZE
-#define CFG_FLASH_WORD_SIZE unsigned short
+#undef  CONFIG_SYS_FLASH_WORD_SIZE
+#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
 
 /*
  * The following code cannot be run from FLASH!
@@ -486,29 +486,29 @@
 static ulong flash_get_size_16(vu_long * addr, flash_info_t * info)
 {
 	short i;
-	CFG_FLASH_WORD_SIZE value;
+	CONFIG_SYS_FLASH_WORD_SIZE value;
 	ulong base = (ulong) addr;
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) addr;
 
 	DEBUGF("get_size16: FLASH ADDR: %08x\n", (unsigned)addr);
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
 
 	/* Write auto select command: read Manufacturer ID */
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
-	addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
-	addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90009000;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+	addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+	addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x90009000;
 	udelay(1000);
 
 	value = swap16(addr2[0]);
 	DEBUGF("FLASH MANUFACT: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) AMD_MANUFACT:
 			info->flash_id = FLASH_MAN_AMD;
 			break;
-		case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT:
+		case (CONFIG_SYS_FLASH_WORD_SIZE) FUJ_MANUFACT:
 			info->flash_id = FLASH_MAN_FUJ;
 			break;
 		default:
@@ -522,12 +522,12 @@
 	DEBUGF("\nFLASH DEVICEID: %x\n", value);
 
 	switch (value) {
-		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320B:
 			info->flash_id += FLASH_AM320B;
 			info->sector_count = 71;
 			info->size = 0x00400000;
 			break;	/* => 4 MB	*/
-		case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T:
+		case (CONFIG_SYS_FLASH_WORD_SIZE)AMD_ID_LV320T:
 			info->flash_id += FLASH_AM320T;
 			info->sector_count = 71;
 			info->size = 0x00400000;
@@ -569,13 +569,13 @@
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
 		/* D0 = 1 if protected */
-		addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]);
+		addr2 = (volatile CONFIG_SYS_FLASH_WORD_SIZE *)(info->start[i]);
 
 		info->protect[i] = addr2[2] & 1;
 	}
 
 	/* issue bank reset to return to read mode */
-	addr2[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;
+	addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;
 
 	return (info->size);
 }
@@ -583,14 +583,14 @@
 static int wait_for_DQ7_16(flash_info_t * info, int sect)
 {
 	ulong start, now, last;
-	volatile CFG_FLASH_WORD_SIZE *addr =
-		(CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr =
+		(CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
 	start = get_timer(0);
 	last = start;
-	while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
-			(CFG_FLASH_WORD_SIZE) 0x80008000) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+	while ((addr[0] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+			(CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf("Timeout\n");
 			return -1;
 		}
@@ -605,8 +605,8 @@
 
 static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *addr2;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
 	int flag, prot, sect, l_sect;
 
 	if ((s_first < 0) || (s_first > s_last)) {
@@ -641,14 +641,14 @@
 	/* Start erase on unprotected sectors */
 	for (sect = s_first; sect <= s_last; sect++) {
 		if (info->protect[sect] == 0) {	/* not protected */
-			addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]);
+			addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
 
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x80008000;
-			addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
-			addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
-			addr2[0] = (CFG_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
+			addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+			addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+			addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000;	/* sector erase */
 
 			l_sect = sect;
 			/*
@@ -670,8 +670,8 @@
 	udelay(1000);
 
 	/* reset to read mode */
-	addr = (CFG_FLASH_WORD_SIZE *) info->start[0];
-	addr[0] = (CFG_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
+	addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
+	addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000;	/* reset bank */
 
 	printf(" done\n");
 	return 0;
@@ -679,27 +679,27 @@
 
 static int write_word_16(flash_info_t * info, ulong dest, ulong data)
 {
-	volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]);
-	volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest;
-	volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *dest2 = (CONFIG_SYS_FLASH_WORD_SIZE *) dest;
+	volatile CONFIG_SYS_FLASH_WORD_SIZE *data2 = (CONFIG_SYS_FLASH_WORD_SIZE *) & data;
 	ulong start;
 	int i;
 
 	/* Check if Flash is (sufficiently) erased */
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		if ((dest2[i] & swap16(data2[i])) != swap16(data2[i]))
 			return (2);
 	}
 
-	for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) {
+	for (i = 0; i < 4 / sizeof(CONFIG_SYS_FLASH_WORD_SIZE); i++) {
 		int flag;
 
 		/* Disable interrupts which might cause a timeout here */
 		flag = disable_interrupts();
 
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAA00AA00;
-		addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55005500;
-		addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xA000A000;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
+		addr2[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
+		addr2[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xA000A000;
 
 		dest2[i] = swap16(data2[i]);
 
@@ -709,10 +709,10 @@
 
 		/* data polling for D7 */
 		start = get_timer(0);
-		while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x80008000) !=
-				(swap16(data2[i]) & (CFG_FLASH_WORD_SIZE) 0x80008000)) {
+		while ((dest2[i] & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000) !=
+				(swap16(data2[i]) & (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000)) {
 
-			if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
@@ -720,7 +720,7 @@
 
 	return (0);
 }
-#endif /* CFG_FLASH_2ND_16BIT_DEV */
+#endif /* CONFIG_SYS_FLASH_2ND_16BIT_DEV */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -734,7 +734,7 @@
 unsigned long flash_init(void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 
@@ -742,7 +742,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -765,8 +765,8 @@
 		}
 
 		/* Monitor protection ON by default */
-		(void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				    CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1,
+		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				    CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN - 1,
 				    &flash_info[i]);
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 		(void)flash_protect(FLAG_PROTECT_SET, CONFIG_ENV_ADDR,
diff --git a/board/tqc/tqm5200/cmd_stk52xx.c b/board/tqc/tqm5200/cmd_stk52xx.c
index fd1e68b..5483fca 100644
--- a/board/tqc/tqm5200/cmd_stk52xx.c
+++ b/board/tqc/tqm5200/cmd_stk52xx.c
@@ -165,9 +165,9 @@
 	psc->command = (PSC_RX_DISABLE | PSC_TX_DISABLE);
 	psc->sicr = 0x22E00000;		/* 16 bit data; I2S */
 
-	*(vu_long *)(CFG_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x22C) = 0x805d; /* PSC2 CDM MCLK config; MCLK
 						  * 5.617 MHz */
-	*(vu_long *)(CFG_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
+	*(vu_long *)(CONFIG_SYS_MBAR + 0x214) |= 0x00000040; /* CDM clock enable
 						       * register */
 	psc->ccr = 0x1F03;	/* 16 bit data width; 5.617MHz MCLK */
 	psc->ctur = 0x0F;	/* 16 bit frame width */
@@ -751,9 +751,9 @@
 	static int init_done = 0;
 	int i;
 	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
 	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
 
 	/* GPIO configuration of the CAN pins is done in TQM5200.h */
 
@@ -896,9 +896,9 @@
 {
 	int i;
 	struct mpc5xxx_mscan *can1 =
-		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0900);
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0900);
 	struct mpc5xxx_mscan *can2 =
-		(struct mpc5xxx_mscan *)(CFG_MBAR + 0x0980);
+		(struct mpc5xxx_mscan *)(CONFIG_SYS_MBAR + 0x0980);
 
 	/* send a message on CAN1 */
 	can1->cantbsel = 0x01;
diff --git a/board/tqc/tqm5200/tqm5200.c b/board/tqc/tqm5200/tqm5200.c
index 5152331..faa2e02 100644
--- a/board/tqc/tqm5200/tqm5200.c
+++ b/board/tqc/tqm5200/tqm5200.c
@@ -54,7 +54,7 @@
 void ps2mult_early_init(void);
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -101,7 +101,7 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
@@ -111,7 +111,7 @@
 	ulong dramsize2 = 0;
 	uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -132,9 +132,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -161,10 +161,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+	test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *)(CFG_SDRAM_BASE + dramsize), 0x20000000);
+		test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -186,7 +186,7 @@
 		*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 	}
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -203,7 +203,7 @@
 	} else {
 		dramsize2 = 0;
 	}
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
@@ -406,7 +406,7 @@
 	ps2mult_early_init();
 #endif /* CONFIG_PS2MULT */
 
-#if defined(CONFIG_USB_OHCI_NEW) && defined(CFG_USB_OHCI_CPU_INIT)
+#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
 	/* Low level USB init, required for proper kernel operation */
 	usb_cpu_init();
 #endif
@@ -464,34 +464,34 @@
 	 */
 
 	/* save original SRAM content  */
-	save = *(volatile u16 *)CFG_CS2_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS2_START;
 	restore = 1;
 
 	/* write test pattern to SRAM */
-	*(volatile u16 *)CFG_CS2_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in SRAM detection\n");
 
-	if (*(volatile u16 *)CFG_CS2_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
 		/* no SRAM at all, disable cs */
 		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
 		*(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
 		*(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
 		restore = 0;
 		__asm__ volatile ("sync");
-	} else if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0xA5A5) {
+	} else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
 		/* make sure that we access a mirrored address */
-		*(volatile u16 *)CFG_CS2_START = 0x1111;
+		*(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
 		__asm__ volatile ("sync");
-		if (*(volatile u16 *)(CFG_CS2_START + (1<<19)) == 0x1111) {
+		if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
 			/* SRAM size = 512 kByte */
-			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CFG_CS2_START,
+			*(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
 								0x80000);
 			__asm__ volatile ("sync");
 			puts ("SRAM:  512 kB\n");
@@ -503,7 +503,7 @@
 	}
 	/* restore origianl SRAM content  */
 	if (restore) {
-		*(volatile u16 *)CFG_CS2_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS2_START = save;
 		__asm__ volatile ("sync");
 	}
 
@@ -513,21 +513,21 @@
 	 */
 
 	/* save origianl FB content  */
-	save = *(volatile u16 *)CFG_CS1_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 	restore = 1;
 
 	/* write test pattern to FB memory */
-	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in grafic controller detection\n");
 
-	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 		/* no grafic controller at all, disable cs */
 		*(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
 		*(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
@@ -539,7 +539,7 @@
 	}
 	/* restore origianl FB content  */
 	if (restore) {
-		*(volatile u16 *)CFG_CS1_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
 		__asm__ volatile ("sync");
 	}
 
@@ -679,21 +679,21 @@
 	 */
 
 	/* save origianl FB content  */
-	save = *(volatile u16 *)CFG_CS1_START;
+	save = *(volatile u16 *)CONFIG_SYS_CS1_START;
 	restore = 1;
 
 	/* write test pattern to FB memory */
-	*(volatile u16 *)CFG_CS1_START = 0xA5A5;
+	*(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
 	__asm__ volatile ("sync");
 	/*
 	 * Put a different pattern on the data lines: otherwise they may float
 	 * long enough to read back what we wrote.
 	 */
-	tmp = *(volatile u16 *)CFG_FLASH_BASE;
+	tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
 	if (tmp == 0xA5A5)
 		puts ("!! possible error in grafic controller detection\n");
 
-	if (*(volatile u16 *)CFG_CS1_START != 0xA5A5) {
+	if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
 		/* no grafic controller found */
 		restore = 0;
 		ret = 0;
@@ -702,7 +702,7 @@
 	}
 
 	if (restore) {
-		*(volatile u16 *)CFG_CS1_START = save;
+		*(volatile u16 *)CONFIG_SYS_CS1_START = save;
 		__asm__ volatile ("sync");
 	}
 	return ret;
diff --git a/board/tqc/tqm8260/config.mk b/board/tqc/tqm8260/config.mk
index 1fe9952..3ecfc48 100644
--- a/board/tqc/tqm8260/config.mk
+++ b/board/tqc/tqm8260/config.mk
@@ -25,7 +25,7 @@
 # TQM8260 boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/tqc/tqm8260/flash.c b/board/tqc/tqm8260/flash.c
index 500af92..4a6d538 100644
--- a/board/tqc/tqm8260/flash.c
+++ b/board/tqc/tqm8260/flash.c
@@ -31,7 +31,7 @@
 #define V_BYTE(a)	(*(volatile unsigned char *)( a ))
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 /*-----------------------------------------------------------------------
@@ -185,13 +185,13 @@
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Static FLASH Bank configuration here (only one bank) */
 
-	size_b0 = flash_get_size (CFG_FLASH0_BASE, &flash_info[0]);
+	size_b0 = flash_get_size (CONFIG_SYS_FLASH0_BASE, &flash_info[0]);
 	if (flash_info[0].flash_id == FLASH_UNKNOWN || size_b0 == 0) {
 		printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n",
 				size_b0, size_b0 >> 20);
@@ -201,10 +201,10 @@
 	 * protect monitor and environment sectors
 	 */
 
-#if CFG_MONITOR_BASE >= CFG_FLASH0_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH0_BASE
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
 #endif
 
 #if defined(CONFIG_ENV_IS_IN_FLASH) && defined(CONFIG_ENV_ADDR)
@@ -364,7 +364,7 @@
 	while ((V_ULONG (info->start[l_sect]) & 0x00800080) != 0x00800080 ||
 	       (V_ULONG (info->start[l_sect] + 4) & 0x00800080) != 0x00800080)
 	{
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -480,7 +480,7 @@
 	start = get_timer (0);
 	while (((V_ULONG (dest) & 0x00800080) != (ch & 0x00800080)) ||
 		   ((V_ULONG (dest + 4) & 0x00800080) != (cl & 0x00800080))) {
-		if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/tqc/tqm8260/tqm8260.c b/board/tqc/tqm8260/tqm8260.c
index f201045..3039999 100644
--- a/board/tqc/tqm8260/tqm8260.c
+++ b/board/tqc/tqm8260/tqm8260.c
@@ -236,7 +236,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
@@ -261,7 +261,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -272,7 +272,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -285,10 +285,10 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long size8, size9;
 #endif
 	long psize, lsize;
@@ -296,8 +296,8 @@
 	psize = 16 * 1024 * 1024;
 	lsize = 0;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
 #if 0							/* Just for debugging */
 #define	prt_br_or(brX,orX) do {				\
@@ -315,37 +315,37 @@
 	prt_br_or (br3, or3);
 #endif
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-					  (uchar *) CFG_SDRAM_BASE);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
-					  (uchar *) CFG_SDRAM_BASE);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL - %ld MB, ", psize >> 20);
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-						  (uchar *) CFG_SDRAM_BASE);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE);
 		printf ("(60x:8COL - %ld MB, ", psize >> 20);
 	}
 
 	/* Local SDRAM setup:
 	 */
-#ifdef CFG_INIT_LOCAL_SDRAM
-	memctl->memc_lsrt = CFG_LSRT;
-	size8 = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+#ifdef CONFIG_SYS_INIT_LOCAL_SDRAM
+	memctl->memc_lsrt = CONFIG_SYS_LSRT;
+	size8 = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
 					  (uchar *) SDRAM_BASE2_PRELIM);
-	size9 = try_init (memctl, CFG_LSDMR_9COL, CFG_OR2_9COL,
+	size9 = try_init (memctl, CONFIG_SYS_LSDMR_9COL, CONFIG_SYS_OR2_9COL,
 					  (uchar *) SDRAM_BASE2_PRELIM);
 
 	if (size8 < size9) {
 		lsize = size9;
 		printf ("Local:9COL - %ld MB) using ", lsize >> 20);
 	} else {
-		lsize = try_init (memctl, CFG_LSDMR_8COL, CFG_OR2_8COL,
+		lsize = try_init (memctl, CONFIG_SYS_LSDMR_8COL, CONFIG_SYS_OR2_8COL,
 						  (uchar *) SDRAM_BASE2_PRELIM);
 		printf ("Local:8COL - %ld MB) using ", lsize >> 20);
 	}
@@ -354,11 +354,11 @@
 	/* Set up BR2 so that the local SDRAM goes
 	 * right after the 60x SDRAM
 	 */
-	memctl->memc_br2 = (CFG_BR2_PRELIM & ~BRx_BA_MSK) |
-			(CFG_SDRAM_BASE + psize);
+	memctl->memc_br2 = (CONFIG_SYS_BR2_PRELIM & ~BRx_BA_MSK) |
+			(CONFIG_SYS_SDRAM_BASE + psize);
 #endif
-#endif /* CFG_INIT_LOCAL_SDRAM */
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_INIT_LOCAL_SDRAM */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
diff --git a/board/tqc/tqm8272/config.mk b/board/tqc/tqm8272/config.mk
index af7a81e..05c5f0c 100644
--- a/board/tqc/tqm8272/config.mk
+++ b/board/tqc/tqm8272/config.mk
@@ -25,7 +25,7 @@
 # TQM8272 boards
 #
 
-# This should be equal to the CFG_FLASH_BASE define in config_TQM8260.h
+# This should be equal to the CONFIG_SYS_FLASH_BASE define in config_TQM8260.h
 # for the "final" configuration, with U-Boot in flash, or the address
 # in RAM where U-Boot is loaded at for debugging.
 #
diff --git a/board/tqc/tqm8272/nand.c b/board/tqc/tqm8272/nand.c
index b988ffa..8c8341b 100644
--- a/board/tqc/tqm8272/nand.c
+++ b/board/tqc/tqm8272/nand.c
@@ -141,12 +141,12 @@
 static void upmnand_write_byte(struct mtd_info *mtdinfo, u_char byte)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
 
 	if (hwctl & 0x1) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_CMD_OFS);
+		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS);
 	} else if (hwctl & 0x2) {
-		WRITE_NAND_UPM(byte, base, CFG_NAND_UPM_WRITE_ADDR_OFS);
+		WRITE_NAND_UPM(byte, base, CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS);
 	} else {
 		WRITE_NAND(byte, base);
 	}
@@ -171,7 +171,7 @@
 static u_char upmnand_read_byte(struct mtd_info *mtdinfo)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	ulong base = (ulong) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
 
 	return READ_NAND(base);
 }
@@ -187,7 +187,7 @@
 static void tqm8272_read_buf(struct mtd_info *mtdinfo, uint8_t *buf, int len)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
 	int	i;
 
 	for (i = 0; i< len; i++)
@@ -197,7 +197,7 @@
 static void tqm8272_write_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
 	int	i;
 
 	for (i = 0; i< len; i++)
@@ -207,7 +207,7 @@
 static int tqm8272_verify_buf(struct mtd_info *mtdinfo, const uint8_t *buf, int len)
 {
 	struct nand_chip *this = mtdinfo->priv;
-	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CFG_NAND_CS_DIST);
+	unsigned char *base = (unsigned char *) (this->IO_ADDR_W + chipsel * CONFIG_SYS_NAND_CS_DIST);
 	int	i;
 
 	for (i = 0; i < len; i++)
@@ -225,7 +225,7 @@
 int board_nand_init(struct nand_chip *nand)
 {
 	static	int	UpmInit = 0;
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 
 	if (hwinf.nand == 0) return -1;
@@ -250,8 +250,8 @@
 	}
 
 	/* Setup the memctrl */
-	memctl->memc_or3 = CFG_NAND_OR;
-	memctl->memc_br3 = CFG_NAND_BR;
+	memctl->memc_or3 = CONFIG_SYS_NAND_OR;
+	memctl->memc_br3 = CONFIG_SYS_NAND_BR;
 	memctl->memc_mbmr = (MxMR_OP_NORM);
 
 	nand->ecc.mode = NAND_ECC_SOFT;
diff --git a/board/tqc/tqm8272/tqm8272.c b/board/tqc/tqm8272/tqm8272.c
index fc0a29c..5d0741d 100644
--- a/board/tqc/tqm8272/tqm8272.c
+++ b/board/tqc/tqm8272/tqm8272.c
@@ -287,7 +287,7 @@
 	char *p = (char *) HWIB_INFO_START_ADDR;
 
 	puts ("Board: ");
-	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
 		puts (p);
 	} else {
 		puts ("No HWIB assuming TQM8272");
@@ -327,7 +327,7 @@
 {
 #if defined(CONFIG_BOARD_GET_CPU_CLK_F)
 	int	clk = board_get_cpu_clk_f ();
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	int	busmode = (immr->im_siu_conf.sc_bcr & BCR_EBM ? 1 : 0);
 	int	cas;
 
@@ -404,7 +404,7 @@
 	 */
 	maxsize = (1 + (~orx | 0x7fff)) / 2;
 
-	/* Since CFG_SDRAM_BASE is always 0 (??), we assume that
+	/* Since CONFIG_SYS_SDRAM_BASE is always 0 (??), we assume that
 	 * we are configuring CS1 if base != 0
 	 */
 	sdmr_ptr = base ? &memctl->memc_lsdmr : &memctl->memc_psdmr;
@@ -429,7 +429,7 @@
 	 *  accessing the SDRAM with a single-byte transaction."
 	 *
 	 * The appropriate BRx/ORx registers have already been set when we
-	 * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE.
+	 * get here. The SDRAM can be accessed at the address CONFIG_SYS_SDRAM_BASE.
 	 */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_PREA;
@@ -440,7 +440,7 @@
 		*base = c;
 
 	*sdmr_ptr = sdmr | PSDMR_OP_MRW;
-	*(base + CFG_MRS_OFFS) = c;	/* setting MR on address lines */
+	*(base + CONFIG_SYS_MRS_OFFS) = c;	/* setting MR on address lines */
 
 	*sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN;
 	*base = c;
@@ -453,10 +453,10 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	long size8, size9;
 #endif
 	long psize, lsize;
@@ -464,27 +464,27 @@
 	psize = 16 * 1024 * 1024;
 	lsize = 0;
 
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	/* 60x SDRAM setup:
 	 */
-	size8 = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-					  (uchar *) CFG_SDRAM_BASE, 8);
-	size9 = try_init (memctl, CFG_PSDMR_9COL, CFG_OR1_9COL,
-					  (uchar *) CFG_SDRAM_BASE, 9);
+	size8 = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
+	size9 = try_init (memctl, CONFIG_SYS_PSDMR_9COL, CONFIG_SYS_OR1_9COL,
+					  (uchar *) CONFIG_SYS_SDRAM_BASE, 9);
 
 	if (size8 < size9) {
 		psize = size9;
 		printf ("(60x:9COL - %ld MB, ", psize >> 20);
 	} else {
-		psize = try_init (memctl, CFG_PSDMR_8COL, CFG_OR1_8COL,
-						  (uchar *) CFG_SDRAM_BASE, 8);
+		psize = try_init (memctl, CONFIG_SYS_PSDMR_8COL, CONFIG_SYS_OR1_8COL,
+						  (uchar *) CONFIG_SYS_SDRAM_BASE, 8);
 		printf ("(60x:8COL - %ld MB, ", psize >> 20);
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	icache_enable ();
 
@@ -514,7 +514,7 @@
 static int dump_hwib(void)
 {
 	HWIB_INFO	*hw = &hwinf;
-	volatile immap_t *immr = (immap_t *)CFG_IMMR;
+	volatile immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
 	char *s = getenv("serial#");
 
 	if (hw->OK) {
@@ -607,7 +607,7 @@
 
 	deb_printf(" %s pointer: %p\n", __FUNCTION__, p);
 	/* Head = TQM */
-	if (*((unsigned long *)p) != (unsigned long)CFG_HWINFO_MAGIC) {
+	if (*((unsigned long *)p) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
 		deb_printf("No HWIB\n");
 		return -1;
 	}
@@ -704,7 +704,7 @@
 
 	hw->OK = 1;
 	/* search MAC Address */
-	while ((*p != '\0') && (pos < CFG_HWINFO_SIZE)) {
+	while ((*p != '\0') && (pos < CONFIG_SYS_HWINFO_SIZE)) {
 		if (*p < ' ' || *p > '~') { /* ASCII strings! */
 			return 0;
 		}
@@ -744,7 +744,7 @@
 	buf[i++] = 'M';
 	buf[i++] = 'P';
 	buf[i++] = 'C';
-	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
 		buf[i++] = *&p[3];
 		buf[i++] = *&p[4];
 		buf[i++] = *&p[5];
@@ -767,7 +767,7 @@
 	char *p = (char *) HWIB_INFO_START_ADDR;
 	int i = 0;
 
-	if (*((unsigned long *)p) == (unsigned long)CFG_HWINFO_MAGIC) {
+	if (*((unsigned long *)p) == (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
 		if (search_real_busclk (&i))
 			return i;
 	}
@@ -779,7 +779,7 @@
 
 static int can_test (unsigned long off)
 {
-	volatile unsigned char	*base	= (unsigned char *) (CFG_CAN_BASE + off);
+	volatile unsigned char	*base	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
 
 	*(base + 0x17) = 'T';
 	*(base + 0x18) = 'Q';
@@ -794,9 +794,9 @@
 
 static int can_config_one (unsigned long off)
 {
-	volatile unsigned char	*ctrl	= (unsigned char *) (CFG_CAN_BASE + off);
-	volatile unsigned char	*cpu_if = (unsigned char *) (CFG_CAN_BASE + off + 0x02);
-	volatile unsigned char	*clkout = (unsigned char *) (CFG_CAN_BASE + off + 0x1f);
+	volatile unsigned char	*ctrl	= (unsigned char *) (CONFIG_SYS_CAN_BASE + off);
+	volatile unsigned char	*cpu_if = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x02);
+	volatile unsigned char	*clkout = (unsigned char *) (CONFIG_SYS_CAN_BASE + off + 0x1f);
 	unsigned char temp;
 
 	*cpu_if = 0x45;
@@ -825,13 +825,13 @@
 
 static int init_can (void)
 {
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 	int	count = 0;
 
 	if ((hwinf.OK) && (hwinf.can)) {
-		memctl->memc_or4 = CFG_CAN_OR;
-		memctl->memc_br4 = CFG_CAN_BR;
+		memctl->memc_or4 = CONFIG_SYS_CAN_OR;
+		memctl->memc_br4 = CONFIG_SYS_CAN_BR;
 		/* upm Init */
 		upmconfig (UPMC, (uint *) upmTableFast,
 			   sizeof (upmTableFast) / sizeof (uint));
@@ -842,7 +842,7 @@
 					MxMR_OP_NORM);
 		/* can configure */
 		count = can_config ();
-		printf ("CAN:	%d @ %x\n", count, CFG_CAN_BASE);
+		printf ("CAN:	%d @ %x\n", count, CONFIG_SYS_CAN_BASE);
 		if (hwinf.can != count) printf("!!! difference to HWIB\n");
 	} else {
 		printf ("CAN:	No\n");
@@ -870,7 +870,7 @@
 	  "\n"
 );
 
-#ifdef CFG_UPDATE_FLASH_SIZE
+#ifdef CONFIG_SYS_UPDATE_FLASH_SIZE
 static int get_flash_timing (void)
 {
 	/* get it from the option -tf in CIB */
@@ -915,7 +915,7 @@
 /* Update the Flash_Size and the Flash Timing */
 int update_flash_size (int flash_size)
 {
-	volatile immap_t * immr = (immap_t *)CFG_IMMR;
+	volatile immap_t * immr = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immr->im_memctl;
 	unsigned long reg;
 	unsigned long tim;
@@ -937,7 +937,7 @@
 
 int board_early_init_f (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	immap->im_clkrst.car_sccr |= M826X_SCCR_PCI_MODE_EN;
 	return 0;
diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c
index e3d0309..0eedf4a 100644
--- a/board/tqc/tqm834x/pci.c
+++ b/board/tqc/tqm834x/pci.c
@@ -29,8 +29,8 @@
 #ifdef CONFIG_PCI
 
 /* System RAM mapped to PCI space */
-#define CONFIG_PCI_SYS_MEM_BUS	CFG_SDRAM_BASE
-#define CONFIG_PCI_SYS_MEM_PHYS	CFG_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_BUS	CONFIG_SYS_SDRAM_BASE
+#define CONFIG_PCI_SYS_MEM_PHYS	CONFIG_SYS_SDRAM_BASE
 #define CONFIG_PCI_SYS_MEM_SIZE	(1024 * 1024 * 1024)
 
 #ifndef CONFIG_PCI_PNP
@@ -78,7 +78,7 @@
 	u32 reg32;
 	struct	pci_controller * hose;
 
-	immr = (immap_t *)CFG_IMMR;
+	immr = (immap_t *)CONFIG_SYS_IMMR;
 	clk = (clk83xx_t *)&immr->clk;
 	pci_law = immr->sysconf.pcilaw;
 	pci_pot = immr->ios.pot;
@@ -128,10 +128,10 @@
 	/*
 	 * Configure PCI Local Access Windows
 	 */
-	pci_law[0].bar = CFG_PCI1_MEM_PHYS & LAWBAR_BAR;
+	pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
 	pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
 
-	pci_law[1].bar = CFG_PCI1_IO_PHYS & LAWBAR_BAR;
+	pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
 	pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_16M;
 
 	/*
@@ -139,13 +139,13 @@
 	 */
 
 	/* PCI1 mem space */
-	pci_pot[0].potar = (CFG_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[0].pobar = (CFG_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[0].potar = (CONFIG_SYS_PCI1_MEM_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[0].pobar = (CONFIG_SYS_PCI1_MEM_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[0].pocmr = POCMR_EN | (POCMR_CM_512M & POCMR_CM_MASK);
 
 	/* PCI1 IO space */
-	pci_pot[1].potar = (CFG_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
-	pci_pot[1].pobar = (CFG_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
+	pci_pot[1].potar = (CONFIG_SYS_PCI1_IO_BASE >> 12) & POTAR_TA_MASK;
+	pci_pot[1].pobar = (CONFIG_SYS_PCI1_IO_PHYS >> 12) & POBAR_BA_MASK;
 	pci_pot[1].pocmr = POCMR_EN | POCMR_IO | (POCMR_CM_16M & POCMR_CM_MASK);
 
 	/*
@@ -164,16 +164,16 @@
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 0,
-		       CFG_PCI1_MEM_BASE,
-		       CFG_PCI1_MEM_PHYS,
-		       CFG_PCI1_MEM_SIZE,
+		       CONFIG_SYS_PCI1_MEM_BASE,
+		       CONFIG_SYS_PCI1_MEM_PHYS,
+		       CONFIG_SYS_PCI1_MEM_SIZE,
 		       PCI_REGION_MEM);
 
 	/* PCI IO space */
 	pci_set_region(hose->regions + 1,
-		       CFG_PCI1_IO_BASE,
-		       CFG_PCI1_IO_PHYS,
-		       CFG_PCI1_IO_SIZE,
+		       CONFIG_SYS_PCI1_IO_BASE,
+		       CONFIG_SYS_PCI1_IO_PHYS,
+		       CONFIG_SYS_PCI1_IO_SIZE,
 		       PCI_REGION_IO);
 
 	/* System memory space */
@@ -186,8 +186,8 @@
 	hose->region_count = 3;
 
 	pci_setup_indirect(hose,
-			   (CFG_IMMR+0x8300),
-			   (CFG_IMMR+0x8304));
+			   (CONFIG_SYS_IMMR+0x8300),
+			   (CONFIG_SYS_IMMR+0x8304));
 
 	pci_register_hose(hose);
 
diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c
index 278780d..106cac2 100644
--- a/board/tqc/tqm834x/tqm834x.c
+++ b/board/tqc/tqm834x/tqm834x.c
@@ -67,7 +67,7 @@
 static void set_ddr_config(void);
 
 /* Local variable */
-static volatile immap_t *im = (immap_t *)CFG_IMMR;
+static volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
 
 /**************************************************************************
  * Board initialzation after relocation to RAM. Used to detect the number
@@ -92,13 +92,13 @@
 	int cs;
 
 	/* during size detection, set up the max DDRLAW size */
-	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE;
+	im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE;
 	im->sysconf.ddrlaw[0].ar = (LAWAR_EN | LAWAR_SIZE_2G);
 
 	/* set CS bounds to maximum size */
 	for(cs = 0; cs < 4; ++cs) {
 		set_cs_bounds(cs,
-			CFG_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
+			CONFIG_SYS_DDR_BASE + (cs * DDR_MAX_SIZE_PER_CS),
 			DDR_MAX_SIZE_PER_CS);
 
 		set_cs_config(cs, INITIAL_CS_CONFIG);
@@ -122,7 +122,7 @@
 		debug("\nDetecting Bank%d\n", cs);
 
 		bank_size = get_ddr_bank_size(cs,
-			(volatile long*)(CFG_DDR_BASE + size));
+			(volatile long*)(CONFIG_SYS_DDR_BASE + size));
 		size += bank_size;
 
 		debug("DDR Bank%d size: %d MiB\n\n", cs, bank_size >> 20);
@@ -145,7 +145,7 @@
 	volatile immap_t * immr;
 	u32 w, f;
 
-	immr = (immap_t *)CFG_IMMR;
+	immr = (immap_t *)CONFIG_SYS_IMMR;
 	if (!(immr->reset.rcwh & HRCWH_PCI_HOST)) {
 		printf("PCI:   NOT in host mode..?!\n");
 		return 0;
@@ -193,9 +193,9 @@
 	tqm834x_num_flash_banks = 2;	/* assume two banks */
 
 	/* Get bank 1 and 2 information */
-	bank1_size = flash_get_size(CFG_FLASH_BASE, 0);
+	bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0);
 	debug("Bank1 size: %lu\n", bank1_size);
-	bank2_size = flash_get_size(CFG_FLASH_BASE + bank1_size, 1);
+	bank2_size = flash_get_size(CONFIG_SYS_FLASH_BASE + bank1_size, 1);
 	debug("Bank2 size: %lu\n", bank2_size);
 	total_size = bank1_size + bank2_size;
 
@@ -203,8 +203,8 @@
 		/* Seems like we've got bank 2, but maybe it's mirrored 1 */
 
 		/* Set the base addresses */
-		bank1_base = (FPWV *) (CFG_FLASH_BASE);
-		bank2_base = (FPWV *) (CFG_FLASH_BASE + bank1_size);
+		bank1_base = (FPWV *) (CONFIG_SYS_FLASH_BASE);
+		bank2_base = (FPWV *) (CONFIG_SYS_FLASH_BASE + bank1_size);
 
 		/* Put bank 2 into CFI command mode and read */
 		bank2_base[0x55] = 0x00980098;
@@ -253,9 +253,9 @@
 	debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks);
 
 	/* set OR0 and BR0 */
-	im->lbus.bank[0].or = CFG_OR_TIMING_FLASH |
+	im->lbus.bank[0].or = CONFIG_SYS_OR_TIMING_FLASH |
 		(-(total_size) & OR_GPCM_AM);
-	im->lbus.bank[0].br = (CFG_FLASH_BASE & BR_BA) |
+	im->lbus.bank[0].br = (CONFIG_SYS_FLASH_BASE & BR_BA) |
 		(BR_MS_GPCM | BR_PS_32 | BR_V);
 
 	return (0);
diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c
index de3ea00..fc92cd8 100644
--- a/board/tqc/tqm85xx/law.c
+++ b/board/tqc/tqm85xx/law.c
@@ -66,20 +66,20 @@
 #endif
 
 struct law_entry law_table[] = {
-	SET_LAW(CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
-	SET_LAW(CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
-	SET_LAW(CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
-	SET_LAW(CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR),
+	SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI),
+	SET_LAW(CONFIG_SYS_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI),
 #ifdef CONFIG_PCIE1
-	SET_LAW(CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1),
 #else /* !CONFIG_PCIE1 */
-	SET_LAW(CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
+	SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO),
 #endif /* CONFIG_PCIE1 */
 #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND)
-	SET_LAW(CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+	SET_LAW(CONFIG_SYS_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
 #endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */
 #ifdef CONFIG_PCIE1
-	SET_LAW(CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
+	SET_LAW(CONFIG_SYS_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1),
 #endif /* CONFIG_PCIE */
 };
 
diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c
index 9c5c12c..dea652d 100644
--- a/board/tqc/tqm85xx/nand.c
+++ b/board/tqc/tqm85xx/nand.c
@@ -41,10 +41,10 @@
 extern uint get_lbc_clock (void);
 
 /* index of UPM RAM array run pattern for NAND command cycle */
-#define	CFG_NAN_UPM_WRITE_CMD_OFS	0x08
+#define	CONFIG_SYS_NAN_UPM_WRITE_CMD_OFS	0x08
 
 /* index of UPM RAM array run pattern for NAND address cycle */
-#define	CFG_NAND_UPM_WRITE_ADDR_OFS	0x10
+#define	CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS	0x10
 
 /* Structure for table with supported UPM timings */
 struct upm_freq {
@@ -377,7 +377,7 @@
  */
 static void upmb_write (u_char addr, ulong val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	out_be32 (&lbc->mdr, val);
 
@@ -385,7 +385,7 @@
 			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
 	/* dummy access to perform write */
-	out_8 ((void __iomem *)CFG_NAND0_BASE, 0);
+	out_8 ((void __iomem *)CONFIG_SYS_NAND0_BASE, 0);
 
 	clrbits_be32(&lbc->mbmr, MxMR_OP_WARR);
 }
@@ -396,11 +396,11 @@
 static void nand_upm_setup (volatile ccsr_lbc_t *lbc)
 {
 	uint i;
-	uint or3 = CFG_OR3_PRELIM;
+	uint or3 = CONFIG_SYS_OR3_PRELIM;
 	uint clock = get_lbc_clock ();
 
 	out_be32 (&lbc->br3, 0);	/* disable bank and reset all bits */
-	out_be32 (&lbc->br3, CFG_BR3_PRELIM);
+	out_be32 (&lbc->br3, CONFIG_SYS_BR3_PRELIM);
 
 	/*
 	 * Search appropriate UPM table for bus clock.
@@ -455,7 +455,7 @@
 
 int board_nand_init (struct nand_chip *nand)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	if (!nand_upm_patt)
 		nand_upm_setup (lbc);
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c
index 33bc407..783b280 100644
--- a/board/tqc/tqm85xx/sdram.c
+++ b/board/tqc/tqm85xx/sdram.c
@@ -66,9 +66,9 @@
 long int sdram_setup (int casl)
 {
 	int i;
-	volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR);
+	volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 #ifdef CONFIG_TQM8548
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #else /* !CONFIG_TQM8548 */
 	unsigned long cfg_ddr_timing1;
 	unsigned long cfg_ddr_mode;
@@ -296,7 +296,7 @@
 	 * This DLL-Override only used on TQM8540 and TQM8560
 	 */
 	{
-		volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+		volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 		int i, x;
 
 		x = 10;
@@ -336,11 +336,11 @@
 	return dram_size;
 }
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
-	uint *pstart = (uint *) CFG_MEMTEST_START;
-	uint *pend = (uint *) CFG_MEMTEST_END;
+	uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
+	uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
 	uint *p;
 
 	printf ("SDRAM test phase 1:\n");
diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c
index 380448a..16b102d 100644
--- a/board/tqc/tqm85xx/tlb.c
+++ b/board/tqc/tqm85xx/tlb.c
@@ -28,19 +28,19 @@
 
 struct fsl_e_tlb_entry tlb_table[] = {
 	/* TLB 0 - for temp stack in cache */
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024,
-		       CFG_INIT_RAM_ADDR + 4 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024,
-		       CFG_INIT_RAM_ADDR + 8 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
-	SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024,
-		       CFG_INIT_RAM_ADDR + 12 * 1024,
+	SET_TLB_ENTRY (0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
+		       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
 		       MAS3_SX | MAS3_SW | MAS3_SR, 0,
 		       0, 0, BOOKE_PAGESZ_4K, 0),
 
@@ -50,11 +50,11 @@
 	 * 0xf8000000	128M	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 1, BOOKE_PAGESZ_64M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000,
-		       CFG_FLASH_BASE + 0x4000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x4000000,
+		       CONFIG_SYS_FLASH_BASE + 0x4000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 0, BOOKE_PAGESZ_64M, 1),
 
@@ -62,7 +62,7 @@
 	 * TLB 2:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 2, BOOKE_PAGESZ_256M, 1),
 
@@ -70,8 +70,8 @@
 	 * TLB 3:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
-		       CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
 
@@ -80,7 +80,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -88,8 +88,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	PCI express MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000,
-		       CFG_PCIE1_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
+		       CONFIG_SYS_PCIE1_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -97,7 +97,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -105,8 +105,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0xd0000000	256M	Rapid IO MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000,
-		       CFG_RIO_MEM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
+		       CONFIG_SYS_RIO_MEM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 #endif /* CONFIG_PCIE */
@@ -117,7 +117,7 @@
 	 * 0xe2000000	 16M	PCI1 IO
 	 * 0xe3000000	 16M	CAN and NAND Flash
 	 */
-	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_64M, 1),
 
@@ -128,12 +128,12 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 7, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
-		       CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
 
@@ -142,7 +142,7 @@
 	 * TLB 9:	 16M	Non-cacheable, guarded
 	 * 0xef000000	 16M	PCI express IO
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 9, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
@@ -154,19 +154,19 @@
 	 * 0xc0000000	  1G	FLASH
 	 * Out of reset this entry is only 4K.
 	 */
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 3, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000,
-		       CFG_FLASH_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x10000000,
+		       CONFIG_SYS_FLASH_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 2, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000,
-		       CFG_FLASH_BASE + 0x20000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x20000000,
+		       CONFIG_SYS_FLASH_BASE + 0x20000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 1, BOOKE_PAGESZ_256M, 1),
-	SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000,
-		       CFG_FLASH_BASE + 0x30000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_FLASH_BASE + 0x30000000,
+		       CONFIG_SYS_FLASH_BASE + 0x30000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 0, BOOKE_PAGESZ_256M, 1),
 
@@ -174,7 +174,7 @@
 	 * TLB 4:	256M	Non-cacheable, guarded
 	 * 0x80000000	256M	PCI1 MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 4, BOOKE_PAGESZ_256M, 1),
 
@@ -182,8 +182,8 @@
 	 * TLB 5:	256M	Non-cacheable, guarded
 	 * 0x90000000	256M	PCI1 MEM Second half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000,
-		       CFG_PCI1_MEM_PHYS + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
+		       CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 5, BOOKE_PAGESZ_256M, 1),
 
@@ -192,7 +192,7 @@
 	 * TLB 6:	256M	Non-cacheable, guarded
 	 * 0xc0000000	256M	PCI express MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_MEM_BASE, CONFIG_SYS_PCIE1_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_256M, 1),
 #else /* !CONFIG_PCIE */
@@ -200,7 +200,7 @@
 	 * TLB 6:	256M	Non-cacheable, guarded
 	 * 0xb0000000	256M	Rapid IO MEM First half
 	 */
-	SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_RIO_MEM_BASE, CONFIG_SYS_RIO_MEM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 6, BOOKE_PAGESZ_256M, 1),
 
@@ -212,7 +212,7 @@
 	 * 0xa2000000	 16M	PCI1 IO
 	 * 0xa3000000	 16M	CAN and NAND Flash
 	 */
-	SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS,
+	SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 7, BOOKE_PAGESZ_64M, 1),
 
@@ -223,12 +223,12 @@
 	 * Make sure the TLB count at the top of this table is correct.
 	 * Likely it needs to be increased by two for these entries.
 	 */
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 8, BOOKE_PAGESZ_256M, 1),
 
-	SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000,
-		       CFG_DDR_SDRAM_BASE + 0x10000000,
+	SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
+		       CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 9, BOOKE_PAGESZ_256M, 1),
 
@@ -237,7 +237,7 @@
 	 * TLB 10:	 16M	Non-cacheable, guarded
 	 * 0xaf000000	 16M	PCI express IO
 	 */
-	SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE,
+	SET_TLB_ENTRY (1, CONFIG_SYS_PCIE1_IO_BASE, CONFIG_SYS_PCIE1_IO_BASE,
 		       MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G,
 		       0, 10, BOOKE_PAGESZ_16M, 1),
 #endif /* CONFIG_PCIE */
diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c
index 5314d33..f69de95 100644
--- a/board/tqc/tqm85xx/tqm85xx.c
+++ b/board/tqc/tqm85xx/tqm85xx.c
@@ -269,7 +269,7 @@
 
 int misc_init_r (void)
 {
-	volatile ccsr_lbc_t *memctl = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *memctl = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	/*
 	 * Adjust flash start and offset to detected values
@@ -282,9 +282,9 @@
 	 */
 	if (flash_info[0].size > 0) {
 		memctl->or1 = ((-flash_info[0].size) & 0xffff8000) |
-			(CFG_OR1_PRELIM & 0x00007fff);
+			(CONFIG_SYS_OR1_PRELIM & 0x00007fff);
 		memctl->br1 = gd->bd->bi_flashstart |
-			(CFG_BR1_PRELIM & 0x00007fff);
+			(CONFIG_SYS_BR1_PRELIM & 0x00007fff);
 		/*
 		 * Re-check to get correct base address for bank 1
 		 */
@@ -298,9 +298,9 @@
 	 *  If bank 1 is equipped, bank 0 is mapped after bank 1
 	 */
 	memctl->or0 = ((-flash_info[1].size) & 0xffff8000) |
-		(CFG_OR0_PRELIM & 0x00007fff);
+		(CONFIG_SYS_OR0_PRELIM & 0x00007fff);
 	memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) |
-		(CFG_BR0_PRELIM & 0x00007fff);
+		(CONFIG_SYS_BR0_PRELIM & 0x00007fff);
 	/*
 	 * Re-check to get correct base address for bank 0
 	 */
@@ -311,26 +311,26 @@
 	 */
 	flash_protect (FLAG_PROTECT_CLEAR,
 		       gd->bd->bi_flashstart, 0xffffffff,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Monitor protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
-		       CFG_MONITOR_BASE,
-		       CFG_MONITOR_BASE + monitor_flash_len - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       CONFIG_SYS_MONITOR_BASE,
+		       CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 	/* Environment protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR,
 		       CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 
 #ifdef CONFIG_ENV_ADDR_REDUND
 	/* Redundant environment protection ON by default */
 	flash_protect (FLAG_PROTECT_SET,
 		       CONFIG_ENV_ADDR_REDUND,
 		       CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SIZE_REDUND - 1,
-		       &flash_info[CFG_MAX_FLASH_BANKS - 1]);
+		       &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]);
 #endif
 
 	return 0;
@@ -342,7 +342,7 @@
  */
 static void upmc_write (u_char addr, uint val)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 
 	out_be32 (&lbc->mdr, val);
 
@@ -350,7 +350,7 @@
 			MxMR_OP_WARR | (addr & MxMR_MAD_MSK));
 
 	/* dummy access to perform write */
-	out_8 ((void __iomem *)CFG_CAN_BASE, 0);
+	out_8 ((void __iomem *)CONFIG_SYS_CAN_BASE, 0);
 
 	/* normal operation */
 	clrbits_be32(&lbc->mcmr, MxMR_OP_WARR);
@@ -359,7 +359,7 @@
 
 uint get_lbc_clock (void)
 {
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	sys_info_t sys_info;
 	ulong clkdiv = lbc->lcrr & 0x0f;
 
@@ -376,7 +376,7 @@
 		return sys_info.freqSystemBus / clkdiv;
 	}
 
-	puts("Invalid clock divider value in CFG_LBC_LCRR\n");
+	puts("Invalid clock divider value in CONFIG_SYS_LBC_LCRR\n");
 
 	return 0;
 }
@@ -386,8 +386,8 @@
  */
 void local_bus_init (void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
-	volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
+	volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
 	uint lbc_mhz = get_lbc_clock ()  / 1000000;
 
 #ifdef CONFIG_MPC8548
@@ -418,7 +418,7 @@
 		gur->lbiuiplldcr1 = dummy;
 	}
 
-	lcrr = CFG_LBC_LCRR;
+	lcrr = CONFIG_SYS_LBC_LCRR;
 
 	/*
 	 * Local Bus Clock > 83.3 MHz. According to timing
@@ -464,12 +464,12 @@
 	 */
 
 	if (lbc_mhz < 66) {
-		lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR | LCRR_DBYP;	/* DLL Bypass */
 		lbc->ltedr = LTEDR_BMD | LTEDR_PARD | LTEDR_WPD | LTEDR_WARA |
 			     LTEDR_RAWA | LTEDR_CSD;	/* Disable all error checking */
 
 	} else if (lbc_mhz >= 133) {
-		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
 
 	} else {
 		/*
@@ -484,7 +484,7 @@
 			lbc->lcrr = 0x10000004;
 		}
 
-		lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
+		lbc->lcrr = CONFIG_SYS_LBC_LCRR & (~LCRR_DBYP);	/* DLL Enabled */
 		udelay (200);
 
 		/*
@@ -503,10 +503,10 @@
 	 * set if Local Bus Clock is > 83 MHz.
 	 */
 	if (lbc_mhz > 83)
-		out_be32 (&lbc->or2, CFG_OR2_CAN | OR_UPM_EAD);
+		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN | OR_UPM_EAD);
 	else
-		out_be32 (&lbc->or2, CFG_OR2_CAN);
-	out_be32 (&lbc->br2, CFG_BR2_CAN);
+		out_be32 (&lbc->or2, CONFIG_SYS_OR2_CAN);
+	out_be32 (&lbc->br2, CONFIG_SYS_BR2_CAN);
 
 	/* LGPL4 is UPWAIT */
 	out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL_x4DIS | MxMR_WLFx_3X);
@@ -548,10 +548,10 @@
 
 static inline void init_pci1(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #if defined(CONFIG_PCI) || defined(CONFIG_PCI1)
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCI1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pci1_hose;
 
@@ -579,24 +579,24 @@
 
 		/* inbound */
 		pci_set_region (hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 
 		/* outbound memory */
 		pci_set_region (hose->regions + 1,
-				CFG_PCI1_MEM_BASE,
-				CFG_PCI1_MEM_PHYS,
-				CFG_PCI1_MEM_SIZE,
+				CONFIG_SYS_PCI1_MEM_BASE,
+				CONFIG_SYS_PCI1_MEM_PHYS,
+				CONFIG_SYS_PCI1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region (hose->regions + 2,
-				CFG_PCI1_IO_BASE,
-				CFG_PCI1_IO_PHYS,
-				CFG_PCI1_IO_SIZE,
+				CONFIG_SYS_PCI1_IO_BASE,
+				CONFIG_SYS_PCI1_IO_PHYS,
+				CONFIG_SYS_PCI1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;
@@ -636,11 +636,11 @@
 
 static inline void init_pcie1(void)
 {
-	volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
+	volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #ifdef CONFIG_PCIE1
 	uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 	uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
-	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR;
+	volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CONFIG_SYS_PCIE1_ADDR;
 	extern void fsl_pci_init(struct pci_controller *hose);
 	struct pci_controller *hose = &pcie1_hose;
 	int pcie_ep =  (host_agent == 0) || (host_agent == 2 ) ||
@@ -661,23 +661,23 @@
 
 		/* inbound */
 		pci_set_region (hose->regions + 0,
-				CFG_PCI_MEMORY_BUS,
-				CFG_PCI_MEMORY_PHYS,
-				CFG_PCI_MEMORY_SIZE,
+				CONFIG_SYS_PCI_MEMORY_BUS,
+				CONFIG_SYS_PCI_MEMORY_PHYS,
+				CONFIG_SYS_PCI_MEMORY_SIZE,
 				PCI_REGION_MEM | PCI_REGION_MEMORY);
 
 		/* outbound memory */
 		pci_set_region (hose->regions + 1,
-				CFG_PCIE1_MEM_BASE,
-				CFG_PCIE1_MEM_PHYS,
-				CFG_PCIE1_MEM_SIZE,
+				CONFIG_SYS_PCIE1_MEM_BASE,
+				CONFIG_SYS_PCIE1_MEM_PHYS,
+				CONFIG_SYS_PCIE1_MEM_SIZE,
 				PCI_REGION_MEM);
 
 		/* outbound io */
 		pci_set_region (hose->regions + 2,
-				CFG_PCIE1_IO_BASE,
-				CFG_PCIE1_IO_PHYS,
-				CFG_PCIE1_IO_SIZE,
+				CONFIG_SYS_PCIE1_IO_BASE,
+				CONFIG_SYS_PCIE1_IO_PHYS,
+				CONFIG_SYS_PCIE1_IO_SIZE,
 				PCI_REGION_IO);
 
 		hose->region_count = 3;
diff --git a/board/tqc/tqm8xx/load_sernum_ethaddr.c b/board/tqc/tqm8xx/load_sernum_ethaddr.c
index 143f368..d269902 100644
--- a/board/tqc/tqm8xx/load_sernum_ethaddr.c
+++ b/board/tqc/tqm8xx/load_sernum_ethaddr.c
@@ -52,21 +52,21 @@
 void load_sernum_ethaddr (void)
 {
 	unsigned char *hwi;
-	unsigned char  serial [CFG_HWINFO_SIZE];
-	unsigned char  ethaddr[CFG_HWINFO_SIZE];
+	unsigned char  serial [CONFIG_SYS_HWINFO_SIZE];
+	unsigned char  ethaddr[CONFIG_SYS_HWINFO_SIZE];
 	unsigned short ih, is, ie, part;
 
-	hwi = (unsigned char *)(CFG_FLASH_BASE + CFG_HWINFO_OFFSET);
+	hwi = (unsigned char *)(CONFIG_SYS_FLASH_BASE + CONFIG_SYS_HWINFO_OFFSET);
 	ih = is = ie = 0;
 
-	if (*((unsigned long *)hwi) != (unsigned long)CFG_HWINFO_MAGIC) {
+	if (*((unsigned long *)hwi) != (unsigned long)CONFIG_SYS_HWINFO_MAGIC) {
 		return;
 	}
 
 	part = 1;
 
 	/* copy serial # / MAC address */
-	while ((hwi[ih] != '\0') && (ih < CFG_HWINFO_SIZE)) {
+	while ((hwi[ih] != '\0') && (ih < CONFIG_SYS_HWINFO_SIZE)) {
 		if (hwi[ih] < ' ' || hwi[ih] > '~') { /* ASCII strings! */
 			return;
 		}
diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c
index 5537d04..9a0f3a0 100644
--- a/board/tqc/tqm8xx/tqm8xx.c
+++ b/board/tqc/tqm8xx/tqm8xx.c
@@ -139,7 +139,7 @@
 
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	long int size8, size9, size10;
 	long int size_b0 = 0;
@@ -154,7 +154,7 @@
 	 * with two SDRAM banks or four cycles every 31.2 us with one
 	 * bank. It will be adjusted after memory sizing.
 	 */
-	memctl->memc_mptpr = CFG_MPTPR_2BK_8K;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_8K;
 
 	/*
 	 * The following value is used as an address (i.e. opcode) for
@@ -176,19 +176,19 @@
 	 * preliminary addresses - these have to be modified after the
 	 * SDRAM size has been determined.
 	 */
-	memctl->memc_or2 = CFG_OR2_PRELIM;
-	memctl->memc_br2 = CFG_BR2_PRELIM;
+	memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
+	memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
 
 #ifndef	CONFIG_CAN_DRIVER
 	if ((board_type != 'L') &&
 	    (board_type != 'M') &&
 	    (board_type != 'D') ) {	/* only one SDRAM bank on L, M and D modules */
-		memctl->memc_or3 = CFG_OR3_PRELIM;
-		memctl->memc_br3 = CFG_BR3_PRELIM;
+		memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
+		memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
 	}
 #endif							/* CONFIG_CAN_DRIVER */
 
-	memctl->memc_mamr = CFG_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_8COL & (~(MAMR_PTAE));	/* no refresh yet */
 
 	udelay (200);
 
@@ -219,7 +219,7 @@
 	 *
 	 * try 8 column mode
 	 */
-	size8 = dram_size (CFG_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size8 = dram_size (CONFIG_SYS_MAMR_8COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 
 	udelay (1000);
@@ -227,30 +227,30 @@
 	/*
 	 * try 9 column mode
 	 */
-	size9 = dram_size (CFG_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size9 = dram_size (CONFIG_SYS_MAMR_9COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 
 	udelay(1000);
 
-#if defined(CFG_MAMR_10COL)
+#if defined(CONFIG_SYS_MAMR_10COL)
 	/*
 	 * try 10 column mode
 	 */
-	size10 = dram_size (CFG_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
+	size10 = dram_size (CONFIG_SYS_MAMR_10COL, SDRAM_BASE2_PRELIM, SDRAM_MAX_SIZE);
 	debug ("SDRAM Bank 0 in 10 column mode: %ld MB\n", size10 >> 20);
 #else
 	size10 = 0;
-#endif /* CFG_MAMR_10COL */
+#endif /* CONFIG_SYS_MAMR_10COL */
 
 	if ((size8 < size10) && (size9 < size10)) {
 		size_b0 = size10;
 	} else if ((size8 < size9) && (size10 < size9)) {
 		size_b0 = size9;
-		memctl->memc_mamr = CFG_MAMR_9COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_9COL;
 		udelay (500);
 	} else {
 		size_b0 = size8;
-		memctl->memc_mamr = CFG_MAMR_8COL;
+		memctl->memc_mamr = CONFIG_SYS_MAMR_8COL;
 		udelay (500);
 	}
 	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
@@ -281,7 +281,7 @@
 	 */
 	if ((size_b0 < 0x02000000) && (size_b1 < 0x02000000)) {
 		/* reduce to 15.6 us (62.4 us / quad) */
-		memctl->memc_mptpr = CFG_MPTPR_2BK_4K;
+		memctl->memc_mptpr = CONFIG_SYS_MPTPR_2BK_4K;
 		udelay (1000);
 	}
 
@@ -290,15 +290,15 @@
 	 */
 	if (size_b1 > size_b0) {	/* SDRAM Bank 1 is bigger - map first   */
 
-		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-		memctl->memc_br3 = (CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+		memctl->memc_or3 = ((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+		memctl->memc_br3 = (CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b0 > 0) {
 			/*
 			 * Position Bank 0 immediately above Bank 1
 			 */
-			memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
-			memctl->memc_br2 = ((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+			memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
+			memctl->memc_br2 = ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 					   + size_b1;
 		} else {
 			unsigned long reg;
@@ -312,24 +312,24 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 
 	} else {					/* SDRAM Bank 0 is bigger - map first   */
 
-		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+		memctl->memc_or2 = ((-size_b0) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 		memctl->memc_br2 =
-				(CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
+				(CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V;
 
 		if (size_b1 > 0) {
 			/*
 			 * Position Bank 1 immediately above Bank 0
 			 */
 			memctl->memc_or3 =
-					((-size_b1) & 0xFFFF0000) | CFG_OR_TIMING_SDRAM;
+					((-size_b1) & 0xFFFF0000) | CONFIG_SYS_OR_TIMING_SDRAM;
 			memctl->memc_br3 =
-					((CFG_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
+					((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V)
 					+ size_b0;
 		} else {
 			unsigned long reg;
@@ -345,7 +345,7 @@
 
 			/* adjust refresh rate depending on SDRAM type, one bank */
 			reg = memctl->memc_mptpr;
-			reg >>= 1;			/* reduce to CFG_MPTPR_1BK_8K / _4K */
+			reg >>= 1;			/* reduce to CONFIG_SYS_MPTPR_1BK_8K / _4K */
 			memctl->memc_mptpr = reg;
 		}
 	}
@@ -356,8 +356,8 @@
 	/* UPM initialization for CAN @ CLKOUT <= 66 MHz */
 
 	/* Initialize OR3 / BR3 */
-	memctl->memc_or3 = CFG_OR3_CAN;
-	memctl->memc_br3 = CFG_BR3_CAN;
+	memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+	memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 
 	/* Initialize MBMR */
 	memctl->memc_mbmr = MBMR_GPL_B4DIS;	/* GPL_B4 ouput line Disable */
@@ -397,8 +397,8 @@
 
 #ifdef	CONFIG_ISP1362_USB
 	/* Initialize OR5 / BR5 */
-	memctl->memc_or5 = CFG_OR5_ISP1362;
-	memctl->memc_br5 = CFG_BR5_ISP1362;
+	memctl->memc_or5 = CONFIG_SYS_OR5_ISP1362;
+	memctl->memc_br5 = CONFIG_SYS_BR5_ISP1362;
 #endif							/* CONFIG_ISP1362_USB */
 	return (size_b0 + size_b1);
 }
@@ -415,7 +415,7 @@
 
 static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	memctl->memc_mamr = mamr_value;
@@ -451,14 +451,14 @@
 #ifdef CONFIG_MISC_INIT_R
 int misc_init_r (void)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
-#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 	int scy, trlx, flash_or_timing, clk_diff;
 
-	scy = (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
-	if (CFG_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
+	scy = (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_SCY_MSK) >> 4;
+	if (CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & OR_TRLX) {
 		trlx = OR_TRLX;
 		scy *= 2;
 	} else {
@@ -498,29 +498,29 @@
 		scy = 1;
 
 	flash_or_timing = (scy << 4) | trlx |
-		(CFG_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
+		(CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ & ~(OR_TRLX | OR_SCY_MSK));
 
 	memctl->memc_or0 =
 		flash_or_timing | (-flash_info[0].size & OR_AM_MSK);
 #else
 	memctl->memc_or0 =
-		CFG_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
+		CONFIG_SYS_OR_TIMING_FLASH | (-flash_info[0].size & OR_AM_MSK);
 #endif
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	debug ("## BR0: 0x%08x    OR0: 0x%08x\n",
 	       memctl->memc_br0, memctl->memc_or0);
 
 	if (flash_info[1].size) {
-#ifdef	CFG_OR_TIMING_FLASH_AT_50MHZ
+#ifdef	CONFIG_SYS_OR_TIMING_FLASH_AT_50MHZ
 		memctl->memc_or1 = flash_or_timing |
 			(-flash_info[1].size & 0xFFFF8000);
 #else
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH |
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH |
 			(-flash_info[1].size & 0xFFFF8000);
 #endif
 		memctl->memc_br1 =
-			((CFG_FLASH_BASE +
+			((CONFIG_SYS_FLASH_BASE +
 			  flash_info[0].
 			  size) & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
@@ -557,7 +557,7 @@
 # ifdef CONFIG_IDE_LED
 void ide_led (uchar led, uchar status)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 
 	/* We have one led for both pcmcia slots */
 	if (status) {				/* led on */
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index 46110cc..9932790 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -28,7 +28,7 @@
 #include <asm/byteorder.h>
 #include <usb.h>
 
-#ifdef CFG_HUSH_PARSER
+#ifdef CONFIG_SYS_HUSH_PARSER
 #include <hush.h>
 #endif
 
@@ -42,8 +42,8 @@
 #error "must define CONFIG_USB_STORAGE"
 #endif
 
-#ifndef CFG_HUSH_PARSER
-#error "must define CFG_HUSH_PARSER"
+#ifndef CONFIG_SYS_HUSH_PARSER
+#error "must define CONFIG_SYS_HUSH_PARSER"
 #endif
 
 #if !defined(CONFIG_CMD_FAT)
diff --git a/board/trab/flash.c b/board/trab/flash.c
index 08723bd..317b61d 100644
--- a/board/trab/flash.c
+++ b/board/trab/flash.c
@@ -28,7 +28,7 @@
 
 static ulong flash_get_size (vu_long *addr, flash_info_t *info);
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 
 #define CMD_READ_ARRAY		0x00F000F0
@@ -42,9 +42,9 @@
 #define CMD_UNLOCK_BYPASS_RES1	0x00900090
 #define CMD_UNLOCK_BYPASS_RES2	0x00000000
 
-#define MEM_FLASH_ADDR		(*(volatile u32 *)CFG_FLASH_BASE)
-#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CFG_FLASH_BASE + (0x00000555 << 2)))
-#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CFG_FLASH_BASE + (0x000002AA << 2)))
+#define MEM_FLASH_ADDR		(*(volatile u32 *)CONFIG_SYS_FLASH_BASE)
+#define MEM_FLASH_ADDR1		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 2)))
+#define MEM_FLASH_ADDR2		(*(volatile u32 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 2)))
 
 #define BIT_ERASE_DONE		0x00800080
 #define BIT_RDY_MASK		0x00800080
@@ -63,17 +63,17 @@
 	int i, j;
 	ulong size = 0;
 
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		ulong flashbase = 0;
 		flash_info_t *info = &flash_info[i];
 
 		/* Init: no FLASHes known */
 		info->flash_id = FLASH_UNKNOWN;
 
-		size += flash_get_size (CFG_FLASH_BASE, info);
+		size += flash_get_size (CONFIG_SYS_FLASH_BASE, info);
 
 		if (i == 0)
-			flashbase = CFG_FLASH_BASE;
+			flashbase = CONFIG_SYS_FLASH_BASE;
 		else
 			panic ("configured too many flash banks!\n");
 		for (j = 0; j < info->sector_count; j++) {
@@ -102,8 +102,8 @@
 	 * Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0]);
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -257,7 +257,7 @@
 				result = *addr;
 
 				/* check timeout */
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					MEM_FLASH_ADDR1 = CMD_READ_ARRAY;
 					chip1 = TMO;
 					break;
@@ -356,7 +356,7 @@
 		result = *addr;
 
 		/* check timeout */
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			chip1 = ERR | TMO;
 			break;
 		}
@@ -559,10 +559,10 @@
 
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	return (info->size);
diff --git a/board/trab/memory.c b/board/trab/memory.c
index 052432e..8fb3d2c 100644
--- a/board/trab/memory.c
+++ b/board/trab/memory.c
@@ -155,7 +155,7 @@
 #include <post.h>
 #include <watchdog.h>
 
-/* #if CONFIG_POST & CFG_POST_MEMORY */
+/* #if CONFIG_POST & CONFIG_SYS_POST_MEMORY */
 
 /*
  * Define INJECT_*_ERRORS for testing error detection in the presence of
@@ -465,7 +465,7 @@
 
 
 	if (flags & POST_SLOWTEST) {
-		ret = memory_post_tests (CFG_SDRAM_BASE, memsize);
+		ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
 	} else {			/* POST_NORMAL */
 
 		unsigned long i;
@@ -482,5 +482,5 @@
 }
 #endif /* 0 */
 
-/* #endif */ /* CONFIG_POST & CFG_POST_MEMORY */
+/* #endif */ /* CONFIG_POST & CONFIG_SYS_POST_MEMORY */
 /* #endif */ /* CONFIG_POST */
diff --git a/board/trab/trab.c b/board/trab/trab.c
index b869023..57ff718 100644
--- a/board/trab/trab.c
+++ b/board/trab/trab.c
@@ -30,7 +30,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CFG_BRIGHTNESS
+#ifdef CONFIG_SYS_BRIGHTNESS
 static void spi_init(void);
 static void wait_transmit_done(void);
 static void tsc2000_write(unsigned int page, unsigned int reg,
@@ -199,7 +199,7 @@
 		free (str);
 	}
 
-#ifdef CFG_BRIGHTNESS
+#ifdef CONFIG_SYS_BRIGHTNESS
 	tsc2000_set_brightness();
 #endif
 	return (0);
@@ -333,7 +333,7 @@
 }
 #endif	/* CONFIG_MODEM_SUPPORT */
 
-#ifdef CFG_BRIGHTNESS
+#ifdef CONFIG_SYS_BRIGHTNESS
 
 static inline void SET_CS_TOUCH(void)
 {
@@ -415,7 +415,7 @@
 	i = getenv_r("brightness", tmp, sizeof(tmp));
 	br = (i > 0)
 		? (int) simple_strtoul (tmp, NULL, 10)
-		: CFG_BRIGHTNESS;
+		: CONFIG_SYS_BRIGHTNESS;
 
 	tsc2000_write(0, 0xb, br & 0xff);
 }
diff --git a/board/trizepsiv/lowlevel_init.S b/board/trizepsiv/lowlevel_init.S
index d886938..128d554 100644
--- a/board/trizepsiv/lowlevel_init.S
+++ b/board/trizepsiv/lowlevel_init.S
@@ -49,119 +49,119 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr		r0,	=GPSR0
-	ldr		r1,	=CFG_GPSR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR1
-	ldr		r1,	=CFG_GPSR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR2
-	ldr		r1,	=CFG_GPSR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPSR3
-	ldr		r1,	=CFG_GPSR3_VAL
+	ldr		r1,	=CONFIG_SYS_GPSR3_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR0
-	ldr		r1,	=CFG_GPCR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR1
-	ldr		r1,	=CFG_GPCR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR2
-	ldr		r1,	=CFG_GPCR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPCR3
-	ldr		r1,	=CFG_GPCR3_VAL
+	ldr		r1,	=CONFIG_SYS_GPCR3_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GRER0
-	ldr		r1,	=CFG_GRER0_VAL
+	ldr		r1,	=CONFIG_SYS_GRER0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GRER1
-	ldr		r1,	=CFG_GRER1_VAL
+	ldr		r1,	=CONFIG_SYS_GRER1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GRER2
-	ldr		r1,	=CFG_GRER2_VAL
+	ldr		r1,	=CONFIG_SYS_GRER2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GRER3
-	ldr		r1,	=CFG_GRER3_VAL
+	ldr		r1,	=CONFIG_SYS_GRER3_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GFER0
-	ldr		r1,	=CFG_GFER0_VAL
+	ldr		r1,	=CONFIG_SYS_GFER0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GFER1
-	ldr		r1,	=CFG_GFER1_VAL
+	ldr		r1,	=CONFIG_SYS_GFER1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GFER2
-	ldr		r1,	=CFG_GFER2_VAL
+	ldr		r1,	=CONFIG_SYS_GFER2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GFER3
-	ldr		r1,	=CFG_GFER3_VAL
+	ldr		r1,	=CONFIG_SYS_GFER3_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR0
-	ldr		r1,	=CFG_GPDR0_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR0_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR1
-	ldr		r1,	=CFG_GPDR1_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR1_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR2
-	ldr		r1,	=CFG_GPDR2_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR2_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GPDR3
-	ldr		r1,	=CFG_GPDR3_VAL
+	ldr		r1,	=CONFIG_SYS_GPDR3_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_L
-	ldr		r1,	=CFG_GAFR0_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR0_U
-	ldr		r1,	=CFG_GAFR0_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR0_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_L
-	ldr		r1,	=CFG_GAFR1_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR1_U
-	ldr		r1,	=CFG_GAFR1_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR1_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_L
-	ldr		r1,	=CFG_GAFR2_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR2_U
-	ldr		r1,	=CFG_GAFR2_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR2_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR3_L
-	ldr		r1,	=CFG_GAFR3_L_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR3_L_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=GAFR3_U
-	ldr		r1,	=CFG_GAFR3_U_VAL
+	ldr		r1,	=CONFIG_SYS_GAFR3_U_VAL
 	str		r1,   [r0]
 
 	ldr		r0,	=PSSR		/* enable GPIO pins */
-	ldr		r1,	=CFG_PSSR_VAL
+	ldr		r1,	=CONFIG_SYS_PSSR_VAL
 	str		r1,   [r0]
 
 	/* ---------------------------------------------------------------- */
@@ -199,17 +199,17 @@
 	/* MSC registers: timing, bus width, mem type			    */
 
 	/* MSC0: nCS(0,1)						    */
-	ldr	r2,   =CFG_MSC0_VAL
+	ldr	r2,   =CONFIG_SYS_MSC0_VAL
 	str	r2,   [r1, #MSC0_OFFSET]
 	ldr	r2,   [r1, #MSC0_OFFSET]	/* read back to ensure	    */
 						/* that data latches	    */
 	/* MSC1: nCS(2,3)						    */
-	ldr	r2,  =CFG_MSC1_VAL
+	ldr	r2,  =CONFIG_SYS_MSC1_VAL
 	str	r2,  [r1, #MSC1_OFFSET]
 	ldr	r2,  [r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)						    */
-	ldr	r2,  =CFG_MSC2_VAL
+	ldr	r2,  =CONFIG_SYS_MSC2_VAL
 	str	r2,  [r1, #MSC2_OFFSET]
 	ldr	r2,  [r1, #MSC2_OFFSET]
 
@@ -218,44 +218,44 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register				    */
-	ldr	r2,  =CFG_MECR_VAL
+	ldr	r2,  =CONFIG_SYS_MECR_VAL
 	str	r2,  [r1, #MECR_OFFSET]
 	ldr	r2,	[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing				    */
-	ldr	r2,  =CFG_MCMEM0_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
 	str	r2,  [r1, #MCMEM0_OFFSET]
 	ldr	r2,	[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing				    */
-	ldr	r2,  =CFG_MCMEM1_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
 	str	r2,  [r1, #MCMEM1_OFFSET]
 	ldr	r2,	[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0	    */
-	ldr	r2,  =CFG_MCATT0_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
 	str	r2,  [r1, #MCATT0_OFFSET]
 	ldr	r2,	[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1	    */
-	ldr	r2,  =CFG_MCATT1_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
 	str	r2,  [r1, #MCATT1_OFFSET]
 	ldr	r2,	[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0		    */
-	ldr	r2,  =CFG_MCIO0_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
 	str	r2,  [r1, #MCIO0_OFFSET]
 	ldr	r2,	[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1		    */
-	ldr	r2,  =CFG_MCIO1_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
 	str	r2,  [r1, #MCIO1_OFFSET]
 	ldr	r2,	[r1, #MCIO1_OFFSET]
 
 	/* ---------------------------------------------------------------- */
 	/* Step 2c: Write FLYCNFG  FIXME: what's that???		    */
 	/* ---------------------------------------------------------------- */
-	ldr	r2,  =CFG_FLYCNFG_VAL
+	ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
 	str	r2,  [r1, #FLYCNFG_OFFSET]
 	str	r2,	[r1, #FLYCNFG_OFFSET]
 
@@ -270,7 +270,7 @@
 	ldr	r2,	=0xFFF
 	bic	r4,	r4, r2
 
-	ldr	r3,	=CFG_MDREFR_VAL
+	ldr	r3,	=CONFIG_SYS_MDREFR_VAL
 	and	r3,	r3,  r2
 
 	orr	r4,	r4, r3
@@ -300,7 +300,7 @@
 	/* synchronous static memory. Note that SXLCR need not be written   */
 	/* at this time.						    */
 
-	ldr	r2,  =CFG_SXCNFG_VAL
+	ldr	r2,  =CONFIG_SYS_SXCNFG_VAL
 	str	r2,  [r1, #SXCNFG_OFFSET]
 
 	/* ---------------------------------------------------------------- */
@@ -329,7 +329,7 @@
 	/* Step 4d: write MDCNFG with MDCNFG:DEx deasserted (set to 0), to  */
 	/*	    configure but not enable each SDRAM partition pair.	    */
 
-	ldr	r4,	=CFG_MDCNFG_VAL
+	ldr	r4,	=CONFIG_SYS_MDCNFG_VAL
 	bic	r4,	r4,	#(MDCNFG_DE0|MDCNFG_DE1)
 	bic	r4,	r4,	#(MDCNFG_DE2|MDCNFG_DE3)
 
@@ -357,7 +357,7 @@
 	/*	    documented in SDRAM data sheets. The address(es) used   */
 	/*	    for this purpose must not be cacheable.		    */
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
@@ -379,7 +379,7 @@
 
 	/* Step 4h: Write MDMRS.					    */
 
-	ldr	r2,  =CFG_MDMRS_VAL
+	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
 	str	r2,  [r1, #MDMRS_OFFSET]
 
 	/* enable APD */
@@ -443,11 +443,11 @@
 	/* Turn Off on-chip peripheral clocks (except for memory)	    */
 	/* for re-configuration.					    */
 	ldr	r1,  =CKEN
-	ldr	r2,  =CFG_CKEN
+	ldr	r2,  =CONFIG_SYS_CKEN
 	str	r2,  [r1]
 
 	/* ... and write the core clock config register			    */
-	ldr	r2,  =CFG_CCCR
+	ldr	r2,  =CONFIG_SYS_CCCR
 	ldr	r1,  =CCCR
 	str	r2,  [r1]
 
diff --git a/board/uc100/pcmcia.c b/board/uc100/pcmcia.c
index 407bdb7..ad25678 100644
--- a/board/uc100/pcmcia.c
+++ b/board/uc100/pcmcia.c
@@ -24,7 +24,7 @@
 {
 	volatile immap_t	*immap;
 
-	immap = (immap_t *)CFG_IMMR;
+	immap = (immap_t *)CONFIG_SYS_IMMR;
 
 	/*
 	* Configure Port A for MAX1602 PC-Card Power-Interface Switch
@@ -49,10 +49,10 @@
 
 	udelay(10000);
 
-	immap = (immap_t *)CFG_IMMR;
-	sysp  = (sysconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_siu_conf));
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
-	cp    = (cpm8xx_t *)(&(((immap_t *)CFG_IMMR)->im_cpm));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	sysp  = (sysconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_siu_conf));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
+	cp    = (cpm8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_cpm));
 
 	/* Configure Ports for TPS2211A PC-Card Power-Interface Switch */
 	cfg_ports ();
@@ -133,8 +133,8 @@
 
 	debug ("hardware_disable: " PCMCIA_BOARD_MSG " Slot %c\n", 'A'+slot);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	/* switch VCC off */
 	immap->im_ioport.iop_padat &= ~0x8000; /* power disable 3.3V */
@@ -163,8 +163,8 @@
 			" Slot %c, Vcc=%d.%d, Vpp=%d.%d\n",
 	'A'+slot, vcc/10, vcc%10, vpp/10, vcc%10);
 
-	immap = (immap_t *)CFG_IMMR;
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	immap = (immap_t *)CONFIG_SYS_IMMR;
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 	/*
 	* Disable PCMCIA buffers (isolate the interface)
 	* and assert RESET signal
diff --git a/board/uc100/uc100.c b/board/uc100/uc100.c
index 896f969..38c7be6 100644
--- a/board/uc100/uc100.c
+++ b/board/uc100/uc100.c
@@ -138,7 +138,7 @@
 {
 	volatile pcmconf8xx_t	*pcmp;
 
-	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CFG_IMMR)->im_pcmcia));
+	pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 
 	return ((pcmp->pcmc_pipr >> 24) & 0xf);
 }
@@ -171,7 +171,7 @@
  */
 phys_size_t initdram (int board_type)
 {
-	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/*---------------------------------------------------------------------*/
@@ -187,8 +187,8 @@
 	/*---------------------------------------------------------------------*/
 	memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
 
-	memctl->memc_mamr = CFG_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
-	memctl->memc_mbmr = CFG_MBMR_VAL;
+	memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
+	memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
 
 	/*---------------------------------------------------------------------*/
 	/* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
@@ -198,8 +198,8 @@
 	/*       clock rate (16.67MHz) to allow proper operation for all ADS   */
 	/*       clock frequencies.                                            */
 	/*---------------------------------------------------------------------*/
-	memctl->memc_or1 = CFG_OR1_PRELIM;
-	memctl->memc_br1 = CFG_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 
 	/*-------------------------------------------------------------------*/
 	/* Wait at least 200 usec for DRAM to stabilize, this magic number   */
@@ -209,8 +209,8 @@
 
 	memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
 
-	memctl->memc_br1 = CFG_BR1_PRELIM;
-	memctl->memc_or1 = CFG_OR1_PRELIM;
+	memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
+	memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 
 	/*---------------------------------------------------------------------*/
 	/* run MRS command in location 5-8 of UPMB.                            */
@@ -236,7 +236,7 @@
 	/*---------------------------------------------------------------------*/
 	/* rerstore MBMR value (4-beat refresh burst.)                         */
 	/*---------------------------------------------------------------------*/
-	memctl->memc_mamr = CFG_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
+	memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
 
 	udelay(200);
 
@@ -251,9 +251,9 @@
 	/*
 	 * Make sure that RTC has clock output enabled (triggers watchdog!)
 	 */
-	val = i2c_reg_read (CFG_I2C_RTC_ADDR, 0x0D);
+	val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
 	val |= 0x80;
-	i2c_reg_write (CFG_I2C_RTC_ADDR, 0x0D, val);
+	i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
 
 	/*
 	 * Configure PHY to setup LED's correctly and use 100MBit, FD
diff --git a/board/uc101/uc101.c b/board/uc101/uc101.c
index 69ba507..7df349f 100644
--- a/board/uc101/uc101.c
+++ b/board/uc101/uc101.c
@@ -99,7 +99,7 @@
 #define GP_TIMER_GET_I(n, v) ( \
 	(((volatile struct mpc5xxx_gpt *)(MPC5XXX_GPT + n))->sr & 0x100) >> 8)
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start (int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -142,14 +142,14 @@
 
 /*
  * ATTENTION: Although partially referenced initdram does NOT make real use
- *	      use of CFG_SDRAM_BASE. The code does not work if CFG_SDRAM_BASE
+ *	      use of CONFIG_SYS_SDRAM_BASE. The code does not work if CONFIG_SYS_SDRAM_BASE
  *	      is something else than 0x00000000.
  */
 
 phys_size_t initdram (int board_type)
 {
 	ulong dramsize = 0;
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -170,9 +170,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x20000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -194,7 +194,7 @@
 	}
 
 	*(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -212,7 +212,7 @@
 		dramsize2 = 0;
 	}
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 /*	return dramsize + dramsize2; */
 	return dramsize;
@@ -222,7 +222,7 @@
 {
 	puts ("Board: MAN UC101\n");
 	/* clear the Display */
-	*(char *)(CFG_DISP_CWORD) = 0x80;
+	*(char *)(CONFIG_SYS_DISP_CWORD) = 0x80;
 	return 0;
 }
 
@@ -345,9 +345,9 @@
 {
 	*(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1; /* clear RO */
 	*(vu_long *)MPC5XXX_BOOTCS_START =
-	*(vu_long *)MPC5XXX_CS0_START = START_REG(CFG_FLASH_BASE);
+	*(vu_long *)MPC5XXX_CS0_START = START_REG(CONFIG_SYS_FLASH_BASE);
 	*(vu_long *)MPC5XXX_BOOTCS_STOP =
-	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CFG_FLASH_BASE, CFG_FLASH_SIZE);
+	*(vu_long *)MPC5XXX_CS0_STOP = STOP_REG(CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_SIZE);
 	/* Interbus enable it here ?? */
 	*(vu_long *)MPC5XXX_GPT6_ENABLE = GPT_OUT_1;
 	return 0;
diff --git a/board/utx8245/flash.c b/board/utx8245/flash.c
index 5aab886..aac8116 100644
--- a/board/utx8245/flash.c
+++ b/board/utx8245/flash.c
@@ -35,7 +35,7 @@
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -50,7 +50,7 @@
 #define	SECT_SIZE_32KB	0x8000
 #define	SECT_SIZE_8KB	0x2000
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static int write_word (flash_info_t * info, ulong dest, ulong data);
 #if 0
@@ -80,8 +80,8 @@
 	ulong total_size = 0, device_size = 1;
 	unsigned char manuf_id, device_id;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
-		vu_char *addr = (vu_char *) (CFG_FLASH_BASE + i * FLASH_BANK_SIZE);
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
+		vu_char *addr = (vu_char *) (CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE);
 
 		addr[0x555] = 0xAA;		/* get manuf/device info command */
 		addr[0x2AA] = 0x55;		/* 3-cycle command */
@@ -97,7 +97,7 @@
 			device_size *= 2;
 
 		flash_info[i].size = device_size;
-		flash_info[i].sector_count = CFG_MAX_FLASH_SECT;
+		flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 
 #if defined DEBUG_FLASH
 		printf ("manuf_id = %x, device_id = %x\n", manuf_id, device_id);
@@ -112,7 +112,7 @@
 			/* set individual sector start addresses */
 			for (j = 0; j < flash_info[i].sector_count; j++) {
 				flash_info[i].start[j] =
-						(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+						(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
 						 j * MAIN_SECT_SIZE);
 			}
 		}
@@ -126,14 +126,14 @@
 			/* set individual sector start addresses */
 			for (j = 0; j < flash_info[i].sector_count; j++) {
 				flash_info[i].start[j] =
-						(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+						(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
 						 j * MAIN_SECT_SIZE);
 
-				if (j < (CFG_MAX_FLASH_SECT - 3)) {
+				if (j < (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
 					flash_info[i].start[j] =
-							(CFG_FLASH_BASE + i * FLASH_BANK_SIZE +
+							(CONFIG_SYS_FLASH_BASE + i * FLASH_BANK_SIZE +
 							 j * MAIN_SECT_SIZE);
-				} else if (j == (CFG_MAX_FLASH_SECT - 3)) {
+				} else if (j == (CONFIG_SYS_MAX_FLASH_SECT - 3)) {
 					flash_info[i].start[j] =
 							(flash_info[i].start[j - 1] + SECT_SIZE_32KB);
 
@@ -156,16 +156,16 @@
 
 		addr[0] = 0xFF;
 
-		memset (flash_info[i].protect, 0, CFG_MAX_FLASH_SECT);
+		memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
 		total_size += flash_info[i].size;
 	}
 
 	/* Protect monitor and environment sectors
 	 */
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
-	flash_protect (FLAG_PROTECT_SET, CFG_MONITOR_BASE,
-				   CFG_MONITOR_BASE + monitor_flash_len - 1,
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
+	flash_protect (FLAG_PROTECT_SET, CONFIG_SYS_MONITOR_BASE,
+				   CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1,
 				   &flash_info[0]);
 #endif
 
@@ -383,7 +383,7 @@
 												   start[0]) << sh8b));
 	while ((addr[0] & (FLASH_WORD_SIZE) 0x00800080) !=
 		   (FLASH_WORD_SIZE) 0x00800080) {
-		if ((now = get_timer (start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer (start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -524,7 +524,7 @@
 		start = get_timer (0);
 		while ((dest2[i << sh8b] & (FLASH_WORD_SIZE) 0x00800080) !=
 			   (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/utx8245/utx8245.c b/board/utx8245/utx8245.c
index e7ca669..8402689 100644
--- a/board/utx8245/utx8245.c
+++ b/board/utx8245/utx8245.c
@@ -55,7 +55,7 @@
 	long mear1;
 	long emear1;
 
-	size = get_ram_size(CFG_SDRAM_BASE, CFG_MAX_RAM_SIZE);
+	size = get_ram_size(CONFIG_SYS_SDRAM_BASE, CONFIG_SYS_MAX_RAM_SIZE);
 
 	new_bank0_end = size/2 - 1;
 	new_bank1_end = size - 1;
diff --git a/board/v37/flash.c b/board/v37/flash.c
index d845f65..9b817ec 100644
--- a/board/v37/flash.c
+++ b/board/v37/flash.c
@@ -38,7 +38,7 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -54,42 +54,42 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	short manu, dev_id;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
 	/* Do sizing to get full correct info */
 
-	flash_get_id_word((void*)CFG_FLASH_BASE0,&manu,&dev_id);
+	flash_get_id_word((void*)CONFIG_SYS_FLASH_BASE0,&manu,&dev_id);
 
 	size_b0 = flash_get_size(manu, dev_id, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE0, &flash_info[0],0);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE0, &flash_info[0],0);
 
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (0 - size_b0);
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b0);
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE0
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE0
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
-	flash_get_id_long((void*)CFG_FLASH_BASE1,&manu,&dev_id);
+	flash_get_id_long((void*)CONFIG_SYS_FLASH_BASE1,&manu,&dev_id);
 
 	size_b1 = 2 * flash_get_size(manu, dev_id, &flash_info[1]);
 
-	flash_get_offsets(CFG_FLASH_BASE1, &flash_info[1],1);
+	flash_get_offsets(CONFIG_SYS_FLASH_BASE1, &flash_info[1],1);
 
-	memctl->memc_or1 = CFG_OR_TIMING_FLASH | (0 - size_b1);
+	memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (0 - size_b1);
 
 	flash_info[0].size = size_b0;
 	flash_info[1].size = size_b1;
@@ -395,7 +395,7 @@
 	last  = start;
 	addr = (vu_short *)(info->start[l_sect]);
 	while ((addr[0] & 0x8080) != 0x8080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -524,7 +524,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_short *)dest) & 0x8080) != (sdata & 0x8080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
@@ -548,7 +548,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_short *)dest + 1) & 0x8080) != (sdata & 0x8080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/v37/v37.c b/board/v37/v37.c
index 2067fed..9c7bad5 100644
--- a/board/v37/v37.c
+++ b/board/v37/v37.c
@@ -92,7 +92,7 @@
 
 phys_size_t initdram (int board_type)
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile memctl8xx_t *memctl = &immap->im_memctl;
     unsigned long temp;
     volatile int delay_cnt;
@@ -136,8 +136,8 @@
 
 #ifdef	CONFIG_CAN_DRIVER
     /* Initialize OR3 / BR3 */
-    memctl->memc_or3 = CFG_OR3_CAN;
-    memctl->memc_br3 = CFG_BR3_CAN;
+    memctl->memc_or3 = CONFIG_SYS_OR3_CAN;
+    memctl->memc_br3 = CONFIG_SYS_BR3_CAN;
 
     /* Initialize MBMR */
     memctl->memc_mamr = MAMR_GPL_A4DIS;	/* GPL_A4 ouput line Disable */
@@ -191,7 +191,7 @@
 
 static long int dram_size ()
 {
-    volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+    volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
     volatile sysconf8xx_t *siu = &immap->im_siu_conf;
     volatile pcmconf8xx_t *pcm = &immap->im_pcmcia;
     long int		  i, memory=1;
diff --git a/board/v38b/v38b.c b/board/v38b/v38b.c
index 8815a0c..d774295 100644
--- a/board/v38b/v38b.c
+++ b/board/v38b/v38b.c
@@ -29,7 +29,7 @@
 #include <asm/processor.h>
 
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 static void sdram_start(int hi_addr)
 {
 	long hi_addr_bit = hi_addr ? 0x01000000 : 0;
@@ -68,7 +68,7 @@
 	*(vu_long *) MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
 	__asm__ volatile ("sync");
 }
-#endif /* !CFG_RAMBOOT */
+#endif /* !CONFIG_SYS_RAMBOOT */
 
 
 phys_size_t initdram(int board_type)
@@ -77,7 +77,7 @@
 	ulong dramsize2 = 0;
 	uint svr, pvr;
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	ulong test1, test2;
 
 	/* setup SDRAM chip selects */
@@ -98,9 +98,9 @@
 
 	/* find RAM size using SDRAM CS0 only */
 	sdram_start(0);
-	test1 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	sdram_start(1);
-	test2 = get_ram_size((long *)CFG_SDRAM_BASE, 0x80000000);
+	test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000);
 	if (test1 > test2) {
 		sdram_start(0);
 		dramsize = test1;
@@ -123,10 +123,10 @@
 	/* find RAM size using SDRAM CS1 only */
 	if (!dramsize)
 		sdram_start(0);
-	test2 = test1 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+	test2 = test1 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	if (!dramsize) {
 		sdram_start(1);
-		test2 = get_ram_size((long *) (CFG_SDRAM_BASE + dramsize), 0x80000000);
+		test2 = get_ram_size((long *) (CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000);
 	}
 	if (test1 > test2) {
 		sdram_start(0);
@@ -145,7 +145,7 @@
 	else
 		*(vu_long *) MPC5XXX_SDRAM_CS1CFG = dramsize; /* disabled */
 
-#else /* CFG_RAMBOOT */
+#else /* CONFIG_SYS_RAMBOOT */
 
 	/* retrieve size of memory connected to SDRAM CS0 */
 	dramsize = *(vu_long *) MPC5XXX_SDRAM_CS0CFG & 0xFF;
@@ -161,7 +161,7 @@
 	else
 		dramsize2 = 0;
 
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/*
 	 * On MPC5200B we need to set the special configuration delay in the
diff --git a/board/versatile/flash.c b/board/versatile/flash.c
index bbe5df7..3bdc895 100644
--- a/board/versatile/flash.c
+++ b/board/versatile/flash.c
@@ -32,7 +32,7 @@
 #include <linux/byteorder/swab.h>
 
 #define PHYS_FLASH_SECT_SIZE	0x00020000	/* 256 KB sectors (x2) */
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -101,7 +101,7 @@
 {
 	int i;
 	ulong size = 0;
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 		        flash_vpp(1);
@@ -119,8 +119,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect (FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, &flash_info[0]);
 
 	return size;
 }
@@ -246,10 +246,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-				info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+				info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;	/* restore read mode */
@@ -342,7 +342,7 @@
 				*addr) & (FPW) 0x00800080) !=
 				(FPW) 0x00800080) {
 					if (get_timer_masked () >
-					CFG_FLASH_ERASE_TOUT) {
+					CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					/* suspend erase     */
 					*addr = (FPW) 0x00B000B0;
@@ -493,7 +493,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			flash_vpp(0);
 			return (1);
diff --git a/board/w7o/cmd_vpd.c b/board/w7o/cmd_vpd.c
index fdd6ceb..310fde0 100644
--- a/board/w7o/cmd_vpd.c
+++ b/board/w7o/cmd_vpd.c
@@ -35,7 +35,7 @@
 int do_vpd (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
 	VPD vpd;			/* Board specific data struct */
-	uchar dev_addr = CFG_DEF_EEPROM_ADDR;
+	uchar dev_addr = CONFIG_SYS_DEF_EEPROM_ADDR;
 
 	/* Validate usage */
 	if (argc > 2) {
diff --git a/board/w7o/flash.c b/board/w7o/flash.c
index 32815fb..6774949 100644
--- a/board/w7o/flash.c
+++ b/board/w7o/flash.c
@@ -29,7 +29,7 @@
 
 #include <watchdog.h>
 
-flash_info_t    flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips    */
+flash_info_t    flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips    */
 
 /*-----------------------------------------------------------------------
  * Functions
@@ -49,7 +49,7 @@
     unsigned long size_b1, base_b1;
 
     /* Init: no FLASHes known */
-    for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) {
+    for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 	flash_info[i].flash_id = FLASH_UNKNOWN;
     }
 
@@ -90,13 +90,13 @@
     /* Protect the FPGA image */
     (void)flash_protect(FLAG_PROTECT_SET,
 			FLASH_BASE1_PRELIM,
-			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN - 1,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN - 1,
 			&flash_info[1]);
 
     /* Protect the default boot image */
     (void)flash_protect(FLAG_PROTECT_SET,
-			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN,
-			FLASH_BASE1_PRELIM + CFG_FPGA_IMAGE_LEN + 0x600000 - 1,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN,
+			FLASH_BASE1_PRELIM + CONFIG_SYS_FPGA_IMAGE_LEN + 0x600000 - 1,
 			&flash_info[1]);
 
     /* Setup offsets for Main Flash */
@@ -294,11 +294,11 @@
 	}
     }
 
-    /* Make sure we don't exceed CFG_MAX_FLASH_SECT */
-    if (info->sector_count > CFG_MAX_FLASH_SECT) {
+    /* Make sure we don't exceed CONFIG_SYS_MAX_FLASH_SECT */
+    if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 	printf ("** ERROR: sector count %d > max (%d) **\n",
-		info->sector_count, CFG_MAX_FLASH_SECT);
-	info->sector_count = CFG_MAX_FLASH_SECT;
+		info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+	info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
     }
 
     /* set up sector start address table */
@@ -520,7 +520,7 @@
 	    udelay (1000);
 
 	    while (((status = *addr) & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 		    printf ("Timeout\n");
 		    *addr = 0x00B000B0;      /* suspend erase      */
 		    *addr = 0x00FF00FF;      /* reset to read mode */
@@ -787,7 +787,7 @@
 
     while (((status = *addr) & 0x00800080) != 0x00800080) {
 	WATCHDOG_RESET();
-	if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+	if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 	    *addr = 0x00FF00FF;              /* restore read mode */
 	    return (1);
 	}
diff --git a/board/w7o/init.S b/board/w7o/init.S
index 35d7dbc..2fd84ba 100644
--- a/board/w7o/init.S
+++ b/board/w7o/init.S
@@ -64,11 +64,11 @@
 	mflr	r3			/* get address of ..getAddr */
 
 	/* Calculate number of cache lines for this function */
-	addi	r4, 0, (((.Lfe0 - ..getAddr) / CFG_CACHELINE_SIZE) + 2)
+	addi	r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
 	mtctr	r4
 ..ebcloop:
 	icbt	r0, r3			/* prefetch cache line for addr in r3*/
-	addi	r3, r3, CFG_CACHELINE_SIZE /* move to next cache line */
+	addi	r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
 	bdnz	..ebcloop		/* continue for $CTR cache lines */
 
 	/********************************************************************
@@ -103,14 +103,14 @@
 	 *******************************************************************/
 	addi	r3, 0, pb0ap
 	mtdcr	ebccfga, r3
-	addis	r4, 0, CFG_W7O_EBC_PB0AP@h
-	ori	r4, r4, CFG_W7O_EBC_PB0AP@l
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0AP@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0AP@l
 	mtdcr	ebccfgd, r4
 
 	addi	r3, 0, pb0cr
 	mtdcr	ebccfga, r3
-	addis	r4, 0, CFG_W7O_EBC_PB0CR@h
-	ori	r4, r4, CFG_W7O_EBC_PB0CR@l
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB0CR@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB0CR@l
 	mtdcr	ebccfgd, r4
 
 	/********************************************************************
@@ -118,14 +118,14 @@
 	 *******************************************************************/
 	addi	r3, 0, pb7ap
 	mtdcr	ebccfga, r3
-	addis	r4, 0, CFG_W7O_EBC_PB7AP@h
-	ori	r4, r4, CFG_W7O_EBC_PB7AP@l
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7AP@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7AP@l
 	mtdcr	ebccfgd, r4
 
 	addi	r3, 0, pb7cr
 	mtdcr	ebccfga, r3
-	addis	r4, 0, CFG_W7O_EBC_PB7CR@h
-	ori	r4, r4, CFG_W7O_EBC_PB7CR@l
+	addis	r4, 0, CONFIG_SYS_W7O_EBC_PB7CR@h
+	ori	r4, r4, CONFIG_SYS_W7O_EBC_PB7CR@l
 	mtdcr	ebccfgd, r4
 
 	/* We are all done */
diff --git a/board/w7o/post2.c b/board/w7o/post2.c
index 6ee33eb..1dfaa2f 100644
--- a/board/w7o/post2.c
+++ b/board/w7o/post2.c
@@ -38,7 +38,7 @@
 #if defined(CONFIG_RTC_M48T35A)
 void rtctest(void)
 {
-    volatile uchar *tchar = (uchar*)(CFG_NVRAM_BASE_ADDR + CFG_NVRAM_SIZE - 9);
+    volatile uchar *tchar = (uchar*)(CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 9);
     struct rtc_time tmp;
 
     /* set up led code for RTC tests */
@@ -89,9 +89,9 @@
     hyst = dtt_read(sensor, DTT_TEMP_HYST) / 256;
 
     /* check values */
-    if ((hyst != (CFG_DTT_MAX_TEMP - CFG_DTT_HYSTERESIS)) ||
-	(trip != CFG_DTT_MAX_TEMP) ||
-	(temp < CFG_DTT_LOW_TEMP) || (temp > CFG_DTT_MAX_TEMP))
+    if ((hyst != (CONFIG_SYS_DTT_MAX_TEMP - CONFIG_SYS_DTT_HYSTERESIS)) ||
+	(trip != CONFIG_SYS_DTT_MAX_TEMP) ||
+	(temp < CONFIG_SYS_DTT_LOW_TEMP) || (temp > CONFIG_SYS_DTT_MAX_TEMP))
 	return 1;
 
     return 0;
diff --git a/board/w7o/vpd.c b/board/w7o/vpd.c
index 2ce1568..57558e8 100644
--- a/board/w7o/vpd.c
+++ b/board/w7o/vpd.c
@@ -24,7 +24,7 @@
 #if defined(VXWORKS)
 # include <stdio.h>
 # include <string.h>
-# define CFG_DEF_EEPROM_ADDR 0xa0
+# define CONFIG_SYS_DEF_EEPROM_ADDR 0xa0
 extern char iicReadByte( char, char );
 extern ulong_t crc32( unsigned char *, unsigned long );
 #else
@@ -47,7 +47,7 @@
      * SDRAM SPD in the first 128 bytes,
      * so skew the offset.
      */
-    if (dev_addr == CFG_DEF_EEPROM_ADDR)
+    if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
 	offset += SDRAM_SPD_DATA_SIZE;
 
     /* Try to read the I2C EEPROM */
@@ -127,7 +127,7 @@
     /* Check Eyecatcher */
     if (strncmp((char *)(vpd->header.eyecatcher), VPD_EYECATCHER, VPD_EYE_SIZE) != 0) {
 	unsigned offset = 0;
-	if (dev_addr == CFG_DEF_EEPROM_ADDR)
+	if (dev_addr == CONFIG_SYS_DEF_EEPROM_ADDR)
 	    offset += SDRAM_SPD_DATA_SIZE;
 	printf("Error: VPD EEPROM 0x%x corrupt @ 0x%x\n", dev_addr, offset);
 
diff --git a/board/w7o/w7o.c b/board/w7o/w7o.c
index 0e3b84c..22cdfcd 100644
--- a/board/w7o/w7o.c
+++ b/board/w7o/w7o.c
@@ -132,7 +132,7 @@
 	puts ("Board: ");
 
 	/* VPD data present in I2C EEPROM */
-	if (vpd_get_data (CFG_DEF_EEPROM_ADDR, &vpd) == 0) {
+	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, &vpd) == 0) {
 		/*
 		 * Known board type.
 		 */
@@ -204,7 +204,7 @@
 	/*
 	 * Read VPD
 	 */
-	if (vpd_get_data (CFG_DEF_EEPROM_ADDR, vpd) != 0)
+	if (vpd_get_data (CONFIG_SYS_DEF_EEPROM_ADDR, vpd) != 0)
 		return;
 
 	/*
diff --git a/board/w7o/watchdog.c b/board/w7o/watchdog.c
index 4bbd94f..131399c 100644
--- a/board/w7o/watchdog.c
+++ b/board/w7o/watchdog.c
@@ -32,7 +32,7 @@
 
 void hw_watchdog_reset(void)
 {
-    volatile ushort *hwd = (ushort *)(CFG_W7O_EBC_PB7CR & 0xfff00000);
+    volatile ushort *hwd = (ushort *)(CONFIG_SYS_W7O_EBC_PB7CR & 0xfff00000);
 
     /*
      * Read the LMG's hwd register and toggle the
diff --git a/board/wepep250/flash.c b/board/wepep250/flash.c
index 6223ec1..c6e9171 100644
--- a/board/wepep250/flash.c
+++ b/board/wepep250/flash.c
@@ -82,7 +82,7 @@
 #endif
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];
 
 static FLASH_BUS_RET flash_status_reg (void)
 {
@@ -109,7 +109,7 @@
 	return ok;
 }
 
-#if ( CFG_MAX_FLASH_BANKS != 1 )
+#if ( CONFIG_SYS_MAX_FLASH_BANKS != 1 )
 #  error "WEP platform has only one flash bank!"
 #endif
 
@@ -120,11 +120,11 @@
 	FLASH_BUS address = WEP_FLASH_BASE;
 
 	flash_info[0].size = WEP_FLASH_BANK_SIZE;
-	flash_info[0].sector_count = CFG_MAX_FLASH_SECT;
+	flash_info[0].sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	flash_info[0].flash_id = INTEL_MANUFACT;
-	memset (flash_info[0].protect, 0, CFG_MAX_FLASH_SECT);
+	memset (flash_info[0].protect, 0, CONFIG_SYS_MAX_FLASH_SECT);
 
-	for (i = 0; i < CFG_MAX_FLASH_SECT; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_SECT; i++) {
 		flash_info[0].start[i] = address;
 #ifdef WEP_FLASH_UNLOCK
 		/* Some devices are hw locked after start. */
@@ -137,8 +137,8 @@
 	}
 
 	flash_protect (FLAG_PROTECT_SET,
-				   CFG_FLASH_BASE,
-				   CFG_FLASH_BASE + monitor_flash_len - 1,
+				   CONFIG_SYS_FLASH_BASE,
+				   CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 				   &flash_info[0]);
 
 	flash_protect (FLAG_PROTECT_SET,
@@ -209,7 +209,7 @@
 
 		*address = FLASH_CMD (CFI_INTEL_CMD_BLOCK_ERASE);
 		*address = FLASH_CMD (CFI_INTEL_CMD_CONFIRM);
-		if (flash_ready (CFG_FLASH_ERASE_TOUT)) {
+		if (flash_ready (CONFIG_SYS_FLASH_ERASE_TOUT)) {
 			*address = FLASH_CMD (CFI_INTEL_CMD_CLEAR_STATUS_REGISTER);
 			printf ("ok.\n");
 		} else {
@@ -257,7 +257,7 @@
 	*address = FLASH_CMD (CFI_INTEL_CMD_PROGRAM1);
 	*address = data;
 
-	if (!flash_ready (CFG_FLASH_WRITE_TOUT)) {
+	if (!flash_ready (CONFIG_SYS_FLASH_WRITE_TOUT)) {
 		*address = FLASH_CMD (CFI_INTEL_CMD_SUSPEND);
 		rc = ERR_TIMOUT;
 		printf ("timeout! Aborting...\n");
diff --git a/board/westel/amx860/amx860.c b/board/westel/amx860/amx860.c
index 4742aafc..91dcc0d 100644
--- a/board/westel/amx860/amx860.c
+++ b/board/westel/amx860/amx860.c
@@ -64,7 +64,7 @@
 phys_size_t initdram (int board_type)
 {
 
-	volatile immap_t     *immap = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 
 	/* AMX860: has 4 Mb of 60ns EDO DRAM, so start DRAM at 0 */
diff --git a/board/westel/amx860/flash.c b/board/westel/amx860/flash.c
index 7768e2d..fe8bce4 100644
--- a/board/westel/amx860/flash.c
+++ b/board/westel/amx860/flash.c
@@ -24,11 +24,11 @@
 #include <common.h>
 #include <mpc8xx.h>
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
 #if defined(CONFIG_ENV_IS_IN_FLASH)
 # ifndef  CONFIG_ENV_ADDR
-#  define CONFIG_ENV_ADDR	(CFG_FLASH_BASE + CONFIG_ENV_OFFSET)
+#  define CONFIG_ENV_ADDR	(CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 # endif
 # ifndef  CONFIG_ENV_SIZE
 #  define CONFIG_ENV_SIZE	CONFIG_ENV_SECT_SIZE
@@ -60,13 +60,13 @@
 
 unsigned long flash_init (void)
 {
-	volatile immap_t     *immap  = (immap_t *)CFG_IMMR;
+	volatile immap_t     *immap  = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
 	unsigned long size_b0, size_b1;
 	int i;
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 	}
 
@@ -113,24 +113,24 @@
 		memctl->memc_br1, memctl->memc_or1);
 
 	/* Remap FLASH according to real size */
-	memctl->memc_or0 = CFG_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
-	memctl->memc_br0 = (CFG_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
+	memctl->memc_or0 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b0 & OR_AM_MSK);
+	memctl->memc_br0 = (CONFIG_SYS_FLASH_BASE & BR_BA_MSK) | BR_MS_GPCM | BR_V;
 
 	DEBUGF("## BR0: 0x%08x    OR0: 0x%08x\n",
 		memctl->memc_br0, memctl->memc_or0);
 
 	/* Re-do sizing to get full correct info */
-	size_b0 = flash_get_size((vu_long *)CFG_FLASH_BASE, &flash_info[0]);
+	size_b0 = flash_get_size((vu_long *)CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
-	flash_get_offsets (CFG_FLASH_BASE, &flash_info[0]);
+	flash_get_offsets (CONFIG_SYS_FLASH_BASE, &flash_info[0]);
 
 	flash_info[0].size = size_b0;
 
-#if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 	/* monitor protection ON by default */
 	flash_protect(FLAG_PROTECT_SET,
-		      CFG_MONITOR_BASE,
-		      CFG_MONITOR_BASE+monitor_flash_len-1,
+		      CONFIG_SYS_MONITOR_BASE,
+		      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 		      &flash_info[0]);
 #endif
 
@@ -143,26 +143,26 @@
 #endif
 
 	if (size_b1) {
-		memctl->memc_or1 = CFG_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
-		memctl->memc_br1 = ((CFG_FLASH_BASE + size_b0) & BR_BA_MSK) |
+		memctl->memc_or1 = CONFIG_SYS_OR_TIMING_FLASH | (-size_b1 & OR_AM_MSK);
+		memctl->memc_br1 = ((CONFIG_SYS_FLASH_BASE + size_b0) & BR_BA_MSK) |
 				   BR_MS_GPCM | BR_V;
 
 		DEBUGF("## BR1: 0x%08x    OR1: 0x%08x\n",
 			memctl->memc_br1, memctl->memc_or1);
 
 		/* Re-do sizing to get full correct info */
-		size_b1 = flash_get_size((vu_long *)(CFG_FLASH_BASE + size_b0),
+		size_b1 = flash_get_size((vu_long *)(CONFIG_SYS_FLASH_BASE + size_b0),
 					  &flash_info[1]);
 
 		flash_info[1].size = size_b1;
 
-		flash_get_offsets (CFG_FLASH_BASE + size_b0, &flash_info[1]);
+		flash_get_offsets (CONFIG_SYS_FLASH_BASE + size_b0, &flash_info[1]);
 
-# if CFG_MONITOR_BASE >= CFG_FLASH_BASE
+# if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 		/* monitor protection ON by default */
 		flash_protect(FLAG_PROTECT_SET,
-			      CFG_MONITOR_BASE,
-			      CFG_MONITOR_BASE+monitor_flash_len-1,
+			      CONFIG_SYS_MONITOR_BASE,
+			      CONFIG_SYS_MONITOR_BASE+monitor_flash_len-1,
 			      &flash_info[1]);
 # endif
 
@@ -503,7 +503,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -626,7 +626,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/xaeniax/flash.c b/board/xaeniax/flash.c
index cd257df..b051c89 100644
--- a/board/xaeniax/flash.c
+++ b/board/xaeniax/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -65,7 +65,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -85,8 +85,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -203,10 +203,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -276,7 +276,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -410,7 +410,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/xaeniax/lowlevel_init.S b/board/xaeniax/lowlevel_init.S
index fe3e712..57e1620 100644
--- a/board/xaeniax/lowlevel_init.S
+++ b/board/xaeniax/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 	.macro CPWAIT reg
@@ -47,67 +47,67 @@
 	/* Set up GPIO pins first ----------------------------------------- */
 
 	ldr	r0,=GPSR0
-	ldr	r1,=CFG_GPSR0_VAL
+	ldr	r1,=CONFIG_SYS_GPSR0_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPSR1
-	ldr	r1,=CFG_GPSR1_VAL
+	ldr	r1,=CONFIG_SYS_GPSR1_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPSR2
-	ldr	r1,=CFG_GPSR2_VAL
+	ldr	r1,=CONFIG_SYS_GPSR2_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPCR0
-	ldr	r1,=CFG_GPCR0_VAL
+	ldr	r1,=CONFIG_SYS_GPCR0_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPCR1
-	ldr	r1,=CFG_GPCR1_VAL
+	ldr	r1,=CONFIG_SYS_GPCR1_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPCR2
-	ldr	r1,=CFG_GPCR2_VAL
+	ldr	r1,=CONFIG_SYS_GPCR2_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPDR0
-	ldr	r1,=CFG_GPDR0_VAL
+	ldr	r1,=CONFIG_SYS_GPDR0_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPDR1
-	ldr	r1,=CFG_GPDR1_VAL
+	ldr	r1,=CONFIG_SYS_GPDR1_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GPDR2
-	ldr	r1,=CFG_GPDR2_VAL
+	ldr	r1,=CONFIG_SYS_GPDR2_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR0_L
-	ldr	r1,=CFG_GAFR0_L_VAL
+	ldr	r1,=CONFIG_SYS_GAFR0_L_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR0_U
-	ldr	r1,=CFG_GAFR0_U_VAL
+	ldr	r1,=CONFIG_SYS_GAFR0_U_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR1_L
-	ldr	r1,=CFG_GAFR1_L_VAL
+	ldr	r1,=CONFIG_SYS_GAFR1_L_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR1_U
-	ldr	r1,=CFG_GAFR1_U_VAL
+	ldr	r1,=CONFIG_SYS_GAFR1_U_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR2_L
-	ldr	r1,=CFG_GAFR2_L_VAL
+	ldr	r1,=CONFIG_SYS_GAFR2_L_VAL
 	str	r1,[r0]
 
 	ldr	r0,=GAFR2_U
-	ldr	r1,=CFG_GAFR2_U_VAL
+	ldr	r1,=CONFIG_SYS_GAFR2_U_VAL
 	str	r1,[r0]
 
 	ldr	r0,=PSSR		/* enable GPIO pins */
-	ldr	r1,=CFG_PSSR_VAL
+	ldr	r1,=CONFIG_SYS_PSSR_VAL
 	str	r1,[r0]
 
 	/* ---------------------------------------------------------------- */
@@ -145,17 +145,17 @@
 	/* MSC registers: timing, bus width, mem type                       */
 
 	/* MSC0: nCS(0,1)                                                   */
-	ldr     r2,=CFG_MSC0_VAL
+	ldr     r2,=CONFIG_SYS_MSC0_VAL
 	str     r2,[r1, #MSC0_OFFSET]
 	ldr     r2,[r1, #MSC0_OFFSET]	/* read back to ensure data latches */
 
 	/* MSC1: nCS(2,3)                                                   */
-	ldr     r2,=CFG_MSC1_VAL
+	ldr     r2,=CONFIG_SYS_MSC1_VAL
 	str     r2,[r1, #MSC1_OFFSET]
 	ldr     r2,[r1, #MSC1_OFFSET]
 
 	/* MSC2: nCS(4,5)                                                   */
-	ldr     r2,=CFG_MSC2_VAL
+	ldr     r2,=CONFIG_SYS_MSC2_VAL
 	str     r2,[r1, #MSC2_OFFSET]
 	ldr     r2,[r1, #MSC2_OFFSET]
 
@@ -164,37 +164,37 @@
 	/* ---------------------------------------------------------------- */
 
 	/* MECR: Memory Expansion Card Register                             */
-	ldr     r2,=CFG_MECR_VAL
+	ldr     r2,=CONFIG_SYS_MECR_VAL
 	str     r2,[r1, #MECR_OFFSET]
 	ldr	r2,[r1, #MECR_OFFSET]
 
 	/* MCMEM0: Card Interface slot 0 timing                             */
-	ldr     r2,=CFG_MCMEM0_VAL
+	ldr     r2,=CONFIG_SYS_MCMEM0_VAL
 	str     r2,[r1, #MCMEM0_OFFSET]
 	ldr	r2,[r1, #MCMEM0_OFFSET]
 
 	/* MCMEM1: Card Interface slot 1 timing                             */
-	ldr     r2,=CFG_MCMEM1_VAL
+	ldr     r2,=CONFIG_SYS_MCMEM1_VAL
 	str     r2,[r1, #MCMEM1_OFFSET]
 	ldr	r2,[r1, #MCMEM1_OFFSET]
 
 	/* MCATT0: Card Interface Attribute Space Timing, slot 0            */
-	ldr     r2,=CFG_MCATT0_VAL
+	ldr     r2,=CONFIG_SYS_MCATT0_VAL
 	str     r2,[r1, #MCATT0_OFFSET]
 	ldr	r2,[r1, #MCATT0_OFFSET]
 
 	/* MCATT1: Card Interface Attribute Space Timing, slot 1            */
-	ldr     r2,=CFG_MCATT1_VAL
+	ldr     r2,=CONFIG_SYS_MCATT1_VAL
 	str     r2,[r1, #MCATT1_OFFSET]
 	ldr	r2,[r1, #MCATT1_OFFSET]
 
 	/* MCIO0: Card Interface I/O Space Timing, slot 0                   */
-	ldr     r2,=CFG_MCIO0_VAL
+	ldr     r2,=CONFIG_SYS_MCIO0_VAL
 	str     r2,[r1, #MCIO0_OFFSET]
 	ldr	r2,[r1, #MCIO0_OFFSET]
 
 	/* MCIO1: Card Interface I/O Space Timing, slot 1                   */
-	ldr     r2,=CFG_MCIO1_VAL
+	ldr     r2,=CONFIG_SYS_MCIO1_VAL
 	str     r2,[r1, #MCIO1_OFFSET]
 	ldr	r2,[r1, #MCIO1_OFFSET]
 
@@ -207,7 +207,7 @@
 	/* ---------------------------------------------------------------- */
 
 	@ get the mdrefr settings
-	ldr     r4,=CFG_MDREFR_VAL
+	ldr     r4,=CONFIG_SYS_MDREFR_VAL
 
 	@ write back mdrefr
 	str     r4,[r1, #MDREFR_OFFSET]
@@ -261,7 +261,7 @@
 	/* Step 4d:							*/
 	/* fetch platform value of mdcnfg				*/
 	@
-	ldr     r2,  =CFG_MDCNFG_VAL
+	ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 
 	@ disable all sdram banks
 	@
@@ -296,7 +296,7 @@
 	/*          documented in SDRAM data sheets. The address(es) used   */
 	/*          for this purpose must not be cacheable.                 */
 
-	ldr	r3,	=CFG_DRAM_BASE
+	ldr	r3,	=CONFIG_SYS_DRAM_BASE
 	str	r2,	[r3]
 	str	r2,	[r3]
 	str	r2,	[r3]
@@ -326,7 +326,7 @@
 
 	/* Step 4h: Write MDMRS.                                            */
 
-	ldr     r2,	=CFG_MDMRS_VAL
+	ldr     r2,	=CONFIG_SYS_MDMRS_VAL
 	str     r2,	[r1, #MDMRS_OFFSET]
 
 
@@ -342,7 +342,7 @@
 	ldr     r2,  =ICLR
 	str     r1,  [r2]
 
-	ldr     r1,  =CFG_ICMR_VAL /* mask all interrupts at the controller */
+	ldr     r1,  =CONFIG_SYS_ICMR_VAL /* mask all interrupts at the controller */
 	ldr     r2,  =ICMR
 	str     r1,  [r2]
 
@@ -388,7 +388,7 @@
 	@
 test:
 	ldr     r1,  =CKEN
-	ldr     r2,  =CFG_CKEN_VAL
+	ldr     r2,  =CONFIG_SYS_CKEN_VAL
 	str     r2,  [r1]
 
 	/* ---------------------------------------------------------------- */
diff --git a/board/xilinx/ml300/serial.c b/board/xilinx/ml300/serial.c
index 993dfa3..4215513 100644
--- a/board/xilinx/ml300/serial.c
+++ b/board/xilinx/ml300/serial.c
@@ -45,9 +45,9 @@
 DECLARE_GLOBAL_DATA_PTR;
 
 #define USE_CHAN1 \
-	((defined XPAR_UARTNS550_0_BASEADDR) && (defined CFG_INIT_CHAN1))
+	((defined XPAR_UARTNS550_0_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN1))
 #define USE_CHAN2 \
-	((defined XPAR_UARTNS550_1_BASEADDR) && (defined CFG_INIT_CHAN2))
+	((defined XPAR_UARTNS550_1_BASEADDR) && (defined CONFIG_SYS_INIT_CHAN2))
 
 #if USE_CHAN1
 #include <ns16550.h>
@@ -82,21 +82,21 @@
 serial_putc(const char c)
 {
 	if (c == '\n')
-		NS16550_putc(COM_PORTS[CFG_DUART_CHAN], '\r');
+		NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], '\r');
 
-	NS16550_putc(COM_PORTS[CFG_DUART_CHAN], c);
+	NS16550_putc(COM_PORTS[CONFIG_SYS_DUART_CHAN], c);
 }
 
 int
 serial_getc(void)
 {
-	return NS16550_getc(COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_getc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 int
 serial_tstc(void)
 {
-	return NS16550_tstc(COM_PORTS[CFG_DUART_CHAN]);
+	return NS16550_tstc(COM_PORTS[CONFIG_SYS_DUART_CHAN]);
 }
 
 void
diff --git a/board/xilinx/ml401/ml401.c b/board/xilinx/ml401/ml401.c
index 955936d..f388b77 100644
--- a/board/xilinx/ml401/ml401.c
+++ b/board/xilinx/ml401/ml401.c
@@ -32,11 +32,11 @@
 
 void do_reset (void)
 {
-#ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) =
-	    ++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
+	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
 #endif
-#ifdef CFG_RESET_ADDRESS
+#ifdef CONFIG_SYS_RESET_ADDRESS
 	puts ("Reseting board\n");
 	asm ("bra r0");
 #endif
@@ -44,17 +44,17 @@
 
 int gpio_init (void)
 {
-#ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0xFFFFFFFF;
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0xFFFFFFFF;
 #endif
 	return 0;
 }
 
-#ifdef CFG_FSL_2
+#ifdef CONFIG_SYS_FSL_2
 void fsl_isr2 (void *arg) {
 	volatile int num;
-	*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)) =
-	    ++(*((unsigned int *)(CFG_GPIO_0_ADDR + 0x4)));
+	*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)) =
+	    ++(*((unsigned int *)(CONFIG_SYS_GPIO_0_ADDR + 0x4)));
 	GET (num, 2);
 	NGET (num, 2);
 	puts("*");
diff --git a/board/xilinx/ppc440-generic/u-boot-ram.lds b/board/xilinx/ppc440-generic/u-boot-ram.lds
index 2c98d27..5886556 100644
--- a/board/xilinx/ppc440-generic/u-boot-ram.lds
+++ b/board/xilinx/ppc440-generic/u-boot-ram.lds
@@ -127,7 +127,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/xilinx/ppc440-generic/u-boot-rom.lds b/board/xilinx/ppc440-generic/u-boot-rom.lds
index d5da018..debc916 100644
--- a/board/xilinx/ppc440-generic/u-boot-rom.lds
+++ b/board/xilinx/ppc440-generic/u-boot-rom.lds
@@ -137,7 +137,7 @@
    *(COMMON)
   }
 
-  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CFG_MONITOR_BASE, CFG_MONITOR_LEN and TEXT_BASE may need to be modified.");
+  ppcenv_assert = ASSERT(. < 0xFFFFB000, ".bss section too big, overlaps .ppcenv section. Please update your confguration: CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_LEN and TEXT_BASE may need to be modified.");
 
   _end = . ;
   PROVIDE (end = .);
diff --git a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
index 0867226..0c3d667 100644
--- a/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
+++ b/board/xilinx/ppc440-generic/xilinx_ppc440_generic.c
@@ -37,7 +37,7 @@
 phys_size_t __initdram(int board_type)
 {
 	return get_ram_size(XPAR_DDR2_SDRAM_MEM_BASEADDR,
-			    CFG_SDRAM_SIZE_MB * 1024 * 1024);
+			    CONFIG_SYS_SDRAM_SIZE_MB * 1024 * 1024);
 }
 phys_size_t initdram(int) __attribute__((weak, alias("__initdram")));
 
diff --git a/board/xilinx/xilinx_iic/iic_adapter.c b/board/xilinx/xilinx_iic/iic_adapter.c
index ad19ade..58aaeb7 100644
--- a/board/xilinx/xilinx_iic/iic_adapter.c
+++ b/board/xilinx/xilinx_iic/iic_adapter.c
@@ -72,7 +72,7 @@
 		memcpy(&sendBuf[2], &data[pos], wlen);
 
 		/* Send to EEPROM through iic bus */
-		ret = XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1,
+		ret = XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1,
 				sendBuf, wlen + 2);
 
 		udelay(IIC_DELAY);
@@ -93,11 +93,11 @@
 
 	/* Provide EEPROM address */
 	ret =
-	    XIic_Send(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, address,
+	    XIic_Send(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, address,
 		      2);
 	/* Receive data from EEPROM */
 	ret =
-	    XIic_Recv(XPAR_IIC_0_BASEADDR, CFG_I2C_EEPROM_ADDR >> 1, data, len);
+	    XIic_Recv(XPAR_IIC_0_BASEADDR, CONFIG_SYS_I2C_EEPROM_ADDR >> 1, data, len);
 }
 
 /************************************************************************
diff --git a/board/xilinx/xupv2p/xupv2p.c b/board/xilinx/xupv2p/xupv2p.c
index b48103f..b1a76c0 100644
--- a/board/xilinx/xupv2p/xupv2p.c
+++ b/board/xilinx/xupv2p/xupv2p.c
@@ -30,11 +30,11 @@
 
 void do_reset (void)
 {
-#ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) =
-	    ++(*((unsigned long *)(CFG_GPIO_0_ADDR)));
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) =
+	    ++(*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)));
 #endif
-#ifdef CFG_RESET_ADDRESS
+#ifdef CONFIG_SYS_RESET_ADDRESS
 	puts ("Reseting board\n");
 	asm ("bra r0");
 #endif
@@ -42,8 +42,8 @@
 
 int gpio_init (void)
 {
-#ifdef CFG_GPIO_0
-	*((unsigned long *)(CFG_GPIO_0_ADDR)) = 0x0;
+#ifdef CONFIG_SYS_GPIO_0
+	*((unsigned long *)(CONFIG_SYS_GPIO_0_ADDR)) = 0x0;
 #endif
 	return 0;
 }
diff --git a/board/xm250/flash.c b/board/xm250/flash.c
index 893351e..b02149c 100644
--- a/board/xm250/flash.c
+++ b/board/xm250/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -84,7 +84,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -104,8 +104,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -232,10 +232,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -305,7 +305,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -439,7 +439,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
@@ -484,7 +484,7 @@
 	reset_timer_masked ();
 
 	while ((*addr & INTEL_FINISHED) != INTEL_FINISHED) {
-		if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT) {
 			printf("Flash lock bit operation timed out\n");
 			rc = 1;
 			break;
@@ -516,7 +516,7 @@
 				*addr = INTEL_PROTECT;	/* set */
 				while ((*addr & INTEL_FINISHED) != INTEL_FINISHED)
 				{
-					if (get_timer_masked () > CFG_FLASH_UNLOCK_TOUT)
+					if (get_timer_masked () > CONFIG_SYS_FLASH_UNLOCK_TOUT)
 					{
 						printf("Flash lock bit operation timed out\n");
 						rc = 1;
diff --git a/board/xm250/lowlevel_init.S b/board/xm250/lowlevel_init.S
index 2ebd395..8230550 100644
--- a/board/xm250/lowlevel_init.S
+++ b/board/xm250/lowlevel_init.S
@@ -24,7 +24,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 	.macro CPWAIT reg
@@ -51,98 +51,98 @@
 	/* Set up GPIO pins first */
 
 	ldr	r0,   =GPSR0
-	ldr	r1,   =CFG_GPSR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPSR1
-	ldr	r1,   =CFG_GPSR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPSR2
-	ldr	r1,   =CFG_GPSR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPSR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR0
-	ldr	r1,   =CFG_GPCR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR1
-	ldr	r1,   =CFG_GPCR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPCR2
-	ldr	r1,   =CFG_GPCR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPCR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER0
-	ldr	r1,   =CFG_GRER0_VAL
+	ldr	r1,   =CONFIG_SYS_GRER0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER1
-	ldr	r1,   =CFG_GRER1_VAL
+	ldr	r1,   =CONFIG_SYS_GRER1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GRER2
-	ldr	r1,   =CFG_GRER2_VAL
+	ldr	r1,   =CONFIG_SYS_GRER2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER0
-	ldr	r1,   =CFG_GFER0_VAL
+	ldr	r1,   =CONFIG_SYS_GFER0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER1
-	ldr	r1,   =CFG_GFER1_VAL
+	ldr	r1,   =CONFIG_SYS_GFER1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GFER2
-	ldr	r1,   =CFG_GFER2_VAL
+	ldr	r1,   =CONFIG_SYS_GFER2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR0
-	ldr	r1,   =CFG_GPDR0_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR0_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR1
-	ldr	r1,   =CFG_GPDR1_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR1_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GPDR2
-	ldr	r1,   =CFG_GPDR2_VAL
+	ldr	r1,   =CONFIG_SYS_GPDR2_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR0_L
-	ldr	r1,   =CFG_GAFR0_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR0_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR0_U
-	ldr	r1,   =CFG_GAFR0_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR0_U_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR1_L
-	ldr	r1,   =CFG_GAFR1_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR1_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR1_U
-	ldr	r1,   =CFG_GAFR1_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR1_U_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR2_L
-	ldr	r1,   =CFG_GAFR2_L_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR2_L_VAL
 	str	r1,   [r0]
 
 	ldr	r0,   =GAFR2_U
-	ldr	r1,   =CFG_GAFR2_U_VAL
+	ldr	r1,   =CONFIG_SYS_GAFR2_U_VAL
 	str	r1,   [r0]
 
 	/* enable GPIO pins */
 	ldr	r0,   =PSSR
-	ldr	r1,   =CFG_PSSR_VAL
+	ldr	r1,   =CONFIG_SYS_PSSR_VAL
 	str	r1,   [r0]
 
 	/* SET_LED 1 */
 
 	ldr	r3, =MSC1		/* low - bank 2 Lubbock Registers / SRAM */
-	ldr	r2, =CFG_MSC1_VAL	/* high - bank 3 Ethernet Controller */
+	ldr	r2, =CONFIG_SYS_MSC1_VAL	/* high - bank 3 Ethernet Controller */
 	str	r2, [r3]		/* need to set MSC1 before trying to write to the HEX LEDs */
 	ldr	r2, [r3]		/* need to read it back to make sure the value latches (see MSC section of manual) */
 
@@ -181,47 +181,47 @@
 	@ Step 2a
 	@ write msc0, read back to ensure data latches
 	@
-	ldr	r2,   =CFG_MSC0_VAL
+	ldr	r2,   =CONFIG_SYS_MSC0_VAL
 	str	r2,   [r1, #MSC0_OFFSET]
 	ldr	r2,   [r1, #MSC0_OFFSET]
 
 	@ write msc1
-	ldr	r2,  =CFG_MSC1_VAL
+	ldr	r2,  =CONFIG_SYS_MSC1_VAL
 	str	r2,  [r1, #MSC1_OFFSET]
 	ldr	r2,  [r1, #MSC1_OFFSET]
 
 	@ write msc2
-	ldr	r2,  =CFG_MSC2_VAL
+	ldr	r2,  =CONFIG_SYS_MSC2_VAL
 	str	r2,  [r1, #MSC2_OFFSET]
 	ldr	r2,  [r1, #MSC2_OFFSET]
 
 	@ Step 2b
 	@ write mecr
-	ldr	r2,  =CFG_MECR_VAL
+	ldr	r2,  =CONFIG_SYS_MECR_VAL
 	str	r2,  [r1, #MECR_OFFSET]
 
 	@ write mcmem0
-	ldr	r2,  =CFG_MCMEM0_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM0_VAL
 	str	r2,  [r1, #MCMEM0_OFFSET]
 
 	@ write mcmem1
-	ldr	r2,  =CFG_MCMEM1_VAL
+	ldr	r2,  =CONFIG_SYS_MCMEM1_VAL
 	str	r2,  [r1, #MCMEM1_OFFSET]
 
 	@ write mcatt0
-	ldr	r2,  =CFG_MCATT0_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT0_VAL
 	str	r2,  [r1, #MCATT0_OFFSET]
 
 	@ write mcatt1
-	ldr	r2,  =CFG_MCATT1_VAL
+	ldr	r2,  =CONFIG_SYS_MCATT1_VAL
 	str	r2,  [r1, #MCATT1_OFFSET]
 
 	@ write mcio0
-	ldr	r2,  =CFG_MCIO0_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO0_VAL
 	str	r2,  [r1, #MCIO0_OFFSET]
 
 	@ write mcio1
-	ldr	r2,  =CFG_MCIO1_VAL
+	ldr	r2,  =CONFIG_SYS_MCIO1_VAL
 	str	r2,  [r1, #MCIO1_OFFSET]
 
 	/*SET_LED 3 */
@@ -229,14 +229,14 @@
 	@ Step 2c
 	@ fly-by-dma is defeatured on this part
 	@ write flycnfg
-	@ldr	r2,  =CFG_FLYCNFG_VAL
+	@ldr	r2,  =CONFIG_SYS_FLYCNFG_VAL
 	@str	r2,  [r1, #FLYCNFG_OFFSET]
 
 /* FIXME Does this sequence really make sense */
 #ifdef REDBOOT_WAY
 	@ Step 2d
 	@ get the mdrefr settings
-	ldr	r3,  =CFG_MDREFR_VAL
+	ldr	r3,  =CONFIG_SYS_MDREFR_VAL
 
 	@ extract DRI field (we need a valid DRI field)
 	@
@@ -319,7 +319,7 @@
 #else
 	@ Step 2d
 	@ get the mdrefr settings
-	ldr	r4,  =CFG_MDREFR_VAL
+	ldr	r4,  =CONFIG_SYS_MDREFR_VAL
 
 	@ write back mdrefr
 	@
@@ -367,7 +367,7 @@
 	@ Step 4d
 	@ fetch platform value of mdcnfg
 	@
-	ldr	r2,  =CFG_MDCNFG_VAL
+	ldr	r2,  =CONFIG_SYS_MDCNFG_VAL
 
 	@ disable all sdram banks
 	@
@@ -404,7 +404,7 @@
 	@ Access memory *not yet enabled* for CBR refresh cycles (8)
 	@ - CBR is generated for all banks
 
-	ldr	r2, =CFG_DRAM_BASE
+	ldr	r2, =CONFIG_SYS_DRAM_BASE
 	str	r2, [r2]
 	str	r2, [r2]
 	str	r2, [r2]
@@ -434,7 +434,7 @@
 	@ Step 4h
 	@ write mdmrs
 	@
-	ldr	r2,  =CFG_MDMRS_VAL
+	ldr	r2,  =CONFIG_SYS_MDMRS_VAL
 	str	r2,  [r1, #MDMRS_OFFSET]
 
 	@ Done Memory Init
@@ -453,7 +453,7 @@
 
 	@ Set interrupt mask register
 	@
-	ldr	r1,  =CFG_ICMR_VAL
+	ldr	r1,  =CONFIG_SYS_ICMR_VAL
 	ldr	r2,  =ICMR
 	str	r1,  [r2]
 
@@ -469,7 +469,7 @@
 
 	@ set core clocks
 	@
-	ldr	r2,  =CFG_CCCR_VAL
+	ldr	r2,  =CONFIG_SYS_CCCR_VAL
 	ldr	r1,  =CCCR
 	str	r2,  [r1]
 
@@ -492,7 +492,7 @@
 	@ Turn on needed clocks
 	@
 	ldr	r1,  =CKEN
-	ldr	r2,  =CFG_CKEN_VAL
+	ldr	r2,  =CONFIG_SYS_CKEN_VAL
 	str	r2,  [r1]
 
 	/*SET_LED 7 */
diff --git a/board/xpedite1k/config.mk b/board/xpedite1k/config.mk
index e42b273..33dfbf1 100644
--- a/board/xpedite1k/config.mk
+++ b/board/xpedite1k/config.mk
@@ -38,5 +38,5 @@
 endif
 
 ifeq ($(dbcr),1)
-PLATFORM_CPPFLAGS += -DCFG_INIT_DBCR=0x8cff0000
+PLATFORM_CPPFLAGS += -DCONFIG_SYS_INIT_DBCR=0x8cff0000
 endif
diff --git a/board/xpedite1k/flash.c b/board/xpedite1k/flash.c
index ce5d4e1..0711931 100644
--- a/board/xpedite1k/flash.c
+++ b/board/xpedite1k/flash.c
@@ -57,9 +57,9 @@
 #define FLASH_SRAM_SEL_VAL	1
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 
-static unsigned long flash_addr_table[8][CFG_MAX_FLASH_BANKS] = {
+static unsigned long flash_addr_table[8][CONFIG_SYS_MAX_FLASH_BANKS] = {
 	{0xfff80000},	/* 0:000: configuraton 3 */
 	{0xfff90000},	/* 1:001: configuraton 4 */
 	{0xfffa0000},	/* 2:010: configuraton 7 */
@@ -89,7 +89,7 @@
 unsigned long flash_init (void)
 {
 	unsigned long total_b = 0;
-	unsigned long size_b[CFG_MAX_FLASH_BANKS];
+	unsigned long size_b[CONFIG_SYS_MAX_FLASH_BANKS];
 	unsigned short index = 0;
 	int i;
 
@@ -98,7 +98,7 @@
 	DEBUGF("FLASH: Index: %d\n", index);
 
 	/* Init: no FLASHes known */
-	for (i=0; i<CFG_MAX_FLASH_BANKS; ++i) {
+	for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; ++i) {
 		flash_info[i].flash_id = FLASH_UNKNOWN;
 		flash_info[i].sector_count = -1;
 		flash_info[i].size = 0;
@@ -366,7 +366,7 @@
 	start = get_timer (0);
 	last  = start;
 	while ((addr[0] & (FLASH_WORD_SIZE)0x00800080) != (FLASH_WORD_SIZE)0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return -1;
 		}
@@ -594,7 +594,7 @@
 		while ((dest2[i] & (FLASH_WORD_SIZE) 0x00800080) !=
 		       (data2[i] & (FLASH_WORD_SIZE) 0x00800080)) {
 
-			if (get_timer (start) > CFG_FLASH_WRITE_TOUT) {
+			if (get_timer (start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 				return (1);
 			}
 		}
diff --git a/board/xpedite1k/init.S b/board/xpedite1k/init.S
index 6cb20e4..8a04f4f 100644
--- a/board/xpedite1k/init.S
+++ b/board/xpedite1k/init.S
@@ -87,10 +87,10 @@
 tlbtab:
 	tlbtab_start
 	tlbentry( 0xf0000000, SZ_256M, 0xf0000000, 1, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
-	tlbentry( CFG_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
-	tlbentry( CFG_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
-	tlbentry( CFG_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
-	tlbentry( CFG_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PERIPHERAL_BASE, SZ_256M, 0x40000000, 1, AC_R|AC_W|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_ISRAM_BASE, SZ_256K, 0x80000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I)
+	tlbentry( CONFIG_SYS_SDRAM_BASE, SZ_256M, 0x00000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_SDRAM_BASE+0x10000000, SZ_256M, 0x10000000, 0, AC_R|AC_W|AC_X|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_BASE, SZ_256M, 0x00000000, 2, AC_R|AC_W|SA_G|SA_I )
+	tlbentry( CONFIG_SYS_PCI_MEMBASE, SZ_256M, 0x00000000, 3, AC_R|AC_W|SA_G|SA_I )
 	tlbtab_end
diff --git a/board/xpedite1k/xpedite1k.c b/board/xpedite1k/xpedite1k.c
index c94a345..58bcfaf 100644
--- a/board/xpedite1k/xpedite1k.c
+++ b/board/xpedite1k/xpedite1k.c
@@ -40,7 +40,7 @@
 	/* TBS:	 Setup the GPIO access for the user LEDs */
 	mfsdr(sdr_pfc0, sdrreg);
 	mtsdr(sdr_pfc0, (sdrreg & ~0x00000100) | 0x00000E00);
-	out32(CFG_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
+	out32(CONFIG_SYS_GPIO_BASE + 0x018, (USR_LED0 | USR_LED1 | USR_LED2 | USR_LED3));
 	LED0_OFF();
 	LED1_OFF();
 	LED2_OFF();
@@ -129,7 +129,7 @@
 }
 
 
-#if defined(CFG_DRAM_TEST)
+#if defined(CONFIG_SYS_DRAM_TEST)
 int testdram (void)
 {
 	uint *pstart = (uint *) 0x00000000;
@@ -231,7 +231,7 @@
 		return (0);
 	}
 
-#if defined(CFG_PCI_FORCE_PCI_CONV)
+#if defined(CONFIG_SYS_PCI_FORCE_PCI_CONV)
 	/* Setup System Device Register PCIX0_XCR */
 	mfsdr(sdr_xcr, strap);
 	strap &= 0x0f000000;
@@ -249,7 +249,7 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
+#if defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller * hose )
 {
 	/*--------------------------------------------------------------------------+
@@ -264,7 +264,7 @@
 	 * Map all of SDRAM to PCI address 0x0000_0000. Note that the 440 strapping
 	 * options to not support sizes such as 128/256 MB.
 	 *--------------------------------------------------------------------------*/
-	out32r( PCIX0_PIM0LAL, CFG_SDRAM_BASE );
+	out32r( PCIX0_PIM0LAL, CONFIG_SYS_SDRAM_BASE );
 	out32r( PCIX0_PIM0LAH, 0 );
 	out32r( PCIX0_PIM0SA, ~(gd->ram_size - 1) | 1 );
 
@@ -273,12 +273,12 @@
 	/*--------------------------------------------------------------------------+
 	 * Program the board's subsystem id/vendor id
 	 *--------------------------------------------------------------------------*/
-	out16r( PCIX0_SBSYSVID, CFG_PCI_SUBSYS_VENDORID );
-	out16r( PCIX0_SBSYSID, CFG_PCI_SUBSYS_DEVICEID );
+	out16r( PCIX0_SBSYSVID, CONFIG_SYS_PCI_SUBSYS_VENDORID );
+	out16r( PCIX0_SBSYSID, CONFIG_SYS_PCI_SUBSYS_DEVICEID );
 
 	out16r( PCIX0_CMD, in16r(PCIX0_CMD) | PCI_COMMAND_MEMORY );
 }
-#endif /* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
+#endif /* defined(CONFIG_PCI) && defined(CONFIG_SYS_PCI_TARGET_INIT) */
 
 
 /*************************************************************************
@@ -299,7 +299,7 @@
 #if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
-	return ((in32(CFG_GPIO_BASE + 0x1C) & 0x00000800) == 0);
+	return ((in32(CONFIG_SYS_GPIO_BASE + 0x1C) & 0x00000800) == 0);
 }
 #endif /* defined(CONFIG_PCI) */
 
@@ -317,7 +317,7 @@
 void post_word_store (ulong a)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_POST_WORD_ADDR);
+		(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
 
 	*save_addr = a;
 }
@@ -325,7 +325,7 @@
 ulong post_word_load (void)
 {
 	volatile ulong *save_addr =
-		(volatile ulong *)(CFG_POST_WORD_ADDR);
+		(volatile ulong *)(CONFIG_SYS_POST_WORD_ADDR);
 
 	return *save_addr;
 }
@@ -342,7 +342,7 @@
 	unsigned char buff[0x100], *cp;
 
 	/* Initialize I2C					*/
-	i2c_init (CFG_I2C_SPEED, CFG_I2C_SLAVE);
+	i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 
 	/* Read 256 bytes in EEPROM				*/
 	i2c_read (0x50, 0, 1, buff, 0x100);
diff --git a/board/xsengine/flash.c b/board/xsengine/flash.c
index f29def2..736905a 100644
--- a/board/xsengine/flash.c
+++ b/board/xsengine/flash.c
@@ -29,7 +29,7 @@
 
 #define SWAP(x)               __swab32(x)
 
-flash_info_t	flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */
+flash_info_t	flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
 
 /* Functions */
 static ulong flash_get_size (vu_long *addr, flash_info_t *info);
@@ -43,7 +43,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((vu_long *) PHYS_FLASH_1, &flash_info[i]);
@@ -61,7 +61,7 @@
 	}
 
 	/* Protect monitor and environment sectors */
-	flash_protect ( FLAG_PROTECT_SET,CFG_FLASH_BASE,CFG_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
+	flash_protect ( FLAG_PROTECT_SET,CONFIG_SYS_FLASH_BASE,CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,&flash_info[0] );
 	flash_protect ( FLAG_PROTECT_SET,CONFIG_ENV_ADDR,CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0] );
 
 	return size;
@@ -338,7 +338,7 @@
 	last  = start;
 	addr = (vu_long*)(info->start[l_sect]);
 	while ((addr[0] & 0x00800080) != 0x00800080) {
-		if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
+		if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
 			printf ("Timeout\n");
 			return 1;
 		}
@@ -462,7 +462,7 @@
 	/* data polling for D7 */
 	start = get_timer (0);
 	while ((*((vu_long *)dest) & 0x00800080) != (data & 0x00800080)) {
-		if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer(start) > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			return (1);
 		}
 	}
diff --git a/board/xsengine/lowlevel_init.S b/board/xsengine/lowlevel_init.S
index b0b1561..0d94ab6 100644
--- a/board/xsengine/lowlevel_init.S
+++ b/board/xsengine/lowlevel_init.S
@@ -2,7 +2,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 .globl lowlevel_init
 lowlevel_init:
@@ -14,93 +14,93 @@
 
    /* General purpose set registers */
    ldr      r0,   =GPSR0
-   ldr      r1,   =CFG_GPSR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR0_VAL
    str      r1,   [r0]
    ldr      r0,   =GPSR1
-   ldr      r1,   =CFG_GPSR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR1_VAL
    str      r1,   [r0]
    ldr      r0,   =GPSR2
-   ldr      r1,   =CFG_GPSR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPSR2_VAL
    str      r1,   [r0]
 
    /* General purpose clear registers */
    ldr      r0,   =GPCR0
-   ldr      r1,   =CFG_GPCR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR0_VAL
    str      r1,   [r0]
    ldr      r0,   =GPCR1
-   ldr      r1,   =CFG_GPCR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR1_VAL
    str      r1,   [r0]
    ldr      r0,   =GPCR2
-   ldr      r1,   =CFG_GPCR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPCR2_VAL
    str      r1,   [r0]
 
    /* General rising edge registers */
    ldr      r0,   =GRER0
-   ldr      r1,   =CFG_GRER0_VAL
+   ldr      r1,   =CONFIG_SYS_GRER0_VAL
    str      r1,   [r0]
    ldr      r0,   =GRER1
-   ldr      r1,   =CFG_GRER1_VAL
+   ldr      r1,   =CONFIG_SYS_GRER1_VAL
    str      r1,   [r0]
    ldr      r0,   =GRER2
-   ldr      r1,   =CFG_GRER2_VAL
+   ldr      r1,   =CONFIG_SYS_GRER2_VAL
    str      r1,   [r0]
 
    /* General falling edge registers */
    ldr      r0,   =GFER0
-   ldr      r1,   =CFG_GFER0_VAL
+   ldr      r1,   =CONFIG_SYS_GFER0_VAL
    str      r1,   [r0]
    ldr      r0,   =GFER1
-   ldr      r1,   =CFG_GFER1_VAL
+   ldr      r1,   =CONFIG_SYS_GFER1_VAL
    str      r1,   [r0]
    ldr      r0,   =GFER2
-   ldr      r1,   =CFG_GFER2_VAL
+   ldr      r1,   =CONFIG_SYS_GFER2_VAL
    str      r1,   [r0]
 
    /* General edge detect registers */
    ldr      r0,   =GPDR0
-   ldr      r1,   =CFG_GPDR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
    str      r1,   [r0]
    ldr      r0,   =GPDR1
-   ldr      r1,   =CFG_GPDR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
    str      r1,   [r0]
    ldr      r0,   =GPDR2
-   ldr      r1,   =CFG_GPDR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
    str      r1,   [r0]
 
    /* General alternate function registers */
    ldr      r0,   =GAFR0_L		/* [0:15] */
-   ldr      r1,   =CFG_GAFR0_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR0_L_VAL
    str      r1,   [r0]
    ldr      r0,   =GAFR0_U		/* [31:16] */
-   ldr      r1,   =CFG_GAFR0_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR0_U_VAL
    str      r1,   [r0]
    ldr      r0,   =GAFR1_L		/* [47:32] */
-   ldr      r1,   =CFG_GAFR1_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR1_L_VAL
    str      r1,   [r0]
    ldr      r0,   =GAFR1_U		/* [63:48] */
-   ldr      r1,   =CFG_GAFR1_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR1_U_VAL
    str      r1,   [r0]
    ldr      r0,   =GAFR2_L		/* [79:64] */
-   ldr      r1,   =CFG_GAFR2_L_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR2_L_VAL
    str      r1,   [r0]
    ldr      r0,   =GAFR2_U		/* [80] */
-   ldr      r1,   =CFG_GAFR2_U_VAL
+   ldr      r1,   =CONFIG_SYS_GAFR2_U_VAL
    str      r1,   [r0]
 
    /* General purpose direction registers */
    ldr      r0,   =GPDR0
-   ldr      r1,   =CFG_GPDR0_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR0_VAL
    str      r1,   [r0]
    ldr      r0,   =GPDR1
-   ldr      r1,   =CFG_GPDR1_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR1_VAL
    str      r1,   [r0]
    ldr      r0,   =GPDR2
-   ldr      r1,   =CFG_GPDR2_VAL
+   ldr      r1,   =CONFIG_SYS_GPDR2_VAL
    str      r1,   [r0]
 
    /* Power manager sleep status */
    ldr      r0,   =PSSR
-   ldr      r1,   =CFG_PSSR_VAL
+   ldr      r1,   =CONFIG_SYS_PSSR_VAL
    str      r1,   [r0]
 
 /* ---- MEMORY INITIALISATION ---- */
@@ -121,17 +121,17 @@
 
 /* ---- FLASH INITIALISATION ---- */
 /* Write MSC0 and read back to ensure data change is accepted by cpu */
-   ldr     r2,   =CFG_MSC0_VAL
+   ldr     r2,   =CONFIG_SYS_MSC0_VAL
    str     r2,   [r1, #MSC0_OFFSET]
    ldr     r2,   [r1, #MSC0_OFFSET]
 
 /* ---- SDRAM INITIALISATION ---- */
 /* get the MDREFR settings */
-   ldr     r2,  =CFG_MDREFR_VAL
+   ldr     r2,  =CONFIG_SYS_MDREFR_VAL
    str     r2,  [r1, #MDREFR_OFFSET]
 
 /* fetch platform value of MDCNFG */
-   ldr     r2,  =CFG_MDCNFG_VAL
+   ldr     r2,  =CONFIG_SYS_MDCNFG_VAL
 
 /* disable all sdram banks */
    bic     r2,  r2,  #(MDCNFG_DE0 | MDCNFG_DE1)
@@ -153,7 +153,7 @@
 /* Access memory *not yet enabled* for CBR refresh cycles (8) */
 /* CBR is generated for all banks */
 
-   ldr     r2, =CFG_DRAM_BASE
+   ldr     r2, =CONFIG_SYS_DRAM_BASE
    str     r2, [r2]
    str     r2, [r2]
    str     r2, [r2]
@@ -172,7 +172,7 @@
    str     r2,  [r1, #MDCNFG_OFFSET]
 
 /* write MDMRS to trigger an MSR command to all enabled SDRAM banks */
-   ldr     r2,  =CFG_MDMRS_VAL
+   ldr     r2,  =CONFIG_SYS_MDMRS_VAL
    str     r2,  [r1, #MDMRS_OFFSET]
 
 /* ---- INTERRUPT INITIALISATION ---- */
@@ -183,7 +183,7 @@
    str     r1,  [r2]
 
 /* Set interrupt mask register */
-   ldr     r1,  =CFG_ICMR_VAL
+   ldr     r1,  =CONFIG_SYS_ICMR_VAL
    ldr     r2,  =ICMR
    str     r1,  [r2]
 
@@ -196,7 +196,7 @@
    str     r2,  [r1]
 
 /* set core clocks */
-   ldr     r2,  =CFG_CCCR_VAL
+   ldr     r2,  =CONFIG_SYS_CCCR_VAL
    ldr     r1,  =CCCR
    str     r2,  [r1]
 
@@ -215,7 +215,7 @@
 
 /* Turn on needed clocks */
    ldr     r1,  =CKEN
-   ldr     r2,  =CFG_CKEN_VAL
+   ldr     r2,  =CONFIG_SYS_CKEN_VAL
    str     r2,  [r1]
 
    mov   pc, r10
diff --git a/board/zeus/update.c b/board/zeus/update.c
index c76519f..2f2a127 100644
--- a/board/zeus/update.c
+++ b/board/zeus/update.c
@@ -67,12 +67,12 @@
 static int update_boot_eeprom(void)
 {
 	u32 len = 0x20;
-	u8 chip = CFG_I2C_EEPROM_ADDR;
+	u8 chip = CONFIG_SYS_I2C_EEPROM_ADDR;
 	u8 *pbuf;
 	u8 base;
 	int i;
 
-	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE)) {
+	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE)) {
 		pbuf = buf_zeus_pe;
 		base = 0x40;
 	} else {
diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c
index 6fa4eef..974bdf2 100644
--- a/board/zeus/zeus.c
+++ b/board/zeus/zeus.c
@@ -38,7 +38,7 @@
 #define REBOOT_NOP	0x00000000
 #define REBOOT_DO_POST	0x00000001
 
-extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
+extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips	*/
 extern env_t *env_ptr;
 extern uchar default_environment[];
 
@@ -73,8 +73,8 @@
 	u32 post_magic;
 	u32 post_val;
 
-	post_magic = in_be32((void *)CFG_POST_MAGIC);
-	post_val = in_be32((void *)CFG_POST_VAL);
+	post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+	post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
 	if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST)) {
 		/*
 		 * Set special bootline bootparameter to pass this POST boot
@@ -87,7 +87,7 @@
 		 * via the sw-reset button. So disable further tests
 		 * upon next bootup here.
 		 */
-		out_be32((void *)CFG_POST_VAL, REBOOT_NOP);
+		out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_NOP);
 	} else {
 		/*
 		 * Only run POST when initiated via the sw-reset button mechanism
@@ -144,7 +144,7 @@
 
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
-			    -CFG_MONITOR_LEN,
+			    -CONFIG_SYS_MONITOR_LEN,
 			    0xffffffff,
 			    &flash_info[0]);
 
@@ -166,7 +166,7 @@
 
 	puts("Board: Zeus-");
 
-	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_ZEUS_PE))
+	if (in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_ZEUS_PE))
 		puts("PE");
 	else
 		puts("CE");
@@ -180,12 +180,12 @@
 	putc('\n');
 
 	/* both LED's off */
-	gpio_write_bit(CFG_GPIO_LED_RED, 0);
-	gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
 	udelay(10000);
 	/* and on again */
-	gpio_write_bit(CFG_GPIO_LED_RED, 1);
-	gpio_write_bit(CFG_GPIO_LED_GREEN, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 1);
+	gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 1);
 
 	return (0);
 }
@@ -239,7 +239,7 @@
 	 */
 	memset(env_ptr, 0, sizeof(env_t));
 	memcpy(env_ptr->data, default_environment, ENV_SIZE);
-#ifdef CFG_REDUNDAND_ENVIRONMENT
+#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT
 	env_ptr->flags = 0xFF;
 #endif
 	env_crc_update();
@@ -333,7 +333,7 @@
 
 static inline int sw_reset_pressed(void)
 {
-	return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CFG_GPIO_SW_RESET));
+	return !(in_be32((void *)GPIO0_IR) & GPIO_VAL(CONFIG_SYS_GPIO_SW_RESET));
 }
 
 int do_chkreset(cmd_tbl_t* cmdtp, int flag, int argc, char* argv[])
@@ -356,16 +356,16 @@
 		if (!sw_reset_pressed())
 			break;
 
-		if ((delta > CFG_TIME_POST) && !post) {
+		if ((delta > CONFIG_SYS_TIME_POST) && !post) {
 			printf("\nWhen released now, POST tests will be started.");
-			gpio_write_bit(CFG_GPIO_LED_GREEN, 0);
+			gpio_write_bit(CONFIG_SYS_GPIO_LED_GREEN, 0);
 			post = 1;
 		}
 
-		if ((delta > CFG_TIME_FACTORY_RESET) && !factory_reset) {
+		if ((delta > CONFIG_SYS_TIME_FACTORY_RESET) && !factory_reset) {
 			printf("\nWhen released now, factory default values"
 			       " will be restored.");
-			gpio_write_bit(CFG_GPIO_LED_RED, 0);
+			gpio_write_bit(CONFIG_SYS_GPIO_LED_RED, 0);
 			factory_reset = 1;
 		}
 
@@ -377,7 +377,7 @@
 
 	printf("\nSW-Reset Button released after %d milli-seconds!\n", delta);
 
-	if (delta > CFG_TIME_FACTORY_RESET) {
+	if (delta > CONFIG_SYS_TIME_FACTORY_RESET) {
 		printf("Starting factory reset value restoration...\n");
 
 		/*
@@ -393,14 +393,14 @@
 		return 0;
 	}
 
-	if (delta > CFG_TIME_POST) {
+	if (delta > CONFIG_SYS_TIME_POST) {
 		printf("Starting POST configuration...\n");
 
 		/*
 		 * Enable POST upon next bootup
 		 */
-		out_be32((void *)CFG_POST_MAGIC, REBOOT_MAGIC);
-		out_be32((void *)CFG_POST_VAL, REBOOT_DO_POST);
+		out_be32((void *)CONFIG_SYS_POST_MAGIC, REBOOT_MAGIC);
+		out_be32((void *)CONFIG_SYS_POST_VAL, REBOOT_DO_POST);
 		post_bootmode_init();
 
 		/*
@@ -432,8 +432,8 @@
 	u32 post_magic;
 	u32 post_val;
 
-	post_magic = in_be32((void *)CFG_POST_MAGIC);
-	post_val = in_be32((void *)CFG_POST_VAL);
+	post_magic = in_be32((void *)CONFIG_SYS_POST_MAGIC);
+	post_val = in_be32((void *)CONFIG_SYS_POST_VAL);
 
 	if ((post_magic == REBOOT_MAGIC) && (post_val == REBOOT_DO_POST))
 		return 1;
diff --git a/board/zpc1900/zpc1900.c b/board/zpc1900/zpc1900.c
index 103ef71..027d566 100644
--- a/board/zpc1900/zpc1900.c
+++ b/board/zpc1900/zpc1900.c
@@ -183,7 +183,7 @@
     }
 };
 
-#ifdef CFG_NVRAM_ACCESS_ROUTINE
+#ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE
 void *nvram_read(void *dest, long src, size_t count)
 {
 	return memcpy(dest, (const void *)src, count);
@@ -191,8 +191,8 @@
 
 void nvram_write(long dest, const void *src, size_t count)
 {
-	vu_char     *p1 = (vu_char *)(CFG_EEPROM + 0x1555);
-	vu_char     *p2 = (vu_char *)(CFG_EEPROM + 0x0AAA);
+	vu_char     *p1 = (vu_char *)(CONFIG_SYS_EEPROM + 0x1555);
+	vu_char     *p2 = (vu_char *)(CONFIG_SYS_EEPROM + 0x0AAA);
 	vu_char     *d = (vu_char *)dest;
 	const uchar *s = (const uchar *)src;
 
@@ -218,16 +218,16 @@
 	*p1 = 0xA0;
 	udelay(10000);
 }
-#endif /* CFG_NVRAM_ACCESS_ROUTINE */
+#endif /* CONFIG_SYS_NVRAM_ACCESS_ROUTINE */
 
 phys_size_t initdram(int board_type)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
-	volatile immap_t *immap = (immap_t *)CFG_IMMR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
+	volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
 	volatile memctl8260_t *memctl = &immap->im_memctl;
 	vu_char *ramaddr;
 	uchar c = 0xFF;
-	long int msize = CFG_SDRAM_SIZE;
+	long int msize = CONFIG_SYS_SDRAM_SIZE;
 	int i;
 
 	if (bcsr[4] & BCSR_PCI_MODE) { /* PCI mode selected by JP9 */
@@ -237,38 +237,38 @@
 			| SIUMCR_LBPC01;
 	}
 
-#ifndef CFG_RAMBOOT
+#ifndef CONFIG_SYS_RAMBOOT
 	immap->im_siu_conf.sc_ppc_acr  = 0x03;
 	immap->im_siu_conf.sc_ppc_alrh = 0x30126745;
 	immap->im_siu_conf.sc_tescr1   = 0x00004000;
 
-	memctl->memc_mptpr = CFG_MPTPR;
+	memctl->memc_mptpr = CONFIG_SYS_MPTPR;
 
-#ifdef CFG_LSDRAM_BASE
+#ifdef CONFIG_SYS_LSDRAM_BASE
 	/*
 	  Initialise local bus SDRAM only if the pins
 	  are configured as local bus pins and not as PCI.
 	*/
 	if ((immap->im_siu_conf.sc_siumcr & SIUMCR_LBPC11) == SIUMCR_LBPC00) {
-		memctl->memc_lsrt  = CFG_LSRT;
-		memctl->memc_or4   = CFG_LSDRAM_OR;
-		memctl->memc_br4   = CFG_LSDRAM_BR;
-		ramaddr = (vu_char *)CFG_LSDRAM_BASE;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_PREA;
+		memctl->memc_lsrt  = CONFIG_SYS_LSRT;
+		memctl->memc_or4   = CONFIG_SYS_LSDRAM_OR;
+		memctl->memc_br4   = CONFIG_SYS_LSDRAM_BR;
+		ramaddr = (vu_char *)CONFIG_SYS_LSDRAM_BASE;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_PREA;
 		*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_CBRR;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_CBRR;
 		for (i = 0; i < 8; i++)
 			*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_OP_MRW;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_OP_MRW;
 		*ramaddr = c;
-		memctl->memc_lsdmr = CFG_LSDMR | PSDMR_RFEN;
+		memctl->memc_lsdmr = CONFIG_SYS_LSDMR | PSDMR_RFEN;
 	}
-#endif /* CFG_LSDRAM_BASE */
+#endif /* CONFIG_SYS_LSDRAM_BASE */
 
 	/* Initialise 60x bus SDRAM */
-	memctl->memc_psrt = CFG_PSRT;
-	memctl->memc_or2  = CFG_PSDRAM_OR;
-	memctl->memc_br2  = CFG_PSDRAM_BR;
+	memctl->memc_psrt = CONFIG_SYS_PSRT;
+	memctl->memc_or2  = CONFIG_SYS_PSDRAM_OR;
+	memctl->memc_br2  = CONFIG_SYS_PSDRAM_BR;
 	/*
 	 * The mode data for Mode Register Write command must appear on
 	 * the address lines during a mode-set cycle. It is driven by
@@ -278,18 +278,18 @@
 	 * the address lines. BL=0 because for 64-bit port size burst
 	 * length must be 4.
 	 */
-	ramaddr = (vu_char *)(CFG_SDRAM_BASE |
-			      ((CFG_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
-	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
+	ramaddr = (vu_char *)(CONFIG_SYS_SDRAM_BASE |
+			      ((CONFIG_SYS_PSDMR & PSDMR_CL_MSK) << 7) | 0x10);
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_PREA; /* Precharge all banks */
 	*ramaddr = c;
-	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_CBRR; /* CBR refresh */
 	for (i = 0; i < 8; i++)
 		*ramaddr = c;
-	memctl->memc_psdmr = CFG_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_OP_MRW;  /* Mode Register write */
 	*ramaddr = c;
-	memctl->memc_psdmr = CFG_PSDMR | PSDMR_RFEN;    /* Refresh enable */
+	memctl->memc_psdmr = CONFIG_SYS_PSDMR | PSDMR_RFEN;    /* Refresh enable */
 	*ramaddr = c;
-#endif /* CFG_RAMBOOT */
+#endif /* CONFIG_SYS_RAMBOOT */
 
 	/* Return total 60x bus SDRAM size */
 	return msize * 1024 * 1024;
@@ -297,7 +297,7 @@
 
 int checkboard(void)
 {
-	vu_char *bcsr = (vu_char *)CFG_BCSR;
+	vu_char *bcsr = (vu_char *)CONFIG_SYS_BCSR;
 
 	printf("Board: Zephyr ZPC.1900 Rev. %c\n", bcsr[2] + 0x40);
 	return 0;
diff --git a/board/zylonite/flash.c b/board/zylonite/flash.c
index 80b520b..5ba84c6 100644
--- a/board/zylonite/flash.c
+++ b/board/zylonite/flash.c
@@ -28,7 +28,7 @@
 #include <linux/byteorder/swab.h>
 
 
-flash_info_t flash_info[CFG_MAX_FLASH_BANKS];	/* info for FLASH chips    */
+flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS];	/* info for FLASH chips    */
 
 /* Board support for 1 or 2 flash devices */
 #define FLASH_PORT_WIDTH32
@@ -66,7 +66,7 @@
 	int i;
 	ulong size = 0;
 
-	for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
+	for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) {
 		switch (i) {
 		case 0:
 			flash_get_size ((FPW *) PHYS_FLASH_1, &flash_info[i]);
@@ -86,8 +86,8 @@
 	/* Protect monitor and environment sectors
 	 */
 	flash_protect ( FLAG_PROTECT_SET,
-			CFG_FLASH_BASE,
-			CFG_FLASH_BASE + monitor_flash_len - 1,
+			CONFIG_SYS_FLASH_BASE,
+			CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1,
 			&flash_info[0] );
 
 	flash_protect ( FLAG_PROTECT_SET,
@@ -206,10 +206,10 @@
 		break;
 	}
 
-	if (info->sector_count > CFG_MAX_FLASH_SECT) {
+	if (info->sector_count > CONFIG_SYS_MAX_FLASH_SECT) {
 		printf ("** ERROR: sector count %d > max (%d) **\n",
-			info->sector_count, CFG_MAX_FLASH_SECT);
-		info->sector_count = CFG_MAX_FLASH_SECT;
+			info->sector_count, CONFIG_SYS_MAX_FLASH_SECT);
+		info->sector_count = CONFIG_SYS_MAX_FLASH_SECT;
 	}
 
 	addr[0] = (FPW) 0x00FF00FF;		/* restore read mode */
@@ -279,7 +279,7 @@
 			*addr = (FPW) 0x00D000D0;	/* erase confirm */
 
 			while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-				if (get_timer_masked () > CFG_FLASH_ERASE_TOUT) {
+				if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) {
 					printf ("Timeout\n");
 					*addr = (FPW) 0x00B000B0;	/* suspend erase     */
 					*addr = (FPW) 0x00FF00FF;	/* reset to read mode */
@@ -413,7 +413,7 @@
 
 	/* wait while polling the status register */
 	while (((status = *addr) & (FPW) 0x00800080) != (FPW) 0x00800080) {
-		if (get_timer_masked () > CFG_FLASH_WRITE_TOUT) {
+		if (get_timer_masked () > CONFIG_SYS_FLASH_WRITE_TOUT) {
 			*addr = (FPW) 0x00FF00FF;	/* restore read mode */
 			return (1);
 		}
diff --git a/board/zylonite/lowlevel_init.S b/board/zylonite/lowlevel_init.S
index da01765..ff17c7e 100644
--- a/board/zylonite/lowlevel_init.S
+++ b/board/zylonite/lowlevel_init.S
@@ -29,7 +29,7 @@
 #include <version.h>
 #include <asm/arch/pxa-regs.h>
 
-DRAM_SIZE:  .long   CFG_DRAM_SIZE
+DRAM_SIZE:  .long   CONFIG_SYS_DRAM_SIZE
 
 /* wait for coprocessor write complete */
 .macro CPWAIT reg
@@ -235,13 +235,13 @@
 	orr		r1, r1, #0x40000000	@ enable SDRAM for Normal Access
 	str		r1, [r0]
 
-#ifndef CFG_SKIP_DRAM_SCRUB
+#ifndef CONFIG_SYS_SKIP_DRAM_SCRUB
 	/* scrub/init SDRAM if enabled/present */
-/*	ldr	r11, =0xa0000000 /\* base address of SDRAM (CFG_DRAM_BASE) *\/ */
-/*	ldr	r12, =0x04000000 /\* size of memory to scrub (CFG_DRAM_SIZE) *\/ */
+/*	ldr	r11, =0xa0000000 /\* base address of SDRAM (CONFIG_SYS_DRAM_BASE) *\/ */
+/*	ldr	r12, =0x04000000 /\* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) *\/ */
 /*	mov	r8,r12		 /\* save DRAM size (mk: why???) *\/ */
-	ldr	r8, =0xa0000000	 /* base address of SDRAM (CFG_DRAM_BASE) */
-	ldr	r9, =0x04000000	 /* size of memory to scrub (CFG_DRAM_SIZE) */
+	ldr	r8, =0xa0000000	 /* base address of SDRAM (CONFIG_SYS_DRAM_BASE) */
+	ldr	r9, =0x04000000	 /* size of memory to scrub (CONFIG_SYS_DRAM_SIZE) */
 	mov	r0, #0		 /* scrub with 0x0000:0000 */
 	mov	r1, #0
 	mov	r2, #0
@@ -255,7 +255,7 @@
 	stmia	r8!, {r0-r7}
 	beq	15f
 	b	10b
-#endif /* CFG_SKIP_DRAM_SCRUB */
+#endif /* CONFIG_SYS_SKIP_DRAM_SCRUB */
 
 15:
 	/* Mask all interrupts */
diff --git a/board/zylonite/nand.c b/board/zylonite/nand.c
index 7f22935..895fb2b 100644
--- a/board/zylonite/nand.c
+++ b/board/zylonite/nand.c
@@ -28,19 +28,19 @@
 #include <nand.h>
 #include <asm/arch/pxa-regs.h>
 
-#ifdef CFG_DFC_DEBUG1
+#ifdef CONFIG_SYS_DFC_DEBUG1
 # define DFC_DEBUG1(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG1(fmt, args...)
 #endif
 
-#ifdef CFG_DFC_DEBUG2
+#ifdef CONFIG_SYS_DFC_DEBUG2
 # define DFC_DEBUG2(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG2(fmt, args...)
 #endif
 
-#ifdef CFG_DFC_DEBUG3
+#ifdef CONFIG_SYS_DFC_DEBUG3
 # define DFC_DEBUG3(fmt, args...) printf(fmt, ##args)
 #else
 # define DFC_DEBUG3(fmt, args...)
@@ -211,7 +211,7 @@
 static void dfc_clear_nddb(void)
 {
 	NDCR &= ~NDCR_ND_RUN;
-	wait_us(CFG_NAND_OTHER_TO);
+	wait_us(CONFIG_SYS_NAND_OTHER_TO);
 }
 
 /* wait_event with timeout */
@@ -222,9 +222,9 @@
 	if(!event)
 		return 0xff000000;
 	else if(event & (NDSR_CS0_CMDD | NDSR_CS0_BBD))
-		timeout = CFG_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
+		timeout = CONFIG_SYS_NAND_PROG_ERASE_TO * OSCR_CLK_FREQ;
 	else
-		timeout = CFG_NAND_OTHER_TO * OSCR_CLK_FREQ;
+		timeout = CONFIG_SYS_NAND_OTHER_TO * OSCR_CLK_FREQ;
 
 	while(1) {
 		ndsr = NDSR;
@@ -247,7 +247,7 @@
 	int retry = 0;
 	unsigned long status;
 
-	while(retry++ <= CFG_NAND_SENDCMD_RETRY) {
+	while(retry++ <= CONFIG_SYS_NAND_SENDCMD_RETRY) {
 		/* Clear NDSR */
 		NDSR = 0xFFF;
 
@@ -438,8 +438,8 @@
 	/* turn on the NAND Controller Clock (104 MHz @ D0) */
 	CKENA |= (CKENA_4_NAND | CKENA_9_SMC);
 
-#undef CFG_TIMING_TIGHT
-#ifndef CFG_TIMING_TIGHT
+#undef CONFIG_SYS_TIMING_TIGHT
+#ifndef CONFIG_SYS_TIMING_TIGHT
 	tCH = MIN(((unsigned long) (NAND_TIMING_tCH * DFC_CLK_PER_US) + 1),
 		  DFC_MAX_tCH);
 	tCS = MIN(((unsigned long) (NAND_TIMING_tCS * DFC_CLK_PER_US) + 1),
@@ -478,7 +478,7 @@
 		   DFC_MAX_tWHR);
 	tAR = MIN(((unsigned long) (NAND_TIMING_tAR * DFC_CLK_PER_US) - 2),
 		  DFC_MAX_tAR);
-#endif /* CFG_TIMING_TIGHT */
+#endif /* CONFIG_SYS_TIMING_TIGHT */
 
 
 	DFC_DEBUG2("tCH=%u, tCS=%u, tWH=%u, tWP=%u, tRH=%u, tRP=%u, tR=%u, tWHR=%u, tAR=%u.\n", tCH, tCS, tWH, tWP, tRH, tRP, tR, tWHR, tAR);