)]}'
{
  "commit": "7e44f2b710db09a1b02e55246e0915732cc4775e",
  "tree": "e94b2b4fa41c941841bcb5b61214e3b9b82f12d3",
  "parents": [
    "5f4c6f0db930646e9ca3b479b5fe9b8d2691fa77"
  ],
  "author": {
    "name": "Paul Gortmaker",
    "email": "paul.gortmaker@windriver.com",
    "time": "Fri Dec 30 23:53:10 2011 -0500"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Wed Jan 11 13:59:07 2012 -0600"
  },
  "message": "sbc8548: Make enabling SPD RAM configuration work\n\nPreviously, SPD configuration of RAM was non functional on\nthis board.  Now that the root cause is known (an i2c address\nconflict), there is a simple end-user workaround - remove the\nold slower local bus 128MB module and then SPD detection on the\nmain DDR2 memory module works fine.\n\nWe make the enablement of the LBC SDRAM support conditional on\nbeing not SPD enabled.  We can revisit this dependency as the\nhardware workaround becomes available.\n\nTurning off LBC SDRAM support revealed a couple implict dependencies\nin the tlb/law code that always expected an LBC SDRAM address.\n\nThis has been tested with the default 256MB module, a 512MB\na 1GB and a 2GB, of varying speeds, and the SPD autoconfiguration\nworked fine in all cases.\n\nThe default configuration remains to go with the hard coded\nDDR config, so the default build will continue to work on boards\nwhere people don\u0027t bother to read the docs.  But the advantage\nof going to the SPD config is that even the small default module\ngets configured for CL3 instead of CL4.\n\nSigned-off-by: Paul Gortmaker \u003cpaul.gortmaker@windriver.com\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
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}