)]}'
{
  "commit": "7f1913938984ef6c6a46cb53e003719196d9c5de",
  "tree": "127789e73caeb3464c9941c1f96440031b1e3f6c",
  "parents": [
    "15ee4734e4e08003d73d9ead3ca80e2a0672e427"
  ],
  "author": {
    "name": "Grzegorz Bernacki",
    "email": "gjb@semihalf.com",
    "time": "Fri Sep 07 18:20:23 2007 +0200"
  },
  "committer": {
    "name": "Rafal Jaworowski",
    "email": "raj@semihalf.com",
    "time": "Fri Sep 07 18:20:23 2007 +0200"
  },
  "message": "[PPC440SPe] Improve PCIe configuration space access\n\n- correct configuration space mapping\n- correct bus numbering\n- better access to config space\n\nPrior to this patch, the 440SPe host/PCIe bridge was able to configure only the\nfirst device on the first bus. We now allow to configure up to 16 buses;\nalso, scanning for devices behind the PCIe-PCIe bridge is supported, so\nperipheral devices farther in hierarchy can be identified.\n\nSigned-off-by: Grzegorz Bernacki \u003cgjb@semihalf.com\u003e\n",
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