)]}'
{
  "commit": "7f9f4347cf325c63a39fe30910f3fb211ae2cc15",
  "tree": "fa1cf8a170572b65af737680b1000d0324099c60",
  "parents": [
    "e5852787f0c3c442a276262f13d91ca450605ac0"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Mon Jul 14 14:07:02 2008 -0500"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Mon Jul 14 20:19:59 2008 -0500"
  },
  "message": "85xx: Add some L1/L2 SPR register definitions\n\nAdd new L1/L2 SPRs related to e500mc cache config and control.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "673485777ef26cfe6f7cf7fa5cfbab72f07e7618",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/processor.h",
      "new_id": "e6178680918ac078a7e163f454f66acf298a382d",
      "new_mode": 33188,
      "new_path": "include/asm-ppc/processor.h"
    }
  ]
}