)]}'
{
  "commit": "80ee3ce6d7fe9441b4352d7cfaf6afc2507b1106",
  "tree": "272a979e6e9ed0ae0ab583068657c33793b4355c",
  "parents": [
    "aca5f018a8386b85469482ed9867e3e29a2437d0"
  ],
  "author": {
    "name": "Dave Liu",
    "email": "daveliu@freescale.com",
    "time": "Fri Nov 21 16:31:22 2008 +0800"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Fri Jan 23 17:03:13 2009 -0600"
  },
  "message": "fsl-ddr: update the bit mask for DDR3 controller\n\nAccording to the latest 8572 UM, the DDR3 controller\nis expanding the bit mask, and we use the extend ACTTOPRE\nmode when tRAS more than 19 MCLK.\n\nSigned-off-by: Dave Liu \u003cdaveliu@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1783e927a54192daefd5afff20d8a7dd29678322",
      "old_mode": 33188,
      "old_path": "cpu/mpc8xxx/ddr/ctrl_regs.c",
      "new_id": "d5cdc362f2791d722887e60495e34fa99de00bfb",
      "new_mode": 33188,
      "new_path": "cpu/mpc8xxx/ddr/ctrl_regs.c"
    }
  ]
}