tree f3b4cf35403ab7d75034567e52011b1d57fbb56a
parent bd42bbb858dde713f023fc2e4f512ec174a1a8d2
author Poonam Aggrwal <poonam.aggrwal@freescale.com> 1253362817 +0530
committer Kumar Gala <galak@kernel.crashing.org> 1253811899 -0500

ppc/85xx: 32bit DDR changes for P1020/P1011

The P1020/P1011 SOCs support max 32bit DDR width as opposed to P2020/P2010
where max DDR data width supported is 64bit.

As a next step the DDR data width initialization would be made more dynamic
with more flexibility from the board perspective and user choice.
Going forward we would also remove the hardcodings for platforms with onboard
memories and try to use the FSL SPD code for DDR initialization.

Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>