)]}'
{
  "commit": "8d4c4ffb95d528f6a709bf68da5e0beb0f4ee72f",
  "tree": "b81133a302393e68e7e6426a60050a7fa66ba656",
  "parents": [
    "491f2947a1abf12aa119f9412aa259c0b128f859"
  ],
  "author": {
    "name": "Dirk Behme",
    "email": "dirk.behme@gmail.com",
    "time": "Thu May 09 07:19:52 2013 +0200"
  },
  "committer": {
    "name": "Stefano Babic",
    "email": "sbabic@denx.de",
    "time": "Wed Jun 26 16:22:51 2013 +0200"
  },
  "message": "spi: mxc_spi: Fix pre and post divider calculation\n\nFix two issues with the calculation of pre_div and post_div:\n\n1. pre_div: While the calculation of pre_div looks correct, to set the\nCONREG[15-12] bits pre_div needs to be decremented by 1:\n\nThe i.MX 6Dual/6Quad Applications Processor Reference Manual (IMX6DQRM\nRev. 0, 11/2012) states:\n\nCONREG[15-12]: PRE_DIVIDER\n0000 Divide by 1\n0001 Divide by 2\n0010 Divide by 3\n...\n1101 Divide by 14\n1110 Divide by 15\n1111 Divide by 16\n\nI.e. if we want to divide by 2, we have to write 1 to CONREG[15-12].\n\n2. In case the post divider becomes necessary, pre_div will be divided by\n16. So set pre_div to 16, too. And not 15.\n\nBoth issues above are tested using the following examples:\n\nclk_src \u003d 60000000 (60MHz, default i.MX6 ECSPI clock)\n\na) max_hz \u003d\u003d 23000000 (23MHz, max i.MX6 ECSPI read clock)\n\n-\u003e pre_div \u003d  3 (divide by 3 \u003d\u003e CONREG[15-12] \u003d\u003d 2)\n-\u003e post_div \u003d 0 (divide by 1 \u003d\u003e CONREG[11- 8] \u003d\u003d 0)\n               \u003d\u003e 60MHz / 3 \u003d 20MHz SPI clock\n\nb) max_hz \u003d\u003d 2000000 (2MHz)\n\n-\u003e pre_div \u003d  16 (divide by 16 \u003d\u003e CONREG[15-12] \u003d\u003d 15)\n-\u003e post_div \u003d 1  (divide by  2 \u003d\u003e CONREG[11- 8] \u003d\u003d 1)\n               \u003d\u003e 60MHz / 32 \u003d 1.875MHz SPI clock\n\nc) max_hz \u003d\u003d 1000000 (1MHz)\n\n-\u003e pre_div \u003d  16 (divide by 16 \u003d\u003e CONREG[15-12] \u003d\u003d 15)\n-\u003e post_div \u003d 2  (divide by  4 \u003d\u003e CONREG[11- 8] \u003d\u003d 2)\n               \u003d\u003e 60MHz / 64 \u003d 937.5kHz SPI clock\n\nd) max_hz \u003d\u003d 500000 (500kHz)\n\n-\u003e pre_div \u003d  16 (divide by 16 \u003d\u003e CONREG[15-12] \u003d\u003d 15)\n-\u003e post_div \u003d 3  (divide by  8 \u003d\u003e CONREG[11- 8] \u003d\u003d 3)\n               \u003d\u003e 60MHz / 128 \u003d 468.75kHz SPI clock\n\nSigned-off-by: Dirk Behme \u003cdirk.behme@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "5bed858787f610a9c9a46bb2214665a51d60a9e9",
      "old_mode": 33188,
      "old_path": "drivers/spi/mxc_spi.c",
      "new_id": "b553a9c5965a35a4c2d01409663428628979244a",
      "new_mode": 33188,
      "new_path": "drivers/spi/mxc_spi.c"
    }
  ]
}