diff --git a/MAINTAINERS b/MAINTAINERS
index d5249e5..66f0040 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -42,6 +42,10 @@
 	Rattler			MPC8248
 	ZPC1900			MPC8265
 
+Michael Barkowski <michael.barkowski@freescale.com>
+
+	MPC8323ERDB		MPC8323
+
 Jerry Van Baren <gerald.vanbaren@smiths-aerospace.com>
 
 	sacsng			MPC8260
@@ -217,6 +221,10 @@
 
 	ELPT860			MPC860T
 
+Dave Liu <daveliu@freescale.com>
+
+	MPC8360EMDS		MPC8360
+
 Nye Liu <nyet@zumanetworks.com>
 
 	ZUMA			MPC7xx_74xx
@@ -273,6 +281,10 @@
 	MIP405			PPC4xx
 	PIP405			PPC4xx
 
+Kim Phillips <kim.phillips@freescale.com>
+
+	MPC8349EMDS		MPC8349
+
 Daniel Poirot <dan.poirot@windriver.com>
 
 	sbc8240			MPC8240
@@ -296,6 +308,7 @@
 	ocotea			PPC440GX
 	p3p440			PPC440GP
 	pcs440ep		PPC440EP
+	rainier			PPC440GRx
 	sequoia			PPC440EPx
 	sycamore		PPC405GPr
 	taishan			PPC440GX
@@ -320,6 +333,11 @@
 
 	ML2			PPC4xx
 
+Timur Tabi <timur@freescale.com>
+
+	MPC8349E-mITX		MPC8349
+	MPC8349E-mITX-GP	MPC8349
+
 Erik Theisen <etheisen@mindspring.com>
 
 	W7OLMC			PPC4xx
@@ -352,19 +370,6 @@
 
 	svm_sc8xx		MPC8xx
 
-Timur Tabi <timur@freescale.com>
-
-	MPC8349E-mITX		MPC8349
-	MPC8349E-mITX-GP	MPC8349
-
-Kim Phillips <kim.phillips@freescale.com>
-
-	MPC8349EMDS		MPC8349
-
-Dave Liu <daveliu@freescale.com>
-
-	MPC8360EMDS		MPC8360
-
 -------------------------------------------------------------------------
 
 Unknown / orphaned boards:
diff --git a/MAKEALL b/MAKEALL
index 9f47f5f..feacc10 100755
--- a/MAKEALL
+++ b/MAKEALL
@@ -204,6 +204,7 @@
 	PLU405		\
 	PMC405		\
 	PPChameleonEVB	\
+	rainier		\
 	sbc405		\
 	sc3		\
 	sequoia		\
@@ -298,6 +299,7 @@
 LIST_83xx="		\
 	MPC8313ERDB_33	\
 	MPC8313ERDB_66	\
+	MPC8323ERDB	\
 	MPC832XEMDS	\
 	MPC8349EMDS	\
 	MPC8349ITX	\
diff --git a/Makefile b/Makefile
index 65efd3f..62531a5 100644
--- a/Makefile
+++ b/Makefile
@@ -1688,7 +1688,7 @@
 		echo -n "...66M..." ; \
 		echo "#define CFG_66MHZ" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb
+	@$(MKCONFIG) -a MPC8313ERDB ppc mpc83xx mpc8313erdb freescale
 
 MPC8323ERDB_config:	unconfig
 	@$(MKCONFIG) -a MPC8323ERDB ppc mpc83xx mpc8323erdb freescale
@@ -1716,10 +1716,10 @@
 		echo -n "...66M..." ; \
 		echo "#define PCI_66M" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds
+	@$(MKCONFIG) -a MPC832XEMDS ppc mpc83xx mpc832xemds freescale
 
 MPC8349EMDS_config:	unconfig
-	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds
+	@$(MKCONFIG) $(@:_config=) ppc mpc83xx mpc8349emds freescale
 
 MPC8349ITX_config \
 MPC8349ITX_LOWBOOT_config \
@@ -1733,7 +1733,7 @@
 	@if [ "$(findstring LOWBOOT,$@)" ] ; then \
 		echo "TEXT_BASE = 0xFE000000" >$(obj)board/mpc8349itx/config.tmp ; \
 	fi
-	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx
+	@$(MKCONFIG) -a -n $(@:_config=) MPC8349ITX ppc mpc83xx mpc8349itx freescale
 
 MPC8360EMDS_config \
 MPC8360EMDS_HOST_33_config \
@@ -1758,7 +1758,7 @@
 		echo -n "...66M..." ; \
 		echo "#define PCI_66M" >>$(obj)include/config.h ; \
 	fi ;
-	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds
+	@$(MKCONFIG) -a MPC8360EMDS ppc mpc83xx mpc8360emds freescale
 
 sbc8349_config:		unconfig
 	@$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349
diff --git a/board/amcc/sequoia/cmd_sequoia.c b/board/amcc/sequoia/cmd_sequoia.c
index 6fc60ea..f3803c0 100644
--- a/board/amcc/sequoia/cmd_sequoia.c
+++ b/board/amcc/sequoia/cmd_sequoia.c
@@ -26,76 +26,185 @@
 #include <command.h>
 #include <i2c.h>
 
-static u8 boot_533_nor[] = {
-	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30,
-	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+/*
+ * There are 2 versions of production Sequoia & Rainier platforms.
+ * The primary difference is the reference clock. Those with
+ * 33333333 reference clocks will also have 667MHz rated
+ * processors. Not enough differences to have unique clock
+ * settings.
+ *
+ * NOR and NAND boot options change bytes 6, 7, 8, 9, 11. The
+ * values are independent of the rest of the clock settings.
+ *
+ * All Sequoias & Rainiers select from two possible EEPROMs in Boot
+ * Config F. One for 33MHz PCI, one for 66MHz PCI. The following
+ * values are for the 33MHz PCI configuration. Byte 5 (0 base) is
+ * the only  value affected for a 66MHz PCI and simply needs a +0x10.
+ */
+
+#define NAND_COMPATIBLE	0x01
+#define NOR_COMPATIBLE  0x02
+
+/* check with Stefan on CFG_I2C_EEPROM_ADDR */
+#define I2C_EEPROM_ADDR 0x52
+
+static char *config_labels[] = {
+	"CPU: 333 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 333 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 400 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 400 PLB: 160 OPB: 80 EBC: 53",
+	"CPU: 416 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 500 PLB: 166 OPB: 83 EBC: 55",
+	"CPU: 533 PLB: 133 OPB: 66 EBC: 66",
+	"CPU: 667 PLB: 166 OPB: 83 EBC: 55",
+	NULL
 };
 
-static u8 boot_533_nand[] = {
-	0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xd0, 0x10,
-	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+static u8 boot_configs[][17] = {
+	{
+		(NOR_COMPATIBLE),
+		0x84, 0x70, 0xa2, 0xa6, 0x05, 0x57, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0xf3, 0x4e, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xc6, 0x05, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x86, 0x78, 0xc2, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc6, 0x78, 0x52, 0xa6, 0x05, 0xd7, 0xa0, 0x10, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0xc7, 0x78, 0x52, 0xc6, 0x05, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NOR_COMPATIBLE),
+		0x87, 0x78, 0x82, 0x52, 0x09, 0x57, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		(NAND_COMPATIBLE | NOR_COMPATIBLE),
+		0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30, 0x40,
+		0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
+	},
+	{
+		0,
+		0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+	}
 };
 
-static u8 boot_667_nor[] = {
-	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xa0, 0x30,
-	0x40, 0x08, 0x23, 0x50, 0x0d, 0x05, 0x00, 0x00
-};
-
-static u8 boot_667_nand[] = {
-	0x87, 0x78, 0xa2, 0x52, 0x09, 0xd7, 0xd0, 0x10,
-	0xa0, 0x68, 0x23, 0x58, 0x0d, 0x05, 0x00, 0x00
+/*
+ * Bytes 6,8,9,11 change for NAND boot
+ */
+static u8 nand_boot[] = {
+	0xd0,  0xa0, 0x68, 0x58
 };
 
 static int do_bootstrap(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
 {
-	u8 chip;
-	u8 *buf;
-	int cpu_freq;
+	u8 *buf, bNAND;
+	int x, y, nbytes, selcfg;
+	extern char console_buffer[];
 
-	if (argc < 3) {
+	if (argc < 2) {
 		printf("Usage:\n%s\n", cmdtp->usage);
 		return 1;
 	}
 
-	cpu_freq = simple_strtol(argv[1], NULL, 10);
-	if (!((cpu_freq == 533) || (cpu_freq == 667))) {
-		printf("Unsupported cpu-frequency - only 533 and 667 supported\n");
-		return 1;
-	}
-
-	/* use 0x52 as I2C EEPROM address for now */
-	chip = 0x52;
-
-	if ((strcmp(argv[2], "nor") != 0) &&
-	    (strcmp(argv[2], "nand") != 0)) {
+	if ((strcmp(argv[1], "nor") != 0) &&
+	    (strcmp(argv[1], "nand") != 0)) {
 		printf("Unsupported boot-device - only nor|nand support\n");
 		return 1;
 	}
 
-	if (strcmp(argv[2], "nand") == 0) {
-		switch (cpu_freq) {
-		default:
-		case 533:
-			buf = boot_533_nand;
-			break;
-		case 667:
-			buf = boot_667_nand;
-			break;
+	/* set the nand flag based on provided input */
+	if ((strcmp(argv[1], "nand") == 0))
+		bNAND = 1;
+	else
+		bNAND = 0;
+
+	printf("Available configurations: \n\n");
+
+	if (bNAND) {
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nand compatible */
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
 		}
 	} else {
-		switch (cpu_freq) {
-		default:
-		case 533:
-			buf = boot_533_nor;
-			break;
-		case 667:
-			buf = boot_667_nor;
-			break;
+		for(x = 0, y = 0; boot_configs[x][0] != 0; x++) {
+			/* filter on nor compatible */
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				printf(" %d - %s\n", (y+1), config_labels[x]);
+				y++;
+			}
 		}
 	}
 
-	if (i2c_write(chip, 0, 1, buf, 16) != 0)
-		printf("Error writing to EEPROM at address 0x%x\n", chip);
+	do {
+		nbytes = readline(" Selection [1-x / quit]: ");
+
+		if (nbytes) {
+			if (strcmp(console_buffer, "quit") == 0)
+				return 0;
+			selcfg = simple_strtol(console_buffer, NULL, 10);
+			if ((selcfg < 1) || (selcfg > y))
+				nbytes = 0;
+		}
+	} while (nbytes == 0);
+
+
+	y = (selcfg - 1);
+
+	for (x = 0; boot_configs[x][0] != 0; x++) {
+		if (bNAND) {
+			if (boot_configs[x][0] & NAND_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		} else {
+			if (boot_configs[x][0] & NOR_COMPATIBLE) {
+				if (y > 0)
+					y--;
+				else if (y < 1)
+					break;
+			}
+		}
+	}
+
+	buf = &boot_configs[x][1];
+
+	if (bNAND) {
+		buf[6] = nand_boot[0];
+		buf[8] = nand_boot[1];
+		buf[9] = nand_boot[2];
+		buf[11] = nand_boot[3];
+	}
+
+	/* check CPLD register +5 for PCI 66MHz flag */
+	if (in8(CFG_BCSR_BASE + 5) & 0x01)
+		buf[5] += 0x10;
+
+	if (i2c_write(I2C_EEPROM_ADDR, 0, 1, buf, 16) != 0)
+		printf("Error writing to EEPROM at address 0x%x\n", I2C_EEPROM_ADDR);
 	udelay(CFG_EEPROM_PAGE_WRITE_DELAY_MS * 1000);
 
 	printf("Done\n");
@@ -105,7 +214,7 @@
 }
 
 U_BOOT_CMD(
-	bootstrap,	3,	0,	do_bootstrap,
+	bootstrap,	2,	0,	do_bootstrap,
 	"bootstrap - program the I2C bootstrap EEPROM\n",
-	"<cpu-freq> <nor|nand> - program the I2C bootstrap EEPROM\n"
+	"<nand|nor> - strap to boot from NAND or NOR flash\n"
 	);
diff --git a/board/esd/common/auto_update.c b/board/esd/common/auto_update.c
index da147ee..a76b00f 100644
--- a/board/esd/common/auto_update.c
+++ b/board/esd/common/auto_update.c
@@ -24,10 +24,6 @@
 
 #include <common.h>
 
-#if defined(CONFIG_CMD_NAND) && !defined(CFG_NAND_LEGACY)
-#warning CFG_NAND_LEGACY not defined in a file using the legacy NAND support!
-#endif
-
 #include <command.h>
 #include <image.h>
 #include <asm/byteorder.h>
diff --git a/board/freescale/common/pq-mds-pib.c b/board/freescale/common/pq-mds-pib.c
new file mode 100644
index 0000000..8c013c7
--- /dev/null
+++ b/board/freescale/common/pq-mds-pib.c
@@ -0,0 +1,102 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * Tony Li <tony.li@freescale.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/io.h>
+
+#include "pq-mds-pib.h"
+
+int pib_init(void)
+{
+	u8 val8;
+	u8 orig_i2c_bus;
+
+	/* Switch temporarily to I2C bus #2 */
+	orig_i2c_bus = i2c_get_bus_num();
+	i2c_set_bus_num(1);
+
+	val8 = 0;
+#if defined(CONFIG_PCI) && !defined(CONFIG_PCISLAVE)
+	/* Assign PIB PMC slot to desired PCI bus */
+	i2c_write(0x23, 0x6, 1, &val8, 1);
+	i2c_write(0x23, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x23, 0x2, 1, &val8, 1);
+	i2c_write(0x23, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x26, 0x6, 1, &val8, 1);
+	val8 = 0x34;
+	i2c_write(0x26, 0x7, 1, &val8, 1);
+#if defined(CONFIG_MPC832XEMDS)
+	val8 = 0xf9;            /* PMC2, PMC3 slot to PCI bus */
+#else
+	val8 = 0xf3;		/* PMC1, PMC2, PMC3 slot to PCI bus */
+#endif
+	i2c_write(0x26, 0x2, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x26, 0x3, 1, &val8, 1);
+
+	val8 = 0;
+	i2c_write(0x27, 0x6, 1, &val8, 1);
+	i2c_write(0x27, 0x7, 1, &val8, 1);
+	val8 = 0xff;
+	i2c_write(0x27, 0x2, 1, &val8, 1);
+	val8 = 0xef;
+	i2c_write(0x27, 0x3, 1, &val8, 1);
+
+	eieio();
+
+#if defined(CONFIG_MPC832XEMDS)
+	printf("PCI 32bit bus on PMC2 &PMC3\n");
+#else
+	printf("PCI 32bit bus on PMC1 & PMC2 &PMC3\n");
+#endif
+#endif
+
+#if defined(CONFIG_PQ_MDS_PIB_ATM)
+#if defined(CONFIG_MPC8360EMDS)
+	val8 = 0;
+	i2c_write(0x20, 0x6, 1, &val8, 1);
+	i2c_write(0x20, 0x7, 1, &val8, 1);
+
+	val8 = 0xdf;
+	i2c_write(0x20, 0x2, 1, &val8, 1);
+	val8 = 0xf7;
+	i2c_write(0x20, 0x3, 1, &val8, 1);
+
+	eieio();
+
+	printf("QOC3 ATM card on PMC0\n");
+#elif defined(CONFIG_MPC832XEMDS)
+	val = 0;
+	i2c_write(0x26, 0x7, 1, &val, 1);
+	val = 0xf7;
+	i2c_write(0x26, 0x3, 1, &val, 1);
+
+	val = 0;
+	i2c_write(0x21, 0x6, 1, &val, 1);
+	i2c_write(0x21, 0x7, 1, &val, 1);
+
+	val = 0xdf;
+	i2c_write(0x21, 0x2, 1, &val, 1);
+	val = 0xef;
+	i2c_write(0x21, 0x3, 1, &val, 1);
+
+	eieio();
+
+	printf("QOC3 ATM card on PMC1\n");
+#endif
+#endif
+	/* Reset to original I2C bus */
+	i2c_set_bus_num(orig_i2c_bus);
+	return 0;
+}
diff --git a/board/freescale/common/pq-mds-pib.h b/board/freescale/common/pq-mds-pib.h
new file mode 100644
index 0000000..67066fd
--- /dev/null
+++ b/board/freescale/common/pq-mds-pib.h
@@ -0,0 +1,9 @@
+/*
+ * Copyright (C) 2007 Freescale Semiconductor, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation;
+ */
+
+extern int pib_init(void);
diff --git a/board/mpc8313erdb/Makefile b/board/freescale/mpc8313erdb/Makefile
similarity index 100%
rename from board/mpc8313erdb/Makefile
rename to board/freescale/mpc8313erdb/Makefile
diff --git a/board/mpc8313erdb/config.mk b/board/freescale/mpc8313erdb/config.mk
similarity index 100%
rename from board/mpc8313erdb/config.mk
rename to board/freescale/mpc8313erdb/config.mk
diff --git a/board/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c
similarity index 93%
rename from board/mpc8313erdb/mpc8313erdb.c
rename to board/freescale/mpc8313erdb/mpc8313erdb.c
index 999fe9e..861c143 100644
--- a/board/mpc8313erdb/mpc8313erdb.c
+++ b/board/freescale/mpc8313erdb/mpc8313erdb.c
@@ -23,7 +23,11 @@
  */
 
 #include <common.h>
+#if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
 #include <pci.h>
 #include <mpc83xx.h>
 
@@ -96,21 +100,22 @@
 	mpc83xx_pci_init(1, reg, warmboot);
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
+#if defined(CONFIG_OF_BOARD_SETUP)
 void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
 	p = ft_get_prop(blob, "/memory/reg", &len);
-	if (p) {
+	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
 }
 #endif
diff --git a/board/mpc8313erdb/sdram.c b/board/freescale/mpc8313erdb/sdram.c
similarity index 98%
rename from board/mpc8313erdb/sdram.c
rename to board/freescale/mpc8313erdb/sdram.c
index 4b67788..e6e8410 100644
--- a/board/mpc8313erdb/sdram.c
+++ b/board/freescale/mpc8313erdb/sdram.c
@@ -112,8 +112,6 @@
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
-	puts("Initializing\n");
-
 	/* DDR SDRAM - Main SODIMM */
 	msize = fixed_sdram();
 
@@ -127,7 +125,6 @@
 		resume_from_sleep();
 #endif
 
-	puts("   DDR RAM: ");
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return msize;
 }
diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c
index 1886f19..e738613 100644
--- a/board/freescale/mpc8323erdb/mpc8323erdb.c
+++ b/board/freescale/mpc8323erdb/mpc8323erdb.c
@@ -17,7 +17,6 @@
 #include <miiphy.h>
 #include <command.h>
 #include <libfdt.h>
-#include <libfdt_env.h>
 #if defined(CONFIG_PCI)
 #include <pci.h>
 #endif
@@ -92,8 +91,6 @@
 
 	msize = fixed_sdram();
 
-	puts("\n   DDR RAM: ");
-
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
@@ -185,33 +182,21 @@
 }
 
 #if defined(CONFIG_OF_BOARD_SETUP)
-
-/*
- * Prototypes of functions that we use.
- */
-void ft_cpu_setup(void *blob, bd_t *bd);
-
-#ifdef CONFIG_PCI
-void ft_pci_setup(void *blob, bd_t *bd);
-#endif
-
-void
-ft_board_setup(void *blob, bd_t *bd)
+void ft_board_setup(void *blob, bd_t *bd)
 {
-	int nodeoffset;
-	int tmp[2];
+#if defined(CONFIG_OF_FLAT_TREE)
+	u32 *p;
+	int len;
 
-	nodeoffset = fdt_find_node_by_path(blob, "/memory");
-	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(bd->bi_memstart);
-		tmp[1] = cpu_to_be32(bd->bi_memsize);
-		fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
+	p = ft_get_prop(blob, "/memory/reg", &len);
+	if (p != NULL) {
+		*p++ = cpu_to_be32(bd->bi_memstart);
+		*p = cpu_to_be32(bd->bi_memsize);
 	}
-
+#endif
 	ft_cpu_setup(blob, bd);
-
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
 }
-#endif /* CONFIG_OF_BOARD_SETUP */
+#endif
diff --git a/board/mpc832xemds/Makefile b/board/freescale/mpc832xemds/Makefile
similarity index 96%
rename from board/mpc832xemds/Makefile
rename to board/freescale/mpc832xemds/Makefile
index 5ec7a87..ea52484 100644
--- a/board/mpc832xemds/Makefile
+++ b/board/freescale/mpc832xemds/Makefile
@@ -25,7 +25,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o pci.o
+COBJS	:= $(BOARD).o pci.o ../common/pq-mds-pib.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mpc832xemds/config.mk b/board/freescale/mpc832xemds/config.mk
similarity index 100%
rename from board/mpc832xemds/config.mk
rename to board/freescale/mpc832xemds/config.mk
diff --git a/board/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c
similarity index 92%
rename from board/mpc832xemds/mpc832xemds.c
rename to board/freescale/mpc832xemds/mpc832xemds.c
index 772da67..6ba25d4 100644
--- a/board/mpc832xemds/mpc832xemds.c
+++ b/board/freescale/mpc832xemds/mpc832xemds.c
@@ -29,6 +29,11 @@
 #endif
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
 #endif
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -86,6 +91,14 @@
 	return 0;
 }
 
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
 int fixed_sdram(void);
 
 long int initdram(int board_type)
@@ -101,8 +114,6 @@
 
 	msize = fixed_sdram();
 
-	puts("\n   DDR RAM: ");
-
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
@@ -155,22 +166,22 @@
 	return 0;
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
 }
 #endif
diff --git a/board/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c
similarity index 88%
rename from board/mpc832xemds/pci.c
rename to board/freescale/mpc832xemds/pci.c
index d0a407a..6bc35c7 100644
--- a/board/mpc832xemds/pci.c
+++ b/board/freescale/mpc832xemds/pci.c
@@ -20,6 +20,8 @@
 #include <i2c.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
 #endif
 
 #include <asm/fsl_i2c.h>
@@ -129,7 +131,6 @@
 	volatile pcictrl83xx_t *pci_ctrl;
 	volatile pciconf83xx_t *pci_conf;
 
-	u8 val8, orig_i2c_bus;
 	u16 reg16;
 	u32 val32;
 	u32 dev;
@@ -198,43 +199,6 @@
 	    PIWAR_IWS_2G;
 
 	/*
-	 * Assign PIB PMC slot to desired PCI bus
-	 */
-
-	/* Switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-
-	val8 = 0xf9;		/* PMC2, PMC3 slot to PCI bus */
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-	asm("eieio");
-
-	/* Reset to original I2C bus */
-	i2c_set_bus_num(orig_i2c_bus);
-
-	/*
 	 * Release PCI RST Output signal
 	 */
 	udelay(2000);
@@ -290,8 +254,6 @@
 	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
 	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
 
-	printf("PCI 32bit bus on PMC2 & PMC3\n");
-
 	/*
 	 * Hose scan.
 	 */
@@ -299,7 +261,27 @@
 }
 #endif				/* CONFIG_PCISLAVE */
 
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int err;
+	int tmp[2];
+
+	nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+	if (nodeoffset >= 0) {
+		tmp[0] = cpu_to_be32(hose[0].first_busno);
+		tmp[1] = cpu_to_be32(hose[0].last_busno);
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
+	}
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
diff --git a/board/mpc8349emds/Makefile b/board/freescale/mpc8349emds/Makefile
similarity index 100%
rename from board/mpc8349emds/Makefile
rename to board/freescale/mpc8349emds/Makefile
diff --git a/board/mpc8349emds/config.mk b/board/freescale/mpc8349emds/config.mk
similarity index 100%
rename from board/mpc8349emds/config.mk
rename to board/freescale/mpc8349emds/config.mk
diff --git a/board/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c
similarity index 95%
rename from board/mpc8349emds/mpc8349emds.c
rename to board/freescale/mpc8349emds/mpc8349emds.c
index 521d1bb..39c0916 100644
--- a/board/mpc8349emds/mpc8349emds.c
+++ b/board/freescale/mpc8349emds/mpc8349emds.c
@@ -34,6 +34,8 @@
 #endif
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
 #endif
 
 int fixed_sdram(void);
@@ -68,8 +70,6 @@
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
-	puts("Initializing\n");
-
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
@@ -88,7 +88,7 @@
 	 */
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
-	puts("   DDR RAM: ");
+
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
@@ -189,9 +189,6 @@
 	volatile lbus83xx_t *lbc= &immap->lbus;
 	uint *sdram_addr = (uint *)CFG_LBC_SDRAM_BASE;
 
-	puts("\n   SDRAM on Local Bus: ");
-	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
-
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
@@ -253,26 +250,25 @@
 #else
 void sdram_init(void)
 {
-	puts("   SDRAM on Local Bus is NOT available!\n");
 }
 #endif
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
 }
 #endif
diff --git a/board/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c
similarity index 90%
rename from board/mpc8349emds/pci.c
rename to board/freescale/mpc8349emds/pci.c
index d6a12b8..ae94a2f 100644
--- a/board/mpc8349emds/pci.c
+++ b/board/freescale/mpc8349emds/pci.c
@@ -25,6 +25,12 @@
 #include <pci.h>
 #include <asm/mpc8349_pci.h>
 #include <i2c.h>
+#if defined(CONFIG_OF_FLAT_TREE)
+#include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
+#endif
+
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -382,7 +388,40 @@
 
 }
 
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int err;
+	int tmp[2];
+
+	nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+	if (nodeoffset >= 0) {
+		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
+	}
+#ifdef CONFIG_MPC83XX_PCI2
+	nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8600");
+	if (nodeoffset >= 0) {
+		tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+		tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
+	}
+#endif
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
diff --git a/board/mpc8349itx/Makefile b/board/freescale/mpc8349itx/Makefile
similarity index 100%
rename from board/mpc8349itx/Makefile
rename to board/freescale/mpc8349itx/Makefile
diff --git a/board/mpc8349itx/config.mk b/board/freescale/mpc8349itx/config.mk
similarity index 100%
rename from board/mpc8349itx/config.mk
rename to board/freescale/mpc8349itx/config.mk
diff --git a/board/mpc8349itx/mpc8349itx.c b/board/freescale/mpc8349itx/mpc8349itx.c
similarity index 97%
rename from board/mpc8349itx/mpc8349itx.c
rename to board/freescale/mpc8349itx/mpc8349itx.c
index 178b1d3..c82f784 100644
--- a/board/mpc8349itx/mpc8349itx.c
+++ b/board/freescale/mpc8349itx/mpc8349itx.c
@@ -39,6 +39,8 @@
 #endif
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
 #endif
 
 #ifndef CONFIG_SPD_EEPROM
@@ -74,7 +76,7 @@
 
 	im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
 	im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
-	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR;
+	im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
 	im->ddr.sdram_mode =
 	    (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
 	im->ddr.sdram_interval =
@@ -160,7 +162,6 @@
 		ddr_enable_ecc(msize * 1048576);
 #endif
 
-	puts("   DDR RAM: ");
 	/* return total bus RAM size(bytes) */
 	return msize * 1024 * 1024;
 }
@@ -385,22 +386,22 @@
 	return rc;
 }
 
-#if defined(CONFIG_OF_FLAT_TREE) && defined(CONFIG_OF_BOARD_SETUP)
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
 {
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
-#ifdef CONFIG_PCI
-	ft_pci_setup(blob, bd);
-#endif
-	ft_cpu_setup(blob, bd);
-
 	p = ft_get_prop(blob, "/memory/reg", &len);
 	if (p != NULL) {
 		*p++ = cpu_to_be32(bd->bi_memstart);
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
+#endif
+	ft_cpu_setup(blob, bd);
+#ifdef CONFIG_PCI
+	ft_pci_setup(blob, bd);
+#endif
 }
 #endif
diff --git a/board/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c
similarity index 89%
rename from board/mpc8349itx/pci.c
rename to board/freescale/mpc8349itx/pci.c
index e81ad27..5ca094d 100644
--- a/board/mpc8349itx/pci.c
+++ b/board/freescale/mpc8349itx/pci.c
@@ -31,6 +31,8 @@
 #include <i2c.h>
 #if defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
+#elif defined(CONFIG_OF_LIBFDT)
+#include <libfdt.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -332,8 +334,40 @@
 #endif
 }
 
-#endif				/* CONFIG_PCI */
-#ifdef CONFIG_OF_FLAT_TREE
+#if defined(CONFIG_OF_LIBFDT)
+void
+ft_pci_setup(void *blob, bd_t *bd)
+{
+	int nodeoffset;
+	int err;
+	int tmp[2];
+
+	nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+	if (nodeoffset >= 0) {
+		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
+		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
+	}
+#ifdef CONFIG_MPC83XX_PCI2
+	nodeoffset = fdt_find_node_by_path(blob, "/" OF_SOC "/pci@8500");
+	if (nodeoffset >= 0) {
+		tmp[0] = cpu_to_be32(pci_hose[1].first_busno);
+		tmp[1] = cpu_to_be32(pci_hose[1].last_busno);
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
+	}
+#endif
+}
+#elif defined(CONFIG_OF_FLAT_TREE)
 void
 ft_pci_setup(void *blob, bd_t *bd)
 {
@@ -355,3 +389,4 @@
 #endif
 }
 #endif /* CONFIG_OF_FLAT_TREE */
+#endif /* CONFIG_PCI */
diff --git a/board/mpc832xemds/Makefile b/board/freescale/mpc8360emds/Makefile
similarity index 96%
copy from board/mpc832xemds/Makefile
copy to board/freescale/mpc8360emds/Makefile
index 5ec7a87..ea52484 100644
--- a/board/mpc832xemds/Makefile
+++ b/board/freescale/mpc8360emds/Makefile
@@ -25,7 +25,7 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= $(BOARD).o pci.o
+COBJS	:= $(BOARD).o pci.o ../common/pq-mds-pib.o
 
 SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
diff --git a/board/mpc8360emds/config.mk b/board/freescale/mpc8360emds/config.mk
similarity index 100%
rename from board/mpc8360emds/config.mk
rename to board/freescale/mpc8360emds/config.mk
diff --git a/board/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c
similarity index 90%
rename from board/mpc8360emds/mpc8360emds.c
rename to board/freescale/mpc8360emds/mpc8360emds.c
index 3fa093d..e050cd4 100644
--- a/board/mpc8360emds/mpc8360emds.c
+++ b/board/freescale/mpc8360emds/mpc8360emds.c
@@ -29,7 +29,9 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
+#endif
+#if defined(CONFIG_PQ_MDS_PIB)
+#include "../common/pq-mds-pib.h"
 #endif
 
 const qe_iop_conf_t qe_iop_conf_tab[] = {
@@ -107,6 +109,14 @@
 	return 0;
 }
 
+int board_early_init_r(void)
+{
+#ifdef CONFIG_PQ_MDS_PIB
+	pib_init();
+#endif
+	return 0;
+}
+
 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
 extern void ddr_enable_ecc(unsigned int dram_size);
 #endif
@@ -139,7 +149,7 @@
 	 * Initialize SDRAM if it is on local bus.
 	 */
 	sdram_init();
-	puts("   DDR RAM: ");
+
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
@@ -224,8 +234,6 @@
 	volatile lbus83xx_t *lbc = &immap->lbus;
 	uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
 
-	puts("\n   SDRAM on Local Bus: ");
-	print_size(CFG_LBC_SDRAM_SIZE * 1024 * 1024, "\n");
 	/*
 	 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
 	 */
@@ -281,36 +289,13 @@
 #else
 void sdram_init(void)
 {
-	puts("SDRAM on Local Bus is NOT available!\n");
 }
 #endif
 
-#if (defined(CONFIG_OF_FLAT_TREE) || defined(CONFIG_OF_LIBFDT)) \
-     && defined(CONFIG_OF_BOARD_SETUP)
-
-/*
- * Prototypes of functions that we use.
- */
-void ft_cpu_setup(void *blob, bd_t *bd);
-
-#ifdef CONFIG_PCI
-void ft_pci_setup(void *blob, bd_t *bd);
-#endif
-
-void
-ft_board_setup(void *blob, bd_t *bd)
+#if defined(CONFIG_OF_BOARD_SETUP)
+void ft_board_setup(void *blob, bd_t *bd)
 {
-#if defined(CONFIG_OF_LIBFDT)
-	int nodeoffset;
-	int tmp[2];
-
-	nodeoffset = fdt_find_node_by_path(blob, "/memory");
-	if (nodeoffset >= 0) {
-		tmp[0] = cpu_to_be32(bd->bi_memstart);
-		tmp[1] = cpu_to_be32(bd->bi_memsize);
-		fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
-	}
-#else
+#if defined(CONFIG_OF_FLAT_TREE)
 	u32 *p;
 	int len;
 
@@ -320,10 +305,9 @@
 		*p = cpu_to_be32(bd->bi_memsize);
 	}
 #endif
-
+	ft_cpu_setup(blob, bd);
 #ifdef CONFIG_PCI
 	ft_pci_setup(blob, bd);
 #endif
-	ft_cpu_setup(blob, bd);
 }
-#endif /* CONFIG_OF_x */
+#endif
diff --git a/board/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c
similarity index 88%
rename from board/mpc8360emds/pci.c
rename to board/freescale/mpc8360emds/pci.c
index 8f90471..cf7ef90 100644
--- a/board/mpc8360emds/pci.c
+++ b/board/freescale/mpc8360emds/pci.c
@@ -22,7 +22,6 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #endif
 
 #include <asm/fsl_i2c.h>
@@ -132,7 +131,6 @@
 	volatile pcictrl83xx_t *pci_ctrl;
 	volatile pciconf83xx_t *pci_conf;
 
-	u8 val8, orig_i2c_bus;
 	u16 reg16;
 	u32 val32;
 	u32 dev;
@@ -201,43 +199,6 @@
 	    PIWAR_IWS_2G;
 
 	/*
-	 * Assign PIB PMC slot to desired PCI bus
-	 */
-
-	/* Switch temporarily to I2C bus #2 */
-	orig_i2c_bus = i2c_get_bus_num();
-	i2c_set_bus_num(1);
-
-	val8 = 0;
-	i2c_write(0x23, 0x6, 1, &val8, 1);
-	i2c_write(0x23, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x23, 0x2, 1, &val8, 1);
-	i2c_write(0x23, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x26, 0x6, 1, &val8, 1);
-	val8 = 0x34;
-	i2c_write(0x26, 0x7, 1, &val8, 1);
-
-	val8 = 0xf3;		/*PMC1, PMC2, PMC3 slot to PCI bus */
-	i2c_write(0x26, 0x2, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x26, 0x3, 1, &val8, 1);
-
-	val8 = 0;
-	i2c_write(0x27, 0x6, 1, &val8, 1);
-	i2c_write(0x27, 0x7, 1, &val8, 1);
-	val8 = 0xff;
-	i2c_write(0x27, 0x2, 1, &val8, 1);
-	val8 = 0xef;
-	i2c_write(0x27, 0x3, 1, &val8, 1);
-	asm("eieio");
-
-	/* Reset to original I2C bus */
-	i2c_set_bus_num(orig_i2c_bus);
-
-	/*
 	 * Release PCI RST Output signal
 	 */
 	udelay(2000);
@@ -293,8 +254,6 @@
 	pci_hose_write_config_byte(&hose[0], dev, PCI_LATENCY_TIMER, 0x80);
 	pci_hose_write_config_byte(&hose[0], dev, PCI_CACHE_LINE_SIZE, 0x08);
 
-	printf("PCI 32bit bus on PMC1 & PMC2 & PMC3\n");
-
 	/*
 	 * Hose scan.
 	 */
@@ -314,7 +273,12 @@
 	if (nodeoffset >= 0) {
 		tmp[0] = cpu_to_be32(hose[0].first_busno);
 		tmp[1] = cpu_to_be32(hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
 	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c
index f906b85..d4547e2 100644
--- a/board/lwmon5/sdram.c
+++ b/board/lwmon5/sdram.c
@@ -57,7 +57,6 @@
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
-#ifdef CONFIG_ADD_RAM_INFO
 static u32 is_ecc_enabled(void)
 {
 	u32 val;
@@ -87,7 +86,6 @@
 	val = DDR0_03_CASLAT_DECODE(val);
 	printf(", CL%d)", val);
 }
-#endif
 
 static int wait_for_dlllock(void)
 {
diff --git a/board/mpc8360emds/Makefile b/board/mpc8360emds/Makefile
deleted file mode 100644
index 5ec7a87..0000000
--- a/board/mpc8360emds/Makefile
+++ /dev/null
@@ -1,50 +0,0 @@
-#
-# (C) Copyright 2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# See file CREDITS for list of people who contributed to this
-# project.
-#
-# This program is free software; you can redistribute it and/or
-# modify it under the terms of the GNU General Public License as
-# published by the Free Software Foundation; either version 2 of
-# the License, or (at your option) any later version.
-#
-# This program is distributed in the hope that it will be useful,
-# but WITHOUT ANY WARRANTY; without even the implied warranty of
-# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-# GNU General Public License for more details.
-#
-# You should have received a copy of the GNU General Public License
-# along with this program; if not, write to the Free Software
-# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-# MA 02111-1307 USA
-#
-
-include $(TOPDIR)/config.mk
-
-LIB	= $(obj)lib$(BOARD).a
-
-COBJS	:= $(BOARD).o pci.o
-
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
-
-$(LIB):	$(obj).depend $(OBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS)
-
-clean:
-	rm -f $(SOBJS) $(OBJS)
-
-distclean:	clean
-	rm -f $(LIB) core *.bak .depend
-
-#########################################################################
-
-# defines $(obj).depend target
-include $(SRCTREE)/rules.mk
-
-sinclude $(obj).depend
-
-#########################################################################
diff --git a/board/netstal/common/flash.c b/board/netstal/common/hcu_flash.c
similarity index 100%
rename from board/netstal/common/flash.c
rename to board/netstal/common/hcu_flash.c
diff --git a/board/netstal/hcu4/Makefile b/board/netstal/hcu4/Makefile
index d9825a5..af90821 100644
--- a/board/netstal/hcu4/Makefile
+++ b/board/netstal/hcu4/Makefile
@@ -22,16 +22,20 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-vpath flash.c ../common
-COBJS	= $(BOARD).o flash.o
+vpath hcu_flash.c ../common
+
+# NOBJS : Netstal common objects
+NOBJS	= hcu_flash.o
+COBJS	= $(BOARD).o
 SOBJS	=
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
+NOBJS	:= $(addprefix $(obj),$(NOBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(OBJS) $(SOBJS) $(NOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c
index 2b95604..48a3f13 100644
--- a/board/netstal/hcu4/hcu4.c
+++ b/board/netstal/hcu4/hcu4.c
@@ -43,7 +43,7 @@
 	HW_GENERATION_MCU25 = 0x09,
 };
 
-void sysLedSet(u32 value);
+void hcu_led_set(u32 value);
 long int spd_sdram(int(read_spd)(uint addr));
 
 #ifdef CONFIG_SPD_EEPROM
@@ -121,22 +121,24 @@
 		printf ("HCU3: index %d\n\n", index);
 	else if (generation == HW_GENERATION_HCU4)
 		printf ("HCU4: index %d\n\n", index);
-	/* GPIO here noch nicht richtig initialisert !!! */
-	sysLedSet(0);
+	hcu_led_set(0);
 	for (j = 0; j < 7; j++) {
-		sysLedSet(1 << j);
+		hcu_led_set(1 << j);
 		udelay(50 * 1000);
 	}
 
 	return 0;
 }
 
-u32 sysLedGet(void)
+u32 hcu_led_get(void)
 {
 	return (~((*(u32 *)GPIO0_OR)) >> 23) & 0xff;
 }
 
-void sysLedSet(u32 value /* value to place in LEDs */)
+/*---------------------------------------------------------------------------+
+ * hcu_led_set  value to be placed into the LEDs (max 6 bit)
+ *---------------------------------------------------------------------------*/
+void hcu_led_set(u32 value)
 {
 	u32   tmp = ~value;
 	u32   *ledReg;
@@ -243,9 +245,9 @@
 }
 
 /*---------------------------------------------------------------------------+
- * getSerialNr
+ * hcu_serial_number
  *---------------------------------------------------------------------------*/
-static u32 getSerialNr(void)
+static u32 hcu_serial_number(void)
 {
 	u32 *serial = (u32 *)CFG_FLASH_BASE;
 
@@ -265,7 +267,7 @@
 	char *s = getenv("ethaddr");
 	char *e;
 	int i;
-	u32 serial = getSerialNr();
+	u32 serial = hcu_serial_number();
 
 	for (i = 0; i < 6; ++i) {
 		gd->bd->bi_enetaddr[i] = s ? simple_strtoul (s, &e, 16) : 0;
diff --git a/board/netstal/hcu5/Makefile b/board/netstal/hcu5/Makefile
index eee310b..27398b9 100644
--- a/board/netstal/hcu5/Makefile
+++ b/board/netstal/hcu5/Makefile
@@ -22,16 +22,20 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-vpath flash.c ../common
-COBJS	= $(BOARD).o sdram.o flash.o
+vpath hcu_flash.c ../common
+
+# NOBJS : Netstal common objects
+NOBJS	= hcu_flash.o
+COBJS	= $(BOARD).o sdram.o
 SOBJS	= init.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
+SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c) ../common/$(NOBJS:.o=.c)
 OBJS	:= $(addprefix $(obj),$(COBJS))
+NOBJS	:= $(addprefix $(obj),$(NOBJS))
 SOBJS	:= $(addprefix $(obj),$(SOBJS))
 
-$(LIB):	$(OBJS) $(SOBJS)
-	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+$(LIB):	$(OBJS) $(SOBJS) $(NOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) $(NOBJS)
 
 clean:
 	rm -f $(SOBJS) $(OBJS)
diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c
index 23df081..b9b10fd 100644
--- a/board/netstal/hcu5/hcu5.c
+++ b/board/netstal/hcu5/hcu5.c
@@ -22,10 +22,11 @@
 #include <asm/processor.h>
 #include <ppc440.h>
 #include <asm/mmu.h>
+#include <net.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
-void sysLedSet(u32 value);
+void hcu_led_set(u32 value);
 
 extern flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
 
@@ -41,7 +42,8 @@
 #define SDR0_ECID2		0x0082
 #define SDR0_ECID3		0x0083
 
-#define SYS_IO_ADDRESS		0xcce00000
+#define SYS_IO_ADDRESS		(CFG_CS_2 + 0x00e00000)
+#define SYS_SLOT_ADDRESS		(CFG_CPLD + 0x00400000)
 
 #define DEFAULT_ETH_ADDR  "ethaddr"
 /* ethaddr for first or etha1ddr for second ethernet */
@@ -182,11 +184,14 @@
 	return 0;
 }
 
+#ifdef CONFIG_BOARD_PRE_INIT
 int board_pre_init(void)
 {
 	return board_early_init_f();
 }
 
+#endif
+
 int checkboard(void)
 {
 	unsigned int j;
@@ -211,38 +216,51 @@
 
 	printf("Chip ID 0x%x 0x%x 0x%x 0x%x\n", ecid0, ecid1, ecid2, ecid3);
 	for (j = 0;j < 6; j++) {
-		sysLedSet(1 << j);
+		hcu_led_set(1 << j);
 		udelay(200 * 1000);
 	}
 
 	return 0;
 }
 
-u32 sysLedGet(void)
+u32 hcu_led_get(void)
 {
 	return in16(SYS_IO_ADDRESS) & 0x3f;
 }
 
-void sysLedSet(u32 value /* value to place in LEDs */)
+/*---------------------------------------------------------------------------+
+ * hcu_led_set  value to be placed into the LEDs (max 6 bit)
+ *---------------------------------------------------------------------------*/
+void hcu_led_set(u32 value)
 {
 	out16(SYS_IO_ADDRESS, value);
 }
 
 /*---------------------------------------------------------------------------+
- * getSerialNr
+ * get_serial_number
  *---------------------------------------------------------------------------*/
-static u32 getSerialNr(void)
+static u32 get_serial_number(void)
 {
 	u32 *serial = (u32 *)CFG_FLASH_BASE;
 
 	if (*serial == 0xffffffff)
-		return get_ticks();
+		return 0;
 
 	return *serial;
 }
 
 
 /*---------------------------------------------------------------------------+
+ * hcu_get_slot
+ *---------------------------------------------------------------------------*/
+u32 hcu_get_slot(void)
+{
+	u16 *slot = (u16 *)SYS_SLOT_ADDRESS;
+	return (*slot) & 0x7f;
+}
+
+
+/*---------------------------------------------------------------------------+
  * misc_init_r.
  *---------------------------------------------------------------------------*/
 int misc_init_r(void)
@@ -250,7 +268,7 @@
 	char *s = getenv(DEFAULT_ETH_ADDR);
 	char *e;
 	int i;
-	u32 serial = getSerialNr();
+	u32 serial = get_serial_number();
 	unsigned long usb2d0cr = 0;
 	unsigned long usb2phy0cr, usb2h0cr = 0;
 	unsigned long sdr0_pfc1;
@@ -272,8 +290,7 @@
 		gd->bd->bi_enetaddr[2] = 0x13;
 		gd->bd->bi_enetaddr[3] = (serial >> 16) & 0xff;
 		gd->bd->bi_enetaddr[4] = (serial >>  8) & 0xff;
-		/* byte[5].bit 0 must be zero */
-		gd->bd->bi_enetaddr[5] = (serial >>  0) & 0xfe;
+		gd->bd->bi_enetaddr[5] = hcu_get_slot();
 		sprintf(ethaddr, "%02X:%02X:%02X:%02X:%02X:%02X\0",
 			gd->bd->bi_enetaddr[0], gd->bd->bi_enetaddr[1],
 			gd->bd->bi_enetaddr[2], gd->bd->bi_enetaddr[3],
@@ -283,6 +300,25 @@
 		setenv(DEFAULT_ETH_ADDR, ethaddr);
 	}
 
+	/* IP-Adress update */
+	{
+		IPaddr_t ipaddr;
+		char *ipstring;
+
+		ipstring = getenv("ipaddr");
+		if (ipstring == 0)
+			ipaddr = string_to_ip("172.25.1.99");
+		else
+			ipaddr = string_to_ip(ipstring);
+		if ((ipaddr & 0xff) != (32 + hcu_get_slot())) {
+			char tmp[22];
+
+			ipaddr = (ipaddr & 0xffffff00) + 32 + hcu_get_slot();
+			ip_to_string (ipaddr, tmp);
+			printf("%s: enforce %s\n",  __FUNCTION__, tmp);
+			setenv("ipaddr", tmp);
+		}
+	}
 #ifdef CFG_ENV_IS_IN_FLASH
 	/* Monitor protection ON by default */
 	(void)flash_protect(FLAG_PROTECT_SET,
@@ -346,6 +382,7 @@
 	return 0;
 }
 
+#if defined(CONFIG_PCI)
 /*************************************************************************
  *  pci_pre_init
  *
@@ -358,7 +395,6 @@
  *	certain pre-initialization actions.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI)
 int pci_pre_init(struct pci_controller *hose)
 {
 	unsigned long addr;
@@ -411,7 +447,6 @@
 
 	return 1;
 }
-#endif	/* defined(CONFIG_PCI) */
 
 /*************************************************************************
  *  pci_target_init
@@ -421,7 +456,6 @@
  *	may not be sufficient for a given board.
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT)
 void pci_target_init(struct pci_controller *hose)
 {
 	/*-------------------------------------------------------------+
@@ -478,13 +512,11 @@
 
 	pci_write_config_dword(0, PCI_BRDGOPT2, 0x00000101);
 }
-#endif	/* defined(CONFIG_PCI) && defined(CFG_PCI_TARGET_INIT) */
 
 /*************************************************************************
  *  pci_master_init
  *
  ************************************************************************/
-#if defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT)
 void pci_master_init(struct pci_controller *hose)
 {
 	unsigned short temp_short;
@@ -499,8 +531,6 @@
 			      temp_short | PCI_COMMAND_MASTER |
 			      PCI_COMMAND_MEMORY);
 }
-#endif
-/* defined(CONFIG_PCI) && defined(CFG_PCI_MASTER_INIT) */
 
 /*************************************************************************
  *  is_pci_host
@@ -517,9 +547,8 @@
  *
  *
  ************************************************************************/
-#if defined(CONFIG_PCI)
 int is_pci_host(struct pci_controller *hose)
 {
 	return 1;
 }
-#endif				/* defined(CONFIG_PCI) */
+#endif	 /* defined(CONFIG_PCI) */
diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c
index 4039195..9ee9ab5 100644
--- a/board/netstal/hcu5/sdram.c
+++ b/board/netstal/hcu5/sdram.c
@@ -36,7 +36,7 @@
 #include <asm/mmu.h>
 #include <ppc440.h>
 
-void sysLedSet(u32 value);
+void hcu_led_set(u32 value);
 void dcbz_area(u32 start_address, u32 num_bytes);
 void dflush(void);
 
@@ -70,7 +70,6 @@
 
 void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value);
 
-#ifdef CONFIG_ADD_RAM_INFO
 void board_add_ram_info(int use_default)
 {
 	PPC440_SYS_INFO board_cfg;
@@ -99,7 +98,6 @@
 	val = DDR0_03_CASLAT_DECODE(val);
 	printf(", CL%d)", val);
 }
-#endif
 
 /*--------------------------------------------------------------------
  * wait_for_dlllock.
@@ -138,7 +136,7 @@
 void sdram_panic(const char *reason)
 {
 	printf("\n%s: reason %s",  __FUNCTION__,  reason);
-	sysLedSet(0xff);
+	hcu_led_set(0xff);
 	while (1) {
 	}
 	/* Never return */
@@ -197,6 +195,13 @@
 	mfsdram(DDR0_00, val);
 	mtsdram(DDR0_00, val | DDR0_00_INT_ACK_ALL);
 
+	/*
+	 * Clear possible errors
+	 * If not done, then we could get an interrupt later on when
+	 * exceptions are enabled.
+	 */
+	mtspr(mcsr, mfspr(mcsr));
+
 	/* Set 'int_mask' parameter to functionnal value */
 	mfsdram(DDR0_01, val);
 	mtsdram(DDR0_01, ((val &~ DDR0_01_INT_MASK_MASK) |
@@ -244,7 +249,6 @@
 		sdram_panic(INVALID_HW_CONFIG);
 		break;
 	}
-	dram_size -= 16 * 1024 * 1024;
 	mtsdram(DDR0_07, 0x00090100);
 	/*
 	 * TCPD=200 cycles of clock input is required to lock the DLL.
@@ -283,6 +287,7 @@
 	/*
 	 * Program tlb entries for this size (dynamic)
 	 */
+	remove_tlb(CFG_SDRAM_BASE, 256 << 20);
 	program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 
 	/*
@@ -291,6 +296,8 @@
 	 */
 	program_tlb(0, CFG_DDR_CACHED_ADDR, dram_size, 0);
 
+	/* Diminish RAM to initialize */
+	dram_size = dram_size - 32 ;
 #ifdef CONFIG_DDR_ECC
 	/*
 	 * If ECC is enabled, initialize the parity bits.
diff --git a/board/sbc8349/sbc8349.c b/board/sbc8349/sbc8349.c
index 4cd447e..86166ea 100644
--- a/board/sbc8349/sbc8349.c
+++ b/board/sbc8349/sbc8349.c
@@ -64,8 +64,6 @@
 	if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
 		return -1;
 
-	puts("Initializing\n");
-
 	/* DDR SDRAM - Main SODIMM */
 	im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
 #if defined(CONFIG_SPD_EEPROM)
@@ -84,7 +82,6 @@
 	 */
 	ddr_enable_ecc(msize * 1024 * 1024);
 #endif
-	puts("   DDR RAM: ");
 	/* return total bus SDRAM size(bytes)  -- DDR */
 	return (msize * 1024 * 1024);
 }
@@ -130,7 +127,7 @@
 #if defined(CONFIG_DDR_2T_TIMING)
 		| SDRAM_CFG_2T_EN
 #endif
-		| 2 << SDRAM_CFG_SDRAM_TYPE_SHIFT;
+		| SDRAM_CFG_SDRAM_TYPE_DDR1;
 #if defined (CONFIG_DDR_32BIT)
 	/* for 32-bit mode burst length is 8 */
 	im->ddr.sdram_cfg |= (SDRAM_CFG_32_BE | SDRAM_CFG_8_BE);
diff --git a/board/tqm834x/tqm834x.c b/board/tqm834x/tqm834x.c
index 9c35e22..7d0b055 100644
--- a/board/tqm834x/tqm834x.c
+++ b/board/tqm834x/tqm834x.c
@@ -114,7 +114,7 @@
 	/* enable DDR controller */
 	im->ddr.sdram_cfg = (SDRAM_CFG_MEM_EN |
 		SDRAM_CFG_SREN |
-		SDRAM_CFG_SDRAM_TYPE_DDR);
+		SDRAM_CFG_SDRAM_TYPE_DDR1);
 	SYNC;
 
 	/* size detection */
@@ -388,7 +388,7 @@
 	/* don't enable DDR controller yet */
 	im->ddr.sdram_cfg =
 		SDRAM_CFG_SREN |
-		SDRAM_CFG_SDRAM_TYPE_DDR;
+		SDRAM_CFG_SDRAM_TYPE_DDR1;
 	SYNC;
 
 	/* Set SDRAM mode */
diff --git a/cpu/mpc83xx/cpu.c b/cpu/mpc83xx/cpu.c
index adf8083..e634f0a 100644
--- a/cpu/mpc83xx/cpu.c
+++ b/cpu/mpc83xx/cpu.c
@@ -35,12 +35,10 @@
 #include <ft_build.h>
 #elif defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
-
 int checkcpu(void)
 {
 	volatile immap_t *immr;
@@ -333,9 +331,7 @@
  */
 static int fdt_set_eth0(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
-	/*
-	 * Fix it up if it exists, don't create it if it doesn't exist.
-	 */
+	/* Fix it up if it exists, don't create it if it doesn't exist */
 	if (fdt_get_property(blob, nodeoffset, name, 0)) {
 		return fdt_setprop(blob, nodeoffset, name, bd->bi_enetaddr, 6);
 	}
@@ -345,9 +341,7 @@
 /* second onboard ethernet port */
 static int fdt_set_eth1(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
-	/*
-	 * Fix it up if it exists, don't create it if it doesn't exist.
-	 */
+	/* Fix it up if it exists, don't create it if it doesn't exist */
 	if (fdt_get_property(blob, nodeoffset, name, 0)) {
 		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet1addr, 6);
 	}
@@ -358,9 +352,7 @@
 /* third onboard ethernet port */
 static int fdt_set_eth2(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
-	/*
-	 * Fix it up if it exists, don't create it if it doesn't exist.
-	 */
+	/* Fix it up if it exists, don't create it if it doesn't exist */
 	if (fdt_get_property(blob, nodeoffset, name, 0)) {
 		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet2addr, 6);
 	}
@@ -371,9 +363,7 @@
 /* fourth onboard ethernet port */
 static int fdt_set_eth3(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
-	/*
-	 * Fix it up if it exists, don't create it if it doesn't exist.
-	 */
+	/* Fix it up if it exists, don't create it if it doesn't exist */
 	if (fdt_get_property(blob, nodeoffset, name, 0)) {
 		return fdt_setprop(blob, nodeoffset, name, bd->bi_enet3addr, 6);
 	}
@@ -384,9 +374,7 @@
 static int fdt_set_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
 	u32  tmp;
-	/*
-	 * Create or update the property.
-	 */
+	/* Create or update the property */
 	tmp = cpu_to_be32(bd->bi_busfreq);
 	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 }
@@ -394,14 +382,38 @@
 static int fdt_set_tbfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
 {
 	u32  tmp;
-	/*
-	 * Create or update the property.
-	 */
+	/* Create or update the property */
 	tmp = cpu_to_be32(OF_TBCLK);
 	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
 }
 
 
+static int fdt_set_clockfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+	u32  tmp;
+	/* Create or update the property */
+	tmp = cpu_to_be32(gd->core_clk);
+	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+#ifdef CONFIG_QE
+static int fdt_set_qe_busfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+	u32  tmp;
+	/* Create or update the property */
+	tmp = cpu_to_be32(gd->qe_clk);
+	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+
+static int fdt_set_qe_brgfreq(void *blob, int nodeoffset, const char *name, bd_t *bd)
+{
+	u32  tmp;
+	/* Create or update the property */
+	tmp = cpu_to_be32(gd->brg_clk);
+	return fdt_setprop(blob, nodeoffset, name, &tmp, sizeof(tmp));
+}
+#endif
+
 /*
  * Fixups to the fdt.
  */
@@ -420,6 +432,10 @@
 	},
 	{	"/cpus/" OF_CPU,
 		"clock-frequency",
+		fdt_set_clockfreq
+	},
+	{	"/" OF_SOC,
+		"bus-frequency",
 		fdt_set_busfreq
 	},
 	{	"/" OF_SOC "/serial@4500",
@@ -450,6 +466,15 @@
 		fdt_set_eth1
 	},
 #endif
+#ifdef CONFIG_QE
+	{	"/" OF_QE,
+		"brg-frequency",
+		fdt_set_qe_brgfreq
+	},
+	{	"/" OF_QE,
+		"bus-frequency",
+		fdt_set_qe_busfreq
+	},
 #ifdef CONFIG_UEC_ETH1
 #if CFG_UEC1_UCC_NUM == 0  /* UCC1 */
 	{	"/" OF_QE "/ucc@2000",
@@ -481,7 +506,7 @@
 		"local-mac-address",
 		fdt_set_eth1
 	},
-#elif CFG_UEC1_UCC_NUM == 3  /* UCC4 */
+#elif CFG_UEC2_UCC_NUM == 3  /* UCC4 */
 	{	"/" OF_QE "/ucc@3200",
 		"mac-address",
 		fdt_set_eth1
@@ -492,14 +517,16 @@
 	},
 #endif
 #endif /* CONFIG_UEC_ETH2 */
+#endif /* CONFIG_QE */
 };
 
 void
 ft_cpu_setup(void *blob, bd_t *bd)
 {
-	int  nodeoffset;
-	int  err;
-	int  j;
+	int nodeoffset;
+	int err;
+	int j;
+	int tmp[2];
 
 	for (j = 0; j < (sizeof(fixup_props) / sizeof(fixup_props[0])); j++) {
 		nodeoffset = fdt_find_node_by_path(blob, fixup_props[j].node);
@@ -508,15 +535,29 @@
 						    fixup_props[j].prop, bd);
 			if (err < 0)
 				debug("Problem setting %s = %s: %s\n",
-					fixup_props[j].node,
-					fixup_props[j].prop,
-					fdt_strerror(err));
+				      fixup_props[j].node, fixup_props[j].prop,
+				      fdt_strerror(err));
 		} else {
 			debug("Couldn't find %s: %s\n",
-				fixup_props[j].node,
-				fdt_strerror(nodeoffset));
+			      fixup_props[j].node, fdt_strerror(nodeoffset));
 		}
 	}
+
+	/* update, or add and update /memory node */
+	nodeoffset = fdt_find_node_by_path(blob, "/memory");
+	if (nodeoffset < 0) {
+		nodeoffset = fdt_add_subnode(blob, 0, "memory");
+		if (nodeoffset < 0)
+			debug("failed to add /memory node: %s\n",
+			      fdt_strerror(nodeoffset));
+	}
+	if (nodeoffset >= 0) {
+		fdt_setprop(blob, nodeoffset, "device_type",
+			    "memory", sizeof("memory"));
+		tmp[0] = cpu_to_be32(bd->bi_memstart);
+		tmp[1] = cpu_to_be32(bd->bi_memsize);
+		fdt_setprop(blob, nodeoffset, "reg", tmp, sizeof(tmp));
+	}
 }
 #elif defined(CONFIG_OF_FLAT_TREE)
 void
diff --git a/cpu/mpc83xx/pci.c b/cpu/mpc83xx/pci.c
index 2298218..5675afe 100644
--- a/cpu/mpc83xx/pci.c
+++ b/cpu/mpc83xx/pci.c
@@ -28,7 +28,6 @@
 
 #if defined(CONFIG_OF_LIBFDT)
 #include <libfdt.h>
-#include <libfdt_env.h>
 #elif defined(CONFIG_OF_FLAT_TREE)
 #include <ft_build.h>
 #endif
@@ -184,7 +183,12 @@
 	if (nodeoffset >= 0) {
 		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
 		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
 	}
 
 	if (pci_num_buses < 2)
@@ -194,7 +198,12 @@
 	if (nodeoffset >= 0) {
 		tmp[0] = cpu_to_be32(pci_hose[0].first_busno);
 		tmp[1] = cpu_to_be32(pci_hose[0].last_busno);
-		err = fdt_setprop(blob, nodeoffset, "bus-range", tmp, sizeof(tmp));
+		err = fdt_setprop(blob, nodeoffset, "bus-range",
+				  tmp, sizeof(tmp));
+
+		tmp[0] = cpu_to_be32(gd->pci_clk);
+		err = fdt_setprop(blob, nodeoffset, "clock-frequency",
+				  tmp, sizeof(tmp[0]));
 	}
 }
 #elif CONFIG_OF_FLAT_TREE
diff --git a/cpu/mpc83xx/spd_sdram.c b/cpu/mpc83xx/spd_sdram.c
index 54f0c83..ee2d038 100644
--- a/cpu/mpc83xx/spd_sdram.c
+++ b/cpu/mpc83xx/spd_sdram.c
@@ -34,6 +34,30 @@
 #include <asm/mmu.h>
 #include <spd_sdram.h>
 
+void board_add_ram_info(int use_default)
+{
+	volatile immap_t *immap = (immap_t *) CFG_IMMR;
+	volatile ddr83xx_t *ddr = &immap->ddr;
+
+	printf(" (DDR%d", ((ddr->sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK)
+			   >> SDRAM_CFG_SDRAM_TYPE_SHIFT) - 1);
+
+	if (ddr->sdram_cfg & SDRAM_CFG_32_BE)
+		puts(", 32-bit");
+	else
+		puts(", 64-bit");
+
+	if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
+		puts(", ECC on)");
+	else
+		puts(", ECC off)");
+
+#if defined(CFG_LB_SDRAM) && defined(CFG_LBC_SDRAM_SIZE)
+	puts("\nSDRAM: ");
+	print_size (CFG_LBC_SDRAM_SIZE * 1024 * 1024, " (local bus)");
+#endif
+}
+
 #ifdef CONFIG_SPD_EEPROM
 
 DECLARE_GLOBAL_DATA_PTR;
@@ -109,7 +133,7 @@
 	unsigned int n_ranks;
 	unsigned int odt_rd_cfg, odt_wr_cfg;
 	unsigned char twr_clk, twtr_clk;
-	unsigned char sdram_type;
+	unsigned int sdram_type;
 	unsigned int memsize;
 	unsigned int law_size;
 	unsigned char caslat, caslat_ctrl;
@@ -137,7 +161,7 @@
 #endif
 	/* Check the memory type */
 	if (spd.mem_type != SPD_MEMTYPE_DDR && spd.mem_type != SPD_MEMTYPE_DDR2) {
-		printf("DDR: Module mem type is %02X\n", spd.mem_type);
+		debug("DDR: Module mem type is %02X\n", spd.mem_type);
 		return 0;
 	}
 
@@ -578,17 +602,17 @@
 			burstlen = 0x03; /* 32 bit data bus, burst len is 8 */
 		else
 			burstlen = 0x02; /* 32 bit data bus, burst len is 4 */
-		printf("\n   DDR DIMM: data bus width is 32 bit");
+		debug("\n   DDR DIMM: data bus width is 32 bit");
 	} else {
 		burstlen = 0x02; /* Others act as 64 bit bus, burst len is 4 */
-		printf("\n   DDR DIMM: data bus width is 64 bit");
+		debug("\n   DDR DIMM: data bus width is 64 bit");
 	}
 
 	/* Is this an ECC DDR chip? */
 	if (spd.config == 0x02)
-		printf(" with ECC\n");
+		debug(" with ECC\n");
 	else
-		printf(" without ECC\n");
+		debug(" without ECC\n");
 
 	/* Burst length is always 4 for 64 bit data bus, 8 for 32 bit data bus,
 	   Burst type is sequential
@@ -718,26 +742,26 @@
 	 * sdram_cfg[13] = 0 (8_BE =0, 4-beat bursts)
 	 */
 	if (spd.mem_type == SPD_MEMTYPE_DDR)
-		sdram_type = 2;
+		sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR1;
 	else
-		sdram_type = 3;
+		sdram_type = SDRAM_CFG_SDRAM_TYPE_DDR2;
 
 	sdram_cfg = (0
-		     | (1 << 31)			/* DDR enable */
-		     | (1 << 30)			/* Self refresh */
-		     | (sdram_type << 24)		/* SDRAM type */
+		     | SDRAM_CFG_MEM_EN		/* DDR enable */
+		     | SDRAM_CFG_SREN		/* Self refresh */
+		     | sdram_type		/* SDRAM type */
 		     );
 
 	/* sdram_cfg[3] = RD_EN - registered DIMM enable */
 	if (spd.mod_attr & 0x02)
-		sdram_cfg |= 0x10000000;
+		sdram_cfg |= SDRAM_CFG_RD_EN;
 
 	/* The DIMM is 32bit width */
 	if (spd.dataw_lsb == 0x20) {
 		if (spd.mem_type == SPD_MEMTYPE_DDR)
-			sdram_cfg |= 0x000C0000;
+			sdram_cfg |= SDRAM_CFG_32_BE | SDRAM_CFG_8_BE;
 		if (spd.mem_type == SPD_MEMTYPE_DDR2)
-			sdram_cfg |= 0x00080000;
+			sdram_cfg |= SDRAM_CFG_32_BE;
 	}
 
 	ddrc_ecc_enable = 0;
@@ -758,7 +782,7 @@
 	debug("DDR:err_disable=0x%08x\n", ddr->err_disable);
 	debug("DDR:err_sbe=0x%08x\n", ddr->err_sbe);
 #endif
-	printf("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
+	debug("   DDRC ECC mode: %s\n", ddrc_ecc_enable ? "ON":"OFF");
 
 #if defined(CONFIG_DDR_2T_TIMING)
 	/*
diff --git a/cpu/mpc83xx/speed.c b/cpu/mpc83xx/speed.c
index bf30616..cba57fa 100644
--- a/cpu/mpc83xx/speed.c
+++ b/cpu/mpc83xx/speed.c
@@ -351,6 +351,7 @@
 	gd->qe_clk = qe_clk;
 	gd->brg_clk = brg_clk;
 #endif
+	gd->pci_clk = pci_sync_in;
 	gd->cpu_clk = gd->core_clk;
 	gd->bus_clk = gd->csb_clk;
 	return 0;
diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c
index 18b90ba..67ba5bd 100644
--- a/cpu/ppc4xx/44x_spd_ddr2.c
+++ b/cpu/ppc4xx/44x_spd_ddr2.c
@@ -621,7 +621,6 @@
 	}
 }
 
-#ifdef CONFIG_ADD_RAM_INFO
 void board_add_ram_info(int use_default)
 {
 	PPC440_SYS_INFO board_cfg;
@@ -642,7 +641,6 @@
 	val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 	printf(", CL%d)", val);
 }
-#endif
 
 /*------------------------------------------------------------------
  * For the memory DIMMs installed, this routine verifies that they
diff --git a/drivers/pci.c b/drivers/pci.c
index 4158919..50ca6b0 100644
--- a/drivers/pci.c
+++ b/drivers/pci.c
@@ -82,8 +82,10 @@
 {									\
 	u32 val32;							\
 									\
-	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0)\
+	if (pci_hose_read_config_dword(hose, dev, offset & 0xfc, &val32) < 0) {	\
+		*val = -1;						\
 		return -1;						\
+	}								\
 									\
 	*val = (val32 >> ((offset & (int)off_mask) * 8));		\
 									\
diff --git a/include/common.h b/include/common.h
index 27a660a..9a5a0ab 100644
--- a/include/common.h
+++ b/include/common.h
@@ -434,6 +434,13 @@
 void	upmconfig     (unsigned int, unsigned int *, unsigned int);
 ulong	get_tbclk     (void);
 void	reset_cpu     (ulong addr);
+#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
+void ft_cpu_setup(void *blob, bd_t *bd);
+#ifdef CONFIG_PCI
+void ft_pci_setup(void *blob, bd_t *bd);
+#endif
+#endif
+
 
 /* $(CPU)/serial.c */
 int	serial_init   (void);
diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h
index 3775037..36b0f16 100644
--- a/include/configs/MPC8313ERDB.h
+++ b/include/configs/MPC8313ERDB.h
@@ -113,12 +113,12 @@
 				/* 0x03200064 */
 #if defined(CONFIG_DDR_2T_TIMING)
 #define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
-				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_2T_EN \
 				| SDRAM_CFG_DBW_32 )
 #else
 #define CFG_SDRAM_CFG		( SDRAM_CFG_SREN \
-				| 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
+				| SDRAM_CFG_SDRAM_TYPE_DDR2 \
 				| SDRAM_CFG_32_BE )
 				/* 0x43080000 */
 #endif
@@ -228,7 +228,7 @@
 #define CFG_LBLAWAR3_PRELIM	0x8000000E	/* 32KB  */
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
 /* maximum size of the flat tree (8K) */
diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h
index f62ca2c4..efc3172 100644
--- a/include/configs/MPC832XEMDS.h
+++ b/include/configs/MPC832XEMDS.h
@@ -30,6 +30,8 @@
 #define CONFIG_MPC83XX		1	/* MPC83xx family */
 #define CONFIG_MPC832X		1	/* MPC832x CPU specific */
 #define CONFIG_MPC832XEMDS	1	/* MPC832XEMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM	/* QOC3 ATM card */
 
 /*
  * System Clock Setup
@@ -87,6 +89,7 @@
 #define CFG_SICRL		0x00000000
 
 #define CONFIG_BOARD_EARLY_INIT_F	/* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /*
  * IMMR new address
@@ -315,7 +318,7 @@
 #endif
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
 /* maximum size of the flat tree (8K) */
diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h
index 48616c0..c1f1c74 100644
--- a/include/configs/MPC8349EMDS.h
+++ b/include/configs/MPC8349EMDS.h
@@ -339,7 +339,7 @@
 #endif
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP	1
 
 /* maximum size of the flat tree (8K) */
diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h
index c5d0362..3311d5c 100644
--- a/include/configs/MPC8349ITX.h
+++ b/include/configs/MPC8349ITX.h
@@ -296,7 +296,7 @@
 #define CFG_NS16550_COM2	(CFG_IMMR + 0x4600)
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE
+#define CONFIG_OF_LIBFDT	1
 #define CONFIG_OF_BOARD_SETUP
 
 /* maximum size of the flat tree (8K) */
diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h
index 4b32a14..094b66e 100644
--- a/include/configs/MPC8360EMDS.h
+++ b/include/configs/MPC8360EMDS.h
@@ -32,6 +32,8 @@
 #define CONFIG_MPC83XX		1 /* MPC83XX family */
 #define CONFIG_MPC8360		1 /* MPC8360 CPU specific */
 #define CONFIG_MPC8360EMDS	1 /* MPC8360EMDS board specific */
+#undef CONFIG_PQ_MDS_PIB /* POWERQUICC MDS Platform IO Board */
+#undef CONFIG_PQ_MDS_PIB_ATM /* QOC3 ATM card */
 
 /*
  * System Clock Setup
@@ -88,6 +90,7 @@
 #define CFG_SICRL		0x40000000
 
 #define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */
+#define CONFIG_BOARD_EARLY_INIT_R
 
 /*
  * IMMR new address
@@ -309,13 +312,13 @@
 /*
  * CS4 on Local Bus, to PIB
  */
-#define CFG_BR4_PRELIM	0xf8008801 /* CS4 base address at 0xf8008000 */
+#define CFG_BR4_PRELIM	0xf8010801 /* CS4 base address at 0xf8010000 */
 #define CFG_OR4_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 
 /*
  * CS5 on Local Bus, to PIB
  */
-#define CFG_BR5_PRELIM	0xf8010801 /* CS5 base address at 0xf8010000 */
+#define CFG_BR5_PRELIM	0xf8008801 /* CS5 base address at 0xf8008000 */
 #define CFG_OR5_PRELIM	0xffffe9f7 /* size 32KB, port size 8bit, GPCM */
 
 /*
diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h
index a330c42..2f23c50 100644
--- a/include/configs/TQM85xx.h
+++ b/include/configs/TQM85xx.h
@@ -94,7 +94,6 @@
  */
 #define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory	*/
 #define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE
-#define CONFIG_ADD_RAM_INFO	1		/* print additional info*/
 
 #if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560)
 /* TQM8540 & 8560 need DLL-override */
diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h
index d0bf251..f95d78e 100644
--- a/include/configs/hcu5.h
+++ b/include/configs/hcu5.h
@@ -43,7 +43,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1		/* Call board_early_init_f */
 #define CONFIG_MISC_INIT_R	1		/* Call misc_init_r	*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/katmai.h b/include/configs/katmai.h
index 110ad44..b6d0f51 100644
--- a/include/configs/katmai.h
+++ b/include/configs/katmai.h
@@ -42,7 +42,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 
 /*-----------------------------------------------------------------------
diff --git a/include/configs/luan.h b/include/configs/luan.h
index 26dbec9..a09dd74 100644
--- a/include/configs/luan.h
+++ b/include/configs/luan.h
@@ -39,7 +39,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R	1	/* call misc_init_r()		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h
index 604b7d1..7116c49 100644
--- a/include/configs/lwmon5.h
+++ b/include/configs/lwmon5.h
@@ -35,7 +35,6 @@
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h
index 8ae38cb..bec442d 100644
--- a/include/configs/p3mx.h
+++ b/include/configs/p3mx.h
@@ -60,7 +60,6 @@
 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1     /* Call board_early_init_f	*/
 #define CONFIG_MISC_INIT_R      1	/* Call misc_init_r()		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 
 /*-----------------------------------------------------------------------
  * Base addresses -- Note these are effective addresses where the
diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h
index 3f75a44..824a812 100644
--- a/include/configs/sequoia.h
+++ b/include/configs/sequoia.h
@@ -343,6 +343,11 @@
 #define CONFIG_CMD_USB
 #endif
 
+#ifndef CONFIG_RAINIER
+#define CFG_POST_FPU_ON		CFG_POST_FPU
+#else
+#define CFG_POST_FPU_ON		0
+#endif
 
 /* POST support */
 #define CONFIG_POST		(CFG_POST_MEMORY   | \
@@ -350,7 +355,7 @@
 				 CFG_POST_UART	   | \
 				 CFG_POST_I2C	   | \
 				 CFG_POST_CACHE	   | \
-				 CFG_POST_FPU	   | \
+				 CFG_POST_FPU_ON   | \
 				 CFG_POST_ETHER	   | \
 				 CFG_POST_SPR)
 
diff --git a/include/configs/yucca.h b/include/configs/yucca.h
index 9c536fd..906f046 100644
--- a/include/configs/yucca.h
+++ b/include/configs/yucca.h
@@ -46,7 +46,6 @@
 #define EXTCLK_83		83333333
 
 #define	CONFIG_MISC_INIT_F	1	/* Use misc_init_f()		*/
-#define CONFIG_ADD_RAM_INFO	1	/* Print additional info	*/
 #undef  CONFIG_SHOW_BOOT_PROGRESS
 #undef  CONFIG_STRESS
 
diff --git a/include/mpc83xx.h b/include/mpc83xx.h
index 829dbf9..4d32c6a 100644
--- a/include/mpc83xx.h
+++ b/include/mpc83xx.h
@@ -705,8 +705,9 @@
 #define SDRAM_CFG_SREN			0x40000000
 #define SDRAM_CFG_ECC_EN		0x20000000
 #define SDRAM_CFG_RD_EN			0x10000000
-#define SDRAM_CFG_SDRAM_TYPE		0x03000000
-#define SDRAM_CFG_SDRAM_TYPE_DDR	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR1	0x02000000
+#define SDRAM_CFG_SDRAM_TYPE_DDR2	0x03000000
+#define SDRAM_CFG_SDRAM_TYPE_MASK	0x07000000
 #define SDRAM_CFG_SDRAM_TYPE_SHIFT	24
 #define SDRAM_CFG_DYN_PWR		0x00200000
 #define SDRAM_CFG_32_BE			0x00080000
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index c87d46c..9aa67f9 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -209,9 +209,12 @@
 
 /***********************************************************************/
 
-#ifdef CONFIG_ADD_RAM_INFO
-void board_add_ram_info(int);
-#endif
+void __board_add_ram_info(int use_default)
+{
+	/* please define platform specific board_add_ram_info() */
+}
+void board_add_ram_info(int) __attribute__((weak, alias("__board_add_ram_info")));
+
 
 static int init_func_ram (void)
 {
@@ -224,9 +227,7 @@
 
 	if ((gd->ram_size = initdram (board_type)) > 0) {
 		print_size (gd->ram_size, "");
-#ifdef CONFIG_ADD_RAM_INFO
 		board_add_ram_info(0);
-#endif
 		putc('\n');
 		return (0);
 	}