)]}'
{
  "commit": "97405d843ece2a53e67b801e02ee42005d26e172",
  "tree": "13c4b866c44ebbbb7033f7490921fcb6dffa6004",
  "parents": [
    "7f36c88f64ee1affd4db78b2c2f4a616abceb84c"
  ],
  "author": {
    "name": "Lokesh Vutla",
    "email": "lokeshvutla@ti.com",
    "time": "Thu May 30 03:19:38 2013 +0000"
  },
  "committer": {
    "name": "Tom Rini",
    "email": "trini@ti.com",
    "time": "Mon Jun 10 08:43:10 2013 -0400"
  },
  "message": "ARM: DRA7xx: clocks: Update PLL values\n\nUpdate PLL values.\nSYS_CLKSEL value for 20MHz is changed to 2. In other platforms\nSYS_CLKSEL value 2 represents reserved. But in sys_clk array\nind 1 is used for 13Mhz. Since other platforms are not using\n13Mhz, reusing index 1 for 20MHz.\n\nSigned-off-by: Lokesh Vutla \u003clokeshvutla@ti.com\u003e\nSigned-off-by: Sricharan R \u003cr.sricharan@ti.com\u003e\n",
  "tree_diff": [
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      "old_path": "arch/arm/cpu/armv7/omap-common/clocks-common.c",
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      "new_mode": 33188,
      "new_path": "arch/arm/cpu/armv7/omap-common/clocks-common.c"
    },
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      "new_path": "include/configs/dra7xx_evm.h"
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}