)]}'
{
  "commit": "9acde129cc3f9c1b3bc11a821480dd446774d618",
  "tree": "408342b2cea52b5b979c0ca86bb5c4af95027076",
  "parents": [
    "27c38689d0cfde0e444239345f97b5eecc9f4067"
  ],
  "author": {
    "name": "Andre Schwarz",
    "email": "andre.schwarz@matrix-vision.de",
    "time": "Tue Apr 29 19:18:32 2008 +0200"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Sat May 03 23:27:04 2008 +0200"
  },
  "message": "TSEC: add config options for VSC8601 RGMII PHY\n\nThe Vitesse VSC8601 RGMII PHY has internal delay for both Rx\nand Tx clock lines. They are configured using 2 bits in extended\nregister 0x17.\nTherefore CFG_VSC8601_SKEW_TX and CFG_VSC8601_SKEW_RX have\nbeen introduced with valid values 0-3 giving 0.0, 1.4,1.7 and 2.0ns delay.\n\nSigned-off-by: Andre Schwarz \u003candre.schwarz@matrix-vision.de\u003e\nAcked-by: Andy Fleming \u003cafleming@freescale.com\u003e\nAcked-by: Ben Warren \u003cbiggerbadderben@gmail.com\u003e\n--\n\n drivers/net/tsec.c |    6 ++++++\n drivers/net/tsec.h |    3 +++\n 2 files changed, 9 insertions(+), 0 deletions(-)\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "9d22aa38be5ce9f7a2ddae06af3c1542a1d30167",
      "old_mode": 33188,
      "old_path": "drivers/net/tsec.c",
      "new_id": "f86bfd7eeab252fef36c1fc1b950b0df57b595a2",
      "new_mode": 33188,
      "new_path": "drivers/net/tsec.c"
    },
    {
      "type": "modify",
      "old_id": "cfa7d1aad77761e431c3293d926c3a03d231a40f",
      "old_mode": 33188,
      "old_path": "drivers/net/tsec.h",
      "new_id": "597ea1d3c7fd8fff8466a143ab717fb1ac15f5c2",
      "new_mode": 33188,
      "new_path": "drivers/net/tsec.h"
    }
  ]
}