)]}'
{
  "commit": "a1d558a20f1eaeae9927abc4e0978725d33bae53",
  "tree": "3af577ebb7be24efd3c23d7a8559512d2f9bfa70",
  "parents": [
    "eb5394120643922626f18e5fe7b0b3dc0ed43b9a"
  ],
  "author": {
    "name": "York Sun",
    "email": "yorksun@freescale.com",
    "time": "Mon Oct 08 07:44:26 2012 +0000"
  },
  "committer": {
    "name": "Andy Fleming",
    "email": "afleming@freescale.com",
    "time": "Mon Oct 22 14:31:29 2012 -0500"
  },
  "message": "powerpc/mpc85xx: Add workaround for DDR erratum A004934\n\nAfter DDR controller is enabled, it performs a calibration for the\ntransmit data vs DQS paths. During this calibration, the DDR controller\nmay make an inaccurate calculation, resulting in a non-optimal tap point.\n\nSigned-off-by: York Sun \u003cyorksun@freescale.com\u003e\nSigned-off-by: Andy Fleming \u003cafleming@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ce5924bc1327f9427c37e79b86bb07feb44c6dc1",
      "old_mode": 33188,
      "old_path": "arch/powerpc/cpu/mpc85xx/cmd_errata.c",
      "new_id": "2be192d578f5ae46818451c459b23203b974d38a",
      "new_mode": 33188,
      "new_path": "arch/powerpc/cpu/mpc85xx/cmd_errata.c"
    },
    {
      "type": "modify",
      "old_id": "8bed5fe925b8130ecc1d14aba850881c8242fa02",
      "old_mode": 33188,
      "old_path": "arch/powerpc/cpu/mpc85xx/ddr-gen3.c",
      "new_id": "21840bfc2a8abecd4aa77785eda4badbd358d36d",
      "new_mode": 33188,
      "new_path": "arch/powerpc/cpu/mpc85xx/ddr-gen3.c"
    },
    {
      "type": "modify",
      "old_id": "ecb156619da30bc5c4e4526a8d5b9f66bab5e136",
      "old_mode": 33188,
      "old_path": "arch/powerpc/include/asm/config_mpc85xx.h",
      "new_id": "92ca2ad74d174f2c8123420fb2de677503286340",
      "new_mode": 33188,
      "new_path": "arch/powerpc/include/asm/config_mpc85xx.h"
    }
  ]
}