)]}'
{
  "commit": "a72dbae2ccd38d2b32f8b814f5a528c88be65bd3",
  "tree": "59d540d16474f386d3600fc5d0f9fdceff21c7da",
  "parents": [
    "258ccd68170b7279ec7d4805c7b914c90374e711"
  ],
  "author": {
    "name": "Peter Tyser",
    "email": "ptyser@xes-inc.com",
    "time": "Thu Oct 28 15:24:59 2010 -0500"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Sun Nov 14 23:45:57 2010 +0100"
  },
  "message": "fsl_pci_init: Make fsl_pci_init_port() PCI/PCIe aware\n\nPreviously fsl_pci_init_port() always assumed that a port was a PCIe\nport and would incorrectly print messages for a PCI port such as the\nfollowing on bootup:\n    PCI1:  32 bit, 33 MHz, sync, host, arbiter\n                Scanning PCI bus 00\n    PCIE1 on bus 00 - 00\n\nThis change corrects the output of fsl_pci_init_port():\n    PCI1:  32 bit, 33 MHz, sync, host, arbiter\n                Scanning PCI bus 00\n    PCI1 on bus 00 - 00\n\nSigned-off-by: Peter Tyser \u003cptyser@xes-inc.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1f021036e5f00040b0a2826664e890d2b92fb78b",
      "old_mode": 33188,
      "old_path": "drivers/pci/fsl_pci_init.c",
      "new_id": "45794dabed3924eaa252a6feb66b4944b89817ec",
      "new_mode": 33188,
      "new_path": "drivers/pci/fsl_pci_init.c"
    }
  ]
}