)]}'
{
  "commit": "a880cf3e0e1c220d780eccd0b101170c4499485d",
  "tree": "5a1d6288e8127ce2de572afff2e8a42e0a4d06a3",
  "parents": [
    "418ec8584343f04048e2cc7ee96b6b29be54ad97"
  ],
  "author": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Sep 17 01:44:00 2009 -0500"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Thu Sep 24 12:05:28 2009 -0500"
  },
  "message": "ppc/p4080: CoreNet platfrom style CCSRBAR setting\n\nOn CoreNet based platforms the CCSRBAR address is split between an high \u0026\nlow register and we no longer shift the address.\n\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\nSigned-off-by: Scott Wood \u003cscottwood@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "7886f868f2ada38c294b76b71c2e47258b79c22e",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/cpu_init_early.c",
      "new_id": "32aa94b612ca0ada037d2dacb890c20e53c31ee6",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/cpu_init_early.c"
    }
  ]
}