)]}'
{
  "commit": "a928a36ff91ba585310491f2d8c08ec2d30bc2b0",
  "tree": "c8e46d7db9d68165341974287f50cab039394fca",
  "parents": [
    "2b26201a2aef0b310b7c04702b0dba5dea493f77"
  ],
  "author": {
    "name": "Marek Vasut",
    "email": "marex@denx.de",
    "time": "Mon Aug 26 17:45:23 2013 +0200"
  },
  "committer": {
    "name": "Jagannadha Sutradharudu Teki",
    "email": "jaganna@xilinx.com",
    "time": "Tue Aug 27 19:39:39 2013 +0530"
  },
  "message": "spi: mxs_spi: Configure chipselect after block reset\n\nThe chipselect must be written into the CTRL0 register after the SSP\nblock is reset, otherwise the block will always use ChipSelect #0.\n\nSigned-off-by: Marek Vasut \u003cmarex@denx.de\u003e\nCc: Fabio Estevam \u003cfabio.estevam@freescale.com\u003e\nCc: Jagannadha Sutradharudu Teki \u003cjagannadh.teki@gmail.com\u003e\nCc: Otavio Salvador \u003cotavio@ossystems.com.br\u003e\nCc: Stefano Babic \u003csbabic@denx.de\u003e\nAcked-by: Stefano Babic \u003csbabic@denx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "3cf7142f5a62d0610fbf938fe74df672d5a5f99b",
      "old_mode": 33188,
      "old_path": "drivers/spi/mxs_spi.c",
      "new_id": "2b9f395a97821568dc12c5e28feaaf42b42ffd50",
      "new_mode": 33188,
      "new_path": "drivers/spi/mxs_spi.c"
    }
  ]
}