)]}' { "commit": "afabb498b749b48ca3ee7e833fe1501e2d6993cb", "tree": "a5e131d0d7f62e41bd9bc1c767452b43b75bf82e", "parents": [ "5e7abce99163a00b8d267cc8045f06b498728288" ], "author": { "name": "Stefan Roese", "email": "sr@denx.de", "time": "Sun Sep 12 06:21:37 2010 +0200" }, "committer": { "name": "Stefan Roese", "email": "sr@denx.de", "time": "Thu Sep 23 09:02:05 2010 +0200" }, "message": "ppc4xx: Big header cleanup part 2, mostly PPC405 related\n\nThis cleanup is done by creating header files for all SoC versions and\nmoving the SoC specific defines into these special headers. This way the\ncommon header ppc405.h and ppc440.h can be cleaned up finally.\n\nAs a part from this cleanup, the GPIO definitions for PPC405EP are\ncorrected. The high and low parts of the registers (for example\nCONFIG_SYS_GPIO0_OSRL vs. CONFIG_SYS_GPIO0_OSRH) have been defined in\nthe wrong order. This patch now fixes this issue by switching these\nxxxH and xxxL values. This brings the GPIO 405EP port in sync with all\nother PPC4xx ports.\n\nSigned-off-by: Stefan Roese \u003csr@denx.de\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "9a11f3bad8dfe304ed694c09d173d7a414cf7ec4", "old_mode": 33188, "old_path": "arch/powerpc/cpu/ppc4xx/4xx_uart.c", "new_id": "5eaeefe8ead24ea6f040dfd5aa81741b8a4def67", "new_mode": 33188, "new_path": "arch/powerpc/cpu/ppc4xx/4xx_uart.c" }, { "type": "modify", "old_id": "677a4b5896619e112bc77d7c1dfa694b7b17536d", "old_mode": 33188, "old_path": "arch/powerpc/cpu/ppc4xx/cpu_init.c", "new_id": "d54b30e26f099b5172a1c2ac589daaf9903835f1", "new_mode": 33188, "new_path": "arch/powerpc/cpu/ppc4xx/cpu_init.c" }, { "type": "modify", "old_id": "1f9f93a696c2d70163ae33f8218842df76c9c78a", "old_mode": 33188, "old_path": "arch/powerpc/cpu/ppc4xx/gpio.c", "new_id": "20f0572203871825d276e58d1dfd3ce4c5b37e3c", "new_mode": 33188, "new_path": "arch/powerpc/cpu/ppc4xx/gpio.c" }, { "type": "modify", "old_id": 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