)]}'
{
  "commit": "b71ea33699bb694964929e2cdced80ef794bde69",
  "tree": "aadaa4c2e5edd0b040c629286fdf16636c736f9d",
  "parents": [
    "509e19cab43ba38311749eba5ceebd806116ce38"
  ],
  "author": {
    "name": "Priyanka Jain",
    "email": "Priyanka.Jain@freescale.com",
    "time": "Thu Mar 03 09:18:56 2011 +0530"
  },
  "committer": {
    "name": "Kumar Gala",
    "email": "galak@kernel.crashing.org",
    "time": "Mon Mar 07 08:49:28 2011 -0600"
  },
  "message": "fsl_esdhc: Correcting esdhc timeout counter calculation\n\n- Timeout counter value is set as DTOCV bits in SYSCTL register\n  For counter value set as timeout,\n  Timeout period \u003d (2^(timeout + 13)) SD Clock cycles\n\n- As per 4.6.2.2 section of SD Card specification v2.00, host should\n  cofigure timeout period value to minimum 0.25 sec.\n\n- Number of SD Clock cycles for 0.25sec should be minimum\n\t(SD Clock/sec * 0.25 sec) SD Clock cycles\n\t\u003d (mmc-\u003etran_speed * 1/4) SD Clock cycles\n\n- Calculating timeout based on\n\t(2^(timeout + 13)) \u003e\u003d  mmc-\u003etran_speed * 1/4\n\tTaking log2 both the sides and rounding up to next power of 2\n\t\u003d\u003e timeout + 13 \u003d log2(mmc-\u003etran_speed/4) + 1\n\nSigned-off-by: Priyanka Jain \u003cPriyanka.Jain@freescale.com\u003e\nSigned-off-by: Andy Fleming \u003cafleming@freescale.com\u003e\nAcked-by: Mingkai Hu \u003cMingkai.Hu@freescale.com\u003e\nTested-by: Stefano Babic \u003csbabic@denx.de\u003e\nSigned-off-by: Kumar Gala \u003cgalak@kernel.crashing.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f3cccbe9bfdc4ed0bbbc8d373af7def8a44af8cf",
      "old_mode": 33188,
      "old_path": "drivers/mmc/fsl_esdhc.c",
      "new_id": "0962ac4476aaef82b51616c08add152330fccb78",
      "new_mode": 33188,
      "new_path": "drivers/mmc/fsl_esdhc.c"
    }
  ]
}