)]}'
{
  "commit": "ce47eb402c5e29a025399dc282246414fc492940",
  "tree": "993313336b71bf495461cc8dd89f8afbb8858c9b",
  "parents": [
    "c0d2f87d6c450128b88e73eea715fa3654f65b6c"
  ],
  "author": {
    "name": "Peter Tyser",
    "email": "ptyser@xes-inc.com",
    "time": "Tue Sep 16 10:04:47 2008 -0500"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Tue Sep 16 11:32:45 2008 -0500"
  },
  "message": "Support for multiple SGMII/TBI interfaces for TSEC ethernet\n\nFix TBI PHY accesses to use the proper offset in CPU register space. The\nprevious code would incorrectly access the TBI PHY by reading/writing to CPU\nregister space at the same location as would be used to access external PHYs.\n\nSigned-off-by: Peter Tyser \u003cptyser@xes-inc.com\u003e\nAcked-by: Andy Fleming \u003cafleming@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f81211adb9820d18f84d4fd6bf2067fd23c9e8d6",
      "old_mode": 33188,
      "old_path": "drivers/net/tsec.c",
      "new_id": "8ab6d07303be19e7d076f0ac6425fa8aea4f6d93",
      "new_mode": 33188,
      "new_path": "drivers/net/tsec.c"
    }
  ]
}