)]}'
{
  "commit": "d111d6382c99fdea08c2312eeeae8786945e189a",
  "tree": "689badef14549bda5ac780242e9e2a6f8047a522",
  "parents": [
    "3db0bef59eab1155801618cef5c481e97553b597"
  ],
  "author": {
    "name": "Haiying Wang",
    "email": "Haiying.Wang@freescale.com",
    "time": "Tue Jun 19 14:18:32 2007 -0400"
  },
  "committer": {
    "name": "Andrew Fleming-AFLEMING",
    "email": "afleming@freescale.com",
    "time": "Tue Aug 14 01:45:51 2007 -0500"
  },
  "message": "Empirically set cpo and clk_adjust for mpc85xx DDR2 support\n\nThis patch is against u-boot-mpc85xx.git of www.denx.com\n\nSetting cpo to 0x9 for frequencies higher than 333MHz is verified on\nboth MPC8548CDS board and MPC8568MDS board, especially for supporting\n533MHz DDR2.\n\nSetting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for\nDDR2 on all current board versions especially ver 1.92 or later to bring\nup.\n\nSigned-off-by: Haiying Wang \u003cHaiying.Wang@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "679f3608f72e40c4766f022bf1822ae27303f7be",
      "old_mode": 33188,
      "old_path": "cpu/mpc85xx/spd_sdram.c",
      "new_id": "5dc223a53e3ff3d82ea55a841c0b8eaceed1acf5",
      "new_mode": 33188,
      "new_path": "cpu/mpc85xx/spd_sdram.c"
    }
  ]
}