)]}'
{
  "commit": "d4c02e6f5d49880123e7f584b88f857ffd874381",
  "tree": "40f22cb79ca2c973ffca60fb077d6b9c3dbe58f2",
  "parents": [
    "9c48a8ea383098a5b217aba91b6d44cefd5cbeeb"
  ],
  "author": {
    "name": "Yoshihiro Shimoda",
    "email": "shimoda.yoshihiro@renesas.com",
    "time": "Wed Feb 25 14:27:24 2009 +0900"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Tue Apr 28 00:18:10 2009 +0200"
  },
  "message": "rtl8169: fix cache coherency problem\n\nFix the problem that cannot access actual data when CPU data cache enabled.\n\nSigned-off-by: Yoshihiro Shimoda \u003cshimoda.yoshihiro@renesas.com\u003e\nTested-by: Nobuhiro Iwamatsu \u003ciwamatsu.nobuhiro@renesas.com\u003e\nAcked-by: Ben Warren \u003cbiggerbadderben@gmail.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f8c14b42873803b7bd3873a9a3e944aa461e9193",
      "old_mode": 33188,
      "old_path": "drivers/net/rtl8169.c",
      "new_id": "83a05b45b9e5b19b47b1a4dd9acf33287a728fec",
      "new_mode": 33188,
      "new_path": "drivers/net/rtl8169.c"
    }
  ]
}