diff --git a/CHANGELOG b/CHANGELOG
index 4c0bd2b..4745c8f 100644
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,22 @@
 Changes since U-Boot 1.0.0:
 ======================================================================
 
+* Minor code cleanup (coding style)
+
+* Patch by Reinhard Meyer, 30 Dec 2003:
+  - cpu/mpc5xxx/fec.c: added CONFIG_PHY_ADDR, added CONFIG_PHY_TYPE,
+  - added CONFIG_PHY_ADDR to include/configs/IceCube.h,
+  - turned debug print of PHY registers into a function (called in two places)
+  - added support for EMK MPC5200 based modules
+
+* Fix MPC8xx PLPRCR_MFD_SHIFT typo
+
+* Add support for TQM866M modules
+
+* Fixes for TQM855M with 4 MB flash (Am29DL163 = _no_ mirror bit flash)
+
+* Fix a few compiler warnings
+
 * Patch by Reinhard Meyer, 28 Dec 2003:
   Add initial support for TOP5200 board
 
diff --git a/MAINTAINERS b/MAINTAINERS
index 29084f6..8752564 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -180,7 +180,8 @@
 
 Reinhard Meyer <r.meyer@emk-elektronik.de>
 
-	TOP860			MPC860
+	TOP860			MPC860T
+	TOP5200			MPC5200
 
 Scott McNutt <smcnutt@artesyncp.com>
 
diff --git a/MAKEALL b/MAKEALL
index 459b54b..1472694 100644
--- a/MAKEALL
+++ b/MAKEALL
@@ -25,7 +25,7 @@
 #########################################################################
 
 LIST_5xxx="	\
-	IceCube_5100	IceCube_5200					\
+	IceCube_5100	IceCube_5200	EVAL5200	\
 "
 
 #########################################################################
diff --git a/Makefile b/Makefile
index 48788af..bb62b0e 100644
--- a/Makefile
+++ b/Makefile
@@ -1,5 +1,5 @@
 #
-# (C) Copyright 2000, 2001, 2002
+# (C) Copyright 2000-2004
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
 # See file CREDITS for list of people who contributed to this
@@ -204,6 +204,7 @@
 MPC5200LITE_config		\
 MPC5200LITE_LOWBOOT_config	\
 MPC5200LITE_LOWBOOT08_config	\
+icecube_5200_DDR_LOWBOOT_config	\
 icecube_5200_DDR_config		\
 IceCube_5200_DDR_config		\
 icecube_5200_config		\
@@ -218,20 +219,26 @@
 		{ echo "TEXT_BASE = 0xFF800000" >board/icecube/config.tmp ; \
 		  echo "... with 8 MB flash only" ; \
 		}
-	@[ -z "$(findstring 5200,$@)" ] || \
-		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
-		  echo "... with MPC5200 processor" ; \
-		}
 	@[ -z "$(findstring DDR,$@)" ] || \
 		{ echo "#define CONFIG_MPC5200_DDR"	>>include/config.h ; \
 		  echo "... DDR memory revision" ; \
 		}
+	@[ -z "$(findstring 5200,$@)" ] || \
+		{ echo "#define CONFIG_MPC5200"		>>include/config.h ; \
+		  echo "... with MPC5200 processor" ; \
+		}
 	@[ -z "$(findstring 5100,$@)" ] || \
 		{ echo "#define CONFIG_MGT5100"		>>include/config.h ; \
 		  echo "... with MGT5100 processor" ; \
 		}
 	@./mkconfig -a IceCube ppc mpc5xxx icecube
 
+MINI5200_config	\
+EVAL5200_config	\
+TOP5200_config:	unconfig
+	@ echo "#define CONFIG_$(@:_config=) 1"	>include/config.h
+	@./mkconfig -a TOP5200 ppc mpc5xxx top5200 emk
+
 #########################################################################
 ## MPC8xx Systems
 #########################################################################
@@ -438,7 +445,7 @@
 # All boards can come with 50 MHz (default), 66MHz, 80MHz or 100 MHz clock,
 # but only 855 and 860 boards may come with FEC
 # and 823 boards may have LCD support
-xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _LCD,,$(subst _config,,$1)))))
+xtract_8xx = $(subst _66MHz,,$(subst _80MHz,,$(subst _100MHz,,$(subst _133MHz,,$(subst _LCD,,$(subst _config,,$1))))))
 
 FPS850L_config		\
 FPS860L_config		\
@@ -476,7 +483,12 @@
 TQM862M_config		\
 TQM862M_66MHz_config	\
 TQM862M_80MHz_config	\
-TQM862M_100MHz_config:	unconfig
+TQM862M_100MHz_config	\
+TQM866M_config		\
+TQM866M_66MHz_config	\
+TQM866M_80MHz_config	\
+TQM866M_100MHz_config	\
+TQM866M_133MHz_config:	unconfig
 	@ >include/config.h
 	@[ -z "$(findstring _66MHz,$@)" ] || \
 		{ echo "#define CONFIG_66MHz"		>>include/config.h ; \
@@ -490,6 +502,10 @@
 		{ echo "#define CONFIG_100MHz"		>>include/config.h ; \
 		  echo "... with 100MHz system clock" ; \
 		}
+	@[ -z "$(findstring _133MHz,$@)" ] || \
+		{ echo "#define CONFIG_133MHz"		>>include/config.h ; \
+		  echo "... with 133MHz system clock" ; \
+		}
 	@[ -z "$(findstring _LCD,$@)" ] || \
 		{ echo "#define CONFIG_LCD"		>>include/config.h ; \
 		  echo "#define CONFIG_NEC_NL6448BC20"	>>include/config.h ; \
diff --git a/README b/README
index e440e0b..2d1a038 100644
--- a/README
+++ b/README
@@ -490,10 +490,10 @@
 		default i/o. Serial console can be forced with
 		environment 'console=serial'.
 
-                When CONFIG_SILENT_CONSOLE is defined, all console
-                messages (by U-Boot and Linux!) can be silenced with
-                the "silent" environment variable. See
-                doc/README.silent for more information.
+		When CONFIG_SILENT_CONSOLE is defined, all console
+		messages (by U-Boot and Linux!) can be silenced with
+		the "silent" environment variable. See
+		doc/README.silent for more information.
 
 - Console Baudrate:
 		CONFIG_BAUDRATE - in bps
@@ -1472,16 +1472,16 @@
 
 - Interrupt support (PPC):
 
-                There are common interrupt_init() and timer_interrupt()
-                for all PPC archs. interrupt_init() calls interrupt_init_cpu()
-                for cpu specific initialization. interrupt_init_cpu()
-                should set decrementer_count to appropriate value. If
-                cpu resets decrementer automatically after interrupt
-                (ppc4xx) it should set decrementer_count to zero.
-                timer_interrupt() calls timer_interrupt_cpu() for cpu
-                specific handling. If board has watchdog / status_led
-                / other_activity_monitor it works automatically from
-                general timer_interrupt().
+		There are common interrupt_init() and timer_interrupt()
+		for all PPC archs. interrupt_init() calls interrupt_init_cpu()
+		for cpu specific initialization. interrupt_init_cpu()
+		should set decrementer_count to appropriate value. If
+		cpu resets decrementer automatically after interrupt
+		(ppc4xx) it should set decrementer_count to zero.
+		timer_interrupt() calls timer_interrupt_cpu() for cpu
+		specific handling. If board has watchdog / status_led
+		/ other_activity_monitor it works automatically from
+		general timer_interrupt().
 
 - General:
 
@@ -1766,7 +1766,7 @@
 
 - CFG_ENV_IS_IN_DATAFLASH:
 
-	Define this if you have a DataFlash memory device which you 
+	Define this if you have a DataFlash memory device which you
 	want to use for the environment.
 
 	- CFG_ENV_OFFSET:
diff --git a/board/bubinga405ep/bubinga405ep.c b/board/bubinga405ep/bubinga405ep.c
index 8694ebe..f73b166 100644
--- a/board/bubinga405ep/bubinga405ep.c
+++ b/board/bubinga405ep/bubinga405ep.c
@@ -79,7 +79,6 @@
 int checkboard (void)
 {
 	unsigned char *s = getenv ("serial#");
-	unsigned char *e;
 
 	puts ("Board: IBM 405EP Eval Board");
 
diff --git a/board/emk/top5200/config.mk b/board/emk/top5200/config.mk
index 14af97a..84131fe 100644
--- a/board/emk/top5200/config.mk
+++ b/board/emk/top5200/config.mk
@@ -2,6 +2,9 @@
 # (C) Copyright 2003
 # Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 #
+# (C) Copyright 2003
+# Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+#
 # See file CREDITS for list of people who contributed to this
 # project.
 #
@@ -24,8 +27,15 @@
 #
 # TOP5200 board, on optional MINI5200 and EVAL5200 boards
 #
+# allowed and functional TEXT_BASE values:
+#
+#   0xff000000		low boot at 0x00000100 (default board setting)
+#   0xfff00000		high boot at 0xfff00100 (board needs modification)
+#	0x00100000		RAM load and test
+#
 
-TEXT_BASE = 0xfff00000
+TEXT_BASE = 0xff000000
+#TEXT_BASE = 0xfff00000
 #TEXT_BASE = 0x00100000
 
 PLATFORM_CPPFLAGS += -DTEXT_BASE=$(TEXT_BASE) -I$(TOPDIR)/board
diff --git a/board/emk/top5200/flash.c b/board/emk/top5200/flash.c
index b951b5f..216bce3 100644
--- a/board/emk/top5200/flash.c
+++ b/board/emk/top5200/flash.c
@@ -2,6 +2,9 @@
  * (C) Copyright 2003
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
+ * (C) Copyright 2003
+ * Reinhard Meyer, EMK Elektronik GmbH, r.meyer@emk-elektronik.de
+ *
  * See file CREDITS for list of people who contributed to this
  * project.
  *
@@ -51,7 +54,7 @@
 unsigned long flash_init (void)
 {
 	unsigned long size = 0;
-	int i;
+	int i = 0;
 	extern void flash_preinit(void);
 	extern void flash_afterinit(uint, ulong, ulong);
 	ulong flashbase = CFG_FLASH_BASE;
@@ -59,10 +62,10 @@
 	flash_preinit();
 
 	/* There is only ONE FLASH device */
-	memset(&flash_info[0], 0, sizeof(flash_info_t));
-	flash_info[0].size =
-			flash_get_size((FPW *)flashbase, &flash_info[0]);
-	size += flash_info[0].size;
+	memset(&flash_info[i], 0, sizeof(flash_info_t));
+	flash_info[i].size =
+			flash_get_size((FPW *)flashbase, &flash_info[i]);
+	size += flash_info[i].size;
 
 #if CFG_MONITOR_BASE >= CFG_FLASH_BASE
 	/* monitor protection ON by default */
@@ -81,7 +84,7 @@
 #endif
 
 
-	flash_afterinit(0, flash_info[0].start[0], flash_info[0].size);
+	flash_afterinit(i, flash_info[i].start[0], flash_info[i].size);
 	return size ? size : 1;
 }
 
@@ -151,7 +154,8 @@
 	if (info->flash_id & FLASH_BTYPE) {
 		boottype = botboottype;
 		bootletter = botbootletter;
-	} else {
+	}
+	else {
 		boottype = topboottype;
 		bootletter = topbootletter;
 	}
@@ -238,12 +242,17 @@
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00200000;
+#ifdef CFG_LOWBOOT
+		offset = 0;
+#else
 		offset = 0x00e00000;
+#endif
 		info->start[0] = (ulong)addr + offset;
 		info->start[1] = (ulong)addr + offset + 0x4000;
 		info->start[2] = (ulong)addr + offset + 0x6000;
 		info->start[3] = (ulong)addr + offset + 0x8000;
-		for (i = 4; i < info->sector_count; i++) {
+		for (i = 4; i < info->sector_count; i++)
+		{
 			info->start[i] = (ulong)addr + offset + 0x10000 * (i-3);
 		}
 		break;
@@ -252,8 +261,12 @@
 		info->flash_id += FLASH_AMDLV065D;
 		info->sector_count = 128;
 		info->size = 0x00800000;
+#ifdef CFG_LOWBOOT
+		offset = 0;
+#else
 		offset = 0x00800000;
-		for (i = 0; i < info->sector_count; i++)
+#endif
+		for( i = 0; i < info->sector_count; i++ )
 			info->start[i] = (ulong)addr + offset + (i * 0x10000);
 		break;				/* => 8 or 16 MB	*/
 
diff --git a/board/emk/top5200/top5200.c b/board/emk/top5200/top5200.c
index 536a515..3969e2a 100644
--- a/board/emk/top5200/top5200.c
+++ b/board/emk/top5200/top5200.c
@@ -36,8 +36,10 @@
 {
 	ulong dramsize = 0;
 #ifndef CFG_RAMBOOT
+#if 0
 	ulong	t;
 	ulong	tap_del;
+#endif
 
 	#define	MODE_EN		0x80000000
 	#define	SOFT_PRE	2
@@ -73,16 +75,19 @@
 	*(vu_long *)MPC5XXX_CDM_PORCFG = CFG_DRAM_TAP_DEL << 24;
 
 #if 0
-	for (tap_del = 0; tap_del < 32; tap_del++) {
+	for (tap_del = 0; tap_del < 32; tap_del++)
+	{
 		*(vu_long *)MPC5XXX_CDM_PORCFG = tap_del << 24;
 
 		printf ("\nTAP Delay:%x Filling DRAM...", *(vu_long *)MPC5XXX_CDM_PORCFG);
 		for (t = 0; t < 0x04000000; t+=4)
 			*(vu_long *) t = t;
 		printf ("Checking DRAM...\n");
-		for (t = 0; t < 0x04000000; t+=4) {
+		for (t = 0; t < 0x04000000; t+=4)
+		{
 			ulong	rval = *(vu_long *) t;
-			if (rval != t) {
+			if (rval != t)
+			{
 				printf ("mismatch at %x: ", t);
 				printf (" 1.read %x", rval);
 				printf (" 2.read %x", *(vu_long *) t);
diff --git a/board/icecube/icecube.c b/board/icecube/icecube.c
index e0adec3..27b7bab 100644
--- a/board/icecube/icecube.c
+++ b/board/icecube/icecube.c
@@ -126,7 +126,7 @@
 	/* setup config registers */
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG1 = 0x73722930;
 	*(vu_long *)MPC5XXX_SDRAM_CONFIG2 = 0x47770000;
-	
+
 	/* set tap delay to 0x10 */
 	*(vu_long *)MPC5XXX_CDM_PORCFG = 0x10000000;
 #else
diff --git a/board/incaip/memsetup.S b/board/incaip/memsetup.S
index 70d2885..b438484 100644
--- a/board/incaip/memsetup.S
+++ b/board/incaip/memsetup.S
@@ -13,7 +13,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -27,35 +27,35 @@
 #include <asm/regdef.h>
 
 
-#define EBU_MODUL_BASE          0xB8000200
-#define EBU_CLC(value)          0x0000(value)
-#define EBU_CON(value)          0x0010(value)
-#define EBU_ADDSEL0(value)      0x0020(value)
-#define EBU_ADDSEL1(value)      0x0024(value)
-#define EBU_ADDSEL2(value)      0x0028(value)
-#define EBU_BUSCON0(value)      0x0060(value)
-#define EBU_BUSCON1(value)      0x0064(value)
-#define EBU_BUSCON2(value)      0x0068(value)
+#define EBU_MODUL_BASE		0xB8000200
+#define EBU_CLC(value)		0x0000(value)
+#define EBU_CON(value)		0x0010(value)
+#define EBU_ADDSEL0(value)	0x0020(value)
+#define EBU_ADDSEL1(value)	0x0024(value)
+#define EBU_ADDSEL2(value)	0x0028(value)
+#define EBU_BUSCON0(value)	0x0060(value)
+#define EBU_BUSCON1(value)	0x0064(value)
+#define EBU_BUSCON2(value)	0x0068(value)
 
-#define MC_MODUL_BASE           0xBF800000
-#define MC_ERRCAUSE(value)      0x0100(value)
-#define MC_ERRADDR(value)       0x0108(value)
-#define MC_IOGP(value)          0x0800(value)
-#define MC_SELFRFSH(value)      0x0A00(value)
-#define MC_CTRLENA(value)       0x1000(value)
-#define MC_MRSCODE(value)       0x1008(value)
-#define MC_CFGDW(value)         0x1010(value)
-#define MC_CFGPB0(value)        0x1018(value)
-#define MC_LATENCY(value)       0x1038(value)
-#define MC_TREFRESH(value)      0x1040(value)
+#define MC_MODUL_BASE		0xBF800000
+#define MC_ERRCAUSE(value)	0x0100(value)
+#define MC_ERRADDR(value)	0x0108(value)
+#define MC_IOGP(value)		0x0800(value)
+#define MC_SELFRFSH(value)	0x0A00(value)
+#define MC_CTRLENA(value)	0x1000(value)
+#define MC_MRSCODE(value)	0x1008(value)
+#define MC_CFGDW(value)		0x1010(value)
+#define MC_CFGPB0(value)	0x1018(value)
+#define MC_LATENCY(value)	0x1038(value)
+#define MC_TREFRESH(value)	0x1040(value)
 
-#define CGU_MODUL_BASE          0xBF107000
-#define CGU_PLL1CR(value)       0x0008(value)
-#define CGU_DIVCR(value)        0x0010(value)
-#define CGU_MUXCR(value)        0x0014(value)
-#define CGU_PLL1SR(value)       0x000C(value)
+#define CGU_MODUL_BASE		0xBF107000
+#define CGU_PLL1CR(value)	0x0008(value)
+#define CGU_DIVCR(value)	0x0010(value)
+#define CGU_MUXCR(value)	0x0014(value)
+#define CGU_PLL1SR(value)	0x000C(value)
 
-	.set	noreorder		
+	.set	noreorder
 
 
 /*
@@ -234,4 +234,3 @@
 	j	ra
 	nop
 	.end	memsetup
-
diff --git a/board/mpl/common/common_util.c b/board/mpl/common/common_util.c
index 17871d2..9c98c93 100644
--- a/board/mpl/common/common_util.c
+++ b/board/mpl/common/common_util.c
@@ -54,7 +54,7 @@
 static image_header_t header;
 
 
-static int 
+static int
 mpl_prg(uchar *src, ulong size)
 {
 	ulong start;
@@ -105,7 +105,6 @@
 		flash_perror(rc);
 		return (1);
 	}
-	
 
 #elif defined(CONFIG_VCMA9)
 	start = 0;
@@ -125,7 +124,8 @@
 	}
 
 #endif
-	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",src,size);
+	printf("flash erased, programming from 0x%lx 0x%lx Bytes\n",
+		(ulong)src, size);
 	if ((rc = flash_write (src, start, size)) != 0) {
 		puts("ERROR ");
 		flash_perror(rc);
@@ -136,14 +136,14 @@
 }
 
 
-static int 
+static int
 mpl_prg_image(uchar *ld_addr)
 {
 	unsigned long len, checksum;
 	uchar *data;
 	image_header_t *hdr = &header;
 	int rc;
-	
+
 	/* Copy header so we can blank CRC field for re-calculation */
 	memcpy (&header, (char *)ld_addr, sizeof(image_header_t));
 	if (ntohl(hdr->ih_magic)  != IH_MAGIC) {
@@ -183,7 +183,7 @@
 		    	puts("Insufficient space for decompression\n");
 			return 1;
 		}
-				 
+
 		switch (hdr->ih_comp) {
 		case IH_COMP_GZIP:
 			puts("Uncompressing (GZIP) ... ");
@@ -217,13 +217,13 @@
 			free(buf);
 			return 1;
 		}
-		
+
 		rc = mpl_prg(buf, len);
 		free(buf);
 	} else {
 		rc = mpl_prg(data, len);
 	}
-	
+
 	return(rc);
 }
 
@@ -445,7 +445,7 @@
 				ld_addr=CFG_LOAD_ADDR;
 				result=do_fdcboot(cmdtp, 0, 1, local_args);
 			}
-			result=mpl_prg_image(ld_addr);
+			result=mpl_prg_image((uchar *)ld_addr);
 			return result;
 		}
 #endif /* (CONFIG_COMMANDS & CFG_CMD_FDC) */
diff --git a/board/mvblue/mvblue.c b/board/mvblue/mvblue.c
index 6827a23..0cec63f 100644
--- a/board/mvblue/mvblue.c
+++ b/board/mvblue/mvblue.c
@@ -11,80 +11,86 @@
 #include <ns16550.h>
 
 #ifdef CONFIG_PCI
-	#include <pci.h>
+#include <pci.h>
 #endif
 
-u32 get_BoardType(void);
+u32 get_BoardType (void);
 
 #define PCI_CONFIG(b,d,f,r)    cpu_to_le32(0x80000000 | ((b&0xff)<<16) \
-                                                      | ((d&0x1f)<<11) \
-                                                      | ((f&0x7)<<7)   \
-                                                      | (r&0xfc) )
+						      | ((d&0x1f)<<11) \
+						      | ((f&0x7)<<7)   \
+						      | (r&0xfc) )
 
-int mv_pci_read( int bus, int dev, int func, int reg )
+int mv_pci_read (int bus, int dev, int func, int reg)
 {
-    *(u32*)(0xfec00cf8) = PCI_CONFIG(bus,dev,func,reg);
-    asm("sync");
-    return cpu_to_le32( *(u32*)(0xfee00cfc) );
-}
-u32 get_BoardType() {
-	return ( mv_pci_read(0,0xe,0,0) == 0x06801095 ? 0 : 1 );
+	*(u32 *) (0xfec00cf8) = PCI_CONFIG (bus, dev, func, reg);
+	asm ("sync");
+	return cpu_to_le32 (*(u32 *) (0xfee00cfc));
 }
 
-void init_2nd_DUART(void)
+u32 get_BoardType ()
 {
-	NS16550_t console = (NS16550_t)CFG_NS16550_COM2;
+	return (mv_pci_read (0, 0xe, 0, 0) == 0x06801095 ? 0 : 1);
+}
+
+void init_2nd_DUART (void)
+{
+	NS16550_t console = (NS16550_t) CFG_NS16550_COM2;
 	int clock_divisor = CFG_NS16550_CLK / 16 / CONFIG_BAUDRATE;
-	*(u8*)(0xfc004511) = 0x1;
-	NS16550_init(console, clock_divisor);
+
+	*(u8 *) (0xfc004511) = 0x1;
+	NS16550_init (console, clock_divisor);
 }
-void hw_watchdog_reset(void)
+void hw_watchdog_reset (void)
 {
-	if (get_BoardType() == 0 ) {
-    	*(u32*)(0xff000005) = 0;
-    	asm("sync");
+	if (get_BoardType () == 0) {
+		*(u32 *) (0xff000005) = 0;
+		asm ("sync");
 	}
 }
 int checkboard (void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
-	ulong busfreq  = get_bus_freq(0);
-	char  buf[32];
-	u32   BoardType = get_BoardType();
+	ulong busfreq = get_bus_freq (0);
+	char buf[32];
+	u32 BoardType = get_BoardType ();
 	char *BoardName[2] = { "mvBlueBOX", "mvBlueLYNX" };
 	char *p;
 	bd_t *bd = gd->bd;
 
-	hw_watchdog_reset();
+	hw_watchdog_reset ();
 
-	printf("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
-	printf("       Found %s running at %s MHz memory clock.\n", BoardName[BoardType], strmhz(buf, busfreq) );
+	printf ("U-Boot (%s) running on mvBLUE device.\n", MV_VERSION);
+	printf ("       Found %s running at %s MHz memory clock.\n",
+		BoardName[BoardType], strmhz (buf, busfreq));
 
-	init_2nd_DUART();
+	init_2nd_DUART ();
 
-    if ( (p = getenv("console_nr")) != NULL ) {
-        unsigned long con_nr = simple_strtoul( p, NULL, 10) & 3;
-        bd->bi_baudrate &= ~3;
-        bd->bi_baudrate |= con_nr & 3;
+	if ((p = getenv ("console_nr")) != NULL) {
+		unsigned long con_nr = simple_strtoul (p, NULL, 10) & 3;
+
+		bd->bi_baudrate &= ~3;
+		bd->bi_baudrate |= con_nr & 3;
 	}
 	return 0;
 }
 
 long int initdram (int board_type)
 {
-	int              i, cnt;
-	volatile uchar * base= CFG_SDRAM_BASE;
-	volatile ulong * addr;
-	ulong            save[32];
-	ulong            val, ret  = 0;
+	int i, cnt;
+	volatile uchar *base = CFG_SDRAM_BASE;
+	volatile ulong *addr;
+	ulong save[32];
+	ulong val, ret = 0;
 
-	for (i=0, cnt=(CFG_MAX_RAM_SIZE / sizeof(long)) >> 1; cnt > 0; cnt >>= 1) {
-		addr = (volatile ulong *)base + cnt;
+	for (i = 0, cnt = (CFG_MAX_RAM_SIZE / sizeof (long)) >> 1; cnt > 0;
+	     cnt >>= 1) {
+		addr = (volatile ulong *) base + cnt;
 		save[i++] = *addr;
 		*addr = ~cnt;
 	}
 
-	addr = (volatile ulong *)base;
+	addr = (volatile ulong *) base;
 	save[i] = *addr;
 	*addr = 0;
 
@@ -93,102 +99,113 @@
 		goto Done;
 	}
 
-	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof(long); cnt <<= 1) {
-		addr = (volatile ulong *)base + cnt;
+	for (cnt = 1; cnt <= CFG_MAX_RAM_SIZE / sizeof (long); cnt <<= 1) {
+		addr = (volatile ulong *) base + cnt;
 		val = *addr;
 		*addr = save[--i];
 		if (val != ~cnt) {
-			ulong new_bank0_end = cnt * sizeof(long) - 1;
-			ulong mear1  = mpc824x_mpc107_getreg(MEAR1);
-			ulong emear1 = mpc824x_mpc107_getreg(EMEAR1);
-			mear1 =  (mear1  & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT);
+			ulong new_bank0_end = cnt * sizeof (long) - 1;
+			ulong mear1 = mpc824x_mpc107_getreg (MEAR1);
+			ulong emear1 = mpc824x_mpc107_getreg (EMEAR1);
+
+			mear1 = (mear1 & 0xFFFFFF00) |
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_ADDR_SHIFT);
 			emear1 = (emear1 & 0xFFFFFF00) |
-			  ((new_bank0_end & MICR_ADDR_MASK) >> MICR_EADDR_SHIFT);
-			mpc824x_mpc107_setreg(MEAR1,  mear1);
-			mpc824x_mpc107_setreg(EMEAR1, emear1);
-			ret = cnt * sizeof(long);
+				((new_bank0_end & MICR_ADDR_MASK) >>
+				 MICR_EADDR_SHIFT);
+			mpc824x_mpc107_setreg (MEAR1, mear1);
+			mpc824x_mpc107_setreg (EMEAR1, emear1);
+			ret = cnt * sizeof (long);
 			goto Done;
 		}
 	}
 
 	ret = CFG_MAX_RAM_SIZE;
-Done:
+      Done:
 	return ret;
 }
 
 /* ------------------------------------------------------------------------- */
-u8 *dhcp_vendorex_prep(u8 *e)
+u8 *dhcp_vendorex_prep (u8 * e)
 {
-char *ptr;
+	char *ptr;
 
 	/* DHCP vendor-class-identifier = 60 */
-    if ((ptr = getenv("dhcp_vendor-class-identifier"))) {
-        *e++ = 60;
-        *e++ = strlen(ptr);
-        while (*ptr)
-            *e++ = *ptr++;
-    }
+	if ((ptr = getenv ("dhcp_vendor-class-identifier"))) {
+		*e++ = 60;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
 	/* my DHCP_CLIENT_IDENTIFIER = 61 */
-    if ((ptr = getenv("dhcp_client_id"))) {
-        *e++ = 61;
-        *e++ = strlen(ptr);
-        while (*ptr)
-            *e++ = *ptr++;
-    }
-    return e;
+	if ((ptr = getenv ("dhcp_client_id"))) {
+		*e++ = 61;
+		*e++ = strlen (ptr);
+		while (*ptr)
+			*e++ = *ptr++;
+	}
+	return e;
 }
-u8 *dhcp_vendorex_proc(u8 *popt)
+
+u8 *dhcp_vendorex_proc (u8 * popt)
 {
-    return NULL;
+	return NULL;
 }
+
 /* ------------------------------------------------------------------------- */
 
 /*
  * Initialize PCI Devices
  */
 #ifdef CONFIG_PCI
-void pci_mvblue_clear_base( struct pci_controller *hose, pci_dev_t dev )
+void pci_mvblue_clear_base (struct pci_controller *hose, pci_dev_t dev)
 {
 	u32 cnt;
-	printf("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV(dev), PCI_FUNC(dev) );
-    for( cnt = 0; cnt < 6; cnt++ )
-    	pci_hose_write_config_dword( hose, dev, 0x10 + (4*cnt), 0x0 );
-	printf("done\n");
+
+	printf ("clear base @ dev/func 0x%02x/0x%02x ... ", PCI_DEV (dev),
+		PCI_FUNC (dev));
+	for (cnt = 0; cnt < 6; cnt++)
+		pci_hose_write_config_dword (hose, dev, 0x10 + (4 * cnt),
+					     0x0);
+	printf ("done\n");
 }
 
-void duart_setup( u32 base, u16 divisor )
+void duart_setup (u32 base, u16 divisor)
 {
-	printf("duart setup ...");
-	out_8( (u8*)( CFG_ISA_IO+base+3), 0x80);
-    out_8( (u8*)( CFG_ISA_IO+base+0), divisor & 0xff);
-    out_8( (u8*)( CFG_ISA_IO+base+1), divisor >> 8 );
-    out_8( (u8*)( CFG_ISA_IO+base+3), 0x03);
-    out_8( (u8*)( CFG_ISA_IO+base+4), 0x03);
-    out_8( (u8*)( CFG_ISA_IO+base+2), 0x07);
-	printf("done\n");
+	printf ("duart setup ...");
+	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x80);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 0), divisor & 0xff);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 1), divisor >> 8);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 3), 0x03);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 4), 0x03);
+	out_8 ((u8 *) (CFG_ISA_IO + base + 2), 0x07);
+	printf ("done\n");
 }
 
-void pci_mvblue_fixup_irq_behind_bridge( struct pci_controller *hose, pci_dev_t bridge, unsigned char irq)
+void pci_mvblue_fixup_irq_behind_bridge (struct pci_controller *hose,
+					 pci_dev_t bridge, unsigned char irq)
 {
 	pci_dev_t d;
-	unsigned char 	bus;
-	unsigned short 	vendor,
-					class;
+	unsigned char bus;
+	unsigned short vendor, class;
 
-	pci_hose_read_config_byte( hose, bridge, PCI_SECONDARY_BUS, &bus );
-	for (d =  PCI_BDF(bus,0,0);
-         d <  PCI_BDF(bus,PCI_MAX_PCI_DEVICES-1,PCI_MAX_PCI_FUNCTIONS-1);
-       	 d += PCI_BDF(0,0,1))
-	{
-        pci_hose_read_config_word(hose, d, PCI_VENDOR_ID, &vendor);
-        if (vendor != 0xffff && vendor != 0x0000)
-        {
-			pci_hose_read_config_word( hose, d, PCI_CLASS_DEVICE, &class );
-			if ( class == PCI_CLASS_BRIDGE_PCI )
-				pci_mvblue_fixup_irq_behind_bridge( hose, d, irq );
+	pci_hose_read_config_byte (hose, bridge, PCI_SECONDARY_BUS, &bus);
+	for (d = PCI_BDF (bus, 0, 0);
+	     d < PCI_BDF (bus, PCI_MAX_PCI_DEVICES - 1,
+			  PCI_MAX_PCI_FUNCTIONS - 1);
+	     d += PCI_BDF (0, 0, 1)) {
+		pci_hose_read_config_word (hose, d, PCI_VENDOR_ID, &vendor);
+		if (vendor != 0xffff && vendor != 0x0000) {
+			pci_hose_read_config_word (hose, d, PCI_CLASS_DEVICE,
+						   &class);
+			if (class == PCI_CLASS_BRIDGE_PCI)
+				pci_mvblue_fixup_irq_behind_bridge (hose, d,
+								    irq);
 			else
-				pci_hose_write_config_byte( hose, d, PCI_INTERRUPT_LINE, irq );
+				pci_hose_write_config_byte (hose, d,
+							    PCI_INTERRUPT_LINE,
+							    irq);
 		}
 	}
 }
@@ -196,58 +213,64 @@
 #define MV_MAX_PCI_BUSSES	3
 #define SLOT0_IRQ	3
 #define SLOT1_IRQ	4
-void pci_mvblue_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+void pci_mvblue_fixup_irq (struct pci_controller *hose, pci_dev_t dev)
 {
-    unsigned char 	line=0xff;
-	unsigned short 	class;
+	unsigned char line = 0xff;
+	unsigned short class;
 
-	if( PCI_BUS(dev) == 0 ) {
-	    switch(PCI_DEV(dev)) {
-	    case 0xd:
-			if ( get_BoardType() == 0 ) {
+	if (PCI_BUS (dev) == 0) {
+		switch (PCI_DEV (dev)) {
+		case 0xd:
+			if (get_BoardType () == 0) {
 				line = 1;
 			} else
 				/* mvBL */
-		        line = 2;
-	        break;
-	    case 0xe:
+				line = 2;
+			break;
+		case 0xe:
 			/* mvBB: IDE */
 			line = 2;
-    		pci_hose_write_config_byte(hose, dev, 0x8a, 0x20 );
+			pci_hose_write_config_byte (hose, dev, 0x8a, 0x20);
 			break;
 		case 0xf:
 			/* mvBB: Slot0 (Grabber) */
-			pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
-			if ( class == PCI_CLASS_BRIDGE_PCI ) {
-				pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT0_IRQ );
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT0_IRQ);
 				line = 0xff;
 			} else
 				line = SLOT0_IRQ;
 			break;
 		case 0x10:
 			/* mvBB: Slot1 */
-			pci_hose_read_config_word( hose, dev, PCI_CLASS_DEVICE, &class );
-			if ( class == PCI_CLASS_BRIDGE_PCI ) {
-				pci_mvblue_fixup_irq_behind_bridge( hose, dev, SLOT1_IRQ );
+			pci_hose_read_config_word (hose, dev,
+						   PCI_CLASS_DEVICE, &class);
+			if (class == PCI_CLASS_BRIDGE_PCI) {
+				pci_mvblue_fixup_irq_behind_bridge (hose, dev,
+								    SLOT1_IRQ);
 				line = 0xff;
 			} else
 				line = SLOT1_IRQ;
 			break;
-	    default:
-			printf("***pci_scan: illegal dev = 0x%08x\n", PCI_DEV(dev) );
+		default:
+			printf ("***pci_scan: illegal dev = 0x%08x\n",
+				PCI_DEV (dev));
 			line = 0xff;
 			break;
-	    }
-    	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, line );
+		}
+		pci_hose_write_config_byte (hose, dev, PCI_INTERRUPT_LINE,
+					    line);
 	}
 }
 
 struct pci_controller hose = {
-	fixup_irq: pci_mvblue_fixup_irq
+	fixup_irq:pci_mvblue_fixup_irq
 };
 
-void pci_init_board(void)
+void pci_init_board (void)
 {
-	pci_mpc824x_init(&hose);
+	pci_mpc824x_init (&hose);
 }
 #endif
diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c
index d4e2cbb..d2f169b 100644
--- a/board/snmc/qs850/flash.c
+++ b/board/snmc/qs850/flash.c
@@ -151,7 +151,6 @@
 }
 
 
-
 /*-----------------------------------------------------------------------
  This code is specific to the AM29DL163/AM29DL232 for the QS850/QS823.
  */
diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c
index ab7c8a1..c84d08d 100644
--- a/board/snmc/qs860t/flash.c
+++ b/board/snmc/qs860t/flash.c
@@ -170,7 +170,6 @@
 }
 
 
-
 /*-----------------------------------------------------------------------
  */
 
diff --git a/board/tqm8260/tqm8260.c b/board/tqm8260/tqm8260.c
index a0a38ca..f716cf2 100644
--- a/board/tqm8260/tqm8260.c
+++ b/board/tqm8260/tqm8260.c
@@ -299,8 +299,7 @@
 	*addr = 0;
 
 	if ((val = *addr) != 0) {
-		/* Restore the original data before leaving the function.
-		 */
+		/* Restore the original data before leaving the function.  */
 		*addr = save[i];
 		for (cnt = 1; cnt <= maxsize / sizeof(long); cnt <<= 1) {
 			addr  = (volatile ulong *) base + cnt;
@@ -315,8 +314,7 @@
 		*addr = save[--i];
 		if (val != ~cnt) {
 			size = cnt * sizeof (long);
-			/* Restore the original data before leaving the function.
-			 */ 
+			/* Restore the original data before leaving the function.  */
 			for (cnt <<= 1; cnt <= maxsize / sizeof (long); cnt <<= 1) {
 				addr  = (volatile ulong *) base + cnt;
 				*addr = save[--i];
diff --git a/board/tqm8xx/flash.c b/board/tqm8xx/flash.c
index a974e23..b8a3595 100644
--- a/board/tqm8xx/flash.c
+++ b/board/tqm8xx/flash.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,7 +21,9 @@
  * MA 02111-1307 USA
  */
 
-/* #define DEBUG */
+#if 0
+#define DEBUG
+#endif
 
 #include <common.h>
 #include <mpc8xx.h>
@@ -214,6 +216,8 @@
 				break;
 	case FLASH_AMLV640U:	printf ("AM29LV640ML (64Mbit, uniform sector size)\n");
 				break;
+	case FLASH_AMLV320B:	printf ("AM29LV320MB (32Mbit, bottom boot sect)\n");
+				break;
 # else	/* ! TQM8xxM */
 	case FLASH_AM400B:	printf ("AM29LV400B (4 Mbit, bottom boot sect)\n");
 				break;
@@ -232,6 +236,8 @@
 				break;
 	case FLASH_AM160T:	printf ("AM29LV160T (16 Mbit, top boot sector)\n");
 				break;
+	case FLASH_AMDL163B:	printf ("AM29DL163B (16 Mbit, bottom boot sect)\n");
+				break;
 	default:		printf ("Unknown Chip Type\n");
 				break;
 	}
@@ -280,12 +286,15 @@
 
 	switch (value) {
 	case AMD_MANUFACT:
+		debug ("Manufacturer: AMD\n");
 		info->flash_id = FLASH_MAN_AMD;
 		break;
 	case FUJ_MANUFACT:
+		debug ("Manufacturer: FUJITSU\n");
 		info->flash_id = FLASH_MAN_FUJ;
 		break;
 	default:
+		debug ("Manufacturer: *** unknown ***\n");
 		info->flash_id = FLASH_UNKNOWN;
 		info->sector_count = 0;
 		info->size = 0;
@@ -299,36 +308,53 @@
 	switch (value) {
 #ifdef CONFIG_TQM8xxM	/* mirror bit flash */
 	case AMD_ID_MIRROR:
+		debug ("Mirror Bit flash: addr[14] = %08lX  addr[15] = %08lX\n",
+			addr[14], addr[15]);
 		/* Special case for AMLV320MH/L */
 		if ((addr[14] & 0x00ff00ff) == 0x001d001d &&
-			(addr[15] & 0x00ff00ff) == 0x00000000) {
+		    (addr[15] & 0x00ff00ff) == 0x00000000) {
+			debug ("Chip: AMLV320MH/L\n");
 			info->flash_id += FLASH_AMLV320U;
 			info->sector_count = 64;
-			info->size = 0x00800000; /* => 8 MB */
+			info->size = 0x00800000;	/* => 8 MB */
 			break;
 		}
 		switch(addr[14]) {
 		case AMD_ID_LV128U_2:
 			if (addr[15] != AMD_ID_LV128U_3) {
+				debug ("Chip: AMLV128U -> unknown\n");
 				info->flash_id = FLASH_UNKNOWN;
-			}
-			else {
+			} else {
+				debug ("Chip: AMLV128U\n");
 				info->flash_id += FLASH_AMLV128U;
 				info->sector_count = 256;
 				info->size = 0x02000000;
 			}
-			break;				/* => 32 MB		*/
+			break;				/* => 32 MB	*/
 		case AMD_ID_LV640U_2:
 			if (addr[15] != AMD_ID_LV640U_3) {
+				debug ("Chip: AMLV640U -> unknown\n");
 				info->flash_id = FLASH_UNKNOWN;
-			}
-			else {
+			} else {
+				debug ("Chip: AMLV640U\n");
 				info->flash_id += FLASH_AMLV640U;
 				info->sector_count = 128;
 				info->size = 0x01000000;
 			}
-			break;				/* => 16 MB		*/
+			break;				/* => 16 MB	*/
+		case AMD_ID_LV320B_2:
+			if (addr[15] != AMD_ID_LV320B_3) {
+				debug ("Chip: AMLV320B -> unknown\n");
+				info->flash_id = FLASH_UNKNOWN;
+			} else {
+				debug ("Chip: AMLV320B\n");
+				info->flash_id += FLASH_AMLV320B;
+				info->sector_count = 71;
+				info->size = 0x00800000;
+			}
+			break;				/* =>  8 MB	*/
 		default:
+			debug ("Chip: *** unknown ***\n");
 			info->flash_id = FLASH_UNKNOWN;
 			break;
 		}
@@ -338,50 +364,56 @@
 		info->flash_id += FLASH_AM400T;
 		info->sector_count = 11;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;					/* => 1 MB		*/
 
 	case AMD_ID_LV400B:
 		info->flash_id += FLASH_AM400B;
 		info->sector_count = 11;
 		info->size = 0x00100000;
-		break;				/* => 1 MB		*/
+		break;					/* => 1 MB		*/
 
 	case AMD_ID_LV800T:
 		info->flash_id += FLASH_AM800T;
 		info->sector_count = 19;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;					/* => 2 MB	*/
 
 	case AMD_ID_LV800B:
 		info->flash_id += FLASH_AM800B;
 		info->sector_count = 19;
 		info->size = 0x00200000;
-		break;				/* => 2 MB		*/
+		break;					/* => 2 MB	*/
 
 	case AMD_ID_LV320T:
 		info->flash_id += FLASH_AM320T;
 		info->sector_count = 71;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;					/* => 8 MB	*/
 
 	case AMD_ID_LV320B:
 		info->flash_id += FLASH_AM320B;
 		info->sector_count = 71;
 		info->size = 0x00800000;
-		break;				/* => 8 MB		*/
+		break;					/* => 8 MB	*/
 #endif	/* TQM8xxM */
 
 	case AMD_ID_LV160T:
 		info->flash_id += FLASH_AM160T;
 		info->sector_count = 35;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;					/* => 4 MB	*/
 
 	case AMD_ID_LV160B:
 		info->flash_id += FLASH_AM160B;
 		info->sector_count = 35;
 		info->size = 0x00400000;
-		break;				/* => 4 MB		*/
+		break;					/* => 4 MB	*/
+
+	case AMD_ID_DL163B:
+		info->flash_id += FLASH_AMDL163B;
+		info->sector_count = 39;
+		info->size = 0x00400000;
+		break;					/* => 4 MB	*/
 
 	default:
 		info->flash_id = FLASH_UNKNOWN;
@@ -402,6 +434,18 @@
 				base += 0x20000;
 			}
 			break;
+		case FLASH_AMLV320B:
+			for (i = 0; i < info->sector_count; i++) {
+				info->start[i] = base;
+				/*
+				 * The first 8 sectors are 8 kB,
+				 * all the other ones  are 64 kB
+				 */
+				base += (i < 8)
+					?  2 * ( 8 << 10)
+					:  2 * (64 << 10);
+			}
+			break;
 		}
 		break;
 # else	/* ! TQM8xxM */
@@ -472,11 +516,24 @@
 			info->start[i] = base + i * 0x00020000;
 		}
 		break;
+	case AMD_ID_DL163B:
+		for (i = 0; i < info->sector_count; i++) {
+			info->start[i] = base;
+			/*
+			 * The first 8 sectors are 8 kB,
+			 * all the other ones  are 64 kB
+			 */
+			base += (i < 8)
+				?  2 * ( 8 << 10)
+				:  2 * (64 << 10);
+		}
+		break;
 	default:
 		return (0);
 		break;
 	}
 
+#if 0
 	/* check for protected sectors */
 	for (i = 0; i < info->sector_count; i++) {
 		/* read sector protection at sector address, (A7 .. A0) = 0x02 */
@@ -484,6 +541,7 @@
 		addr = (volatile unsigned long *)(info->start[i]);
 		info->protect[i] = addr[2] & 1;
 	}
+#endif
 
 	/*
 	 * Prevent writes to uninitialized FLASH.
diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c
index 5f74650..c6b53ab 100644
--- a/board/tqm8xx/tqm8xx.c
+++ b/board/tqm8xx/tqm8xx.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001, 2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -21,6 +21,10 @@
  * MA 02111-1307 USA
  */
 
+#if 0
+#define DEBUG
+#endif
+
 #include <common.h>
 #include <mpc8xx.h>
 
@@ -92,7 +96,7 @@
  * If present, check for "L" type (no second DRAM bank),
  * otherwise "L" type is assumed as default.
  *
- * Set board_type to 'L' for "L" type, 0 else.
+ * Set board_type to 'L' for "L" type, 'M' for "M" type, 0 else.
  */
 
 int checkboard (void)
@@ -112,6 +116,10 @@
 		gd->board_type = 'L';
 	}
 
+	if ((*(s + 6) == 'M')) {	/* a TQM8xxM type */
+		gd->board_type = 'M';
+	}
+
 	for (; *s; ++s) {
 		if (*s == ' ')
 			break;
@@ -167,7 +175,8 @@
 	memctl->memc_br2 = CFG_BR2_PRELIM;
 
 #ifndef	CONFIG_CAN_DRIVER
-	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
 		memctl->memc_or3 = CFG_OR3_PRELIM;
 		memctl->memc_br3 = CFG_BR3_PRELIM;
 	}
@@ -185,7 +194,8 @@
 	udelay (1);
 
 #ifndef	CONFIG_CAN_DRIVER
-	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
 		memctl->memc_mcr = 0x80006105;	/* SDRAM bank 1 */
 		udelay (1);
 		memctl->memc_mcr = 0x80006230;	/* SDRAM bank 1 - execute twice */
@@ -204,6 +214,7 @@
 	 */
 	size8 = dram_size (CFG_MAMR_8COL, (ulong *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size8 >> 20);
 
 	udelay (1000);
 
@@ -212,33 +223,33 @@
 	 */
 	size9 = dram_size (CFG_MAMR_9COL, (ulong *) SDRAM_BASE2_PRELIM,
 					   SDRAM_MAX_SIZE);
+	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size9 >> 20);
 
 	if (size8 < size9) {		/* leave configuration at 9 columns */
 		size_b0 = size9;
-/*	debug ("SDRAM Bank 0 in 9 column mode: %ld MB\n", size >> 20);	*/
 	} else {					/* back to 8 columns            */
 		size_b0 = size8;
 		memctl->memc_mamr = CFG_MAMR_8COL;
 		udelay (500);
-/*	debug ("SDRAM Bank 0 in 8 column mode: %ld MB\n", size >> 20);	*/
 	}
+	debug ("SDRAM Bank 0: %ld MB\n", size_b0 >> 20);
 
 #ifndef	CONFIG_CAN_DRIVER
-	if (board_type != 'L') {	/* "L" type boards have only one bank SDRAM */
+	if ((board_type != 'L') &&
+	    (board_type != 'M') ) {	/* "L" and "M" type boards have only one bank SDRAM */
 		/*
 		 * Check Bank 1 Memory Size
 		 * use current column settings
 		 * [9 column SDRAM may also be used in 8 column mode,
 		 *  but then only half the real size will be used.]
 		 */
-		size_b1 =
-				dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
-						   SDRAM_MAX_SIZE);
-/*	debug ("SDRAM Bank 1: %ld MB\n", size8 >> 20);	*/
+		size_b1 = dram_size (memctl->memc_mamr, (ulong *) SDRAM_BASE3_PRELIM,
+				     SDRAM_MAX_SIZE);
+		debug ("SDRAM Bank 1: %ld MB\n", size_b1 >> 20);
 	} else {
 		size_b1 = 0;
 	}
-#endif							/* CONFIG_CAN_DRIVER */
+#endif	/* CONFIG_CAN_DRIVER */
 
 	udelay (1000);
 
@@ -383,8 +394,7 @@
  * - short between data lines
  */
 
-static long int dram_size (long int mamr_value, long int *base,
-						   long int maxsize)
+static long int dram_size (long int mamr_value, long int *base, long int maxsize)
 {
 	volatile immap_t *immap = (immap_t *) CFG_IMMR;
 	volatile memctl8xx_t *memctl = &immap->im_memctl;
diff --git a/board/trab/auto_update.c b/board/trab/auto_update.c
index 36fdf18..393e094 100644
--- a/board/trab/auto_update.c
+++ b/board/trab/auto_update.c
@@ -279,8 +279,8 @@
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
-	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK) 
-            && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
+	if ((idx == IDX_APP) && (hdr->ih_type != IH_TYPE_RAMDISK)
+	    && (hdr->ih_type != IH_TYPE_FILESYSTEM)) {
 		printf ("Image %s wrong type\n", aufile[idx]);
 		return -1;
 	}
diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 5e31400..34a74ce 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c
@@ -263,7 +263,7 @@
 	case IH_TYPE_KERNEL:
 		name = "Kernel Image";
 		break;
-	case IH_TYPE_MULTI:	
+	case IH_TYPE_MULTI:
 		name = "Multi-File Image";
 		len  = ntohl(len_ptr[0]);
 		/* OS kernel is always the first image */
diff --git a/common/cmd_flash.c b/common/cmd_flash.c
index 253f9ef..e5b1ca1 100644
--- a/common/cmd_flash.c
+++ b/common/cmd_flash.c
@@ -333,15 +333,15 @@
 			status = dataflash_real_protect(p,addr_first,addr_last);
 			if (status < 0){
 				printf("Bad DataFlash sector specification\n");
-                		return 1;
-        		}
-        		printf("%sProtect %d DataFlash Sectors\n",
-                		p ? "" : "Un-", status);
+				return 1;
+			}
+			printf("%sProtect %d DataFlash Sectors\n",
+				p ? "" : "Un-", status);
 			return 0;
 		}
 	}
 #endif
-	
+
 	if (strcmp(argv[2], "all") == 0) {
 		for (bank=1; bank<=CFG_MAX_FLASH_BANKS; ++bank) {
 			info = &flash_info[bank-1];
diff --git a/common/cmd_fpga.c b/common/cmd_fpga.c
index 41ed459..e674ef4 100644
--- a/common/cmd_fpga.c
+++ b/common/cmd_fpga.c
@@ -45,8 +45,8 @@
 #if defined (CONFIG_FPGA) && ( CONFIG_COMMANDS & CFG_CMD_FPGA )
 
 /* Local functions */
-static void fpga_usage ( cmd_tbl_t *cmdtp );
-static int fpga_get_op( char *opstr );
+static void fpga_usage (cmd_tbl_t * cmdtp);
+static int fpga_get_op (char *opstr);
 
 /* Local defines */
 #define FPGA_NONE   -1
@@ -62,106 +62,106 @@
  * If there is no data addr field, the fpgadata environment variable is used.
  * The info command requires no data address field.
  */
-int
-do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+int do_fpga (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
 {
-    int op, dev = FPGA_INVALID_DEVICE;
-    size_t data_size = 0;
-    void *fpga_data = NULL;
-    char *devstr = getenv("fpga");
-    char *datastr = getenv("fpgadata");
-    int rc = FPGA_FAIL;
+	int op, dev = FPGA_INVALID_DEVICE;
+	size_t data_size = 0;
+	void *fpga_data = NULL;
+	char *devstr = getenv ("fpga");
+	char *datastr = getenv ("fpgadata");
+	int rc = FPGA_FAIL;
 
-	if ( devstr ) dev = (int)simple_strtoul( devstr, NULL, 16 );
-	if ( datastr ) fpga_data = (void *)simple_strtoul( datastr, NULL, 16 );
+	if (devstr)
+		dev = (int) simple_strtoul (devstr, NULL, 16);
+	if (datastr)
+		fpga_data = (void *) simple_strtoul (datastr, NULL, 16);
 
-    switch ( argc )
-    {
-	    case 5: /* fpga <op> <dev> <data> <datasize> */
-		    data_size = simple_strtoul( argv[4], NULL, 16 );
-	    case 4: /* fpga <op> <dev> <data> */
-		    fpga_data = (void *)simple_strtoul( argv[3], NULL, 16 );
-			PRINTF(__FUNCTION__": fpga_data = 0x%x\n", (uint)fpga_data );
-	    case 3: /* fpga <op> <dev | data addr> */
-		    dev = (int)simple_strtoul( argv[2], NULL, 16 );
-			PRINTF(__FUNCTION__": device = %d\n", dev );
-			/* FIXME - this is a really weak test */
-		    if (( argc == 3 ) && ( dev > fpga_count() )) { /* must be buffer ptr */
-				PRINTF(__FUNCTION__": Assuming buffer pointer in arg 3\n");
-			    fpga_data = (void *)dev;
-				PRINTF(__FUNCTION__": fpga_data = 0x%x\n", (uint)fpga_data );
-			    dev = FPGA_INVALID_DEVICE;  /* reset device num */
-		    }
-	    case 2: /* fpga <op> */
-		    op = (int)fpga_get_op( argv[1] );
-		    break;
-	    default:
-			PRINTF(__FUNCTION__": Too many or too few args (%d)\n", argc );
-		    op = FPGA_NONE;    /* force usage display */
-		    break;
-    }
+	switch (argc) {
+	case 5:		/* fpga <op> <dev> <data> <datasize> */
+		data_size = simple_strtoul (argv[4], NULL, 16);
+	case 4:		/* fpga <op> <dev> <data> */
+		fpga_data = (void *) simple_strtoul (argv[3], NULL, 16);
+		PRINTF (__FUNCTION__ ": fpga_data = 0x%x\n",
+			(uint) fpga_data);
+	case 3:		/* fpga <op> <dev | data addr> */
+		dev = (int) simple_strtoul (argv[2], NULL, 16);
+		PRINTF (__FUNCTION__ ": device = %d\n", dev);
+		/* FIXME - this is a really weak test */
+		if ((argc == 3) && (dev > fpga_count ())) {	/* must be buffer ptr */
+			PRINTF (__FUNCTION__
+				": Assuming buffer pointer in arg 3\n");
+			fpga_data = (void *) dev;
+			PRINTF (__FUNCTION__ ": fpga_data = 0x%x\n",
+				(uint) fpga_data);
+			dev = FPGA_INVALID_DEVICE;	/* reset device num */
+		}
+	case 2:		/* fpga <op> */
+		op = (int) fpga_get_op (argv[1]);
+		break;
+	default:
+		PRINTF (__FUNCTION__ ": Too many or too few args (%d)\n",
+			argc);
+		op = FPGA_NONE;	/* force usage display */
+		break;
+	}
 
-    switch ( op ) {
-	    case FPGA_NONE:
-		    fpga_usage( cmdtp );
-		    break;
+	switch (op) {
+	case FPGA_NONE:
+		fpga_usage (cmdtp);
+		break;
 
-	    case FPGA_INFO:
-		    rc = fpga_info( dev );
-		    break;
+	case FPGA_INFO:
+		rc = fpga_info (dev);
+		break;
 
-	    case FPGA_LOAD:
-                    rc = fpga_load( dev, fpga_data, data_size );
-		    break;
+	case FPGA_LOAD:
+		rc = fpga_load (dev, fpga_data, data_size);
+		break;
 
-	    case FPGA_DUMP:
-                    rc = fpga_dump( dev, fpga_data, data_size );
-		    break;
+	case FPGA_DUMP:
+		rc = fpga_dump (dev, fpga_data, data_size);
+		break;
 
-	    default:
-		    printf( "Unknown operation.\n" );
-		    fpga_usage( cmdtp );
-		    break;
-    }
-    return (rc);
+	default:
+		printf ("Unknown operation.\n");
+		fpga_usage (cmdtp);
+		break;
+	}
+	return (rc);
 }
 
-static void fpga_usage ( cmd_tbl_t *cmdtp )
+static void fpga_usage (cmd_tbl_t * cmdtp)
 {
-	printf( "Usage:\n%s\n", cmdtp->usage );
+	printf ("Usage:\n%s\n", cmdtp->usage);
 }
 
 /*
  * Map op to supported operations.  We don't use a table since we
  * would just have to relocate it from flash anyway.
  */
-static int fpga_get_op( char *opstr )
+static int fpga_get_op (char *opstr)
 {
 	int op = FPGA_NONE;
 
 	if (!strcmp ("info", opstr)) {
 		op = FPGA_INFO;
-	}
-	else if (!strcmp ("load", opstr)) {
+	} else if (!strcmp ("load", opstr)) {
 		op = FPGA_LOAD;
-	}
-	else if (!strcmp ("dump", opstr)) {
+	} else if (!strcmp ("dump", opstr)) {
 		op = FPGA_DUMP;
 	}
 
-	if ( op == FPGA_NONE ) {
+	if (op == FPGA_NONE) {
 		printf ("Unknown fpga operation \"%s\"\n", opstr);
 	}
 	return op;
 }
 
-U_BOOT_CMD(
-	fpga,    6,     1,     do_fpga,
-	"fpga   - loadable FPGA image support\n",
-	"fpga [operation type] [device number] [image address] [image size]\n"
-	"fpga operations:\n"
-	"\tinfo\tlist known device information.\n"
-	"\tload\tLoad device from memory buffer.\n"
-	"\tdump\tLoad device to memory buffer.\n"
-);
-#endif	/* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
+U_BOOT_CMD (fpga, 6, 1, do_fpga,
+	    "fpga   - loadable FPGA image support\n",
+	    "fpga [operation type] [device number] [image address] [image size]\n"
+	    "fpga operations:\n"
+	    "\tinfo\tlist known device information.\n"
+	    "\tload\tLoad device from memory buffer.\n"
+	    "\tdump\tLoad device to memory buffer.\n");
+#endif /* CONFIG_FPGA && CONFIG_COMMANDS & CFG_CMD_FPGA */
diff --git a/common/cmd_ide.c b/common/cmd_ide.c
index 3f18b00..331041c 100644
--- a/common/cmd_ide.c
+++ b/common/cmd_ide.c
@@ -771,7 +771,7 @@
 {
 	PRINTF ("ide_outb (dev= %d, port= %d, val= 0x%02x) : @ 0x%08lx\n",
 		dev, port, val, (ATA_CURR_BASE(dev)+port));
-    
+
 	/* Ensure I/O operations complete */
 	__asm__ volatile("eieio");
 	*((uchar *)(ATA_CURR_BASE(dev)+port)) = val;
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index 35b3901..6ccad70 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -146,9 +146,9 @@
 		if ((rc = read_dataflash(addr, (linebytes/size)*size, linebuf)) == DATAFLASH_OK){
 			/* if outside dataflash */
 			/*if (rc != 1) {
-        	                dataflash_perror (rc);
-                	        return (1);
-	                }*/
+				dataflash_perror (rc);
+				return (1);
+			}*/
 			for (i=0; i<linebytes; i+= size) {
 				if (size == 4) {
 					printf(" %08x", *uip++);
@@ -439,9 +439,9 @@
 		int rc;
 		rc = read_dataflash(addr, count * size, (char *) dest);
 		if (rc != 1) {
-                        dataflash_perror (rc);
-                        return (1);
-                }
+			dataflash_perror (rc);
+			return (1);
+		}
 		return 0;
 	}
 
diff --git a/cpu/coldfire/Makefile b/cpu/coldfire/Makefile
index 085d840..3976f56 100644
--- a/cpu/coldfire/Makefile
+++ b/cpu/coldfire/Makefile
@@ -27,7 +27,7 @@
 
 LIB	= lib$(CPU).a
 
-START	= 
+START	=
 OBJS	= kgdb.o serial.o interrupts.o cpu.o speed.o cpu_init.o fec.o
 
 all:	.depend $(START) $(LIB)
diff --git a/cpu/coldfire/fec.c b/cpu/coldfire/fec.c
index 53a93c1..5062741 100644
--- a/cpu/coldfire/fec.c
+++ b/cpu/coldfire/fec.c
@@ -27,7 +27,6 @@
 #include <command.h>
 
 
-
 /**************************************************************
  *
  * FEC Ethernet Initialization Routine
@@ -50,18 +49,14 @@
 #define	FEC_RESET_DELAY		50000
 
 
-
 /* Ethernet Transmit and Receive Buffers */
 #define DBUF_LENGTH  1520
-
 #define TX_BUF_CNT 2
-
 #define TOUT_LOOP 100
 
-#define PKT_MAXBUF_SIZE         1518
-#define PKT_MINBUF_SIZE         64
-#define PKT_MAXBLR_SIZE         1520
-
+#define PKT_MAXBUF_SIZE		1518
+#define PKT_MINBUF_SIZE		64
+#define PKT_MAXBLR_SIZE		1520
 
 
 #ifdef CONFIG_M5272
@@ -76,11 +71,10 @@
 #if (CONFIG_COMMANDS & CFG_CMD_NET) && defined(FEC_ENET)
 
 
-
 static char txbuf[DBUF_LENGTH];
 
-static uint rxIdx;	/* index of the current RX buffer */
-static uint txIdx;	/* index of the current TX buffer */
+static uint rxIdx;		/* index of the current RX buffer */
+static uint txIdx;		/* index of the current TX buffer */
 
 /*
   * FEC Ethernet Tx and Rx buffer descriptors allocated at the
@@ -89,14 +83,14 @@
   */
 
 typedef volatile struct CommonBufferDescriptor {
-    cbd_t rxbd[PKTBUFSRX];		/* Rx BD */
-    cbd_t txbd[TX_BUF_CNT];		/* Tx BD */
+	cbd_t rxbd[PKTBUFSRX];	/* Rx BD */
+	cbd_t txbd[TX_BUF_CNT];	/* Tx BD */
 } RTXBD;
 
 static RTXBD *rtx = 0x380000;
 
 
-int eth_send(volatile void *packet, int length)
+int eth_send (volatile void *packet, int length)
 {
 	int j, rc;
 	volatile fec_t *fecp = FEC_ADDR;
@@ -105,35 +99,37 @@
 	 * Wait for ready
 	 */
 	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-		udelay(1);
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
+	       && (j < TOUT_LOOP)) {
+		udelay (1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
-		printf("TX not ready\n");
+	if (j >= TOUT_LOOP) {
+		printf ("TX not ready\n");
 	}
 
-	rtx->txbd[txIdx].cbd_bufaddr = (uint)packet;
-	rtx->txbd[txIdx].cbd_datlen  = length;
+	rtx->txbd[txIdx].cbd_bufaddr = (uint) packet;
+	rtx->txbd[txIdx].cbd_datlen = length;
 	rtx->txbd[txIdx].cbd_sc |= BD_ENET_TX_READY | BD_ENET_TX_LAST;
 
 	/* Activate transmit Buffer Descriptor polling */
-	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active	*/
+	fecp->fec_x_des_active = 0x01000000;	/* Descriptor polling active    */
 
 	j = 0;
-	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j<TOUT_LOOP)) {
-		udelay(1);
+	while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY)
+	       && (j < TOUT_LOOP)) {
+		udelay (1);
 		j++;
 	}
-	if (j>=TOUT_LOOP) {
-		printf("TX timeout\n");
+	if (j >= TOUT_LOOP) {
+		printf ("TX timeout\n");
 	}
 #ifdef ET_DEBUG
-	printf("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
-	__FILE__,__LINE__,__FUNCTION__,j,rtx->txbd[txIdx].cbd_sc,
-	(rtx->txbd[txIdx].cbd_sc & 0x003C)>>2);
+	printf ("%s[%d] %s: cycles: %d    status: %x  retry cnt: %d\n",
+		__FILE__, __LINE__, __FUNCTION__, j, rtx->txbd[txIdx].cbd_sc,
+		(rtx->txbd[txIdx].cbd_sc & 0x003C) >> 2);
 #endif
-	/* return only status bits */;
+	/* return only status bits */ ;
 	rc = (rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_STATS);
 
 	txIdx = (txIdx + 1) % TX_BUF_CNT;
@@ -141,48 +137,49 @@
 	return rc;
 }
 
-int eth_rx(void)
+int eth_rx (void)
 {
 	int length;
 	volatile fec_t *fecp = FEC_ADDR;
 
-   for (;;)
-   {     
-	/* section 16.9.23.2 */
-	if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
-		length = -1;
-		break;     /* nothing received - leave for() loop */
-	}
+	for (;;) {
+		/* section 16.9.23.2 */
+		if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) {
+			length = -1;
+			break;	/* nothing received - leave for() loop */
+		}
 
-	length = rtx->rxbd[rxIdx].cbd_datlen;
+		length = rtx->rxbd[rxIdx].cbd_datlen;
 
-	if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
+		if (rtx->rxbd[rxIdx].cbd_sc & 0x003f) {
 #ifdef ET_DEBUG
-		printf("%s[%d] err: %x\n",
-		__FUNCTION__,__LINE__,rtx->rxbd[rxIdx].cbd_sc);
+			printf ("%s[%d] err: %x\n",
+				__FUNCTION__, __LINE__,
+				rtx->rxbd[rxIdx].cbd_sc);
 #endif
-	} else {
-		/* Pass the packet up to the protocol layers. */
-		NetReceive(NetRxPackets[rxIdx], length - 4);
+		} else {
+			/* Pass the packet up to the protocol layers. */
+			NetReceive (NetRxPackets[rxIdx], length - 4);
+		}
+
+		/* Give the buffer back to the FEC. */
+		rtx->rxbd[rxIdx].cbd_datlen = 0;
+
+		/* wrap around buffer index when necessary */
+		if ((rxIdx + 1) >= PKTBUFSRX) {
+			rtx->rxbd[PKTBUFSRX - 1].cbd_sc =
+				(BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
+			rxIdx = 0;
+		} else {
+			rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
+			rxIdx++;
+		}
+
+		/* Try to fill Buffer Descriptors */
+		fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
 	}
 
-	/* Give the buffer back to the FEC. */
-	rtx->rxbd[rxIdx].cbd_datlen = 0;
-
-	/* wrap around buffer index when necessary */
-	if ((rxIdx + 1) >= PKTBUFSRX) {
-           rtx->rxbd[PKTBUFSRX - 1].cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY);
-	   rxIdx = 0;
-	} else {
-           rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY;
-	   rxIdx++;
-	}
-	
-	/* Try to fill Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active	*/
-   }
-
-   return length;
+	return length;
 }
 
 
@@ -191,7 +188,7 @@
 
 	int i;
 	volatile fec_t *fecp = FEC_ADDR;
-	
+
 	/* Whack a reset.
 	 * A delay is required between a reset of the FEC block and
 	 * initialization of other FEC registers because the reset takes
@@ -214,21 +211,21 @@
 	/* We use strictly polling mode only
 	 */
 	fecp->fec_imask = 0;
-	
+
 	/* Clear any pending interrupt */
 	fecp->fec_ievent = 0xffffffff;
-	
-	/* Set station address	 */
+
+	/* Set station address   */
 #define ea bd->bi_enetaddr
-	fecp->fec_addr_low   =	(ea[0] << 24) | (ea[1] << 16) |
-				(ea[2] <<  8) | (ea[3]        ) ;
-	fecp->fec_addr_high  =	(ea[4] << 24) | (ea[5] << 16  ) ;
+	fecp->fec_addr_low = (ea[0] << 24) | (ea[1] << 16) |
+		(ea[2] << 8) | (ea[3]);
+	fecp->fec_addr_high = (ea[4] << 24) | (ea[5] << 16);
 #undef ea
 
 	/* Clear multicast address hash table
 	 */
 	fecp->fec_hash_table_high = 0;
-	fecp->fec_hash_table_low  = 0;
+	fecp->fec_hash_table_low = 0;
 
 	/* Set maximum receive buffer size.
 	 */
@@ -246,8 +243,8 @@
 	 *     Empty, Wrap
 	 */
 	for (i = 0; i < PKTBUFSRX; i++) {
-		rtx->rxbd[i].cbd_sc      = BD_ENET_RX_EMPTY;
-		rtx->rxbd[i].cbd_datlen  = 0;	/* Reset */
+		rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY;
+		rtx->rxbd[i].cbd_datlen = 0;	/* Reset */
 		rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i];
 	}
 	rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP;
@@ -258,8 +255,8 @@
 	 *    Last, Tx CRC
 	 */
 	for (i = 0; i < TX_BUF_CNT; i++) {
-	        rtx->txbd[i].cbd_sc      = BD_ENET_TX_LAST | BD_ENET_TX_TC;
-		rtx->txbd[i].cbd_datlen  = 0;	/* Reset */
+		rtx->txbd[i].cbd_sc = BD_ENET_TX_LAST | BD_ENET_TX_TC;
+		rtx->txbd[i].cbd_datlen = 0;	/* Reset */
 		rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]);
 	}
 	rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP;
@@ -273,8 +270,8 @@
 	 */
 
 	/* Half duplex mode */
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
-	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE<<16) | FEC_RCNTRL_MII_MODE;
+	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
+	fecp->fec_r_cntrl = (PKT_MAXBUF_SIZE << 16) | FEC_RCNTRL_MII_MODE;
 	fecp->fec_x_cntrl = 0;
 
 	fecp->fec_mii_speed = 0;
@@ -284,17 +281,16 @@
 	fecp->fec_ecntrl = FEC_ECNTRL_ETHER_EN;
 
 	/* And last, try to fill Rx Buffer Descriptors */
-	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active	*/
+	fecp->fec_r_des_active = 0x01000000;	/* Descriptor polling active    */
 
 	return 1;
 }
 
 
-
-void eth_halt(void)
+void eth_halt (void)
 {
 	volatile fec_t *fecp = FEC_ADDR;
+
 	fecp->fec_ecntrl = 0;
 }
-
 #endif
diff --git a/cpu/coldfire/start.S b/cpu/coldfire/start.S
index 7e02661..4454223 100644
--- a/cpu/coldfire/start.S
+++ b/cpu/coldfire/start.S
@@ -14,7 +14,7 @@
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License
@@ -26,8 +26,8 @@
 #include <config.h>
 #include "version.h"
 
-#ifndef  CONFIG_IDENT_STRING
-#define  CONFIG_IDENT_STRING ""
+#ifndef	 CONFIG_IDENT_STRING
+#define	 CONFIG_IDENT_STRING ""
 #endif
 
 #define MCF_MBAR 0x10000000
@@ -38,30 +38,30 @@
 
 	.text
 
-        .globl  _start
+	.globl	_start
 _start:
 	nop
 	nop
 	move.w #0x2700,%sr
 
-        move.l  #0, %d0
-        movec   %d0, %VBR
+	move.l	#0, %d0
+	movec	%d0, %VBR
 
 #ifdef CONFIG_M5272
-	move.l  #(MCF_MBAR+1), %d0
-        move.c  %d0, %MBAR
+	move.l	#(MCF_MBAR+1), %d0
+	move.c	%d0, %MBAR
 
-	move.l  #(MEM_BUILTIN_ADDR+1), %d0
-        movec   %d0, %RAMBAR0
+	move.l	#(MEM_BUILTIN_ADDR+1), %d0
+	movec	%d0, %RAMBAR0
 
-	move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0xff00c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
 #endif
 
 	move.l	#_sbss,%a0
@@ -71,8 +71,8 @@
 	cmp.l	%a0,%d0
 	bne.s	1b
 
-/*	move.l  #MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
-	move.l  #DRAM_ADDR+DRAM_SIZE, %sp
+/*	move.l	#MEM_BUILTIN_ADDR+MEM_BUILTIN_SIZE, %sp */
+	move.l	#DRAM_ADDR+DRAM_SIZE, %sp
 	clr.l %sp@-
 
 	jsr board_init_f
@@ -107,44 +107,44 @@
 	lea %sp@(60),%sp
 	rte
 
-	.globl  get_endaddr
+	.globl	get_endaddr
 get_endaddr:
 	movel #_end,%d0
 	rts
 
 #ifdef CONFIG_M5272
-	.globl  icache_enable
+	.globl	icache_enable
 icache_enable:
-	move.l  #0x01000000, %d0                /* Invalidate cache cmd */
-        movec   %d0, %CACR                      /* Invalidate cache */
-        move.l  #0x0000c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        move.l  #0xff00c000, %d0                /* Setup cache mask */
-        movec   %d0, %ACR1                      /* Enable cache */
-        move.l  #0x80000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
+	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
+	movec	%d0, %CACR			/* Invalidate cache */
+	move.l	#0x0000c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	move.l	#0xff00c000, %d0		/* Setup cache mask */
+	movec	%d0, %ACR1			/* Enable cache */
+	move.l	#0x80000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
 	moveq	#1, %d0
 	move.l	%d0, icache_state
 	rts
 
-	.globl  icache_disable
+	.globl	icache_disable
 icache_disable:
-        move.l  #0x00000100, %d0                /* Setup cache mask */
-        movec   %d0, %CACR                      /* Enable cache */
-	clr.l   %d0				/* Setup cache mask */
-        movec   %d0, %ACR0                      /* Enable cache */
-        movec   %d0, %ACR1                      /* Enable cache */
+	move.l	#0x00000100, %d0		/* Setup cache mask */
+	movec	%d0, %CACR			/* Enable cache */
+	clr.l	%d0				/* Setup cache mask */
+	movec	%d0, %ACR0			/* Enable cache */
+	movec	%d0, %ACR1			/* Enable cache */
 	moveq	#0, %d0
 	move.l	%d0, icache_state
 	rts
 #endif
 
 #ifdef CONFIG_M5282
-	.globl  icache_enable
+	.globl	icache_enable
 icache_enable:
 	rts
 
-	.globl  icache_disable
+	.globl	icache_disable
 icache_disable:
 	rts
 #endif
@@ -158,7 +158,7 @@
 icache_state:
 	.long	1
 
-	.globl  version_string
+	.globl	version_string
 version_string:
 	.ascii U_BOOT_VERSION
 	.ascii " (", __DATE__, " - ", __TIME__, ")"
diff --git a/cpu/mpc5xxx/fec.c b/cpu/mpc5xxx/fec.c
index 74b786d..e48fa88 100644
--- a/cpu/mpc5xxx/fec.c
+++ b/cpu/mpc5xxx/fec.c
@@ -36,6 +36,33 @@
 } NBUF;
 
 /********************************************************************/
+#if (DEBUG & 0x2)
+static void mpc5xxx_fec_phydump (void)
+{
+	uint16 phyStatus, i;
+	uint8 phyAddr = CONFIG_PHY_ADDR;
+	uint8 reg_mask[] = {
+#if CONFIG_PHY_TYPE == 0x79c874	/* AMD Am79C874 */
+		/* regs to print: 0...7, 16...19, 21, 23, 24 */
+		1, 1, 1, 1,  1, 1, 1, 1,     0, 0, 0, 0,  0, 0, 0, 0,
+		1, 1, 1, 1,  0, 1, 0, 1,     1, 0, 0, 0,  0, 0, 0, 0,
+#else
+		/* regs to print: 0...8, 16...20 */
+		1, 1, 1, 1,  1, 1, 1, 1,     1, 0, 0, 0,  0, 0, 0, 0,
+		1, 1, 1, 1,  1, 0, 0, 0,     0, 0, 0, 0,  0, 0, 0, 0,
+#endif
+	};
+
+	for (i = 0; i < 32; i++) {
+		if (reg_mask[i]) {
+			miiphy_read(phyAddr, i, &phyStatus);
+			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
+		}
+	}
+}
+#endif
+
+/********************************************************************/
 static int mpc5xxx_fec_rbd_init(mpc5xxx_fec_priv *fec)
 {
 	int ix;
@@ -211,7 +238,7 @@
 	DECLARE_GLOBAL_DATA_PTR;
 	mpc5xxx_fec_priv *fec = (mpc5xxx_fec_priv *)dev->priv;
 	struct mpc5xxx_sdma *sdma = (struct mpc5xxx_sdma *)MPC5XXX_SDMA;
-	const uint8 phyAddr = 0;	/* Only one PHY */
+	const uint8 phyAddr = CONFIG_PHY_ADDR;	/* Only one PHY */
 
 #if (DEBUG & 0x1)
 	printf ("mpc5xxx_fec_init... Begin\n");
@@ -472,21 +499,11 @@
 	 */
 	fec->eth->ecntrl |= 0x00000006;
 
-	if (fec->xcv_type != SEVENWIRE) {
 #if (DEBUG & 0x2)
-		uint16 phyStatus, i;
-		uint8 phyAddr = 0;
-
-		for (i = 0; i < 9; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-		for (i = 16; i < 21; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
+	if (fec->xcv_type != SEVENWIRE)
+		mpc5xxx_fec_phydump ();
 #endif
-	}
+
 	/*
 	 * Enable SmartDMA receive task
 	 */
@@ -509,22 +526,10 @@
 	int counter = 0xffff;
 
 #if (DEBUG & 0x2)
-	if (fec->xcv_type != SEVENWIRE) {
-		uint16 phyStatus, i;
-		uint8 phyAddr = 0;
-
-		for (i = 0; i < 9; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-		for (i = 16; i < 21; i++) {
-			miiphy_read(phyAddr, i, &phyStatus);
-			printf ("Mii reg %d: 0x%04x\n", i, phyStatus);
-		}
-	}
+	if (fec->xcv_type != SEVENWIRE)
+		mpc5xxx_fec_phydump ();
 #endif
 
-
 	/*
 	 * mask FEC chip interrupts
 	 */
@@ -587,7 +592,7 @@
 
 static void tfifo_print(mpc5xxx_fec_priv *fec)
 {
-	uint16 phyAddr = 0;
+	uint16 phyAddr = CONFIG_PHY_ADDR;
 	uint16 phyStatus;
 
 	if ((fec->eth->tfifo_lrf_ptr != fec->eth->tfifo_lwf_ptr)
@@ -611,7 +616,7 @@
 
 static void rfifo_print(mpc5xxx_fec_priv *fec)
 {
-	uint16 phyAddr = 0;
+	uint16 phyAddr = CONFIG_PHY_ADDR;
 	uint16 phyStatus;
 
 	if ((fec->eth->rfifo_lrf_ptr != fec->eth->rfifo_lwf_ptr)
@@ -825,12 +830,12 @@
 	fec->eth = (ethernet_regs *)MPC5XXX_FEC;
 	fec->tbdBase = (FEC_TBD *)FEC_BD_BASE;
 	fec->rbdBase = (FEC_RBD *)(FEC_BD_BASE + FEC_TBD_NUM * sizeof(FEC_TBD));
-#ifdef CONFIG_ICECUBE
-#ifndef CONFIG_FEC_10MBIT
+#if defined(CONFIG_ICECUBE) || defined(CONFIG_TOP5200)
+#  ifndef CONFIG_FEC_10MBIT
 	fec->xcv_type = MII100;
-#else
+#  else
 	fec->xcv_type = MII10;
-#endif
+#  endif
 #else
 #error fec->xcv_type not initialized.
 #endif
diff --git a/cpu/mpc5xxx/start.S b/cpu/mpc5xxx/start.S
index e0873ed..a001e1c 100644
--- a/cpu/mpc5xxx/start.S
+++ b/cpu/mpc5xxx/start.S
@@ -118,18 +118,12 @@
 	ori	r3, r3, 0x02010000@l
 	stw	r3, 0x54(r4)
 
-#if defined(CFG_LOWBOOT08)
-	lis	r3,     0xff800160@h
-	ori	r3, r3, 0xff800160@l
-#endif
-#if defined(CFG_LOWBOOT16)
-	lis	r3,     0xff000160@h
-	ori	r3, r3, 0xff000160@l
-#endif
+	lis     r3,	lowboot_reentry@h
+	ori     r3, r3, lowboot_reentry@l
 	mtlr	r3
-	blr
-lowboot_reentry:	/* FLASH_BASE + 0x160 */
-	
+	blr				/* jump to flash based address */
+
+lowboot_reentry:
 	lis	r3,     0x0000FF00@h
 	ori	r3, r3, 0x0000FF00@l
 	stw	r3, 0x4c(r4)
@@ -143,7 +137,7 @@
 	ori	r3, r3, 0x02000001@l
 	stw	r3, 0x54(r4)
 #endif	/* CFG_LOWBOOT */
-	
+
 #if defined(CFG_DEFAULT_MBAR) && !defined(CFG_RAMBOOT)
 	lis	r3, CFG_MBAR@h
 	ori	r3, r3, CFG_MBAR@l
diff --git a/cpu/mpc8xx/speed.c b/cpu/mpc8xx/speed.c
index 12ef82b..3815537 100644
--- a/cpu/mpc8xx/speed.c
+++ b/cpu/mpc8xx/speed.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -160,7 +160,7 @@
 	timerp->cpmt_tgcr &= ~(TGCR_RST2 | TGCR_FRZ2 | TGCR_STP2);
 	immr->im_sit.sit_piscr &= ~PISCR_PTE;
 
-#ifdef CONFIG_MPC866_et_al
+#if defined(CONFIG_MPC866_et_al)
 	/* not using OSCM, using XIN, so scale appropriately */
 	return (((timer2_val + 2) / 4) * (CFG_8XX_XIN/512))/8192 * 100000L;
 #else
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c
index 1a9ae9d..974797f 100644
--- a/cpu/ppc4xx/interrupts.c
+++ b/cpu/ppc4xx/interrupts.c
@@ -92,7 +92,7 @@
 
 	/* decrementer is automatically reloaded */
 	*decrementer_count = 0;
-	
+
 	/*
 	 * Mark all irqs as free
 	 */
diff --git a/drivers/rtl8019.h b/drivers/rtl8019.h
index b53e142..38116ad 100644
--- a/drivers/rtl8019.h
+++ b/drivers/rtl8019.h
@@ -115,21 +115,3 @@
 
 
 #endif /*end of CONFIG_DRIVER_RTL8019*/
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
diff --git a/include/asm-m68k/ptrace.h b/include/asm-m68k/ptrace.h
index 343a9f4..8205518 100644
--- a/include/asm-m68k/ptrace.h
+++ b/include/asm-m68k/ptrace.h
@@ -105,4 +105,3 @@
 #define PT_FPSCR (PT_FPR0 + 2*32 + 1)
 
 #endif
-
diff --git a/include/asm-m68k/u-boot.h b/include/asm-m68k/u-boot.h
index eaf1de7..b414490 100644
--- a/include/asm-m68k/u-boot.h
+++ b/include/asm-m68k/u-boot.h
@@ -39,9 +39,9 @@
 	unsigned long	bi_sramstart;	/* start of SRAM memory */
 	unsigned long	bi_sramsize;	/* size	 of SRAM memory */
 	unsigned long	bi_bootflags;	/* boot / reboot flag (for LynxOS) */
-        unsigned long   bi_boot_params; /* where this board expects params */
+	unsigned long	bi_boot_params; /* where this board expects params */
 	unsigned long	bi_ip_addr;	/* IP Address */
-	unsigned char	bi_enetaddr[6];	/* Ethernet adress */
+	unsigned char	bi_enetaddr[6]; /* Ethernet adress */
 	unsigned short	bi_ethspeed;	/* Ethernet speed in Mbps */
 	unsigned long	bi_intfreq;	/* Internal Freq, in MHz */
 	unsigned long	bi_busfreq;	/* Bus Freq, in MHz */
@@ -56,11 +56,11 @@
  *
  * Keep it *SMALL* and remember to set CFG_INIT_DATA_SIZE > sizeof(init_data_t)
  */
-typedef	struct	init_data {
+typedef struct	init_data {
 	unsigned long	cpu_clk;	/* VCOOUT = CPU clock in Hz!		*/
 	unsigned long	env_addr;	/* Address  of Environment struct	*/
 	unsigned long	env_valid;	/* Checksum of Environment valid?	*/
-	unsigned long	relocated;	/* Relocat. offset when running in RAM 	*/
+	unsigned long	relocated;	/* Relocat. offset when running in RAM	*/
 	unsigned long	have_console;	/* serial_init() was called		*/
 #ifdef CONFIG_LCD
 	unsigned long	lcd_base;	/* Base address of LCD frambuffer mem	*/
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
index 1fd00cc..845dd7c 100644
--- a/include/asm-mips/addrspace.h
+++ b/include/asm-mips/addrspace.h
@@ -14,21 +14,21 @@
 /*
  * Memory segments (32bit kernel mode addresses)
  */
-#define KUSEG                   0x00000000
-#define KSEG0                   0x80000000
-#define KSEG1                   0xa0000000
-#define KSEG2                   0xc0000000
-#define KSEG3                   0xe0000000
+#define KUSEG			0x00000000
+#define KSEG0			0x80000000
+#define KSEG1			0xa0000000
+#define KSEG2			0xc0000000
+#define KSEG3			0xe0000000
 
-#define K0BASE  KSEG0
+#define K0BASE	KSEG0
 
 /*
  * Returns the kernel segment base of a given address
  */
 #ifndef __ASSEMBLY__
-#define KSEGX(a)                (((unsigned long)(a)) & 0xe0000000)
+#define KSEGX(a)		(((unsigned long)(a)) & 0xe0000000)
 #else
-#define KSEGX(a)                ((a) & 0xe0000000)
+#define KSEGX(a)		((a) & 0xe0000000)
 #endif
 
 /*
@@ -40,8 +40,8 @@
 #define PHYSADDR(a)		((a) & 0x1fffffff)
 #endif
 
-/* 
- * Returns the uncached address of a sdram address 
+/*
+ * Returns the uncached address of a sdram address
  */
 #ifndef __ASSEMBLY__
 #ifdef CONFIG_AU1X00
@@ -49,7 +49,7 @@
    cannot access physical memory directly from core */
 #define UNCACHED_SDRAM(a) (((unsigned long)(a)) | 0x20000000)
 #else	/* !CONFIG_AU1X00 */
-#define UNCACHED_SDRAM(a) PHYSADDR(a) 
+#define UNCACHED_SDRAM(a) PHYSADDR(a)
 #endif	/* CONFIG_AU1X00 */
 #endif	/* __ASSEMBLY__ */
 /*
@@ -70,13 +70,13 @@
 /*
  * Memory segments (64bit kernel mode addresses)
  */
-#define XKUSEG                  0x0000000000000000
-#define XKSSEG                  0x4000000000000000
-#define XKPHYS                  0x8000000000000000
-#define XKSEG                   0xc000000000000000
-#define CKSEG0                  0xffffffff80000000
-#define CKSEG1                  0xffffffffa0000000
-#define CKSSEG                  0xffffffffc0000000
-#define CKSEG3                  0xffffffffe0000000
+#define XKUSEG			0x0000000000000000
+#define XKSSEG			0x4000000000000000
+#define XKPHYS			0x8000000000000000
+#define XKSEG			0xc000000000000000
+#define CKSEG0			0xffffffff80000000
+#define CKSEG1			0xffffffffa0000000
+#define CKSSEG			0xffffffffc0000000
+#define CKSEG3			0xffffffffe0000000
 
 #endif /* __ASM_MIPS_ADDRSPACE_H */
diff --git a/include/common.h b/include/common.h
index ece5d64..73a5a2e 100644
--- a/include/common.h
+++ b/include/common.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -49,11 +49,11 @@
 #ifdef CONFIG_MPC860T
 #define CONFIG_MPC86x 1
 #endif
-#if defined(CONFIG_MPC866P) || \
-    defined(CONFIG_MPC866T) || \
-    defined(CONFIG_MPC859T) || \
-    defined(CONFIG_MPC859DSL) || \
-    defined(CONFIG_MPC852T)
+#if defined(CONFIG_MPC852)	|| defined(CONFIG_MPC852T)	|| \
+    defined(CONFIG_MPC859)	|| defined(CONFIG_MPC859T)	|| \
+    defined(CONFIG_MPC859DSL)	|| \
+    defined(CONFIG_MPC866)	|| defined(CONFIG_MPC866T)	|| \
+    defined(CONFIG_MPC866P)
 #define CONFIG_MPC866_et_al 1
 #define CONFIG_MPC86x 1
 #endif
@@ -100,7 +100,7 @@
  */
 #if defined(CONFIG_TQM823M) || defined(CONFIG_TQM850M) || \
     defined(CONFIG_TQM855M) || defined(CONFIG_TQM860M) || \
-    defined(CONFIG_TQM862M)
+    defined(CONFIG_TQM862M) || defined(CONFIG_TQM866M)
 # ifndef CONFIG_TQM8xxM
 #  define CONFIG_TQM8xxM
 # endif
diff --git a/include/commproc.h b/include/commproc.h
index 3da804f..8bab522 100644
--- a/include/commproc.h
+++ b/include/commproc.h
@@ -2,6 +2,9 @@
  * MPC8xx Communication Processor Module.
  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
  *
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
  * This file contains structures and information for the communication
  * processor channels.  Some CPM control and status is available
  * throught the MPC8xx internal memory map.  See immap.h for details.
@@ -1430,11 +1433,12 @@
 #define SICR_ENET_CLKRT	((uint)0x00002600)
 #endif	/* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */
 
-/***  TQM855L/M, TQM860L/M, TQM862L/M  ********************************/
+/***  TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M  *********************/
 
 #if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \
     defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \
-    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M)
+    defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \
+    defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M)
 
 # ifdef CONFIG_SCC1_ENET	/* use SCC for 10Mbps Ethernet	*/
 
diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h
index 2f0a875..194f62f 100644
--- a/include/configs/IceCube.h
+++ b/include/configs/IceCube.h
@@ -215,6 +215,7 @@
  */
 #define CONFIG_MPC5XXX_FEC	1
 #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */
+#define CONFIG_PHY_ADDR		0x00
 
 /*
  * GPIO configuration
diff --git a/include/configs/MVBLUE.h b/include/configs/MVBLUE.h
index 6965e1c..32f9e91 100644
--- a/include/configs/MVBLUE.h
+++ b/include/configs/MVBLUE.h
@@ -53,7 +53,7 @@
 #define ERR_LED(code)
 #endif
 
-#undef DEBUG 
+#undef DEBUG
 
 #define CONFIG_MPC824X		1
 #define CONFIG_MPC8245		1
@@ -71,14 +71,14 @@
 #define CONFIG_BOOT_RETRY_TIME	-1
 
 #define CONFIG_AUTOBOOT_KEYED
-#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds (stop with 's')...\n\0"
-#define CONFIG_AUTOBOOT_STOP_STR	"s\0"
+#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds (stop with 's')...\n"
+#define CONFIG_AUTOBOOT_STOP_STR	"s"
 #define CONFIG_ZERO_BOOTDELAY_CHECK
 #define CONFIG_RESET_TO_RETRY		60
 
 #define CONFIG_COMMANDS		( CFG_CMD_ASKENV | CFG_CMD_BOOTD | CFG_CMD_CACHE | CFG_CMD_DHCP	| \
-							  CFG_CMD_ECHO	 | CFG_CMD_ENV   | CFG_CMD_FLASH | CFG_CMD_IMI	| \
-							  CFG_CMD_IRQ	 | CFG_CMD_NET	 | CFG_CMD_PCI	 | CFG_CMD_RUN   )  
+				  CFG_CMD_ECHO	 | CFG_CMD_ENV   | CFG_CMD_FLASH | CFG_CMD_IMI	| \
+				  CFG_CMD_IRQ	 | CFG_CMD_NET	 | CFG_CMD_PCI	 | CFG_CMD_RUN   )
 
 
 #define CONFIG_BOOTP_MASK   ( 0xffffffff )
@@ -103,19 +103,19 @@
 
 #define CONFIG_NFSBOOTCOMMAND  	"bootp; run nfsargs addcons;bootm"
 
-#define CONFIG_EXTRA_ENV_SETTINGS                   \
-	"console_nr=0\0"								\
-    "dhcp_client_id=mvBOX-XP\0"                     \
-    "dhcp_vendor-class-identifier=mvBOX\0"          \
-    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0" 	\
-    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0" 	\
-    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0" 	\
-    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0" 								\
-	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "				\
-			"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"			\
-	"addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0"	\
+#define CONFIG_EXTRA_ENV_SETTINGS			\
+	"console_nr=0\0"				\
+    "dhcp_client_id=mvBOX-XP\0"				\
+    "dhcp_vendor-class-identifier=mvBOX\0"		\
+    "adminboot=setenv bootargs root=/dev/mtdblock5 rw rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "flashboot=setenv bootargs root=/dev/mtdblock5 ro rootfstype=jffs2;run addcons;bootm ffc00000\0"	\
+    "safeboot=setenv bootargs root=/dev/mtdblock2 rw rootfstype=cramfs;run addcons;bootm ffc00000\0"	\
+    "hdboot=setenv bootargs root=/dev/hda1;run addcons;bootm ffc00000\0"	\
+	"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "	\
+			"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off\0"	\
+	"addcons=setenv bootargs $(bootargs) console=ttyS$(console_nr),$(baudrate)N8\0" \
     "mv_version=" MV_VERSION "\0"	\
-	"bootretry=30\0"			
+	"bootretry=30\0"
 
 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 
@@ -124,11 +124,11 @@
  *-----------------------------------------------------------------------
  */
 
-#define CONFIG_PCI      	
+#define CONFIG_PCI
 #define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 
-#define CONFIG_NET_MULTI	
+#define CONFIG_NET_MULTI
 #define CONFIG_NET_RETRY_COUNT 5
 
 #define CONFIG_TULIP
@@ -144,8 +144,8 @@
  */
 #define CFG_SDRAM_BASE	    0x00000000
 
-#define CFG_FLASH_BASE      0xFFF00000  
-#define CFG_MONITOR_BASE    TEXT_BASE    
+#define CFG_FLASH_BASE      0xFFF00000
+#define CFG_MONITOR_BASE    TEXT_BASE
 
 #define CFG_RESET_ADDRESS   0xFFF00100
 #define CFG_EUMB_ADDR	    0xFC000000
@@ -196,7 +196,7 @@
  * For the detail description refer to the MPC8240 user's manual.
  */
 
-#define CONFIG_SYS_CLK_FREQ  33000000	
+#define CONFIG_SYS_CLK_FREQ  33000000
 #define CFG_HZ		     	 10000
 
 /* Bit-field values for MCCR1.  */
@@ -205,17 +205,17 @@
 
 /* Bit-field values for MCCR2.  */
 #define CFG_TSWAIT      0x5
-#define CFG_REFINT      430   
+#define CFG_REFINT      430
 
 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.  */
-#define CFG_BSTOPRE     121 
+#define CFG_BSTOPRE     121
 
 /* Bit-field values for MCCR3.  */
 #define CFG_REFREC      8
 
 /* Bit-field values for MCCR4.  */
-#define CFG_PRETOACT    3  
-#define CFG_ACTTOPRE    5     
+#define CFG_PRETOACT    3
+#define CFG_ACTTOPRE    5
 #define CFG_ACTORW      3
 #define CFG_SDMODE_CAS_LAT  3
 #define CFG_REGISTERD_TYPE_BUFFER 1
@@ -292,7 +292,7 @@
 /*-----------------------------------------------------------------------
  * FLASH organization
  */
-#undef  CFG_FLASH_PROTECTION    
+#undef  CFG_FLASH_PROTECTION
 #define CFG_MAX_FLASH_BANKS		1	/* Max number of flash banks		*/
 #define CFG_MAX_FLASH_SECT		63	/* Max number of sectors per flash	*/
 
@@ -300,11 +300,11 @@
 #define CFG_FLASH_WRITE_TOUT	1000
 
 
-#define CFG_ENV_IS_IN_FLASH	    
+#define CFG_ENV_IS_IN_FLASH
 
 #define CFG_ENV_OFFSET		0x00010000
-#define CFG_ENV_SIZE        0x00010000 
-#define CFG_ENV_SECT_SIZE	0x00010000 
+#define CFG_ENV_SIZE		0x00010000
+#define CFG_ENV_SECT_SIZE	0x00010000
 
 /*-----------------------------------------------------------------------
  * Cache Configuration
diff --git a/include/configs/QS860T.h b/include/configs/QS860T.h
index 92eccd3..8d29a31 100644
--- a/include/configs/QS860T.h
+++ b/include/configs/QS860T.h
@@ -47,7 +47,6 @@
 #define CONFIG_ENV_OVERWRITE	1	/* allow overwrite MAC address */
 
 
-
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -368,7 +367,6 @@
 /* #define CFG_BR5		0xE4000000 */
 
 
-
 /*
  * BR6 and OR6 (Expansion bus)
  * Base address = 0xE800_0000 - 0xEBFF_FFFF
@@ -381,7 +379,6 @@
 /* #define CFG_BR6		0xE8000000 */
 
 
-
 /*
  * BR7 and OR7 (Expansion bus)
  * Base address = 0xEC00_0000 - 0xEFFF_FFFF
@@ -394,7 +391,6 @@
 /* #define CFG_BR7		0xE8000000 */
 
 
-
 /*
  * Internal Definitions
  *
diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h
index 21daa2d..624beed 100644
--- a/include/configs/TOP5200.h
+++ b/include/configs/TOP5200.h
@@ -1,16 +1,17 @@
 /*
  * (C) Copyright 2003
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * modified for TOP5200 by Reinhard Meyer, www.emk-elektronik.de
- * TOP5200 differences from IceCube:
- * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
- *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
- * 1 SDRAM/DDRAM Bank up to 256 MB
- * local VPD I2C Bus is software driven and uses
- *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
- * FLASH is located at 0x80000000
- * Internal regs are at 0xfff00000
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * modified for TOP5200-series by Reinhard Meyer, www.emk-elektronik.de
+ *
+ * TOP5200 differences from IceCube:
+ * 1 FLASH Bank for one Chip only, up to 64 MB in 16 MB Banks
+ *   bank switch controlled by TIMER_6(LSB) and TIMER_7(MSB) Pins
+ * 1 SDRAM/DDRAM Bank up to 256 MB
+ * local VPD I2C Bus is software driven and uses
+ *   GPIO_WKUP_6 for SDA, GPIO_WKUP_7 for SCL
+ * FLASH is re-located at 0xff000000
+ * Internal regs are at 0xf0000000
  * Reset jumps to 0x00000100
  *
  * See file CREDITS for list of people who contributed to this
@@ -44,7 +45,7 @@
 #define CONFIG_MPC5200		1	/* More exactly a MPC5200 */
 #define CONFIG_TOP5200		1	/* ... on TOP5200 board - we need this for FEC.C */
 
-#define CFG_MPC5XXX_CLKIN	33333333 /* ... running at 33MHz */
+#define CFG_MPC5XXX_CLKIN	33000000 /* ... running at 33.000000MHz */
 
 #define BOOTFLAG_COLD		0x01	/* Normal Power-On: Boot from FLASH  */
 #define BOOTFLAG_WARM		0x02	/* Software reboot	     */
@@ -98,17 +99,48 @@
 #include <cmd_confdefs.h>
 
 /*
+ * low boot
+ */
+#if (TEXT_BASE == 0xFF000000)		/* Boot low with 16 MB Flash */
+#   define CFG_LOWBOOT		1
+#   define CFG_LOWBOOT16	1
+#endif
+
+/*
  * Autobooting
  */
 #define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds */
-#define CONFIG_BOOTCOMMAND	"bootm 100000"	/* autoboot command */
-#define CONFIG_BOOTARGS		"root=/dev/ram rw"
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_82xx\0"					\
+	"bootfile=/tftpboot/MPC5200/uImage\0"				\
+	""
+
+#define CONFIG_BOOTCOMMAND	"run flash_self"
 
 /*
  * IPB Bus clocking configuration.
  */
 #undef CFG_IPBSPEED_133   		/* define for 133MHz speed */
-
+
 /*
  * I2C configuration
  */
@@ -120,21 +152,21 @@
 
 #define CFG_I2C_EEPROM_ADDR_LEN 2
 #define CFG_EEPROM_SIZE 0x2000
-
+
 #define CONFIG_ENV_OVERWRITE
 #define CONFIG_MISC_INIT_R
-
+
 #undef	CONFIG_HARD_I2C			/* I2C with hardware support */
 #define	CONFIG_SOFT_I2C		1
-
+
 #if defined (CONFIG_SOFT_I2C)
 #  define SDA0			0x40
 #  define SCL0			0x80
-#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
-#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
-#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
-#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
-#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
+#  define GPIOE0		*((volatile uchar*)(CFG_MBAR+0x0c00))
+#  define DDR0			*((volatile uchar*)(CFG_MBAR+0x0c08))
+#  define DVO0			*((volatile uchar*)(CFG_MBAR+0x0c0c))
+#  define DVI0			*((volatile uchar*)(CFG_MBAR+0x0c20))
+#  define ODE0			*((volatile uchar*)(CFG_MBAR+0x0c04))
 #  define I2C_INIT		{GPIOE0|=(SDA0|SCL0);ODE0|=(SDA0|SCL0);DVO0|=(SDA0|SCL0);DDR0|=(SDA0|SCL0);}
 #  define I2C_READ		((DVI0&SDA0)?1:0)
 #  define I2C_SDA(x)	{if(x)DVO0|=SDA0;else DVO0&=~SDA0;}
@@ -145,12 +177,12 @@
 #  define CFG_I2C_SPEED		100000
 #  define CFG_I2C_SLAVE		0x7F
 #endif
-
-#if defined (CONFIG_HARD_I2C)
+
+#if defined (CONFIG_HARD_I2C)
 #  define CFG_I2C_MODULE	2		/* Select I2C module #1 or #2 */
 #  define CFG_I2C_SPEED		100000	/* 100 kHz */
 #  define CFG_I2C_SLAVE		0x7F
-#endif
+#endif
 
 /*
  * Flash configuration, expect one 16 Megabyte Bank at most
@@ -158,7 +190,7 @@
 #define CFG_FLASH_BASE		0xff000000
 #define CFG_FLASH_SIZE		0x01000000
 #define CFG_MAX_FLASH_BANKS	1	/* max num of memory banks      */
-#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)
+#define CFG_ENV_ADDR		(CFG_FLASH_BASE + 0)
 
 #define CFG_MAX_FLASH_SECT	256	/* max num of sects on one chip */
 
@@ -167,32 +199,32 @@
 
 #undef CONFIG_FLASH_16BIT	/* Flash is 8-bit */
 
-/*
- * DRAM configuration - will be read from VPD later... TODO!
- */
-#if 0
-/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x008D
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xC2233A00
-#define CFG_DRAM_CONFIG2	0x88B70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
-#endif
-#if 1
-/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
-#define	CFG_DRAM_DDR		0
-#define CFG_DRAM_EMODE		0
-#define CFG_DRAM_MODE		0x00CD
-#define CFG_DRAM_CONTROL	0x514F0000
-#define CFG_DRAM_CONFIG1	0xD2333A00
-#define CFG_DRAM_CONFIG2	0x8AD70004
-#define	CFG_DRAM_TAP_DEL	0x08
-#define CFG_DRAM_RAM_SIZE	0x19
-#endif
-
+/*
+ * DRAM configuration - will be read from VPD later... TODO!
+ */
+#if 0
+/* 2x MT48LC16M16A2 - 7.0 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x008D
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xC2233A00
+#define CFG_DRAM_CONFIG2	0x88B70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+#if 1
+/* 2x MT48LC16M16A2 - 7.5 ns SDRAMS = 64 MegaBytes Total */
+#define	CFG_DRAM_DDR		0
+#define CFG_DRAM_EMODE		0
+#define CFG_DRAM_MODE		0x00CD
+#define CFG_DRAM_CONTROL	0x514F0000
+#define CFG_DRAM_CONFIG1	0xD2333A00
+#define CFG_DRAM_CONFIG2	0x8AD70004
+#define	CFG_DRAM_TAP_DEL	0x08
+#define CFG_DRAM_RAM_SIZE	0x19
+#endif
+
 /*
  * Environment settings
  */
@@ -201,17 +233,17 @@
 #define CFG_ENV_SIZE		0x0700
 #define CFG_I2C_EEPROM_ADDR 0x57
 
-/*
- * VPD settings
- */
+/*
+ * VPD settings
+ */
 #define CFG_FACT_OFFSET		0x1800
 #define CFG_FACT_SIZE		0x0800
 #define CFG_I2C_FACT_ADDR	0x57
-
+
 /*
- * Memory map
- *
- * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
+ * Memory map
+ *
+ * Warning!!! with the current BestComm Task, MBAR MUST BE set to 0xf0000000
  */
 #define CFG_MBAR			0xf0000000	/* DO NOT CHANGE this */
 #define CFG_SDRAM_BASE		0x00000000
@@ -240,12 +272,12 @@
  */
 #define CONFIG_MPC5XXX_FEC	1
 #define CONFIG_FEC_10MBIT	1		/* Workaround for FEC 100Mbit problem */
-#define	CONFIG_PHY_ADDR		0x1f
+#define	CONFIG_PHY_ADDR		0x1f
 #define	CONFIG_PHY_TYPE		0x79c874
 /*
- * GPIO configuration:
- * PSC1,2,3 predefined as UART
- * PCI disabled
+ * GPIO configuration:
+ * PSC1,2,3 predefined as UART
+ * PCI disabled
  * Ethernet 100 with MD
  */
 #define CFG_GPS_PORT_CONFIG	0x00058444
diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h
index e926d93..cb4a16a 100644
--- a/include/configs/TQM855M.h
+++ b/include/configs/TQM855M.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2003
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -83,6 +83,39 @@
 
 #undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
 
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C64	*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
+#if 0
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* takes up to 10 msec	*/
+#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01
+#define CFG_EEPROM_PAGE_WRITE_BITS	5
+#endif
+
 #define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
 
 #define CONFIG_MAC_PARTITION
@@ -93,6 +126,7 @@
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_ASKENV	| \
 				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
 				CFG_CMD_IDE	| \
 				CFG_CMD_DATE	)
 
diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h
new file mode 100644
index 0000000..0219836
--- /dev/null
+++ b/include/configs/TQM866M.h
@@ -0,0 +1,526 @@
+/*
+ * (C) Copyright 2000-2003
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * board/config.h - configuration options, board specific
+ */
+
+#ifndef __CONFIG_H
+#define __CONFIG_H
+
+/*
+ * High Level Configuration Options
+ * (easy to change)
+ */
+
+#define CONFIG_MPC866		1	/* This is a MPC866 CPU		*/
+#define CONFIG_TQM866M		1	/* ...on a TQM8xxM module	*/
+
+#define	CFG_8XX_XIN	10000000 /* XXX XXX XXX */
+
+#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
+#undef	CONFIG_8xx_CONS_SMC2
+#undef	CONFIG_8xx_CONS_NONE
+
+#define CONFIG_BAUDRATE		115200	/* console baudrate = 115kbps	*/
+
+#define	CONFIG_BOOTCOUNT_LIMIT
+
+#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
+
+#define CONFIG_BOARD_TYPES	1	/* support board types		*/
+
+#define CONFIG_PREBOOT	"echo;"	\
+	"echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
+	"echo"
+
+#undef	CONFIG_BOOTARGS
+
+#define	CONFIG_EXTRA_ENV_SETTINGS					\
+	"netdev=eth0\0"							\
+	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
+		"nfsroot=$(serverip):$(rootpath)\0"			\
+	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
+	"addip=setenv bootargs $(bootargs) "				\
+		"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"	\
+		":$(hostname):$(netdev):off panic=1\0"			\
+	"flash_nfs=run nfsargs addip;"					\
+		"bootm $(kernel_addr)\0"				\
+	"flash_self=run ramargs addip;"					\
+		"bootm $(kernel_addr) $(ramdisk_addr)\0"		\
+	"net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0"	\
+	"rootpath=/opt/eldk/ppc_8xx\0"					\
+	"bootfile=/tftpboot/TQM855M/uImage\0"				\
+	"kernel_addr=40080000\0"					\
+	"ramdisk_addr=40180000\0"					\
+	""
+#define CONFIG_BOOTCOMMAND	"run flash_self"
+
+#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
+#undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
+
+#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
+
+#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
+
+#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/
+
+/* enable I2C and select the hardware/software driver */
+#undef	CONFIG_HARD_I2C			/* I2C with hardware support	*/
+#define	CONFIG_SOFT_I2C         1	/* I2C bit-banged		*/
+
+#define CFG_I2C_SPEED		93000	/* 93 kHz is supposed to work	*/
+#define CFG_I2C_SLAVE		0xFE
+
+#ifdef CONFIG_SOFT_I2C
+/*
+ * Software (bit-bang) I2C driver configuration
+ */
+#define PB_SCL		0x00000020	/* PB 26 */
+#define PB_SDA		0x00000010	/* PB 27 */
+
+#define I2C_INIT	(immr->im_cpm.cp_pbdir |=  PB_SCL)
+#define I2C_ACTIVE	(immr->im_cpm.cp_pbdir |=  PB_SDA)
+#define I2C_TRISTATE	(immr->im_cpm.cp_pbdir &= ~PB_SDA)
+#define I2C_READ	((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
+#define I2C_SDA(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SDA
+#define I2C_SCL(bit)	if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
+			else    immr->im_cpm.cp_pbdat &= ~PB_SCL
+#define I2C_DELAY	udelay(2)	/* 1/4 I2C clock duration */
+#endif	/* CONFIG_SOFT_I2C */
+
+#define CFG_I2C_EEPROM_ADDR	0x50		/* EEPROM AT24C256	*/
+#define CFG_I2C_EEPROM_ADDR_LEN	2		/* two byte address	*/
+#define CFG_EEPROM_PAGE_WRITE_BITS	4
+#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10	/* and takes up to 10 msec */
+
+#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
+
+#define CONFIG_MAC_PARTITION
+#define CONFIG_DOS_PARTITION
+
+#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
+
+#define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
+				CFG_CMD_ASKENV	| \
+				CFG_CMD_DHCP	| \
+				CFG_CMD_EEPROM	| \
+				CFG_CMD_IDE	| \
+				CFG_CMD_I2C	| \
+				CFG_CMD_DATE	)
+
+/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
+#include <cmd_confdefs.h>
+
+/*
+ * Miscellaneous configurable options
+ */
+#define	CFG_LONGHELP			/* undef to save memory		*/
+#define	CFG_PROMPT		"=> "	/* Monitor Command Prompt	*/
+
+#if 0
+#define	CFG_HUSH_PARSER		1	/* use "hush" command parser	*/
+#endif
+#ifdef	CFG_HUSH_PARSER
+#define	CFG_PROMPT_HUSH_PS2	"> "
+#endif
+
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define	CFG_CBSIZE		1024	/* Console I/O Buffer Size	*/
+#else
+#define	CFG_CBSIZE		256	/* Console I/O Buffer Size	*/
+#endif
+#define	CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
+#define	CFG_MAXARGS		16	/* max number of command args	*/
+#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
+
+#define CFG_MEMTEST_START	0x0400000	/* memtest works on	*/
+#define CFG_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/
+
+#define	CFG_LOAD_ADDR		0x100000	/* default load address	*/
+
+#define	CFG_HZ			1000	/* decrementer freq: 1 ms ticks	*/
+
+#define CFG_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
+
+/*
+ * Low Level Configuration Settings
+ * (address mappings, register initial values, etc.)
+ * You should know what you are doing if you make changes here.
+ */
+/*-----------------------------------------------------------------------
+ * Internal Memory Mapped Register
+ */
+#define CFG_IMMR		0xFFF00000
+
+/*-----------------------------------------------------------------------
+ * Definitions for initial stack pointer and data area (in DPRAM)
+ */
+#define CFG_INIT_RAM_ADDR	CFG_IMMR
+#define	CFG_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
+#define	CFG_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
+#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
+#define	CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET
+
+/*-----------------------------------------------------------------------
+ * Start addresses for the final memory configuration
+ * (Set up by the startup code)
+ * Please note that CFG_SDRAM_BASE _must_ start at 0
+ */
+#define	CFG_SDRAM_BASE		0x00000000
+#define CFG_FLASH_BASE		0x40000000
+#define	CFG_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
+#define CFG_MONITOR_BASE	CFG_FLASH_BASE
+#define	CFG_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/
+
+/*
+ * For booting Linux, the board info and command line data
+ * have to be in the first 8 MB of memory, since this is
+ * the maximum mapped by the Linux kernel during initialization.
+ */
+#define	CFG_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/
+
+/*-----------------------------------------------------------------------
+ * FLASH organization
+ */
+#define CFG_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
+#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/
+
+#define CFG_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
+#define CFG_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/
+
+#define	CFG_ENV_IS_IN_FLASH	1
+#define	CFG_ENV_OFFSET		0x40000	/*   Offset   of Environment Sector	*/
+#define	CFG_ENV_SIZE		0x08000	/* Total Size of Environment Sector	*/
+#define	CFG_ENV_SECT_SIZE	0x20000	/* Total Size of Environment Sector	*/
+
+/* Address and size of Redundant Environment Sector	*/
+#define CFG_ENV_OFFSET_REDUND	(CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE)
+#define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
+
+/*-----------------------------------------------------------------------
+ * Hardware Information Block
+ */
+#define CFG_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
+#define CFG_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
+#define CFG_HWINFO_MAGIC	0x54514D38	/* 'TQM8' */
+
+/*-----------------------------------------------------------------------
+ * Cache Configuration
+ */
+#define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
+#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
+#endif
+
+/*-----------------------------------------------------------------------
+ * SYPCR - System Protection Control				11-9
+ * SYPCR can only be written once after reset!
+ *-----------------------------------------------------------------------
+ * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
+ */
+#if defined(CONFIG_WATCHDOG)
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
+			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
+#else
+#define CFG_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
+#endif
+
+/*-----------------------------------------------------------------------
+ * SIUMCR - SIU Module Configuration				11-6
+ *-----------------------------------------------------------------------
+ * PCMCIA config., multi-function pin tri-state
+ */
+#ifndef	CONFIG_CAN_DRIVER
+#define CFG_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#else	/* we must activate GPL5 in the SIUMCR for CAN */
+#define CFG_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*-----------------------------------------------------------------------
+ * TBSCR - Time Base Status and Control				11-26
+ *-----------------------------------------------------------------------
+ * Clear Reference Interrupt Status, Timebase freezing enabled
+ */
+#define CFG_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
+
+/*-----------------------------------------------------------------------
+ * RTCSC - Real-Time Clock Status and Control Register		11-27
+ *-----------------------------------------------------------------------
+ */
+#define CFG_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
+
+/*-----------------------------------------------------------------------
+ * PISCR - Periodic Interrupt Status and Control		11-31
+ *-----------------------------------------------------------------------
+ * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
+ */
+#define CFG_PISCR	(PISCR_PS | PISCR_PITF)
+
+/*-----------------------------------------------------------------------
+ * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
+ *-----------------------------------------------------------------------
+ * Reset PLL lock status sticky bit, timer expired status bit and timer
+ * interrupt status bit
+ *
+ * set PLL multiplication factor
+ */
+#if defined(CONFIG_133MHz)
+    /* for 133 MHz, we use a 10 MHz clock:
+     * MFN = 0x09, MFD = 0x1D, S = 0, MFI = 13
+     */
+#define CFG_PLPRCR							\
+		( 9 << PLPRCR_MFN_SHIFT | 0x1D << PLPRCR_MFD_SHIFT  |	\
+		  0 << PLPRCR_S_SHIFT	| 0x0D << PLPRCR_MFI_SHIFT  |	\
+		  PLPRCR_TEXPS )
+#elif defined(CONFIG_80MHz) /* for  80 MHz, we use a 16 MHz clock *  5 */
+#define CFG_PLPRCR							\
+		( (5-1)<<PLPRCR_MFI_SHIFT | PLPRCR_TEXPS )
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_PLPRCR	( PLPRCR_SPLSS | PLPRCR_TEXPS )
+#endif	/* CONFIG_??MHz */
+
+/*-----------------------------------------------------------------------
+ * SCCR - System Clock and reset Control Register		15-27
+ *-----------------------------------------------------------------------
+ * Set clock output, timebase and RTC source and divider,
+ * power management and some other internal clocks
+ */
+#define SCCR_MASK	SCCR_EBDF11
+#if defined(CONFIG_133MHz)  /* for 133 MHz, we use a 10 MHz clock * 13 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#elif defined(CONFIG_80MHz) /* for  80 MHz, we use a 16 MHz clock *  5 */
+#define CFG_SCCR	(/* SCCR_TBS  | */ \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#else			/* up to 66 MHz we use a 1:1 clock */
+#define CFG_SCCR	(SCCR_TBS     | \
+			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
+			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFALCD00)
+#endif	/* CONFIG_??MHz */
+
+/*-----------------------------------------------------------------------
+ * PCMCIA stuff
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_PCMCIA_MEM_ADDR	(0xE0000000)
+#define CFG_PCMCIA_MEM_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_DMA_ADDR	(0xE4000000)
+#define CFG_PCMCIA_DMA_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_ATTRB_ADDR	(0xE8000000)
+#define CFG_PCMCIA_ATTRB_SIZE	( 64 << 20 )
+#define CFG_PCMCIA_IO_ADDR	(0xEC000000)
+#define CFG_PCMCIA_IO_SIZE	( 64 << 20 )
+
+/*-----------------------------------------------------------------------
+ * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
+ *-----------------------------------------------------------------------
+ */
+
+#define	CONFIG_IDE_8xx_PCCARD	1	/* Use IDE with PC Card	Adapter	*/
+
+#undef	CONFIG_IDE_8xx_DIRECT		/* Direct IDE    not supported	*/
+#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
+#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/
+
+#define CFG_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
+#define CFG_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/
+
+#define CFG_ATA_IDE0_OFFSET	0x0000
+
+#define CFG_ATA_BASE_ADDR	CFG_PCMCIA_MEM_ADDR
+
+/* Offset for data I/O			*/
+#define CFG_ATA_DATA_OFFSET	(CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for normal register accesses	*/
+#define CFG_ATA_REG_OFFSET	(2 * CFG_PCMCIA_MEM_SIZE + 0x320)
+
+/* Offset for alternate registers	*/
+#define CFG_ATA_ALT_OFFSET	0x0100
+
+/*-----------------------------------------------------------------------
+ *
+ *-----------------------------------------------------------------------
+ *
+ */
+#define CFG_DER	0
+
+/*
+ * Init Memory Controller:
+ *
+ * BR0/1 and OR0/1 (FLASH)
+ */
+
+#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
+#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/
+
+/* used to re-map FLASH both when starting from SRAM or FLASH:
+ * restrict access enough to keep SRAM working (if any)
+ * but not too much to meddle with FLASH accesses
+ */
+#define CFG_REMAP_OR_AM		0x80000000	/* OR addr mask */
+#define CFG_PRELIM_OR_AM	0xE0000000	/* OR addr mask */
+
+/*
+ * FLASH timing:
+ */
+#if defined(CONFIG_133MHz)
+/* 133 MHz CPU - 66 MHz bus: */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_100MHz)
+/* 100 MHz CPU - 50 MHz bus: */
+#elif defined(CONFIG_80MHz)
+/* 80 MHz CPU - 40 MHz bus: ACS = 00, TRLX = 0, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | 0       | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#elif defined(CONFIG_66MHz)
+/* 66 MHz CPU - 66 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_3_CLK | OR_EHTR | OR_BI)
+#else		/*   50 MHz */
+/* 50 MHz CPU - 50 MHz bus: ACS = 00, TRLX = 1, CSNT = 1, SCY = 2, EHTR = 1 */
+#define CFG_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
+				 OR_SCY_2_CLK | OR_EHTR | OR_BI)
+#endif	/*CONFIG_??MHz */
+
+#define CFG_OR0_REMAP	(CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
+#define CFG_OR0_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
+#define CFG_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
+
+#define CFG_OR1_REMAP	CFG_OR0_REMAP
+#define CFG_OR1_PRELIM	CFG_OR0_PRELIM
+#define CFG_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
+
+/*
+ * BR2/3 and OR2/3 (SDRAM)
+ *
+ */
+#define SDRAM_BASE2_PRELIM	0x00000000	/* SDRAM bank #0	*/
+#define SDRAM_BASE3_PRELIM	0x20000000	/* SDRAM bank #1	*/
+#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256 MB per bank	*/
+
+/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
+#define CFG_OR_TIMING_SDRAM	0x00000A00
+
+#define CFG_OR2_PRELIM	(CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
+#define CFG_BR2_PRELIM	((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+
+#ifndef	CONFIG_CAN_DRIVER
+#define	CFG_OR3_PRELIM	CFG_OR2_PRELIM
+#define CFG_BR3_PRELIM	((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
+#else	/* CAN uses CS3#, so we can have only one SDRAM bank anyway */
+#define	CFG_CAN_BASE		0xC0000000	/* CAN mapped at 0xC0000000	*/
+#define CFG_CAN_OR_AM		0xFFFF8000	/* 32 kB address mask		*/
+#define CFG_OR3_CAN		(CFG_CAN_OR_AM | OR_G5LA | OR_BI)
+#define CFG_BR3_CAN		((CFG_CAN_BASE & BR_BA_MSK) | \
+					BR_PS_8 | BR_MS_UPMB | BR_V )
+#endif	/* CONFIG_CAN_DRIVER */
+
+/*
+ * Memory Periodic Timer Prescaler
+ *
+ * The Divider for PTA (refresh timer) configuration is based on an
+ * example SDRAM configuration (64 MBit, one bank). The adjustment to
+ * the number of chip selects (NCS) and the actually needed refresh
+ * rate is done by setting MPTPR.
+ *
+ * PTA is calculated from
+ *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
+ *
+ *	gclk	  CPU clock (not bus clock!)
+ *	Trefresh  Refresh cycle * 4 (four word bursts used)
+ *
+ * 4096  Rows from SDRAM example configuration
+ * 1000  factor s -> ms
+ *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
+ *    4  Number of refresh cycles per period
+ *   64  Refresh cycle in ms per number of rows
+ * --------------------------------------------
+ * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
+ *
+ * 50 MHz => 50.000.000 / Divider =  98
+ * 66 Mhz => 66.000.000 / Divider = 129
+ * 80 Mhz => 80.000.000 / Divider = 156
+ */
+#if   defined(CONFIG_133MHz)
+#define CFG_MAMR_PTA		129
+#elif defined(CONFIG_100MHz)
+#define CFG_MAMR_PTA		 98
+#elif defined(CONFIG_80MHz)
+#define CFG_MAMR_PTA		156
+#elif defined(CONFIG_66MHz)
+#define CFG_MAMR_PTA		129
+#else		/*   50 MHz */
+#define CFG_MAMR_PTA		 98
+#endif	/*CONFIG_??MHz */
+
+/*
+ * For 16 MBit, refresh rates could be 31.3 us
+ * (= 64 ms / 2K = 125 / quad bursts).
+ * For a simpler initialization, 15.6 us is used instead.
+ *
+ * #define CFG_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
+ * #define CFG_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
+ */
+#define CFG_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/
+
+/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
+#define CFG_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
+#define CFG_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/
+
+/*
+ * MAMR settings for SDRAM
+ */
+
+/* 8 column SDRAM */
+#define CFG_MAMR_8COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+/* 9 column SDRAM */
+#define CFG_MAMR_9COL	((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
+			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
+			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)
+
+/*
+ * Internal Definitions
+ *
+ * Boot Flags
+ */
+#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
+#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
+
+#define CONFIG_SCC1_ENET
+#define CONFIG_FEC_ENET
+#define CONFIG_ETHPRIME		"SCC ETHERNET"
+
+#endif	/* __CONFIG_H */
diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h
index 6f647f2..d78b727 100644
--- a/include/configs/dbau1x00.h
+++ b/include/configs/dbau1x00.h
@@ -30,24 +30,24 @@
 
 #define CONFIG_MIPS32		1  /* MIPS32 CPU core	*/
 #define CONFIG_DBAU1X00		1
-#define CONFIG_AU1X00           1  /* alchemy series cpu */
+#define CONFIG_AU1X00		1  /* alchemy series cpu */
 
 #ifdef CONFIG_DBAU1000
 /* Also known as Merlot */
-#define CONFIG_AU1000           1
+#define CONFIG_AU1000		1
 #else
 #ifdef CONFIG_DBAU1100
-#define CONFIG_AU1100           1
+#define CONFIG_AU1100		1
 #else
 #ifdef CONFIG_DBAU1500
-#define CONFIG_AU1500           1
-#else  
+#define CONFIG_AU1500		1
+#else
 #error "No valid board set"
 #endif
 #endif
 #endif
 
-#define CONFIG_ETHADDR          DE:AD:BE:EF:01:01    /* Ethernet address */
+#define CONFIG_ETHADDR		DE:AD:BE:EF:01:01    /* Ethernet address */
 
 #define CONFIG_BOOTDELAY	2	/* autoboot after 2 seconds	*/
 
@@ -158,7 +158,7 @@
 
 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 
-/* Offset for data I/O                  */
+/* Offset for data I/O			*/
 #define CFG_ATA_DATA_OFFSET     8
 
 /* Offset for normal register accesses  */
diff --git a/include/dataflash.h b/include/dataflash.h
index c404016..650454e 100644
--- a/include/dataflash.h
+++ b/include/dataflash.h
@@ -91,7 +91,6 @@
 } AT91S_DataFlash, *AT91PS_DataFlash;
 
 
-
 typedef struct _AT91S_DATAFLASH_INFO {
 
 	AT91S_DataflashDesc Desc;
diff --git a/include/flash.h b/include/flash.h
index 800fb4d..a0c9cad 100644
--- a/include/flash.h
+++ b/include/flash.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000, 2001
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -165,10 +165,13 @@
 
 #define AMD_ID_DL640	0x227E227E	/* 29DL640D ID (64 M, dual boot sectors)*/
 #define AMD_ID_MIRROR	0x227E227E	/* 1st ID word for MirrorBit family */
-#define AMD_ID_LV640U_2	0x220C220C	/* 2d ID word for AM29LV640M at 0x38 */
-#define AMD_ID_LV640U_3	0x22012201	/* 3d ID word for AM29LV640M at 0x3c */
-#define AMD_ID_LV128U_2 0x22122212	/* 2d ID word for AM29LV128M at 0x38 */
-#define AMD_ID_LV128U_3 0x22002200	/* 3d ID word for AM29LV128M at 0x3c */
+#define AMD_ID_LV640U_2	0x220C220C	/* 2d ID word for AM29LV640M  at 0x38 */
+#define AMD_ID_LV640U_3	0x22012201	/* 3d ID word for AM29LV640M  at 0x3c */
+#define AMD_ID_LV128U_2 0x22122212	/* 2d ID word for AM29LV128M  at 0x38 */
+#define AMD_ID_LV128U_3 0x22002200	/* 3d ID word for AM29LV128M  at 0x3c */
+
+#define AMD_ID_LV320B_2	0x221A221A	/* 2d ID word for AM29LV320MB at 0x38 */
+#define AMD_ID_LV320B_3 0x22002200	/* 3d ID word for AM29LV320MB at 0x3c */
 
 #define AMD_ID_LV640U	0x22D722D7	/* 29LV640U ID (64 M, uniform sectors)	*/
 
@@ -322,13 +325,15 @@
 #define FLASH_28F320C3B 0x009F		/* Intel 28F320C3B ( 32M = 2M x 16 )	*/
 #define FLASH_28F640C3T 0x00A0		/* Intel 28F640C3T ( 64M = 4M x 16 )	*/
 #define FLASH_28F640C3B 0x00A1		/* Intel 28F640C3B ( 64M = 4M x 16 )	*/
-#define FLASH_AMLV320U	0x00A2		/* AMD 29LV128M    ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320U	0x00A2		/* AMD 29LV320M    ( 32M = 2M x 16 )	*/
 #define FLASH_AMLV640U	0x00A4		/* AMD 29LV640M    ( 64M = 4M x 16 )	*/
 #define FLASH_AMLV128U	0x00A6		/* AMD 29LV128M	   ( 128M = 8M x 16 )	*/
+#define FLASH_AMLV320B  0x00A7		/* AMD 29LV320MB   ( 32M = 2M x 16 )	*/
+#define FLASH_AMLV320T	0x00A8		/* AMD 29LV320MT   ( 32M = 2M x 16 )	*/
 /* Intel 28F256L18T 256M = 128K x 255 + 32k x 4	*/
-#define FLASH_28F256L18T 0x00A8
-#define FLASH_AMDL163T	0x00A2		/* AMD AM29DL163T (2M x 16 )			*/
-#define FLASH_AMDL163B	0x00A3
+#define FLASH_28F256L18T 0x00B0
+#define FLASH_AMDL163T	0x00B2		/* AMD AM29DL163T (2M x 16 )			*/
+#define FLASH_AMDL163B	0x00B3
 
 #define FLASH_UNKNOWN	0xFFFF		/* unknown flash type			*/
 
diff --git a/include/mpc8xx.h b/include/mpc8xx.h
index 4c0c73c..847c2b4 100644
--- a/include/mpc8xx.h
+++ b/include/mpc8xx.h
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -135,18 +135,18 @@
  * PLPRCR - PLL, Low-Power, and Reset Control Register			15-30
  */
 #ifdef CONFIG_MPC866_et_al
-#define PLPRCR_MF_MSK	0xffff001e	/* Multiplication factor + PDF bits	*/
-#define PLPRCR_MFN_MSK	0xf8000000	/* Multiplication factor numerator bits */
-#define PLPRCR_MFN_SHIFT 0x0000001b	/* Multiplication factor numerator shift*/
-#define PLPRCR_MFD_MSK	0x07c00000	/* Multiplication factor denominator bits */
-#define PLPRCR_MFD_SHIFT 0x00000017	/* Multiplication factor denominator shift*/
+#define PLPRCR_MF_MSK	0xFFFF001E	/* Multiplication factor + PDF bits	*/
+#define PLPRCR_MFN_MSK	0xF8000000	/* Multiplication factor numerator bits */
+#define PLPRCR_MFN_SHIFT	27	/* Multiplication factor numerator shift*/
+#define PLPRCR_MFD_MSK	0x07C00000	/* Multiplication factor denominator bits */
+#define PLPRCR_MFD_SHIFT	22	/* Multiplication factor denominator shift*/
 #define PLPRCR_S_MSK	0x00300000	/* Multiplication factor integer bits	*/
-#define PLPRCR_S_SHIFT	0x00000014	/* Multiplication factor integer shift	*/
-#define PLPRCR_MFI_MSK	0x000f0000	/* Multiplication factor integer bits	*/
-#define PLPRCR_MFI_SHIFT 0x00000010	/* Multiplication factor integer shift	*/
+#define PLPRCR_S_SHIFT		20	/* Multiplication factor integer shift	*/
+#define PLPRCR_MFI_MSK	0x000F0000	/* Multiplication factor integer bits	*/
+#define PLPRCR_MFI_SHIFT	16	/* Multiplication factor integer shift	*/
 #else
-#define PLPRCR_MF_MSK	0xfff00000	/* Multiplication factor bits		*/
-#define PLPRCR_MF_SHIFT 0x00000014	/* Multiplication factor shift value	*/
+#define PLPRCR_MF_MSK	0xFFF00000	/* Multiplication factor bits		*/
+#define PLPRCR_MF_SHIFT		20	/* Multiplication factor shift value	*/
 #endif
 #define PLPRCR_SPLSS	0x00008000	/* SPLL Lock Status Sticky bit		*/
 #define PLPRCR_TEXPS	0x00004000	/* TEXP Status				*/
@@ -166,8 +166,8 @@
 #define PLPRCR_LOLRE	0x00000040	/* Loss Of Lock Reset Enable		*/
 #define PLPRCR_FIOPD	0x00000020	/* Force I/O Pull Down			*/
 #ifdef CONFIG_MPC866_et_al
-#define PLPRCR_PDF_MSK	0x0000001e	/* Predivision Factor bits		*/
-#define PLPRCR_PDF_SHIFT 0x00000001	/* Predivision Factor shift value	*/
+#define PLPRCR_PDF_MSK	0x0000001E	/* Predivision Factor bits		*/
+#define PLPRCR_PDF_SHIFT	 1	/* Predivision Factor shift value	*/
 #define PLPRCR_DBRMO	0x00000001	/* DPLL BRM Order bit			*/
 #endif
 
diff --git a/include/pci_ids.h b/include/pci_ids.h
index a27d31c..a5d7ed5 100644
--- a/include/pci_ids.h
+++ b/include/pci_ids.h
@@ -1543,4 +1543,3 @@
 #define PCI_DEVICE_ID_SMI_710           0x0710
 #define PCI_DEVICE_ID_SMI_712           0x0712
 #define PCI_DEVICE_ID_SMI_810           0x0810
-
diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index b4c6119..0bf637d 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c
@@ -310,7 +310,7 @@
 	bd_t *bd;
 
 	bd = gd->bd;
-	// icache_enable(); /* it's time to enable the instruction cache */
+	/* icache_enable(); /XX* it's time to enable the instruction cache */
 
 	/*
 	 * Setup trap handlers
diff --git a/lib_nios/board.c b/lib_nios/board.c
index ff0d9f5..0bbedfd 100644
--- a/lib_nios/board.c
+++ b/lib_nios/board.c
@@ -174,4 +174,3 @@
 	puts("### ERROR ### Please reset board ###\n");
 	for (;;);
 }
-
diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index ea8adb91..8e05df1 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2000-2002
+ * (C) Copyright 2000-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
diff --git a/lib_ppc/interrupts.c b/lib_ppc/interrupts.c
index 1e540a5..b803952 100644
--- a/lib_ppc/interrupts.c
+++ b/lib_ppc/interrupts.c
@@ -46,11 +46,11 @@
 
 static __inline__ unsigned long get_msr (void)
 {
-        unsigned long msr;
+	unsigned long msr;
 
-        asm volatile ("mfmsr %0":"=r" (msr):);
+	asm volatile ("mfmsr %0":"=r" (msr):);
 
-        return msr;
+	return msr;
 }
 
 static __inline__ void set_msr (unsigned long msr)
@@ -93,7 +93,7 @@
 {
 	int ret;
 
-        /* call cpu specific function from $(CPU)/interrupts.c */
+	/* call cpu specific function from $(CPU)/interrupts.c */
 	ret = interrupt_init_cpu (&decrementer_count);
 
 	if (ret)
@@ -124,7 +124,7 @@
 #endif    /* CONFIG_WATCHDOG || CONFIG_HW_WATCHDOG */
 
 #ifdef CONFIG_STATUS_LED
-        status_led_tick (timestamp);
+	status_led_tick (timestamp);
 #endif /* CONFIG_STATUS_LED */
 
 #ifdef CONFIG_SHOW_ACTIVITY
diff --git a/net/eth.c b/net/eth.c
index eabbf63..f295782 100644
--- a/net/eth.c
+++ b/net/eth.c
@@ -1,5 +1,5 @@
 /*
- * (C) Copyright 2001, 2002
+ * (C) Copyright 2001-2004
  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  *
  * See file CREDITS for list of people who contributed to this
@@ -217,9 +217,8 @@
 	char *end;
 	int i;
 
-#ifdef DEBUG
-	printf("eth_set_enetaddr(num=%d, addr=%s)\n", num, addr);
-#endif
+	debug ("eth_set_enetaddr(num=%d, addr=%s)\n", num, addr);
+
 	if (!eth_devices)
 		return;
 
@@ -237,14 +236,12 @@
 			return;
 	}
 
-#ifdef DEBUG
-	printf("Setting new HW address on %s\n", dev->name);
-	printf("New Address is             "
-	       "%02X:%02X:%02X:%02X:%02X:%02X\n",
-	       dev->enetaddr[0], dev->enetaddr[1],
-	       dev->enetaddr[2], dev->enetaddr[3],
-	       dev->enetaddr[4], dev->enetaddr[5]);
-#endif
+	debug ( "Setting new HW address on %s\n"
+		"New Address is             %02X:%02X:%02X:%02X:%02X:%02X\n",
+		dev->name,
+		dev->enetaddr[0], dev->enetaddr[1],
+		dev->enetaddr[2], dev->enetaddr[3],
+		dev->enetaddr[4], dev->enetaddr[5]);
 
 	memcpy(dev->enetaddr, enetaddr, 6);
 }
@@ -258,19 +255,14 @@
 
 	old_current = eth_current;
 	do {
-#ifdef DEBUG
-		printf("Trying %s\n", eth_current->name);
-#endif
+		debug ("Trying %s\n", eth_current->name);
 
 		if (eth_current->init(eth_current, bis)) {
 			eth_current->state = ETH_STATE_ACTIVE;
 
 			return 1;
 		}
-
-#ifdef DEBUG
-		puts ("FAIL\n");
-#endif
+		debug  ("FAIL\n");
 
 		eth_try_another(0);
 	} while (old_current != eth_current);