)]}'
{
  "commit": "d9b94f28a442b0013caef99de084d7b72e2d4607",
  "tree": "1b293a551e021a4a696717231ec03206d9f172de",
  "parents": [
    "288693abe1f7c23e69479fd85c2c0d8d7fdbf8f2"
  ],
  "author": {
    "name": "Jon Loeliger",
    "email": "jdl@freescale.com",
    "time": "Mon Jul 25 14:05:07 2005 -0500"
  },
  "committer": {
    "name": "Jon Loeliger",
    "email": "jdl@freescale.com",
    "time": "Mon Jul 25 14:05:07 2005 -0500"
  },
  "message": "* Patch by Jon Loeliger, 2005-05-05\n  Implemented support for MPC8548CDS board.\n  Added DDR II support based on SPD values for MPC85xx boards.\n  This roll-up patch also includes bugfies for the previously\n  published patches:\n    DDRII CPO, pre eTSEC, 8548 LBIU, Andy\u0027s TSEC, eTSEC 3\u00264 I/O\n",
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