)]}'
{
  "commit": "dbbbb3abeff325855cae76e33d69d5665631443f",
  "tree": "2df59a7ac7364e4c501e228c74db3cd5f14ad3b1",
  "parents": [
    "1c9aa76bf9013069e24258f46f4687c9f98a02d6"
  ],
  "author": {
    "name": "Haiying Wang",
    "email": "Haiying.Wang@freescale.com",
    "time": "Fri Oct 03 12:36:39 2008 -0400"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Sat Oct 18 21:54:04 2008 +0200"
  },
  "message": "Make DDR interleaving mode work correctly\n\nFix some bugs:\n  1. Correctly set intlv_ctl in cs_config.\n  2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled.\n  3. Set base_address and total memory for each ddr controller in memory\n     controller interleaving mode.\n\nSigned-off-by: Haiying Wang \u003cHaiying.Wang@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e6c2a5ce7cf03bc77d659c904c894cbad048eba9",
      "old_mode": 33188,
      "old_path": "cpu/mpc8xxx/ddr/ctrl_regs.c",
      "new_id": "6297141167285808f0fb03805fd92f1e63615376",
      "new_mode": 33188,
      "new_path": "cpu/mpc8xxx/ddr/ctrl_regs.c"
    },
    {
      "type": "modify",
      "old_id": "c340d569fa942eba0b1264fe28241345bcf3c14e",
      "old_mode": 33188,
      "old_path": "cpu/mpc8xxx/ddr/main.c",
      "new_id": "d26c5c5c29ae08ac84665c448f44c8c2e9f1bba3",
      "new_mode": 33188,
      "new_path": "cpu/mpc8xxx/ddr/main.c"
    },
    {
      "type": "modify",
      "old_id": "8adde34247bd1364c6bfd419206e6895bf5ef438",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/fsl_ddr_sdram.h",
      "new_id": "c1ea7cd6bb16a3ff3ec68fa951e28f04dee6fbd5",
      "new_mode": 33188,
      "new_path": "include/asm-ppc/fsl_ddr_sdram.h"
    }
  ]
}