)]}'
{
  "commit": "e1d8ed2c08da14b168658cc5fa78529d461aea70",
  "tree": "941ab24acee735ca97acdcb04e6fa7a66c28c797",
  "parents": [
    "b5cdd7df4a06edb91539c9a2ea7c178a870c3a95"
  ],
  "author": {
    "name": "Poonam Aggrwal",
    "email": "b10812@freescale.com",
    "time": "Mon Jan 14 09:41:14 2008 +0530"
  },
  "committer": {
    "name": "Kim Phillips",
    "email": "kim.phillips@freescale.com",
    "time": "Wed Jan 16 12:00:49 2008 -0600"
  },
  "message": "Changes in uboot DDR configuration for MPC8313eRDB\n\nThese changes were identified by HighSmith Bill ,Mazzyar and Joseph for\nDDR configuration in u-boot code. Some are related to performance, some\naffect stability and some correct few basic errors in the current\nconfiguration.\n\nThe changes have been tested and found to give better memory latency\nfigures on MPC8313eRDB.LMBench figures prove it.\n\nThe changes are:\n\n- CS0_CONFIG[ AP_n_EN] is changed from 1 to 0\n  (this may improve performance for application with many read\n  or write to open pages).\n- CS0_CONFIG[ODT_WR_CFG] is currently changed from 100 to\n  001 (activating all the CS when only one is used may cause\n  unwanted noise on the system)\n\n- TIMING_CFG_1[ACTTOPRE] is changed from 9clks to 8clks (based on\n  Tras\u003d45ns)\n- TIMING_CFG_1[REFREC] changed from 21 clks to 18clks.\n\n- TIMING_CFG_2[AL] value changed from 0 setting to 1 clk to\n  comply with the 3 ODT clk requirements)\n- TIMING_CFG_2[CPO] was set to a reserved value, changed to RL+3/4.\n- TIMING_CFG_2[FOUR_ACT] is changed from 10 clks to 6clks.\n\n- DDR_SDRAM_MODE[AL]changed from 0 to 1.\n- DDR_SDRAM_MODE[WRREC] changed from 1 clk to 3 clks.\n\n- DDR_SDRAM_INTERVAL[REFINT] is changed from 0x0320 to 0x0510.\n- DDR_SDRAM_INTERVAL[BSTOPRE] is changed from 0x64 to 0x0500.\n\nThe patch is based of git://www.denx.de/git/u-boot-mpc83xx.git\nThe last commit on this tree was 6775c68683a53c7abc778774641aac6f833a2cbf\n\nSigned-off-by: Poonam Aggrwal-b10812 \u003cb10812@freescale.com\u003e\nCc: Bill HighSmith \u003cBill.Highsmith@freescale.com\u003e\nCc: Razzaz Mazyar \u003cMRazzaz@freescale.com\u003e\nCc: Josep P J \u003cPJ.Joseph@freescale.com\u003e\nSigned-off-by: Kim Phillips \u003ckim.phillips@freescale.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "455bbe0cf7da3173a83f5af79377f598f2698f0c",
      "old_mode": 33188,
      "old_path": "include/configs/MPC8313ERDB.h",
      "new_id": "f12a3e605e665295cc1cebd982ea7991d5771a1c",
      "new_mode": 33188,
      "new_path": "include/configs/MPC8313ERDB.h"
    }
  ]
}