)]}'
{
  "commit": "e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6",
  "tree": "5cc265595c6f75283f7e67e8d3a3ea5575afa868",
  "parents": [
    "535cfa4f3de86cf48d6c0af1daf33aebdca089f9"
  ],
  "author": {
    "name": "Gururaja Hebbar K R",
    "email": "gururajakr@sanyo.co.in",
    "time": "Mon Aug 25 11:11:34 2008 +0200"
  },
  "committer": {
    "name": "Jean-Christophe PLAGNIOL-VILLARD",
    "email": "plagnioj@jcrosoft.com",
    "time": "Mon Aug 25 13:00:03 2008 +0200"
  },
  "message": "Correct ARM Versatile Timer Initialization\n\n - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),\n   -- Timer Value Register @ TIMER Base + 4 is Read-only.\n   -- Prescale Value (Bits 3-2 of TIMER Control register)\n\tcan only be one of 00,01,10. 11 is undefined.\n   -- CFG_HZ for Versatile board is set to\n\t#define CFG_HZ\t\t(1000000 / 256)\n\tSo Prescale bits is set to indicate\n\t- 8 Stages of Prescale, Clock divided by 256\n - The Timer Control Register has one Undefined/Shouldn\u0027t Use Bit\n   So we should do read/modify/write Operation\n\nSigned-off-by: Gururaja Hebbar \u003cgururajakr@sanyo.co.in\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "32872d2b66c2e4ed1545f65977c46b5a1a035af7",
      "old_mode": 33188,
      "old_path": "cpu/arm926ejs/versatile/timer.c",
      "new_id": "f01f318509a040fc292cff8a980973b37d69ae86",
      "new_mode": 33261,
      "new_path": "cpu/arm926ejs/versatile/timer.c"
    }
  ]
}