)]}'
{
  "commit": "eb5394120643922626f18e5fe7b0b3dc0ed43b9a",
  "tree": "968121a3577cf3c8e14bd435d9c8c303140f3cd1",
  "parents": [
    "f31cfd19253713eea59311dec9e99df5d43b2db9"
  ],
  "author": {
    "name": "York Sun",
    "email": "yorksun@freescale.com",
    "time": "Mon Oct 08 07:44:25 2012 +0000"
  },
  "committer": {
    "name": "Andy Fleming",
    "email": "afleming@freescale.com",
    "time": "Mon Oct 22 14:31:28 2012 -0500"
  },
  "message": "powerpc/mpc85xx: software workaround for DDR erratum A-004468\n\nBoot space translation utilizes the pre-translation address to select\nthe DDR controller target. However, the post-translation address will be\npresented to the selected DDR controller. It is possible that the pre-\ntranslation address selects one DDR controller but the post-translation\naddress exists in a different DDR controller when using certain DDR\ncontroller interleaving modes. The device may fail to boot under these\ncircumstances. Note that a DDR MSE error will not be detected since DDR\ncontroller bounds registers are programmed to be the same when configured\nfor DDR controller interleaving.\n\nSigned-off-by: York Sun \u003cyorksun@freescale.com\u003e\nSigned-off-by: Andy Fleming \u003cafleming@freescale.com\u003e\n",
  "tree_diff": [
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