)]}'
{
  "commit": "ec081c2c190148b374e86a795fb6b1c49caeb549",
  "tree": "ceb0ef625ec62f918147f0b296f59f662b340c37",
  "parents": [
    "b4dbacf69a669a17487054552fc2761149dd6767"
  ],
  "author": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Fri Oct 17 12:51:46 2008 +0200"
  },
  "committer": {
    "name": "Stefan Roese",
    "email": "sr@denx.de",
    "time": "Fri Oct 17 12:51:46 2008 +0200"
  },
  "message": "ppc4xx: PPC44x MQ initialization\n\nSet the MQ Read Passing \u0026 MCIF Cycle limits to the recommended by AMCC\nvalues. This fixes the occasional 440SPe hard locking issues when the 440SPe\u0027s\ndedicated DMA engines are used (e.g. by the h/w accelerated RAID driver).\n\nPreviously the appropriate initialization had been made in Linux, by the\nppc440spe ADMA driver, which is wrong because modifying the MQ configuration\nregisters after normal operation has begun is not supported and could\nhave unpredictable results.\n\nComment from Stefan: This patch doesn\u0027t change the resulting value of the\nMQ registers. It explicitly sets/clears all bits to the desired state which\nbetter documents the resulting register value instead of relying on pre-set\ndefault values.\n\nSigned-off-by: Yuri Tikhonov \u003cyur@emcraft.com\u003e\nSigned-off-by: Stefan Roese \u003csr@denx.de\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "f1d76840f21a365115685d558ba14804f7a94443",
      "old_mode": 33188,
      "old_path": "cpu/ppc4xx/44x_spd_ddr2.c",
      "new_id": "995d5fec747822fa8872f7dce2e93f46b1c01d9b",
      "new_mode": 33188,
      "new_path": "cpu/ppc4xx/44x_spd_ddr2.c"
    },
    {
      "type": "modify",
      "old_id": "8efa557972e6802d4f402e66d4853d9d203d7502",
      "old_mode": 33188,
      "old_path": "include/asm-ppc/ppc4xx-sdram.h",
      "new_id": "98faced366c814b387a9e0baad43e35f5b9ece1e",
      "new_mode": 33188,
      "new_path": "include/asm-ppc/ppc4xx-sdram.h"
    }
  ]
}