)]}'
{
  "commit": "f781dd383a0a28930612d48df11ccb2f3bca4eaa",
  "tree": "c67ef781efeaa228695575a92a29018c981d6dda",
  "parents": [
    "96d21237ec2b799f60a827ea680594b7ebfdac7f"
  ],
  "author": {
    "name": "Anton staaf",
    "email": "robotboy@chromium.org",
    "time": "Mon Oct 03 13:54:59 2011 +0000"
  },
  "committer": {
    "name": "Wolfgang Denk",
    "email": "wd@denx.de",
    "time": "Tue Oct 25 09:25:13 2011 +0200"
  },
  "message": "mmc: dcache: allocate cache aligned buffer for scr and switch_status\n\nCurrently the sd_change_freq function allocates two buffers on the\nstack that it passes down to the MMC device driver.  These buffers\ncould be unaligned to the L1 dcache line size.  This causes problems\nwhen using DMA and with caches enabled.\n\nThis patch correctly cache alignes the buffers used for reading the\nscr register and switch status values from an MMC device.\n\nChange-Id: Ifa8414f572ef907681bd2d5ff3950285a215357d\nSigned-off-by: Anton Staaf \u003crobotboy@chromium.org\u003e\nCc: Lukasz Majewski \u003cl.majewski@samsung.com\u003e\nCc: Mike Frysinger \u003cvapier@gentoo.org\u003e\nCc: Albert ARIBAUD \u003calbert.u.boot@aribaud.net\u003e\nAcked-by: Mike Frysinger \u003cvapier@gentoo.org\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "391bc2bafa0f3393d377425d995ac9939fc1831b",
      "old_mode": 33188,
      "old_path": "drivers/mmc/mmc.c",
      "new_id": "ba6fbfe7ac2d1156b6d39040f7a012b9b2cbab9c",
      "new_mode": 33188,
      "new_path": "drivers/mmc/mmc.c"
    }
  ]
}