| #include <common.h> |
| #include <asm/arch/secure_apb.h> |
| //#include<stdio.h> |
| |
| //#include <asm/io.h> |
| //#include <asm/arch/io.h> |
| //#include <asm/arch/register.h> |
| //#include <asm/arch-g9tv/mmc.h> //jiaxing debug |
| |
| //extern void aml_cache_disable(void); |
| //#ifndef char* itoa(intnum,char*str,intradix) |
| |
| |
| |
| char* itoa_ddr_test(int num,char*str,int radix) |
| {/*Ë÷Òý±í*/ |
| printf("\nitoa_ddr_test 1\n"); |
| char index[]="0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ"; |
| unsigned unum;/*Öмä±äÁ¿*/ |
| int i=0,j,k; |
| /*È·¶¨unumµÄÖµ*/ |
| if (radix == 10 && num<0) /*Ê®½øÖƸºÊý*/ |
| { |
| unum=(unsigned)-num; |
| str[i++]='-'; |
| } |
| else unum=(unsigned)num;/*ÆäËûÇé¿ö*/ |
| /*ת»»*/ |
| printf("\nitoa_ddr_test 2\n"); |
| printf("\nunum=0x%08x\n",unum); |
| printf("\nunum2=0x%08x\n",(unum%(unsigned)radix)); |
| printf("\nradix=0x%08x\n",radix); |
| str[0]=index[0]; |
| printf("\nitoa_ddr_test 22\n"); |
| unum/=radix; |
| printf("\nitoa_ddr_test 23\n"); |
| do { |
| str[i++]=index[unum%(unsigned)radix]; |
| unum/=radix; |
| }while(unum); |
| printf("\nitoa_ddr_test 3\n"); |
| str[i]='\0'; |
| /*ÄæÐò*/ |
| if (str[0] == '-') k=1;/*Ê®½øÖƸºÊý*/ |
| else k=0; |
| char temp; |
| printf("\nitoa_ddr_test 4\n"); |
| for (j=k;j<=(i-1)/2;j++) |
| { |
| temp=str[j]; |
| str[j]=str[i-1+k-j]; |
| str[i-1+k-j]=temp; |
| } |
| return str; |
| } |
| //#endif |
| |
| #define TDATA32F 0xffffffff |
| #define TDATA32A 0xaaaaaaaa |
| #define TDATA325 0x55555555 |
| |
| //#define DDR_TEST_ACLCDLR |
| |
| unsigned int global_ddr_clk=1; |
| unsigned int error_count =0; |
| unsigned int error_outof_count_flag=0; |
| unsigned int copy_test_flag = 0; |
| unsigned int training_pattern_flag = 0; |
| unsigned int test_start_addr=0x1080000; |
| |
| unsigned int dq_lcd_bdl_value_wdq_org_a[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_org_a[4]; |
| unsigned int dq_lcd_bdl_value_wdq_min_a[4]; |
| unsigned int dq_lcd_bdl_value_wdq_max_a[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_min_a[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_max_a[4]; |
| |
| unsigned int dq_lcd_bdl_value_wdq_org_b[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_org_b[4]; |
| unsigned int dq_lcd_bdl_value_wdq_min_b[4]; |
| unsigned int dq_lcd_bdl_value_wdq_max_b[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_min_b[4]; |
| unsigned int dq_lcd_bdl_value_rdqs_max_b[4]; |
| unsigned int acbdlr0_9_reg_org[10]; |
| unsigned int acbdlr0_9_reg_setup_max[40]; |
| unsigned int acbdlr0_9_reg_hold_max[40]; |
| unsigned int acbdlr0_9_reg_setup_time[40]; |
| unsigned int acbdlr0_9_reg_hold_time[40]; |
| // unsigned int data_bdlr0_5_reg_org[6]; |
| unsigned int data_bdlr0_5_reg_org[28];//4//4lane |
| unsigned int bdlr0_9_reg_setup_max[24*4];//4//4 lane 96 bdlr |
| unsigned int bdlr0_9_reg_hold_max[24*4]; |
| unsigned int bdlr0_9_reg_setup_time[24*4]; |
| unsigned int bdlr0_9_reg_hold_time[24*4]; |
| |
| #define readl(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr) |
| #define writel(data ,addr) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data) |
| |
| #define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int )addr)))=(data) //wr_reg(addr, data) |
| #define rd_reg(addr) (unsigned int )(*((volatile unsigned int *)((unsigned long)(unsigned int )addr))) //rd_reg(addr) |
| |
| |
| |
| //#define ddr_udelay(a) do{}while((a<<5)--); |
| #define P_EE_TIMER_E1 ((0x2662 << 2) + 0xc1100000) |
| void ddr_udelay(unsigned int us) |
| { |
| //#ifndef CONFIG_PXP_EMULATOR |
| unsigned int t0 = (*((volatile unsigned *)(P_EE_TIMER_E1))); |
| |
| while ((*((volatile unsigned *)(P_EE_TIMER_E1))) - t0 <= us) |
| ; |
| //#endif |
| } |
| |
| void ddr_test_watchdog_init(uint32_t msec) |
| { |
| #define P_WATCHDOG_CNTL 0xc11098d0 |
| #define P_WATCHDOG_CNTL1 0xc11098d4 |
| #define P_WATCHDOG_TCNT 0xc11098d8 |
| #define P_WATCHDOG_RESET 0xc11098dc |
| // src: 24MHz |
| // div: 24000 for 1ms |
| // reset ao-22 and ee-21 |
| writel( (1<<24)|(1<<25)|(1<<23)|(1<<21)|(24000-1),P_WATCHDOG_CNTL); |
| |
| // set timeout |
| //*P_WATCHDOG_TCNT = msec; |
| writel(msec,P_WATCHDOG_TCNT); //bit0-15 |
| writel(0,P_WATCHDOG_RESET); |
| //*P_WATCHDOG_RESET = 0; |
| |
| // enable |
| writel((readl(P_WATCHDOG_CNTL))|(1<<18),P_WATCHDOG_CNTL); |
| //*P_WATCHDOG_CNTL |= (1<<18); |
| } |
| |
| void ddr_test_watchdog_reset_system(void) |
| { |
| #define P_WATCHDOG_CNTL 0xc11098d0 |
| #define P_WATCHDOG_CNTL1 0xc11098d4 |
| #define P_WATCHDOG_TCNT 0xc11098d8 |
| #define P_WATCHDOG_RESET 0xc11098dc |
| int i; |
| |
| while (1) { |
| writel( 0x3 | (1 << 21) // sys reset en ao ee 3 |
| | (1 << 23) // interrupt en |
| | (1 << 24) // clk en |
| | (1 << 25) // clk div en |
| | (1 << 26) // sys reset now ao ee 3 |
| , P_WATCHDOG_CNTL); |
| printf("\nP_WATCHDOG_CNTL==%x08",readl(P_WATCHDOG_CNTL)); |
| printf("\nP_WATCHDOG_CNTL==%x08",readl(P_WATCHDOG_CNTL)); |
| printf("\nP_WATCHDOG_CNTL==%x08",readl(P_WATCHDOG_CNTL)); |
| writel(0, P_WATCHDOG_RESET); |
| |
| writel(readl(P_WATCHDOG_CNTL) | (1<<18), // watchdog en |
| P_WATCHDOG_CNTL); |
| for (i=0; i<100; i++) |
| readl(P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */ |
| } |
| } |
| |
| //#define CONFIG_DDR_CMD_BDL_TUNE |
| //#define CONFIG_CMD_DDR_TEST |
| #define P_DDR_PHY_DEFAULT 0 |
| #define P_DDR_PHY_GX_BABY 1 |
| #define P_DDR_PHY_GX_TV_BABY 2 |
| #define P_DDR_PHY_905X 3 |
| |
| #define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY |
| |
| #define PATTERN_USE_DDR_DES |
| #define USE_64BIT_POINTER |
| //#define USE_32BIT_POINTER |
| #ifdef USE_64BIT_POINTER |
| #define p_convter_int(a) ( unsigned int )( unsigned long )(a) |
| #define int_convter_p(a) ( unsigned long )(a) |
| |
| #else |
| #define p_convter_int(a) ( unsigned int )(a) |
| #define int_convter_p(a) ( unsigned int )(a) |
| #endif |
| |
| #ifdef PATTERN_USE_DDR_DES |
| #define des_pattern(a,b,c,d) (des[a]^pattern_##b[c][d]) |
| #define des_inv_pattern(a,b,c,d) ( des[a]^(~(pattern_##b[c][d]))) |
| #define des_xor_pattern(a,b) ( a^b) |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| |
| #else |
| #define des_pattern(a,b,c,d) (des[a]&0)+pattern_##b[c][d] |
| #define des_inv_pattern(a,b,c,d) (des[a]&0)+~(pattern_##b[c][d]) |
| #define des_xor_pattern(a,b) (a&0+b) |
| #endif |
| |
| |
| #define DDR_LCDLR_CK_USE_FAST_PATTERN |
| |
| #define DDR_PREFETCH_CACHE |
| #ifdef DDR_PREFETCH_CACHE |
| #define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P)) |
| #else |
| #define ddr_pld_cache(P) |
| #endif |
| |
| #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) |
| #define DDR0_PUB_REG_BASE 0xc8836000 |
| #define DDR1_PUB_REG_BASE 0xc8836000 |
| #define CHANNEL_A_REG_BASE 0 |
| #define CHANNEL_B_REG_BASE 0x2000 |
| #define P_DDR0_CLK_CTRL 0xc8836c00 |
| #define P_DDR1_CLK_CTRL 0xc8836c00 |
| #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00)) |
| #define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8836c00)) |
| #define CLOSE_CHANNEL_A_PHY_CLK() (writel((5), 0xc8836c00)) |
| #define CLOSE_CHANNEL_B_PHY_CLK() (writel((5), 0xc8836c00)) |
| #define P_ISA_TIMERE 0xc1109988 |
| #define get_us_time() (readl(P_ISA_TIMERE)) |
| #define AM_DDR_PLL_CNTL 0xc8836800 |
| #define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2)) |
| #define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2)) |
| #define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2)) |
| |
| #define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2)) |
| #define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2)) |
| #define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2)) |
| |
| #define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2)) |
| #define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2)) |
| #define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2)) |
| //0x98 reserved) |
| #define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2)) |
| #define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2)) |
| #define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2)) |
| //0x9c reserved) |
| #define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2)) |
| #define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2)) |
| #define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2)) |
| #define ACBDLR_MAX 0X1F |
| #define ACLCDLR_MAX 0XFF |
| #define DQBDLR_MAX 0X1F |
| #define DQLCDLR_MAX 0XFF |
| #define DXNGTR_MAX 0X7 |
| #define ACBDLR_NUM 10 |
| |
| |
| |
| #define DMC_REG_BASE 0xc8838000 |
| #define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 )) |
| //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. |
| //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. |
| //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer. |
| //bit 19:16. qos monitor channel select. select one at one time only. |
| //bit 15:0. port select for the selected channel. |
| #define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 )) |
| // qos_mon_clk_timer. How long to measure the bandwidth. |
| |
| |
| #define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 )) |
| // at the test period, the whole MMC request time. |
| #define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 )) |
| // at the test period, the whole MMC granted data cycles. 64bits unit. |
| #define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 )) |
| |
| |
| #elif (CONFIG_DDR_PHY == P_DDR_PHY_GX_TV_BABY) |
| |
| |
| #define DDR0_PUB_REG_BASE 0xc8836000 |
| #define DDR1_PUB_REG_BASE 0xc8837000 |
| #define CHANNEL_A_REG_BASE 0 |
| #define CHANNEL_B_REG_BASE 0x1000 |
| #define P_DDR0_CLK_CTRL 0xc8836c00 |
| #define P_DDR1_CLK_CTRL 0xc8836c00 |
| #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00)) |
| #define OPEN_CHANNEL_B_PHY_CLK() (writel((0), 0xc8837c00)) |
| #define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8836c00)) |
| #define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8837c00)) |
| #define P_ISA_TIMERE 0xc1109988 |
| #define get_us_time() (readl(P_ISA_TIMERE) ) |
| #define AM_DDR_PLL_CNTL 0xc8836800 |
| #define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2)) |
| #define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2)) |
| #define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2)) |
| #define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2)) |
| #define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2)) |
| #define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2)) |
| |
| |
| |
| #define DDR0_PUB_ZQ0SR (DDR0_PUB_REG_BASE+(0x93<<2)) |
| //0x94 reserved) |
| #define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE+(0x95<<2)) |
| #define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE+(0x96<<2)) |
| #define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE+(0x97<<2)) |
| //0x98 reserved) |
| #define DDR0_PUB_ZQ2PR (DDR0_PUB_REG_BASE+(0x99<<2)) |
| #define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE+(0x9A<<2)) |
| #define DDR0_PUB_ZQ2SR (DDR0_PUB_REG_BASE+(0x9B<<2)) |
| //0x9c reserved) |
| #define DDR0_PUB_ZQ3PR (DDR0_PUB_REG_BASE+(0x9D<<2)) |
| #define DDR0_PUB_ZQ3DR (DDR0_PUB_REG_BASE+(0x9E<<2)) |
| #define DDR0_PUB_ZQ3SR (DDR0_PUB_REG_BASE+(0x9F<<2)) |
| #define ACBDLR_MAX 0X1F |
| #define ACLCDLR_MAX 0XFF |
| #define DQBDLR_MAX 0X1F |
| #define DQLCDLR_MAX 0XFF |
| #define DXNGTR_MAX 0X7 |
| |
| #define DMC_REG_BASE 0xc8838000 |
| #define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 )) |
| //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. |
| //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. |
| //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer. |
| //bit 19:16. qos monitor channel select. select one at one time only. |
| //bit 15:0. port select for the selected channel. |
| #define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 )) |
| // qos_mon_clk_timer. How long to measure the bandwidth. |
| |
| |
| #define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 )) |
| // at the test period, the whole MMC request time. |
| #define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 )) |
| // at the test period, the whole MMC granted data cycles. 64bits unit. |
| #define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 )) |
| // at the test period, the granted data cycles for the selected channel and ports. |
| |
| #elif (CONFIG_DDR_PHY == P_DDR_PHY_905X) |
| |
| #define P_ISA_TIMERE 0xc1109988 |
| #define get_us_time() (readl(P_ISA_TIMERE) ) |
| |
| #define DDR0_PUB_REG_BASE 0xc8836000 |
| #define DDR1_PUB_REG_BASE 0xc8836000 |
| #define CHANNEL_A_REG_BASE 0 |
| #define CHANNEL_B_REG_BASE 0//0x1000 |
| #define MMC_REG_BASE 0xc8837000 |
| #define DDR_CLK_CNTL (MMC_REG_BASE + ( 0x7 << 2 )) |
| #define P_DDR0_CLK_CTRL DDR_CLK_CNTL |
| #define P_DDR1_CLK_CTRL DDR_CLK_CNTL |
| #define OPEN_CHANNEL_A_PHY_CLK() (writel((0Xb000a000), DDR_CLK_CNTL)) |
| #define OPEN_CHANNEL_B_PHY_CLK() (writel((0Xb000a000), DDR_CLK_CNTL)) |
| #define CLOSE_CHANNEL_A_PHY_CLK() (writel((0Xb000a005), DDR_CLK_CNTL)) |
| #define CLOSE_CHANNEL_B_PHY_CLK() (writel((0Xb000a005), DDR_CLK_CNTL)) |
| |
| |
| |
| #define AM_DDR_PLL_CNTL0 (MMC_REG_BASE + ( 0x0 << 2 )) |
| #define AM_DDR_PLL_CNTL AM_DDR_PLL_CNTL0 |
| #define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE + ( 0x1a0 << 2 )) |
| #define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE + ( 0x1a1 << 2 )) |
| #define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE + ( 0x1a2 << 2 )) |
| #define DDR0_PUB_ZQ0SR ( DDR0_PUB_REG_BASE + ( 0x1a3 << 2 )) |
| |
| #define DDR0_PUB_ZQ1PR (DDR0_PUB_REG_BASE + ( 0x1a5 << 2 )) |
| #define DDR0_PUB_ZQ1DR (DDR0_PUB_REG_BASE + ( 0x1a6 << 2 )) |
| #define DDR0_PUB_ZQ1SR (DDR0_PUB_REG_BASE + ( 0x1a7 << 2 )) |
| |
| #define DDR0_PUB_ZQ2PR ( DDR0_PUB_REG_BASE + ( 0x1a9 << 2 )) |
| #define DDR0_PUB_ZQ2DR (DDR0_PUB_REG_BASE + ( 0x1aA << 2 )) |
| #define DDR0_PUB_ZQ2SR ( DDR0_PUB_REG_BASE + ( 0x1aB << 2 )) |
| |
| #define DDR1_PUB_ZQCR DDR0_PUB_ZQ0PR |
| #define DDR1_PUB_ZQ0PR DDR0_PUB_ZQ0PR |
| #define DDR1_PUB_ZQ0DR DDR0_PUB_ZQ0DR |
| |
| #define ACBDLR_MAX 0X3F |
| #define ACLCDLR_MAX 0X1FF |
| #define DQBDLR_MAX 0X3F |
| #define DQLCDLR_MAX 0X1FF |
| #define DXNGTR_MAX 0X1F |
| |
| #define DMC_REG_BASE MMC_REG_BASE |
| #define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 )) |
| //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. |
| //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. |
| //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer. |
| //bit 19:16. qos monitor channel select. select one at one time only. |
| //bit 15:0. port select for the selected channel. |
| #define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 )) |
| // qos_mon_clk_timer. How long to measure the bandwidth. |
| |
| |
| #define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 )) |
| // at the test period, the whole MMC request time. |
| #define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 )) |
| // at the test period, the whole MMC granted data cycles. 64bits unit. |
| #define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 )) |
| // at the test period, the granted data cycles for the selected channel and ports. |
| |
| #elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT) |
| |
| #define DDR0_PUB_REG_BASE 0xc8001000 //0xc8836000 |
| #define DDR1_PUB_REG_BASE 0xc8001000 // 0xc8836000 |
| #define CHANNEL_A_REG_BASE 0 |
| #define CHANNEL_B_REG_BASE 0x2000 |
| #define P_DDR0_CLK_CTRL 0xc8000800 |
| #define P_DDR1_CLK_CTRL 0xc8002800 |
| #define OPEN_CHANNEL_A_PHY_CLK() (writel((0x12b), 0xc8000800)) |
| #define OPEN_CHANNEL_B_PHY_CLK() (writel((0x12b), 0xc8002800)) |
| #define CLOSE_CHANNEL_A_PHY_CLK() (writel((0x12a), 0xc8000800)) |
| #define CLOSE_CHANNEL_B_PHY_CLK() (writel((0x12a), 0xc8002800)) |
| #define P_ISA_TIMERE 0xc1109988 |
| #define get_us_time() (readl(P_ISA_TIMERE)) |
| #define AM_DDR_PLL_CNTL 0xc8000400 |
| #define DDR0_PUB_ZQCR (DDR0_PUB_REG_BASE+(0x90<<2)) |
| #define DDR0_PUB_ZQ0PR (DDR0_PUB_REG_BASE+(0x91<<2)) |
| #define DDR0_PUB_ZQ0DR (DDR0_PUB_REG_BASE+(0x92<<2)) |
| #define DDR1_PUB_ZQCR (DDR1_PUB_REG_BASE+(0x90<<2)) |
| #define DDR1_PUB_ZQ0PR (DDR1_PUB_REG_BASE+(0x91<<2)) |
| #define DDR1_PUB_ZQ0DR (DDR1_PUB_REG_BASE+(0x92<<2)) |
| #define ACBDLR_MAX 0X1F |
| #define ACLCDLR_MAX 0XFF |
| #define DQBDLR_MAX 0X1F |
| #define DQLCDLR_MAX 0XFF |
| #define DXNGTR_MAX 0X7 |
| |
| #define DMC_REG_BASE 0xc8006000 |
| #define DMC_MON_CTRL2 (DMC_REG_BASE + (0x26 <<2 )) |
| //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish. |
| //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt. |
| //bit 20. qos_mon_trig_sel. 1 = vsync. 0 = timer. |
| //bit 19:16. qos monitor channel select. select one at one time only. |
| //bit 15:0. port select for the selected channel. |
| #define DMC_MON_CTRL3 (DMC_REG_BASE + (0x27 <<2 )) |
| // qos_mon_clk_timer. How long to measure the bandwidth. |
| |
| |
| #define DMC_MON_ALL_REQ_CNT (DMC_REG_BASE + (0x28 <<2 )) |
| // at the test period, the whole MMC request time. |
| #define DMC_MON_ALL_GRANT_CNT (DMC_REG_BASE + (0x29 <<2 )) |
| // at the test period, the whole MMC granted data cycles. 64bits unit. |
| #define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 )) |
| // at the test period, the granted data cycles for the selected channel and ports. |
| #endif |
| |
| |
| |
| #if (CONFIG_DDR_PHY == P_DDR_PHY_905X) |
| |
| #define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2)) |
| #define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 ))// R/W - PHY General Configuration Register 0 |
| #define DDR0_PUB_PGCR1 ( DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1 |
| #define DDR0_PUB_PGCR2 (DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2 |
| #define DDR0_PUB_PGCR3 ( DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3 |
| #define DDR0_PUB_PGCR4 ( DDR0_PUB_REG_BASE + ( 0x008 << 2 )) // R/W - PHY General Configuration Register 4 |
| #define DDR0_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5 |
| #define DDR0_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6 |
| #define DDR0_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7 |
| #define DDR0_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 )) // R/W - PHY General Configuration Register 8 |
| |
| #define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2)) |
| #define DDR1_PUB_PGCR0 (DDR0_PUB_REG_BASE + ( 0x004 << 2 )) // R/W - PHY General Configuration Register 0 |
| #define DDR1_PUB_PGCR1 (DDR0_PUB_REG_BASE + ( 0x005 << 2 )) // R/W - PHY General Configuration Register 1 |
| #define DDR1_PUB_PGCR2 ( DDR0_PUB_REG_BASE + ( 0x006 << 2 )) // R/W - PHY General Configuration Register 2 |
| #define DDR1_PUB_PGCR3 (DDR0_PUB_REG_BASE + ( 0x007 << 2 )) // R/W - PHY General Configuration Register 3 |
| #define DDR1_PUB_PGCR4 (DDR0_PUB_REG_BASE + ( 0x008 << 2 ) )// R/W - PHY General Configuration Register 4 |
| #define DDR1_PUB_PGCR5 (DDR0_PUB_REG_BASE + ( 0x009 << 2 )) // R/W - PHY General Configuration Register 5 |
| #define DDR1_PUB_PGCR6 (DDR0_PUB_REG_BASE + ( 0x00A << 2 )) // R/W - PHY General Configuration Register 6 |
| #define DDR1_PUB_PGCR7 (DDR0_PUB_REG_BASE + ( 0x00B << 2 )) // R/W - PHY General Configuration Register 7 |
| #define DDR1_PUB_PGCR8 (DDR0_PUB_REG_BASE + ( 0x00C << 2 ) )// R/W - PHY General Configuration Register 8 |
| |
| #define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE + ( 0x1d0 << 2 )) |
| #define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE + ( 0x1d1 << 2 )) |
| #define DDR0_PUB_DX0BDLR2 ( DDR0_PUB_REG_BASE + ( 0x1d2 << 2 )) |
| #define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 )) |
| #define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2 )) |
| #define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2 )) |
| #define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2 )) |
| #define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE + ( 0x1e0 << 2 )) |
| #define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 )) |
| #define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE + ( 0x1e2 << 2 )) |
| #define DDR0_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 )) |
| #define DDR0_PUB_DX0LCDLR4 (DDR0_PUB_REG_BASE + ( 0x1e4 << 2 )) |
| #define DDR0_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 )) |
| #define DDR0_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 )) |
| #define DDR0_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2) ) |
| #define DDR0_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 )) |
| #define DDR0_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) ) |
| #define DDR0_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) ) |
| #define DDR0_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2)) |
| |
| #define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2) ) |
| #define DDR0_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2) ) |
| #define DDR0_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2) ) |
| #define DDR0_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2) ) |
| #define DDR0_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2) ) |
| #define DDR0_PUB_DX1BDLR5 ( DDR0_PUB_REG_BASE + ( 0x216 << 2) ) |
| #define DDR0_PUB_DX1BDLR6 ( DDR0_PUB_REG_BASE + ( 0x218 << 2) ) |
| #define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2) ) |
| #define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2) ) |
| #define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE + ( 0x222 << 2) ) |
| #define DDR0_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2) ) |
| #define DDR0_PUB_DX1LCDLR4 (DDR0_PUB_REG_BASE + ( 0x224 << 2) ) |
| #define DDR0_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2) ) |
| #define DDR0_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2) ) |
| #define DDR0_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2) ) |
| #define DDR0_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 )) |
| #define DDR0_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2) ) |
| #define DDR0_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2) ) |
| #define DDR0_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2) ) |
| |
| #define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2) ) |
| #define DDR0_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2) ) |
| #define DDR0_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2) ) |
| #define DDR0_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2) ) |
| #define DDR0_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2) ) |
| #define DDR0_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2) ) |
| #define DDR0_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2) ) |
| #define DDR0_PUB_DX2LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x260 << 2) ) |
| #define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2) ) |
| #define DDR0_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2) ) |
| #define DDR0_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2) ) |
| #define DDR0_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2) ) |
| #define DDR0_PUB_DX2LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x265 << 2) ) |
| #define DDR0_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2) ) |
| #define DDR0_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2) ) |
| #define DDR0_PUB_DX2GTR0 ( DDR0_PUB_REG_BASE + ( 0x270 << 2 )) |
| #define DDR0_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2) ) |
| #define DDR0_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2) ) |
| #define DDR0_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2) ) |
| |
| #define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2) ) |
| #define DDR0_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2) ) |
| #define DDR0_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2) ) |
| #define DDR0_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2) ) |
| #define DDR0_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2) ) |
| #define DDR0_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2) ) |
| #define DDR0_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2) ) |
| #define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2) ) |
| #define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2) ) |
| #define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE + ( 0x2a2 << 2) ) |
| #define DDR0_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2) ) |
| #define DDR0_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2) ) |
| #define DDR0_PUB_DX3LCDLR5 (DDR0_PUB_REG_BASE + ( 0x2a5 << 2) ) |
| #define DDR0_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2) ) |
| #define DDR0_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2) ) |
| #define DDR0_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 )) |
| #define DDR0_PUB_DX3GTR1 ( DDR0_PUB_REG_BASE + ( 0x2b1 << 2) ) |
| #define DDR0_PUB_DX3GTR2 ( DDR0_PUB_REG_BASE + ( 0x2b2 << 2) ) |
| #define DDR0_PUB_DX3GTR3 ( DDR0_PUB_REG_BASE + ( 0x2b3 << 2) ) |
| |
| #define DDR1_PUB_DX0BDLR0 ( DDR0_PUB_REG_BASE + ( 0x1d0 << 2) ) |
| #define DDR1_PUB_DX0BDLR1 ( DDR0_PUB_REG_BASE + ( 0x1d1 << 2) ) |
| #define DDR1_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE + ( 0x1d2 << 2 )) |
| #define DDR1_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE + ( 0x1d4 << 2 )) |
| #define DDR1_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE + ( 0x1d5 << 2) ) |
| #define DDR1_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE + ( 0x1d6 << 2) ) |
| #define DDR1_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE + ( 0x1d8 << 2) ) |
| #define DDR1_PUB_DX0LCDLR0 ( DDR0_PUB_REG_BASE + ( 0x1e0 << 2) ) |
| #define DDR1_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE + ( 0x1e1 << 2 )) |
| #define DDR1_PUB_DX0LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x1e2 << 2) ) |
| #define DDR1_PUB_DX0LCDLR3 (DDR0_PUB_REG_BASE + ( 0x1e3 << 2 )) |
| #define DDR1_PUB_DX0LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x1e4 << 2) ) |
| #define DDR1_PUB_DX0LCDLR5 (DDR0_PUB_REG_BASE + ( 0x1e5 << 2 )) |
| #define DDR1_PUB_DX0MDLR0 (DDR0_PUB_REG_BASE + ( 0x1e8 << 2 )) |
| #define DDR1_PUB_DX0MDLR1 (DDR0_PUB_REG_BASE + ( 0x1e9 << 2 )) |
| #define DDR1_PUB_DX0GTR0 (DDR0_PUB_REG_BASE + ( 0x1f0 << 2 )) |
| #define DDR1_PUB_DX0GTR1 (DDR0_PUB_REG_BASE + ( 0x1f1 << 2) ) |
| #define DDR1_PUB_DX0GTR2 (DDR0_PUB_REG_BASE + ( 0x1f2 << 2) ) |
| #define DDR1_PUB_DX0GTR3 (DDR0_PUB_REG_BASE + ( 0x1f3 << 2)) |
| |
| #define DDR1_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE + ( 0x210 << 2 )) |
| #define DDR1_PUB_DX1BDLR1 (DDR0_PUB_REG_BASE + ( 0x211 << 2 )) |
| #define DDR1_PUB_DX1BDLR2 (DDR0_PUB_REG_BASE + ( 0x212 << 2 )) |
| #define DDR1_PUB_DX1BDLR3 (DDR0_PUB_REG_BASE + ( 0x214 << 2 )) |
| #define DDR1_PUB_DX1BDLR4 (DDR0_PUB_REG_BASE + ( 0x215 << 2 )) |
| #define DDR1_PUB_DX1BDLR5 (DDR0_PUB_REG_BASE + ( 0x216 << 2 )) |
| #define DDR1_PUB_DX1BDLR6 (DDR0_PUB_REG_BASE + ( 0x218 << 2 )) |
| #define DDR1_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE + ( 0x220 << 2 )) |
| #define DDR1_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE + ( 0x221 << 2 )) |
| #define DDR1_PUB_DX1LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x222 << 2 )) |
| #define DDR1_PUB_DX1LCDLR3 (DDR0_PUB_REG_BASE + ( 0x223 << 2 )) |
| #define DDR1_PUB_DX1LCDLR4 ( DDR0_PUB_REG_BASE + ( 0x224 << 2 )) |
| #define DDR1_PUB_DX1LCDLR5 (DDR0_PUB_REG_BASE + ( 0x225 << 2 )) |
| #define DDR1_PUB_DX1MDLR0 (DDR0_PUB_REG_BASE + ( 0x228 << 2 )) |
| #define DDR1_PUB_DX1MDLR1 (DDR0_PUB_REG_BASE + ( 0x229 << 2 )) |
| #define DDR1_PUB_DX1GTR0 (DDR0_PUB_REG_BASE + ( 0x230 << 2 )) |
| #define DDR1_PUB_DX1GTR1 (DDR0_PUB_REG_BASE + ( 0x231 << 2 )) |
| #define DDR1_PUB_DX1GTR2 (DDR0_PUB_REG_BASE + ( 0x232 << 2 )) |
| #define DDR1_PUB_DX1GTR3 (DDR0_PUB_REG_BASE + ( 0x233 << 2 )) |
| |
| #define DDR1_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE + ( 0x250 << 2 )) |
| #define DDR1_PUB_DX2BDLR1 (DDR0_PUB_REG_BASE + ( 0x251 << 2 )) |
| #define DDR1_PUB_DX2BDLR2 (DDR0_PUB_REG_BASE + ( 0x252 << 2 )) |
| #define DDR1_PUB_DX2BDLR3 (DDR0_PUB_REG_BASE + ( 0x254 << 2 )) |
| #define DDR1_PUB_DX2BDLR4 (DDR0_PUB_REG_BASE + ( 0x255 << 2 )) |
| #define DDR1_PUB_DX2BDLR5 (DDR0_PUB_REG_BASE + ( 0x256 << 2 )) |
| #define DDR1_PUB_DX2BDLR6 (DDR0_PUB_REG_BASE + ( 0x258 << 2 )) |
| #define DDR1_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE + ( 0x260 << 2 )) |
| #define DDR1_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE + ( 0x261 << 2 )) |
| #define DDR1_PUB_DX2LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x262 << 2 )) |
| #define DDR1_PUB_DX2LCDLR3 (DDR0_PUB_REG_BASE + ( 0x263 << 2 )) |
| #define DDR1_PUB_DX2LCDLR4 (DDR0_PUB_REG_BASE + ( 0x264 << 2 )) |
| #define DDR1_PUB_DX2LCDLR5 (DDR0_PUB_REG_BASE + ( 0x265 << 2 )) |
| #define DDR1_PUB_DX2MDLR0 (DDR0_PUB_REG_BASE + ( 0x268 << 2 )) |
| #define DDR1_PUB_DX2MDLR1 (DDR0_PUB_REG_BASE + ( 0x269 << 2 )) |
| #define DDR1_PUB_DX2GTR0 (DDR0_PUB_REG_BASE + ( 0x270 << 2 )) |
| #define DDR1_PUB_DX2GTR1 (DDR0_PUB_REG_BASE + ( 0x271 << 2 )) |
| #define DDR1_PUB_DX2GTR2 (DDR0_PUB_REG_BASE + ( 0x272 << 2 )) |
| #define DDR1_PUB_DX2GTR3 (DDR0_PUB_REG_BASE + ( 0x273 << 2 )) |
| |
| #define DDR1_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE + ( 0x290 << 2 )) |
| #define DDR1_PUB_DX3BDLR1 (DDR0_PUB_REG_BASE + ( 0x291 << 2 )) |
| #define DDR1_PUB_DX3BDLR2 (DDR0_PUB_REG_BASE + ( 0x292 << 2 )) |
| #define DDR1_PUB_DX3BDLR3 (DDR0_PUB_REG_BASE + ( 0x294 << 2 )) |
| #define DDR1_PUB_DX3BDLR4 (DDR0_PUB_REG_BASE + ( 0x295 << 2 )) |
| #define DDR1_PUB_DX3BDLR5 (DDR0_PUB_REG_BASE + ( 0x296 << 2 )) |
| #define DDR1_PUB_DX3BDLR6 (DDR0_PUB_REG_BASE + ( 0x298 << 2 )) |
| #define DDR1_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE + ( 0x2a0 << 2 )) |
| #define DDR1_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE + ( 0x2a1 << 2 )) |
| #define DDR1_PUB_DX3LCDLR2 ( DDR0_PUB_REG_BASE + ( 0x2a2 << 2 )) |
| #define DDR1_PUB_DX3LCDLR3 (DDR0_PUB_REG_BASE + ( 0x2a3 << 2 )) |
| #define DDR1_PUB_DX3LCDLR4 (DDR0_PUB_REG_BASE + ( 0x2a4 << 2 )) |
| #define DDR1_PUB_DX3LCDLR5 ( DDR0_PUB_REG_BASE + ( 0x2a5 << 2 )) |
| #define DDR1_PUB_DX3MDLR0 (DDR0_PUB_REG_BASE + ( 0x2a8 << 2 )) |
| #define DDR1_PUB_DX3MDLR1 (DDR0_PUB_REG_BASE + ( 0x2a9 << 2 )) |
| #define DDR1_PUB_DX3GTR0 (DDR0_PUB_REG_BASE + ( 0x2b0 << 2 )) |
| #define DDR1_PUB_DX3GTR1 (DDR0_PUB_REG_BASE + ( 0x2b1 << 2 )) |
| #define DDR1_PUB_DX3GTR2 (DDR0_PUB_REG_BASE + ( 0x2b2 << 2 )) |
| #define DDR1_PUB_DX3GTR3 (DDR0_PUB_REG_BASE + ( 0x2b3 << 2 )) |
| |
| |
| #define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 )) // R/W - LC Delay Line Present Register |
| #define DDR0_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0 |
| #define DDR0_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1 |
| #define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE + ( 0x150 << 2 )) // R/W - AC Bit Delay Line Register 0 |
| #define DDR0_PUB_ACBDLR3 ( DDR0_PUB_REG_BASE + ( 0x153 << 2 ) ) // R/W - AC Bit Delay Line Register 3 |
| |
| #define DDR1_PUB_ACLCDLR (DDR0_PUB_REG_BASE + ( 0x160 << 2 ) )// R/W - LC Delay Line Present Register |
| #define DDR1_PUB_ACMDLR0 ( DDR0_PUB_REG_BASE + ( 0x168 << 2 )) // R/W - AC Master Delay Line Register 0 |
| #define DDR1_PUB_ACMDLR1 ( DDR0_PUB_REG_BASE + ( 0x169 << 2 )) // R/W - Master Delay Line Register 1 |
| #define DDR1_PUB_ACBDLR0 ( DDR0_PUB_REG_BASE + ( 0x150 << 2 ) )// R/W - AC Bit Delay Line Register 0 |
| |
| |
| #define DDR0_PUB_ACMDLR DDR0_PUB_ACMDLR0 |
| #define DDR1_PUB_ACMDLR DDR1_PUB_ACMDLR0 |
| #define DDR0_PUB_DX0GTR DDR0_PUB_DX0GTR0 |
| #define DDR0_PUB_DX1GTR DDR0_PUB_DX1GTR0 |
| #define DDR0_PUB_DX2GTR DDR0_PUB_DX2GTR0 |
| #define DDR0_PUB_DX3GTR DDR0_PUB_DX3GTR0 |
| #define DDR1_PUB_DX0GTR DDR0_PUB_DX0GTR0 |
| #define DDR1_PUB_DX1GTR DDR0_PUB_DX1GTR0 |
| #define DDR1_PUB_DX2GTR DDR0_PUB_DX2GTR0 |
| #define DDR1_PUB_DX3GTR DDR0_PUB_DX3GTR0 |
| |
| |
| #define DDR0_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0 |
| #define DDR0_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1 |
| #define DDR0_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 ) )// R/W - VREF Training Control Register 0 |
| #define DDR0_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1 |
| #define DDR1_PUB_IOVCR0 ( DDR0_PUB_REG_BASE + ( 0x148 << 2 )) // R/W - IO VREF Control Register 0 |
| #define DDR1_PUB_IOVCR1 ( DDR0_PUB_REG_BASE + ( 0x149 << 2 )) // R/W - IO VREF Control Register 1 |
| #define DDR1_PUB_VTCR0 ( DDR0_PUB_REG_BASE + ( 0x14A << 2 )) // R/W - VREF Training Control Register 0 |
| #define DDR1_PUB_VTCR1 ( DDR0_PUB_REG_BASE + ( 0x14B << 2 )) // R/W - VREF Training Control Register 1 |
| |
| #define DDR0_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6 |
| #define DDR1_PUB_MR6 ( DDR0_PUB_REG_BASE + ( 0x066 << 2 ) ) // R/W - Extended Mode Register 6 |
| #define DDR0_PUB_DX0GCR6 ( DDR0_PUB_REG_BASE + ( 0x1c6 << 2 ) ) |
| #define DDR0_PUB_DX1GCR6 ( DDR0_PUB_REG_BASE + ( 0x206 << 2 ) ) |
| #define DDR0_PUB_DX2GCR6 ( DDR0_PUB_REG_BASE + ( 0x246 << 2 ) ) |
| #define DDR0_PUB_DX3GCR6 ( DDR0_PUB_REG_BASE + ( 0x286 << 2 ) ) |
| #else |
| |
| #define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2)) |
| #define DDR0_PUB_PGCR0 (DDR0_PUB_REG_BASE+(0x02<<2)) |
| #define DDR0_PUB_PGCR1 (DDR0_PUB_REG_BASE+(0x03<<2)) |
| |
| #define DDR1_PUB_PIR (DDR1_PUB_REG_BASE+(0x01<<2)) |
| #define DDR1_PUB_PGCR0 (DDR1_PUB_REG_BASE+(0x02<<2)) |
| #define DDR1_PUB_PGCR1 (DDR1_PUB_REG_BASE+(0x03<<2)) |
| |
| #define DDR0_PUB_DX0BDLR0 (DDR0_PUB_REG_BASE+(0xA7<<2)) |
| #define DDR0_PUB_DX1BDLR0 (DDR0_PUB_REG_BASE+(0xC7<<2)) |
| #define DDR0_PUB_DX2BDLR0 (DDR0_PUB_REG_BASE+(0xE7<<2)) |
| #define DDR0_PUB_DX3BDLR0 (DDR0_PUB_REG_BASE+(0x107<<2)) |
| |
| #define DDR0_PUB_DX0BDLR1 (DDR0_PUB_REG_BASE+(0xA8<<2)) |
| #define DDR0_PUB_DX0BDLR2 (DDR0_PUB_REG_BASE+(0xA9<<2)) |
| #define DDR0_PUB_DX0BDLR3 (DDR0_PUB_REG_BASE+(0xAA<<2)) |
| #define DDR0_PUB_DX0BDLR4 (DDR0_PUB_REG_BASE+(0xAB<<2)) |
| #define DDR0_PUB_DX0BDLR5 (DDR0_PUB_REG_BASE+(0xAC<<2)) |
| #define DDR0_PUB_DX0BDLR6 (DDR0_PUB_REG_BASE+(0xAD<<2)) |
| |
| #define DDR0_PUB_DX0LCDLR0 (DDR0_PUB_REG_BASE+(0xAE<<2)) |
| #define DDR0_PUB_DX0LCDLR1 (DDR0_PUB_REG_BASE+(0xAF<<2)) |
| #define DDR0_PUB_DX0LCDLR2 (DDR0_PUB_REG_BASE+(0xB0<<2)) |
| #define DDR0_PUB_DX0MDLR (DDR0_PUB_REG_BASE+(0xB1<<2)) |
| #define DDR0_PUB_DX0GTR (DDR0_PUB_REG_BASE+(0xB2<<2)) |
| #define DDR0_PUB_DX1LCDLR0 (DDR0_PUB_REG_BASE+(0xCE<<2)) |
| #define DDR0_PUB_DX1LCDLR1 (DDR0_PUB_REG_BASE+(0xCF<<2)) |
| #define DDR0_PUB_DX1LCDLR2 (DDR0_PUB_REG_BASE+(0xD0<<2)) |
| #define DDR0_PUB_DX1MDLR (DDR0_PUB_REG_BASE+(0xD1<<2)) |
| #define DDR0_PUB_DX1GTR (DDR0_PUB_REG_BASE+(0xD2<<2)) |
| #define DDR0_PUB_DX2LCDLR0 (DDR0_PUB_REG_BASE+(0xEE<<2)) |
| #define DDR0_PUB_DX2LCDLR1 (DDR0_PUB_REG_BASE+(0xEF<<2)) |
| #define DDR0_PUB_DX2LCDLR2 (DDR0_PUB_REG_BASE+(0xF0<<2)) |
| #define DDR0_PUB_DX2MDLR (DDR0_PUB_REG_BASE+(0xF1<<2)) |
| #define DDR0_PUB_DX3LCDLR0 (DDR0_PUB_REG_BASE+(0x10E<<2)) |
| #define DDR0_PUB_DX3LCDLR1 (DDR0_PUB_REG_BASE+(0x10F<<2)) |
| #define DDR0_PUB_DX3LCDLR2 (DDR0_PUB_REG_BASE+(0x110<<2)) |
| #define DDR0_PUB_DX3MDLR (DDR0_PUB_REG_BASE+(0x111<<2)) |
| #define DDR0_PUB_DX3GTR (DDR0_PUB_REG_BASE+(0x112<<2)) |
| |
| #define DDR1_PUB_DX0LCDLR0 (DDR1_PUB_REG_BASE+(0xAE<<2)) |
| #define DDR1_PUB_DX0LCDLR1 (DDR1_PUB_REG_BASE+(0xAF<<2)) |
| #define DDR1_PUB_DX0LCDLR2 (DDR1_PUB_REG_BASE+(0xB0<<2)) |
| #define DDR1_PUB_DX0MDLR (DDR1_PUB_REG_BASE+(0xB1<<2)) |
| #define DDR1_PUB_DX0GTR (DDR1_PUB_REG_BASE+(0xB2<<2)) |
| #define DDR1_PUB_DX1LCDLR0 (DDR1_PUB_REG_BASE+(0xCE<<2)) |
| #define DDR1_PUB_DX1LCDLR1 (DDR1_PUB_REG_BASE+(0xCF<<2)) |
| #define DDR1_PUB_DX1LCDLR2 (DDR1_PUB_REG_BASE+(0xD0<<2)) |
| #define DDR1_PUB_DX1MDLR (DDR1_PUB_REG_BASE+(0xD1<<2)) |
| #define DDR1_PUB_DX1GTR (DDR1_PUB_REG_BASE+(0xD2<<2)) |
| #define DDR1_PUB_DX2LCDLR0 (DDR1_PUB_REG_BASE+(0xEE<<2)) |
| #define DDR1_PUB_DX2LCDLR1 (DDR1_PUB_REG_BASE+(0xEF<<2)) |
| #define DDR1_PUB_DX2LCDLR2 (DDR1_PUB_REG_BASE+(0xF0<<2)) |
| #define DDR1_PUB_DX2MDLR (DDR1_PUB_REG_BASE+(0xF1<<2)) |
| #define DDR1_PUB_DX3LCDLR0 (DDR1_PUB_REG_BASE+(0x10E<<2)) |
| #define DDR1_PUB_DX3LCDLR1 (DDR1_PUB_REG_BASE+(0x10F<<2)) |
| #define DDR1_PUB_DX3LCDLR2 (DDR1_PUB_REG_BASE+(0x110<<2)) |
| #define DDR1_PUB_DX3MDLR (DDR1_PUB_REG_BASE+(0x111<<2)) |
| #define DDR1_PUB_DX3GTR (DDR1_PUB_REG_BASE+(0x112<<2)) |
| |
| |
| #define DDR0_PUB_ACMDLR (DDR0_PUB_REG_BASE+(0x0E<<2)) |
| #define DDR0_PUB_ACLCDLR (DDR0_PUB_REG_BASE+(0x0F<<2)) |
| #define DDR0_PUB_ACBDLR0 (DDR0_PUB_REG_BASE+(0x10<<2)) |
| #define DDR0_PUB_ACBDLR3 (DDR0_PUB_REG_BASE+(0x13<<2)) |
| #define DDR1_PUB_ACMDLR (DDR1_PUB_REG_BASE+(0x0E<<2)) |
| #define DDR1_PUB_ACLCDLR (DDR1_PUB_REG_BASE+(0x0F<<2)) |
| #define DDR1_PUB_ACBDLR0 (DDR1_PUB_REG_BASE+(0x10<<2)) |
| |
| #define DDR0_PUB_ACMDLR0 DDR0_PUB_ACMDLR |
| #define DDR1_PUB_ACMDLR0 DDR1_PUB_ACMDLR |
| #define DDR0_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR |
| #define DDR0_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR |
| #define DDR0_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR |
| #define DDR0_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR |
| #define DDR1_PUB_DX0MDLR0 DDR0_PUB_DX0MDLR |
| #define DDR1_PUB_DX1MDLR0 DDR0_PUB_DX1MDLR |
| #define DDR1_PUB_DX2MDLR0 DDR0_PUB_DX2MDLR |
| #define DDR1_PUB_DX3MDLR0 DDR0_PUB_DX3MDLR |
| |
| #ifndef P_DDR0_CLK_CTRL |
| #define P_DDR0_CLK_CTRL 0xc8000800 |
| #endif |
| #ifndef P_DDR1_CLK_CTRL |
| #define P_DDR1_CLK_CTRL 0xc8002800 |
| #endif |
| |
| #define DDR0_PUB_IOVCR0 (DDR0_PUB_REG_BASE+(0x8E<<2)) |
| #define DDR0_PUB_IOVCR1 (DDR0_PUB_REG_BASE+(0x8F<<2)) |
| #endif |
| |
| #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) |
| //unsigned int des[8]; |
| /* |
| unsigned int pattern_1[4][8]= |
| { |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| 0xff00ff00 , |
| |
| }; |
| unsigned int pattern_2[4][8]={ |
| 0x0001fe00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0002fd00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0004fb00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0008f700 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0010ef00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0020df00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0040bf00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x00807f00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| 0x0000ff00 , |
| |
| }; |
| unsigned int pattern_3[4][8]={ |
| 0x00010000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00020000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00040000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00080000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00100000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00200000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00400000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00800000 , |
| 0x00000000 , |
| 0x00000000 , |
| 0x00000000 , |
| }; |
| unsigned int pattern_4[4][8]={ |
| 0x51c8c049 , |
| 0x2d43592c , |
| 0x0777b50b , |
| 0x9cd2ebe5 , |
| 0xc04199d5 , |
| 0xdc968dc0 , |
| 0xb8ba8a33 , |
| 0x35e4327f , |
| 0x51c8c049 , |
| 0x2d43592c , |
| 0x0777b50b , |
| 0x9cd2ebe5 , |
| 0xc04199d5 , |
| 0xdc968dc0 , |
| 0xb8ba8a33 , |
| 0x35e4327f , |
| 0x51c8c049 , |
| 0x2d43592c , |
| 0x0777b50b , |
| 0x9cd2ebe5 , |
| 0xc04199d5 , |
| 0xdc968dc0 , |
| 0xb8ba8a33 , |
| 0x35e4327f , |
| 0x51c8c049 , |
| 0x2d43592c , |
| 0x0777b50b , |
| 0x9cd2ebe5 , |
| 0xc04199d5 , |
| 0xdc968dc0 , |
| 0xb8ba8a33 , |
| 0x35e4327f , |
| }; |
| unsigned int pattern_5[4][8]={ |
| 0xaec9c149 , |
| 0xd243592c , |
| 0xf877b50b , |
| 0x63d2ebe5 , |
| 0x3f439bd5 , |
| 0x23968dc0 , |
| 0x47ba8a33 , |
| 0xcae4327f , |
| 0xaeccc449 , |
| 0xd243592c , |
| 0xf877b50b , |
| 0x63d2ebe5 , |
| 0x3f4991d5 , |
| 0x23968dc0 , |
| 0x47ba8a33 , |
| 0xcae4327f , |
| 0xaed8d049 , |
| 0xd243592c , |
| 0xf877b50b , |
| 0x63d2ebe5 , |
| 0x3f61b9d5 , |
| 0x23968dc0 , |
| 0x47ba8a33 , |
| 0xcae4327f , |
| 0xae888049 , |
| 0xd243592c , |
| 0xf877b50b , |
| 0x63d2ebe5 , |
| 0x3fc119d5 , |
| 0x23968dc0 , |
| 0x47ba8a33 , |
| 0xcae4327f , |
| }; |
| unsigned int pattern_6[4][8]={ |
| 0xaec9c149 , |
| 0xd243a62c , |
| 0xf8774a0b , |
| 0x63d214e5 , |
| 0x3f4366d5 , |
| 0x239672c0 , |
| 0x47ba7533 , |
| 0xcae4cd7f , |
| 0xaecc3f49 , |
| 0xd243a62c , |
| 0xf8774a0b , |
| 0x63d214e5 , |
| 0x3f4966d5 , |
| 0x239672c0 , |
| 0x47ba7533 , |
| 0xcae4cd7f , |
| 0xaed83f49 , |
| 0xd243a62c , |
| 0xf8774a0b , |
| 0x63d214e5 , |
| 0x3f6166d5 , |
| 0x239672c0 , |
| 0x47ba7533 , |
| 0xcae4cd7f , |
| 0xae883f49 , |
| 0xd243a62c , |
| 0xf8774a0b , |
| 0x63d214e5 , |
| 0x3fc166d5 , |
| 0x239672c0 , |
| 0x47ba7533 , |
| 0xcae4cd7f , |
| |
| }; |
| unsigned int des[8] ={ |
| 0xaec83f49, |
| 0xd243a62c, |
| 0xf8774a0b, |
| 0x63d214e5, |
| 0x3f4166d5, |
| 0x239672c0, |
| 0x47ba7533, |
| 0xcae4cd7f, |
| }; |
| */ |
| /* |
| unsigned int des[8] ; |
| des[0] = 0xaec83f49; |
| des[1] = 0xd243a62c; |
| des[2] = 0xf8774a0b; |
| des[3] = 0x63d214e5; |
| des[4] = 0x3f4166d5; |
| des[5] = 0x239672c0; |
| des[6] = 0x47ba7533; |
| des[7] = 0xcae4cd7f; |
| pattern_1[0][0] = 0xff00ff00; |
| pattern_1[0][1] = 0xff00ff00; |
| pattern_1[0][2] = 0xff00ff00; |
| pattern_1[0][3] = 0xff00ff00; |
| pattern_1[0][4] = 0xff00ff00; |
| pattern_1[0][5] = 0xff00ff00; |
| pattern_1[0][6] = 0xff00ff00; |
| pattern_1[0][7] = 0xff00ff00; |
| |
| pattern_1[1][0] = 0xff00ff00; |
| pattern_1[1][1] = 0xff00ff00; |
| pattern_1[1][2] = 0xff00ff00; |
| pattern_1[1][3] = 0xff00ff00; |
| pattern_1[1][4] = 0xff00ff00; |
| pattern_1[1][5] = 0xff00ff00; |
| pattern_1[1][6] = 0xff00ff00; |
| pattern_1[1][7] = 0xff00ff00; |
| |
| pattern_1[2][0] = 0xff00ff00; |
| pattern_1[2][1] = 0xff00ff00; |
| pattern_1[2][2] = 0xff00ff00; |
| pattern_1[2][3] = 0xff00ff00; |
| pattern_1[2][4] = 0xff00ff00; |
| pattern_1[2][5] = 0xff00ff00; |
| pattern_1[2][6] = 0xff00ff00; |
| pattern_1[2][7] = 0xff00ff00; |
| |
| pattern_1[3][0] = 0xff00ff00; |
| pattern_1[3][1] = 0xff00ff00; |
| pattern_1[3][2] = 0xff00ff00; |
| pattern_1[3][3] = 0xff00ff00; |
| pattern_1[3][4] = 0xff00ff00; |
| pattern_1[3][5] = 0xff00ff00; |
| pattern_1[3][6] = 0xff00ff00; |
| pattern_1[3][7] = 0xff00ff00; |
| |
| pattern_2[0][0] = 0x0001fe00; |
| pattern_2[0][1] = 0x0000ff00; |
| pattern_2[0][2] = 0x0000ff00; |
| pattern_2[0][3] = 0x0000ff00; |
| pattern_2[0][4] = 0x0002fd00; |
| pattern_2[0][5] = 0x0000ff00; |
| pattern_2[0][6] = 0x0000ff00; |
| pattern_2[0][7] = 0x0000ff00; |
| |
| pattern_2[1][0] = 0x0004fb00; |
| pattern_2[1][1] = 0x0000ff00; |
| pattern_2[1][2] = 0x0000ff00; |
| pattern_2[1][3] = 0x0000ff00; |
| pattern_2[1][4] = 0x0008f700; |
| pattern_2[1][5] = 0x0000ff00; |
| pattern_2[1][6] = 0x0000ff00; |
| pattern_2[1][7] = 0x0000ff00; |
| |
| pattern_2[2][0] = 0x0010ef00; |
| pattern_2[2][1] = 0x0000ff00; |
| pattern_2[2][2] = 0x0000ff00; |
| pattern_2[2][3] = 0x0000ff00; |
| pattern_2[2][4] = 0x0020df00; |
| pattern_2[2][5] = 0x0000ff00; |
| pattern_2[2][6] = 0x0000ff00; |
| pattern_2[2][7] = 0x0000ff00; |
| |
| pattern_2[3][0] = 0x0040bf00; |
| pattern_2[3][1] = 0x0000ff00; |
| pattern_2[3][2] = 0x0000ff00; |
| pattern_2[3][3] = 0x0000ff00; |
| pattern_2[3][4] = 0x00807f00; |
| pattern_2[3][5] = 0x0000ff00; |
| pattern_2[3][6] = 0x0000ff00; |
| pattern_2[3][7] = 0x0000ff00; |
| |
| pattern_3[0][0] = 0x00010000; |
| pattern_3[0][1] = 0x00000000; |
| pattern_3[0][2] = 0x00000000; |
| pattern_3[0][3] = 0x00000000; |
| pattern_3[0][4] = 0x00020000; |
| pattern_3[0][5] = 0x00000000; |
| pattern_3[0][6] = 0x00000000; |
| pattern_3[0][7] = 0x00000000; |
| |
| pattern_3[1][0] = 0x00040000; |
| pattern_3[1][1] = 0x00000000; |
| pattern_3[1][2] = 0x00000000; |
| pattern_3[1][3] = 0x00000000; |
| pattern_3[1][4] = 0x00080000; |
| pattern_3[1][5] = 0x00000000; |
| pattern_3[1][6] = 0x00000000; |
| pattern_3[1][7] = 0x00000000; |
| |
| pattern_3[2][0] = 0x00100000; |
| pattern_3[2][1] = 0x00000000; |
| pattern_3[2][2] = 0x00000000; |
| pattern_3[2][3] = 0x00000000; |
| pattern_3[2][4] = 0x00200000; |
| pattern_3[2][5] = 0x00000000; |
| pattern_3[2][6] = 0x00000000; |
| pattern_3[2][7] = 0x00000000; |
| |
| pattern_3[3][0] = 0x00400000; |
| pattern_3[3][1] = 0x00000000; |
| pattern_3[3][2] = 0x00000000; |
| pattern_3[3][3] = 0x00000000; |
| pattern_3[3][4] = 0x00800000; |
| pattern_3[3][5] = 0x00000000; |
| pattern_3[3][6] = 0x00000000; |
| pattern_3[3][7] = 0x00000000; |
| |
| pattern_4[0][0] = 0x51c8c049 ; |
| pattern_4[0][1] = 0x2d43592c ; |
| pattern_4[0][2] = 0x0777b50b ; |
| pattern_4[0][3] = 0x9cd2ebe5 ; |
| pattern_4[0][4] = 0xc04199d5 ; |
| pattern_4[0][5] = 0xdc968dc0 ; |
| pattern_4[0][6] = 0xb8ba8a33 ; |
| pattern_4[0][7] = 0x35e4327f ; |
| |
| pattern_4[1][0] = 0x51c8c049 ; |
| pattern_4[1][1] = 0x2d43592c ; |
| pattern_4[1][2] = 0x0777b50b ; |
| pattern_4[1][3] = 0x9cd2ebe5 ; |
| pattern_4[1][4] = 0xc04199d5 ; |
| pattern_4[1][5] = 0xdc968dc0 ; |
| pattern_4[1][6] = 0xb8ba8a33 ; |
| pattern_4[1][7] = 0x35e4327f ; |
| |
| pattern_4[2][0] = 0x51c8c049 ; |
| pattern_4[2][1] = 0x2d43592c ; |
| pattern_4[2][2] = 0x0777b50b ; |
| pattern_4[2][3] = 0x9cd2ebe5 ; |
| pattern_4[2][4] = 0xc04199d5 ; |
| pattern_4[2][5] = 0xdc968dc0 ; |
| pattern_4[2][6] = 0xb8ba8a33 ; |
| pattern_4[2][7] = 0x35e4327f ; |
| |
| pattern_4[3][0] = 0x51c8c049 ; |
| pattern_4[3][1] = 0x2d43592c ; |
| pattern_4[3][2] = 0x0777b50b ; |
| pattern_4[3][3] = 0x9cd2ebe5 ; |
| pattern_4[3][4] = 0xc04199d5 ; |
| pattern_4[3][5] = 0xdc968dc0 ; |
| pattern_4[3][6] = 0xb8ba8a33 ; |
| pattern_4[3][7] = 0x35e4327f ; |
| |
| pattern_5[0][0] = 0xaec9c149 ; |
| pattern_5[0][1] = 0xd243592c ; |
| pattern_5[0][2] = 0xf877b50b ; |
| pattern_5[0][3] = 0x63d2ebe5 ; |
| pattern_5[0][4] = 0x3f439bd5 ; |
| pattern_5[0][5] = 0x23968dc0 ; |
| pattern_5[0][6] = 0x47ba8a33 ; |
| pattern_5[0][7] = 0xcae4327f ; |
| pattern_5[1][0] = 0xaeccc449 ; |
| pattern_5[1][1] = 0xd243592c ; |
| pattern_5[1][2] = 0xf877b50b ; |
| pattern_5[1][3] = 0x63d2ebe5 ; |
| pattern_5[1][4] = 0x3f4991d5 ; |
| pattern_5[1][5] = 0x23968dc0 ; |
| pattern_5[1][6] = 0x47ba8a33 ; |
| pattern_5[1][7] = 0xcae4327f ; |
| pattern_5[2][0] = 0xaed8d049 ; |
| pattern_5[2][1] = 0xd243592c ; |
| pattern_5[2][2] = 0xf877b50b ; |
| pattern_5[2][3] = 0x63d2ebe5 ; |
| pattern_5[2][4] = 0x3f61b9d5 ; |
| pattern_5[2][5] = 0x23968dc0 ; |
| pattern_5[2][6] = 0x47ba8a33 ; |
| pattern_5[2][7] = 0xcae4327f ; |
| pattern_5[3][0] = 0xae888049 ; |
| pattern_5[3][1] = 0xd243592c ; |
| pattern_5[3][2] = 0xf877b50b ; |
| pattern_5[3][3] = 0x63d2ebe5 ; |
| pattern_5[3][4] = 0x3fc119d5 ; |
| pattern_5[3][5] = 0x23968dc0 ; |
| pattern_5[3][6] = 0x47ba8a33 ; |
| pattern_5[3][7] = 0xcae4327f ; |
| |
| pattern_6[0][1] = 0xd243a62c ; |
| pattern_6[0][2] = 0xf8774a0b ; |
| pattern_6[0][3] = 0x63d214e5 ; |
| pattern_6[0][4] = 0x3f4366d5 ; |
| pattern_6[0][5] = 0x239672c0 ; |
| pattern_6[0][6] = 0x47ba7533 ; |
| pattern_6[0][7] = 0xcae4cd7f ; |
| pattern_6[1][0] = 0xaecc3f49 ; |
| pattern_6[1][1] = 0xd243a62c ; |
| pattern_6[1][2] = 0xf8774a0b ; |
| pattern_6[1][3] = 0x63d214e5 ; |
| pattern_6[1][4] = 0x3f4966d5 ; |
| pattern_6[1][5] = 0x239672c0 ; |
| pattern_6[1][6] = 0x47ba7533 ; |
| pattern_6[1][7] = 0xcae4cd7f ; |
| pattern_6[2][0] = 0xaed83f49 ; |
| pattern_6[2][1] = 0xd243a62c ; |
| pattern_6[2][2] = 0xf8774a0b ; |
| pattern_6[2][3] = 0x63d214e5 ; |
| pattern_6[2][4] = 0x3f6166d5 ; |
| pattern_6[2][5] = 0x239672c0 ; |
| pattern_6[2][6] = 0x47ba7533 ; |
| pattern_6[2][7] = 0xcae4cd7f ; |
| pattern_6[3][0] = 0xae883f49 ; |
| pattern_6[3][1] = 0xd243a62c ; |
| pattern_6[3][2] = 0xf8774a0b ; |
| pattern_6[3][3] = 0x63d214e5 ; |
| pattern_6[3][4] = 0x3fc166d5 ; |
| pattern_6[3][5] = 0x239672c0 ; |
| pattern_6[3][6] = 0x47ba7533 ; |
| pattern_6[3][7] = 0xcae4cd7f ; |
| */ |
| #endif |
| |
| #define DDR_TEST_START_ADDR 0x1080000// 0x10000000 //CONFIG_SYS_MEMTEST_START |
| #define DDR_TEST_SIZE 0x2000000 |
| //#define DDR_TEST_SIZE 0x2000 |
| |
| static void ddr_write(void *buff, unsigned int m_length) |
| { |
| unsigned int *p; |
| unsigned int i, j, n; |
| unsigned int m_len = m_length; |
| |
| p = ( unsigned int *)buff; |
| |
| while (m_len) |
| { |
| for (j=0;j<32;j++) |
| { |
| |
| if (m_len >= 128) |
| n = 32; |
| else |
| n = m_len>>2; |
| |
| for (i = 0; i < n; i++) |
| { |
| #ifdef DDR_PREFETCH_CACHE |
| ddr_pld_cache(p) ; |
| #endif |
| switch (i) |
| { |
| case 0: |
| case 9: |
| case 14: |
| case 25: |
| case 30: |
| *(p+i) = TDATA32F; |
| break; |
| case 1: |
| case 6: |
| case 8: |
| case 17: |
| case 22: |
| *(p+i) = 0; |
| break; |
| case 16: |
| case 23: |
| case 31: |
| *(p+i) = TDATA32A; |
| break; |
| case 7: |
| case 15: |
| case 24: |
| *(p+i) = TDATA325; |
| break; |
| case 2: |
| case 4: |
| case 10: |
| case 12: |
| case 19: |
| case 21: |
| case 27: |
| case 29: |
| *(p+i) = 1<<j; |
| break; |
| case 3: |
| case 5: |
| case 11: |
| case 13: |
| case 18: |
| case 20: |
| case 26: |
| case 28: |
| *(p+i) = ~(1<<j); |
| break; |
| } |
| } |
| |
| if (m_len > 128) |
| { |
| m_len -= 128; |
| p += 32; |
| } |
| else |
| { |
| p += (m_len>>2); |
| m_len = 0; |
| break; |
| } |
| } |
| } |
| } |
| |
| |
| |
| |
| |
| static void ddr_read(void *buff, unsigned int m_length) |
| { |
| unsigned int *p; |
| unsigned int i, j, n; |
| unsigned int m_len = m_length; |
| |
| p = ( unsigned int *)buff; |
| |
| while (m_len) |
| { |
| for (j=0;j<32;j++) |
| { |
| |
| if (m_len >= 128) |
| n = 32; |
| else |
| n = m_len>>2; |
| |
| for (i = 0; i < n; i++) |
| { |
| #ifdef DDR_PREFETCH_CACHE |
| ddr_pld_cache(p) ; |
| #endif |
| if ((error_outof_count_flag) && (error_count)) |
| { |
| printf("Error data out of count"); |
| m_len=0; |
| break; |
| } |
| switch (i) |
| { |
| |
| case 0: |
| case 9: |
| case 14: |
| case 25: |
| case 30: |
| if (*(p+i) != TDATA32F) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| case 1: |
| case 6: |
| case 8: |
| case 17: |
| case 22: |
| if (*(p+i) != 0) {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 0); |
| }break; |
| case 16: |
| case 23: |
| case 31: |
| if (*(p+i) != TDATA32A) {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32A); |
| } break; |
| case 7: |
| case 15: |
| case 24: |
| if (*(p+i) != TDATA325) {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA325); |
| } break; |
| case 2: |
| case 4: |
| case 10: |
| case 12: |
| case 19: |
| case 21: |
| case 27: |
| case 29: |
| if (*(p+i) != 1<<j) {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), 1<<j); |
| } break; |
| case 3: |
| case 5: |
| case 11: |
| case 13: |
| case 18: |
| case 20: |
| case 26: |
| case 28: |
| if (*(p+i) != ~(1<<j)) {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), ~(1<<j)); |
| } break; |
| } |
| } |
| |
| if (m_len > 128) |
| { |
| m_len -= 128; |
| p += 32; |
| } |
| else |
| { |
| p += (m_len>>2); |
| m_len = 0; |
| break; |
| } |
| } |
| } |
| } |
| |
| |
| |
| |
| static void ddr_write4(void *buff, unsigned int m_length) |
| { |
| unsigned int *p; |
| unsigned int i, j, n; |
| unsigned int m_len = m_length; |
| |
| p = ( unsigned int *)buff; |
| |
| while (m_len) |
| { |
| for (j=0;j<32;j++) |
| { |
| |
| if (m_len >= 128) |
| n = 32; |
| else |
| n = m_len>>2; |
| |
| for (i = 0; i < n; i++) |
| { |
| #ifdef DDR_PREFETCH_CACHE |
| ddr_pld_cache(p) ; |
| #endif |
| switch (i) |
| { |
| case 0: |
| case 1: |
| case 2: |
| case 3: |
| |
| *(p+i) = 0xff00ff00; |
| break; |
| case 4: |
| case 5: |
| case 6: |
| case 7: |
| |
| *(p+i) = ~0xff00ff00; |
| break; |
| case 8: |
| case 9: |
| case 10: |
| case 11: |
| *(p+i) = 0xaa55aa55; |
| break; |
| case 12: |
| case 13: |
| case 14: |
| case 15: |
| *(p+i) = ~0xaa55aa55; |
| break; |
| case 16: |
| case 17: |
| case 18: |
| case 19: |
| |
| case 24: |
| case 25: |
| case 26: |
| case 27: |
| |
| *(p+i) = 1<<j; |
| break; |
| |
| case 20: |
| case 21: |
| case 22: |
| case 23: |
| case 28: |
| case 29: |
| case 30: |
| case 31: |
| *(p+i) = ~(1<<j); |
| break; |
| } |
| } |
| |
| if (m_len > 128) |
| { |
| m_len -= 128; |
| p += 32; |
| } |
| else |
| { |
| p += (m_len>>2); |
| m_len = 0; |
| break; |
| } |
| } |
| } |
| } |
| |
| |
| |
| |
| |
| |
| |
| static void ddr_read4(void *buff, unsigned int m_length) |
| { |
| unsigned int *p; |
| unsigned int i, j, n; |
| unsigned int m_len = m_length; |
| |
| p = ( unsigned int *)buff; |
| |
| while (m_len) |
| { |
| for (j=0;j<32;j++) |
| { |
| |
| if (m_len >= 128) |
| n = 32; |
| else |
| n = m_len>>2; |
| |
| for (i = 0; i < n; i++) |
| { |
| #ifdef DDR_PREFETCH_CACHE |
| ddr_pld_cache(p) ; |
| #endif |
| if ((error_outof_count_flag) && (error_count)) |
| { |
| printf("Error data out of count"); |
| m_len=0; |
| break; |
| } |
| switch (i) |
| { |
| |
| case 0: |
| case 1: |
| case 2: |
| case 3: |
| |
| // *(p+i) = 0xff00ff00; |
| if (*(p+i) != 0xff00ff00) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| case 4: |
| case 5: |
| case 6: |
| case 7: |
| |
| // *(p+i) = ~0xff00ff00; |
| if (*(p+i) != ~0xff00ff00) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| case 8: |
| case 9: |
| case 10: |
| case 11: |
| // *(p+i) = 0xaa55aa55; |
| if (*(p+i) != 0xaa55aa55) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| case 12: |
| case 13: |
| case 14: |
| case 15: |
| // *(p+i) = ~0xaa55aa55; |
| if (*(p+i) != ~0xaa55aa55) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| case 16: |
| case 17: |
| case 18: |
| case 19: |
| |
| case 24: |
| case 25: |
| case 26: |
| case 27: |
| |
| // *(p+i) = 1<<j; |
| if (*(p+i) != (1<<j)) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| |
| case 20: |
| case 21: |
| case 22: |
| case 23: |
| case 28: |
| case 29: |
| case 30: |
| case 31: |
| // *(p+i) = ~(1<<j); |
| if (*(p+i) !=~( 1<<j)) |
| {error_count++; |
| printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i), TDATA32F); |
| } |
| break; |
| } |
| } |
| |
| if (m_len > 128) |
| { |
| m_len -= 128; |
| p += 32; |
| } |
| else |
| { |
| p += (m_len>>2); |
| m_len = 0; |
| break; |
| } |
| } |
| } |
| } |
| |
| ///* |
| static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size) |
| { |
| unsigned int *p_dest; |
| unsigned int *p_src; |
| |
| unsigned int m_len = memcpy_size; |
| |
| p_dest = ( unsigned int *)addr_dest; |
| p_src = ( unsigned int *)addr_src; |
| m_len = m_len/4; //assume it's multiple of 4 |
| while (m_len--) { |
| ddr_pld_cache(p_src) ;//#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P)) |
| *p_dest++ = *p_src++; |
| *p_dest++ = *p_src++; |
| *p_dest++ = *p_src++; |
| *p_dest++ = *p_src++; |
| } |
| } |
| //*/ |
| /* |
| static void ddr_test_copy(void *addr_dest,void *addr_src,unsigned int memcpy_size) |
| { |
| // unsigned int *p_dest; |
| // unsigned int *p_src; |
| |
| unsigned int m_len = memcpy_size; |
| unsigned int temp3 = 0; |
| unsigned int temp4 = 0; |
| |
| asm ("mov %0,%1"::"r" (temp4),"r" (addr_dest)); |
| asm ("subs %0,%0,#8"::"r" (m_len)); |
| asm ("1: ldr %0,[%1],#8"::"r" (temp3),"r" (addr_src)); |
| asm ("subs %0,%0,#8"::"r" (m_len)); |
| asm ("str %0,[%1],#8"::"r" (temp3),"r" (temp4)); |
| asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (addr_src)); |
| asm ("b.pl 1b"::); |
| asm ("ret"::); |
| |
| |
| |
| |
| |
| } |
| */ |
| int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) |
| { |
| char *endp; |
| unsigned long loop = 1; |
| unsigned int print_flag =1; |
| // unsigned int start_addr = DDR_TEST_START_ADDR; |
| unsigned int src_addr = DDR_TEST_START_ADDR; |
| unsigned int dec_addr = DDR_TEST_START_ADDR+0x8000000; |
| unsigned int test_size = DDR_TEST_SIZE; |
| |
| |
| print_flag=1; |
| |
| printf("\nargc== 0x%08x\n", argc); |
| int i ; |
| for (i = 0;i<argc;i++) |
| { |
| printf("\nargv[%d]=%s\n",i,argv[i]); |
| } |
| |
| |
| |
| // printf("\nLINE== 0x%08x\n", __LINE__); |
| if (argc ==1) { |
| // start_addr = simple_strtoul(argv[2], &endp, 16); |
| // if (*argv[2] == 0 || *endp != 0) |
| src_addr = DDR_TEST_START_ADDR; |
| loop = 1; |
| |
| } |
| if (argc > 2) { |
| // start_addr = simple_strtoul(argv[2], &endp, 16); |
| if (*argv[2] == 0 || *endp != 0) |
| src_addr = DDR_TEST_START_ADDR; |
| |
| } |
| if (argc > 3) { |
| |
| src_addr = simple_strtoul(argv[1], &endp, 16); |
| dec_addr = simple_strtoul(argv[2], &endp, 16); |
| test_size = simple_strtoul(argv[3], &endp, 16); |
| loop = 1; |
| if (*argv[3] == 0 || *endp != 0) |
| test_size = DDR_TEST_SIZE; |
| |
| } |
| if (test_size<0x1000) |
| test_size = DDR_TEST_SIZE; |
| if (argc > 4) { |
| loop = simple_strtoul(argv[4], &endp, 16); |
| if (*argv[4] == 0 || *endp != 0) |
| loop = 1; |
| } |
| if (argc > 5) { |
| print_flag = simple_strtoul(argv[5], &endp, 16); |
| if (*argv[5] == 0 || *endp != 0) |
| print_flag = 1; |
| } |
| //COPY_TEST_START: |
| |
| ///* |
| unsigned long time_start, time_end,test_loops; |
| test_loops=loop; |
| unsigned long size_count=0; |
| size_count=loop*test_size; |
| time_start = get_us_time();//us |
| |
| do { |
| |
| // loop = 1; |
| |
| |
| ddr_test_copy((void *)(int_convter_p(dec_addr)),(void *)(int_convter_p(src_addr)),test_size); |
| //bcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size); |
| //mcopy((void *)(int_convter_p(src_addr)),(void *)(int_convter_p(dec_addr)),test_size); |
| if (print_flag) |
| { |
| printf("\nloop==0x%08x", ( unsigned int )loop); |
| printf("\n \n"); |
| } |
| }while(--loop); |
| //*/ |
| time_end = get_us_time();//us |
| printf("\ncopy %d times use %dus\n \n",( unsigned int )test_loops,( unsigned int )(time_end-time_start)); |
| |
| printf("\nddr copy bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); |
| printf("\rEnd ddr test. \n"); |
| |
| unsigned int m_len=0,counter=0; |
| unsigned int *p_dest; |
| p_dest= (void *)(int_convter_p(dec_addr)); |
| m_len = test_size/4; //assume it's multiple of 4 |
| counter=(unsigned int)test_loops; |
| size_count=counter*test_size; |
| time_start = get_us_time();//us |
| do { |
| loop = 1; |
| m_len = test_size/4; |
| while (m_len--) { |
| ddr_pld_cache(p_dest) ; |
| *p_dest++ = 0x12345678; |
| *p_dest++ = 0x12345678; |
| *p_dest++ = 0x12345678; |
| *p_dest++ = 0x12345678; |
| } |
| }while(--counter); |
| time_end = get_us_time();//us |
| printf("\nwrite %d bytes use %dus\n \n",( unsigned int )test_size,( unsigned int )(time_end-time_start)); |
| |
| printf("\nddr write bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); |
| |
| unsigned int *p_src; |
| p_src= (void *)(int_convter_p(src_addr)); |
| m_len = test_size/4; //assume it's multiple of 4 |
| unsigned int temp0=0; |
| //unsigned int temp1=0; |
| //unsigned int temp2=0; |
| //unsigned int temp3=0; |
| counter=(unsigned int)test_loops; |
| size_count=counter*test_size; |
| |
| // #define OPEN_CHANNEL_A_PHY_CLK() (writel((0), 0xc8836c00)) |
| //writel((1000000<<0), DMC_MON_CTRL1); |
| //writel((0<<31)|(1<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2); |
| //writel((1<<31)|(0<<30)|(0<<20)|(1<<16)|(1<<0), DMC_MON_CTRL2); |
| time_start = get_us_time();//us |
| do { |
| loop = 1; |
| m_len = test_size/4; |
| while (m_len--) { |
| // ddr_pld_cache(p_src++) ; |
| #ifdef DDR_PREFETCH_CACHE |
| __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]"::"r" (p_src)); |
| #endif |
| p_src++; |
| temp0 =( *p_src); |
| m_len--; |
| m_len--; |
| m_len--; |
| m_len--; |
| m_len--; |
| m_len--; |
| m_len--; |
| } |
| }while(--counter); |
| *p_dest++ = temp0; |
| *p_dest++ = *p_src; |
| *p_dest++ = *p_src; |
| *p_dest++ = *p_src; |
| time_end = get_us_time();//us |
| |
| |
| |
| printf("\nread %d Kbytes use %dus\n \n",(unsigned int)(size_count/1000),( unsigned int )(time_end-time_start)); |
| printf("\nddr read bandwidth==%d MBYTE/S \n \n",(unsigned int)(size_count/(time_end-time_start))); |
| |
| return 0; |
| |
| //usage: |
| // cmd_usage(cmdtp); |
| return 1; |
| } |
| |
| U_BOOT_CMD( |
| ddr_test_copy, 7, 1, do_ddr_test_copy, |
| "ddr_test_copy function", |
| "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n" |
| ); |
| |
| ///* |
| #define DDR_PATTERN_LOOP_1 32 |
| #define DDR_PATTERN_LOOP_2 64 |
| #define DDR_PATTERN_LOOP_3 96 |
| /* |
| __asm |
| { |
| .Global memcpy_pld |
| .type memcpy_pld ,%function |
| .align 8 |
| memcpy_pld: |
| mov x4,x0 |
| subs x2,x2,#8 |
| b.mi 2f |
| 1: ldr x3,[x1],#8 |
| subs x2,x2,#8 |
| str x3,[x4],#8 |
| prfm PLDL1KEEP,[x1,#376] |
| b.pl 1b |
| |
| 2: adds x2,x2,#4 |
| b.mi 3f |
| ldr w3,[x1],#4 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 3: adds x2,x2,#2 |
| b.mi 4f |
| ldr w3,[x1],#2 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 4: adds x2,x2,#1 |
| b.mi 5f |
| ldr w3,[x1],#2 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 5: ret |
| } |
| */ |
| //static void ddr_memcpy_pld(void *addr_dest, void *addr_src, unsigned int m_length) |
| //{ |
| /* |
| asm |
| { |
| //.Global memcpy_pld |
| .type memcpy_pld ,%function |
| .align 8 |
| memcpy_pld: |
| mov x4,x0 |
| subs x2,x2,#8 |
| b.mi 2f |
| 1: ldr x3,[x1],#8 |
| subs x2,x2,#8 |
| str x3,[x4],#8 |
| prfm PLDL1KEEP,[x1,#376] |
| b.pl 1b |
| |
| 2: adds x2,x2,#4 |
| b.mi 3f |
| ldr w3,[x1],#4 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 3: adds x2,x2,#2 |
| b.mi 4f |
| ldr w3,[x1],#2 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 4: adds x2,x2,#1 |
| b.mi 5f |
| ldr w3,[x1],#2 |
| sub x2,x2,#4 |
| str w3,[x4],#4 |
| |
| 5: ret |
| } |
| memcpy_pld(addr_dest,addr_src,m_length); |
| */ |
| //} |
| |
| |
| |
| #if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY) |
| |
| ///* |
| |
| int ddr_test_gx_cross_talk_pattern(int ddr_test_size) |
| { |
| unsigned int start_addr = 0x10000000; |
| error_outof_count_flag=1; |
| error_count=0; |
| |
| unsigned int des[8] ; |
| unsigned int pattern_1[4][8] ; |
| unsigned int pattern_2[4][8] ; |
| unsigned int pattern_3[4][8] ; |
| unsigned int pattern_4[4][8] ; |
| unsigned int pattern_5[4][8] ; |
| unsigned int pattern_6[4][8] ; |
| |
| des[0] = 0xaec83f49; |
| des[1] = 0xd243a62c; |
| des[2] = 0xf8774a0b; |
| des[3] = 0x63d214e5; |
| des[4] = 0x3f4166d5; |
| des[5] = 0x239672c0; |
| des[6] = 0x47ba7533; |
| des[7] = 0xcae4cd7f; |
| pattern_1[0][0] = 0xff00ff00; |
| pattern_1[0][1] = 0xff00ff00; |
| pattern_1[0][2] = 0xff00ff00; |
| pattern_1[0][3] = 0xff00ff00; |
| pattern_1[0][4] = 0xff00ff00; |
| pattern_1[0][5] = 0xff00ff00; |
| pattern_1[0][6] = 0xff00ff00; |
| pattern_1[0][7] = 0xff00ff00; |
| |
| pattern_1[1][0] = 0x00ffff00; |
| pattern_1[1][1] = 0x00ffff00; |
| pattern_1[1][2] = 0x00ffff00; |
| pattern_1[1][3] = 0x00ffff00; |
| pattern_1[1][4] = 0x00ffff00; |
| pattern_1[1][5] = 0x00ffff00; |
| pattern_1[1][6] = 0x00ffff00; |
| pattern_1[1][7] = 0x00ffff00; |
| |
| pattern_1[2][0] = 0xffff0000; |
| pattern_1[2][1] = 0xffff0000; |
| pattern_1[2][2] = 0xffff0000; |
| pattern_1[2][3] = 0xffff0000; |
| pattern_1[2][4] = 0xffff0000; |
| pattern_1[2][5] = 0xffff0000; |
| pattern_1[2][6] = 0xffff0000; |
| pattern_1[2][7] = 0xffff0000; |
| pattern_1[3][0] = 0xff00ff00; |
| pattern_1[3][1] = 0xff00ff00; |
| pattern_1[3][2] = 0xff00ff00; |
| pattern_1[3][3] = 0xff00ff00; |
| pattern_1[3][4] = 0xff00ff00; |
| pattern_1[3][5] = 0xff00ff00; |
| pattern_1[3][6] = 0xff00ff00; |
| pattern_1[3][7] = 0xff00ff00; |
| |
| pattern_2[0][0] = 0x0001fe00; |
| pattern_2[0][1] = 0x0000ff00; |
| pattern_2[0][2] = 0x0000ff00; |
| pattern_2[0][3] = 0x0000ff00; |
| pattern_2[0][4] = 0x0002fd00; |
| pattern_2[0][5] = 0x0000ff00; |
| pattern_2[0][6] = 0x0000ff00; |
| pattern_2[0][7] = 0x0000ff00; |
| |
| pattern_2[1][0] = 0x0004fb00; |
| pattern_2[1][1] = 0x0000ff00; |
| pattern_2[1][2] = 0x0000ff00; |
| pattern_2[1][3] = 0x0000ff00; |
| pattern_2[1][4] = 0x0008f700; |
| pattern_2[1][5] = 0x0000ff00; |
| pattern_2[1][6] = 0x0000ff00; |
| pattern_2[1][7] = 0x0000ff00; |
| |
| pattern_2[2][0] = 0x0010ef00; |
| pattern_2[2][1] = 0x0000ff00; |
| pattern_2[2][2] = 0x0000ff00; |
| pattern_2[2][3] = 0x0000ff00; |
| pattern_2[2][4] = 0x0020df00; |
| pattern_2[2][5] = 0x0000ff00; |
| pattern_2[2][6] = 0x0000ff00; |
| pattern_2[2][7] = 0x0000ff00; |
| |
| pattern_2[3][0] = 0x0040bf00; |
| pattern_2[3][1] = 0x0000ff00; |
| pattern_2[3][2] = 0x0000ff00; |
| pattern_2[3][3] = 0x0000ff00; |
| pattern_2[3][4] = 0x00807f00; |
| pattern_2[3][5] = 0x0000ff00; |
| pattern_2[3][6] = 0x0000ff00; |
| pattern_2[3][7] = 0x0000ff00; |
| |
| pattern_3[0][0] = 0x00010000; |
| pattern_3[0][1] = 0x00000000; |
| pattern_3[0][2] = 0x00000000; |
| pattern_3[0][3] = 0x00000000; |
| pattern_3[0][4] = 0x00020000; |
| pattern_3[0][5] = 0x00000000; |
| pattern_3[0][6] = 0x00000000; |
| pattern_3[0][7] = 0x00000000; |
| |
| pattern_3[1][0] = 0x00040000; |
| pattern_3[1][1] = 0x00000000; |
| pattern_3[1][2] = 0x00000000; |
| pattern_3[1][3] = 0x00000000; |
| pattern_3[1][4] = 0x00080000; |
| pattern_3[1][5] = 0x00000000; |
| pattern_3[1][6] = 0x00000000; |
| pattern_3[1][7] = 0x00000000; |
| |
| pattern_3[2][0] = 0x00100000; |
| pattern_3[2][1] = 0x00000000; |
| pattern_3[2][2] = 0x00000000; |
| pattern_3[2][3] = 0x00000000; |
| pattern_3[2][4] = 0x00200000; |
| pattern_3[2][5] = 0x00000000; |
| pattern_3[2][6] = 0x00000000; |
| pattern_3[2][7] = 0x00000000; |
| |
| pattern_3[3][0] = 0x00400000; |
| pattern_3[3][1] = 0x00000000; |
| pattern_3[3][2] = 0x00000000; |
| pattern_3[3][3] = 0x00000000; |
| pattern_3[3][4] = 0x00800000; |
| pattern_3[3][5] = 0x00000000; |
| pattern_3[3][6] = 0x00000000; |
| pattern_3[3][7] = 0x00000000; |
| |
| ///* |
| pattern_4[0][0] = 0x51c8c049 ; |
| pattern_4[0][1] = 0x2d43592c ; |
| pattern_4[0][2] = 0x0777b50b ; |
| pattern_4[0][3] = 0x9cd2ebe5 ; |
| pattern_4[0][4] = 0xc04199d5 ; |
| pattern_4[0][5] = 0xdc968dc0 ; |
| pattern_4[0][6] = 0xb8ba8a33 ; |
| pattern_4[0][7] = 0x35e4327f ; |
| |
| pattern_4[1][0] = 0xae37c049 ; |
| pattern_4[1][1] = 0xd2bc592c ; |
| pattern_4[1][2] = 0xf888b50b ; |
| pattern_4[1][3] = 0x632debe5 ; |
| pattern_4[1][4] = 0x3fbe99d5 ; |
| pattern_4[1][5] = 0x23698dc0 ; |
| pattern_4[1][6] = 0x47458a33 ; |
| pattern_4[1][7] = 0xca1b327f ; |
| |
| pattern_4[2][0] = 0x51373f49 ; |
| pattern_4[2][1] = 0x2dbca62c ; |
| pattern_4[2][2] = 0x07884a0b ; |
| pattern_4[2][3] = 0x9c2d14e5 ; |
| pattern_4[2][4] = 0xc0be66d5 ; |
| pattern_4[2][5] = 0xdc6972c0 ; |
| pattern_4[2][6] = 0xb8457533 ; |
| pattern_4[2][7] = 0x351bcd7f ; |
| |
| |
| pattern_4[3][0] = 0x51c8c049 ; |
| pattern_4[3][1] = 0x2d43592c ; |
| pattern_4[3][2] = 0x0777b50b ; |
| pattern_4[3][3] = 0x9cd2ebe5 ; |
| pattern_4[3][4] = 0xc04199d5 ; |
| pattern_4[3][5] = 0xdc968dc0 ; |
| pattern_4[3][6] = 0xb8ba8a33 ; |
| pattern_4[3][7] = 0x35e4327f ; |
| |
| pattern_5[0][0] = 0xaec9c149 ; |
| pattern_5[0][1] = 0xd243592c ; |
| pattern_5[0][2] = 0xf877b50b ; |
| pattern_5[0][3] = 0x63d2ebe5 ; |
| pattern_5[0][4] = 0x3f439bd5 ; |
| pattern_5[0][5] = 0x23968dc0 ; |
| pattern_5[0][6] = 0x47ba8a33 ; |
| pattern_5[0][7] = 0xcae4327f ; |
| pattern_5[1][0] = 0xaeccc449 ; |
| pattern_5[1][1] = 0xd243592c ; |
| pattern_5[1][2] = 0xf877b50b ; |
| pattern_5[1][3] = 0x63d2ebe5 ; |
| pattern_5[1][4] = 0x3f4991d5 ; |
| pattern_5[1][5] = 0x23968dc0 ; |
| pattern_5[1][6] = 0x47ba8a33 ; |
| pattern_5[1][7] = 0xcae4327f ; |
| pattern_5[2][0] = 0xaed8d049 ; |
| pattern_5[2][1] = 0xd243592c ; |
| pattern_5[2][2] = 0xf877b50b ; |
| pattern_5[2][3] = 0x63d2ebe5 ; |
| pattern_5[2][4] = 0x3f61b9d5 ; |
| pattern_5[2][5] = 0x23968dc0 ; |
| pattern_5[2][6] = 0x47ba8a33 ; |
| pattern_5[2][7] = 0xcae4327f ; |
| pattern_5[3][0] = 0xae888049 ; |
| pattern_5[3][1] = 0xd243592c ; |
| pattern_5[3][2] = 0xf877b50b ; |
| pattern_5[3][3] = 0x63d2ebe5 ; |
| pattern_5[3][4] = 0x3fc119d5 ; |
| pattern_5[3][5] = 0x23968dc0 ; |
| pattern_5[3][6] = 0x47ba8a33 ; |
| pattern_5[3][7] = 0xcae4327f ; |
| |
| pattern_6[0][0] = 0xaec93f49 ; |
| pattern_6[0][1] = 0xd243a62c ; |
| pattern_6[0][2] = 0xf8774a0b ; |
| pattern_6[0][3] = 0x63d214e5 ; |
| pattern_6[0][4] = 0x3f4366d5 ; |
| pattern_6[0][5] = 0x239672c0 ; |
| pattern_6[0][6] = 0x47ba7533 ; |
| pattern_6[0][7] = 0xcae4cd7f ; |
| pattern_6[1][0] = 0xaecc3f49 ; |
| pattern_6[1][1] = 0xd243a62c ; |
| pattern_6[1][2] = 0xf8774a0b ; |
| pattern_6[1][3] = 0x63d214e5 ; |
| pattern_6[1][4] = 0x3f4966d5 ; |
| pattern_6[1][5] = 0x239672c0 ; |
| pattern_6[1][6] = 0x47ba7533 ; |
| pattern_6[1][7] = 0xcae4cd7f ; |
| pattern_6[2][0] = 0xaed83f49 ; |
| pattern_6[2][1] = 0xd243a62c ; |
| pattern_6[2][2] = 0xf8774a0b ; |
| pattern_6[2][3] = 0x63d214e5 ; |
| pattern_6[2][4] = 0x3f6166d5 ; |
| pattern_6[2][5] = 0x239672c0 ; |
| pattern_6[2][6] = 0x47ba7533 ; |
| pattern_6[2][7] = 0xcae4cd7f ; |
| pattern_6[3][0] = 0xae883f49 ; |
| pattern_6[3][1] = 0xd243a62c ; |
| pattern_6[3][2] = 0xf8774a0b ; |
| pattern_6[3][3] = 0x63d214e5 ; |
| pattern_6[3][4] = 0x3fc166d5 ; |
| pattern_6[3][5] = 0x239672c0 ; |
| pattern_6[3][6] = 0x47ba7533 ; |
| pattern_6[3][7] = 0xcae4cd7f ; |
| //*/ |
| //*/ |
| start_addr=0x10000000; |
| unsigned int test_size = 0x20; |
| unsigned int test_addr; |
| unsigned int temp_i=0; |
| unsigned int temp_k=0; |
| unsigned int pattern_o[8]; |
| unsigned int pattern_d[8]; |
| { |
| // if(lflag) |
| // loop = 888; |
| |
| //if(old_pattern_flag==1) |
| { |
| |
| printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size); |
| |
| /* |
| for ((temp_k=0);(temp_k<4);(temp_k++)) { |
| { |
| |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| flush_dcache_range(start_addr,start_addr + test_size); |
| |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| //printf("\n0x%08x",pattern_5[temp_k][temp_i]); |
| if (pattern_o[temp_i] != pattern_5[temp_k][temp_i]) |
| {error_count++; |
| printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]); |
| } |
| } |
| } |
| } |
| */ |
| //if(pattern_flag1==1) |
| { |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]); |
| // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_4[temp_k][temp_i]); |
| if (pattern_o[temp_i] != pattern_4[temp_k][temp_i]) |
| {error_count++; |
| printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]); |
| } |
| |
| } |
| } |
| } |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]); |
| // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_4[temp_k][temp_i]); |
| pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i])); |
| if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i]) |
| {error_count++; |
| printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_4[temp_k][temp_i]),pattern_d[temp_i]); |
| } |
| |
| } |
| } |
| } |
| } |
| //if(pattern_flag2==1) |
| { |
| for ((temp_k=0);(temp_k<4);(temp_k++)) { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| //printf("\n0x%08x",pattern_5[temp_k][temp_i]); |
| if (pattern_o[temp_i] != pattern_5[temp_k][temp_i]) |
| {error_count++; |
| printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]); |
| } |
| } |
| } |
| } |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| //printf("\n0x%08x",pattern_5[temp_k][temp_i]); |
| pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i])); |
| if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i]) |
| {error_count++; |
| printf("p5 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_5[temp_k][temp_i]),pattern_d[temp_i]); |
| } |
| } |
| } |
| } |
| |
| } |
| |
| // if(pattern_flag3==1) |
| { |
| for ((temp_k=0);(temp_k<4);(temp_k++)) { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_6[temp_k][temp_i]); |
| if (pattern_o[temp_i] != pattern_6[temp_k][temp_i]) |
| {error_count++; |
| printf("p6Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_6[temp_k][temp_i],pattern_3[temp_k][temp_i]); |
| } |
| } |
| } |
| } |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,3,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_3[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_6[temp_k][temp_i]); |
| pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i])); |
| if ((des_xor_pattern((des[temp_i]),(pattern_o[temp_i]))) != pattern_d[temp_i]) |
| {error_count++; |
| printf("p6 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_6[temp_k][temp_i]),pattern_d[temp_i]); |
| } |
| } |
| } |
| } |
| } |
| |
| |
| |
| } |
| |
| printf("\Error count==0x%08x", error_count); |
| printf("\n \n"); |
| } |
| |
| |
| |
| |
| |
| |
| |
| if (error_count) |
| return 1; |
| else |
| return 0; |
| } |
| |
| int ddr_test_gx_training_pattern(int ddr_test_size) |
| { |
| unsigned int start_addr = 0x10000000; |
| error_outof_count_flag=1; |
| error_count=0; |
| |
| unsigned int des[8] ; |
| unsigned int pattern_1[4][8] ; |
| // unsigned int pattern_2[4][8] ; |
| // unsigned int pattern_3[4][8] ; |
| // unsigned int pattern_4[4][8] ; |
| // unsigned int pattern_5[4][8] ; |
| //unsigned int pattern_6[4][8] ; |
| |
| des[0] = 0xaec83f49; |
| des[1] = 0xd243a62c; |
| des[2] = 0xf8774a0b; |
| des[3] = 0x63d214e5; |
| des[4] = 0x3f4166d5; |
| des[5] = 0x239672c0; |
| des[6] = 0x47ba7533; |
| des[7] = 0xcae4cd7f; |
| /* |
| pattern_1[0][0] = 0x55005500; |
| pattern_1[0][1] = 0xaa00aa00; |
| pattern_1[0][2] = 0x55005500; |
| pattern_1[0][3] = 0xaa00aa00; |
| pattern_1[0][4] = 0x55005500; |
| pattern_1[0][5] = 0xaa00aa00; |
| pattern_1[0][6] = 0x55005500; |
| pattern_1[0][7] = 0xaa00aa00; |
| |
| pattern_1[1][0] = 0x55005500; |
| pattern_1[1][1] = 0xaa00aa00; |
| pattern_1[1][2] = 0x55005500; |
| pattern_1[1][3] = 0xaa00aa00; |
| pattern_1[1][4] = 0x55005500; |
| pattern_1[1][5] = 0xaa00aa00; |
| pattern_1[1][6] = 0x55005500; |
| pattern_1[1][7] = 0xaa00aa00; |
| |
| pattern_1[2][0] = 0x55005500; |
| pattern_1[2][1] = 0xaa00aa00; |
| pattern_1[2][2] = 0x55005500; |
| pattern_1[2][3] = 0xaa00aa00; |
| pattern_1[2][4] = 0x55005500; |
| pattern_1[2][5] = 0xaa00aa00; |
| pattern_1[2][6] = 0x55005500; |
| pattern_1[2][7] = 0xaa00aa00; |
| |
| pattern_1[3][0] = 0x55005500; |
| pattern_1[3][1] = 0xaa00aa00; |
| pattern_1[3][2] = 0x55005500; |
| pattern_1[3][3] = 0xaa00aa00; |
| pattern_1[3][4] = 0x55005500; |
| pattern_1[3][5] = 0xaa00aa00; |
| pattern_1[3][6] = 0x55005500; |
| pattern_1[3][7] = 0xaa00aa00; |
| */ |
| // /* |
| pattern_1[0][0] = 0x55aa5500; |
| pattern_1[0][1] = 0x55aa5500; |
| pattern_1[0][2] = 0x55aa5500; |
| pattern_1[0][3] = 0x55aa5500; |
| pattern_1[0][4] = 0xaa00ff00; |
| pattern_1[0][5] = 0xaa00ff00; |
| pattern_1[0][6] = 0xaa00ff00; |
| pattern_1[0][7] = 0xaa00ff00; |
| |
| pattern_1[1][0] = 0x55005500; |
| pattern_1[1][1] = 0xaa00aa00; |
| pattern_1[1][2] = 0x55005500; |
| pattern_1[1][3] = 0xaa00aa00; |
| pattern_1[1][4] = 0x55005500; |
| pattern_1[1][5] = 0xaa00aa00; |
| pattern_1[1][6] = 0x55005500; |
| pattern_1[1][7] = 0xaa00aa00; |
| |
| pattern_1[2][0] = 0x0001fe00; |
| pattern_1[2][1] = 0x0000ff00; |
| pattern_1[2][2] = 0x0000ff00; |
| pattern_1[2][3] = 0x0000ff00; |
| pattern_1[2][4] = 0x0002fd00; |
| pattern_1[2][5] = 0x0000ff00; |
| pattern_1[2][6] = 0x0000ff00; |
| pattern_1[2][7] = 0x0000ff00; |
| |
| pattern_1[3][0] = 0x0004fb00; |
| pattern_1[3][1] = 0x0000ff00; |
| pattern_1[3][2] = 0x0000ff00; |
| pattern_1[3][3] = 0x0000ff00; |
| pattern_1[3][4] = 0x0008f700; |
| pattern_1[3][5] = 0x0000ff00; |
| pattern_1[3][6] = 0x0000ff00; |
| pattern_1[3][7] = 0x0000ff00; |
| //*/ |
| /* |
| pattern_2[0][0] = 0x0001fe00; |
| pattern_2[0][1] = 0x0000ff00; |
| pattern_2[0][2] = 0x0000ff00; |
| pattern_2[0][3] = 0x0000ff00; |
| pattern_2[0][4] = 0x0002fd00; |
| pattern_2[0][5] = 0x0000ff00; |
| pattern_2[0][6] = 0x0000ff00; |
| pattern_2[0][7] = 0x0000ff00; |
| |
| pattern_2[1][0] = 0x0004fb00; |
| pattern_2[1][1] = 0x0000ff00; |
| pattern_2[1][2] = 0x0000ff00; |
| pattern_2[1][3] = 0x0000ff00; |
| pattern_2[1][4] = 0x0008f700; |
| pattern_2[1][5] = 0x0000ff00; |
| pattern_2[1][6] = 0x0000ff00; |
| pattern_2[1][7] = 0x0000ff00; |
| |
| pattern_2[2][0] = 0x0010ef00; |
| pattern_2[2][1] = 0x0000ff00; |
| pattern_2[2][2] = 0x0000ff00; |
| pattern_2[2][3] = 0x0000ff00; |
| pattern_2[2][4] = 0x0020df00; |
| pattern_2[2][5] = 0x0000ff00; |
| pattern_2[2][6] = 0x0000ff00; |
| pattern_2[2][7] = 0x0000ff00; |
| |
| pattern_2[3][0] = 0x0040bf00; |
| pattern_2[3][1] = 0x0000ff00; |
| pattern_2[3][2] = 0x0000ff00; |
| pattern_2[3][3] = 0x0000ff00; |
| pattern_2[3][4] = 0x00807f00; |
| pattern_2[3][5] = 0x0000ff00; |
| pattern_2[3][6] = 0x0000ff00; |
| pattern_2[3][7] = 0x0000ff00; |
| |
| pattern_3[0][0] = 0x00010000; |
| pattern_3[0][1] = 0x00000000; |
| pattern_3[0][2] = 0x00000000; |
| pattern_3[0][3] = 0x00000000; |
| pattern_3[0][4] = 0x00020000; |
| pattern_3[0][5] = 0x00000000; |
| pattern_3[0][6] = 0x00000000; |
| pattern_3[0][7] = 0x00000000; |
| |
| pattern_3[1][0] = 0x00040000; |
| pattern_3[1][1] = 0x00000000; |
| pattern_3[1][2] = 0x00000000; |
| pattern_3[1][3] = 0x00000000; |
| pattern_3[1][4] = 0x00080000; |
| pattern_3[1][5] = 0x00000000; |
| pattern_3[1][6] = 0x00000000; |
| pattern_3[1][7] = 0x00000000; |
| |
| pattern_3[2][0] = 0x00100000; |
| pattern_3[2][1] = 0x00000000; |
| pattern_3[2][2] = 0x00000000; |
| pattern_3[2][3] = 0x00000000; |
| pattern_3[2][4] = 0x00200000; |
| pattern_3[2][5] = 0x00000000; |
| pattern_3[2][6] = 0x00000000; |
| pattern_3[2][7] = 0x00000000; |
| |
| pattern_3[3][0] = 0x00400000; |
| pattern_3[3][1] = 0x00000000; |
| pattern_3[3][2] = 0x00000000; |
| pattern_3[3][3] = 0x00000000; |
| pattern_3[3][4] = 0x00800000; |
| pattern_3[3][5] = 0x00000000; |
| pattern_3[3][6] = 0x00000000; |
| pattern_3[3][7] = 0x00000000; |
| |
| |
| pattern_4[0][0] = 0x51c8c049 ; |
| pattern_4[0][1] = 0x2d43592c ; |
| pattern_4[0][2] = 0x0777b50b ; |
| pattern_4[0][3] = 0x9cd2ebe5 ; |
| pattern_4[0][4] = 0xc04199d5 ; |
| pattern_4[0][5] = 0xdc968dc0 ; |
| pattern_4[0][6] = 0xb8ba8a33 ; |
| pattern_4[0][7] = 0x35e4327f ; |
| |
| pattern_4[1][0] = 0xae37c049 ; |
| pattern_4[1][1] = 0xd2bc592c ; |
| pattern_4[1][2] = 0xf888b50b ; |
| pattern_4[1][3] = 0x632debe5 ; |
| pattern_4[1][4] = 0x3fbe99d5 ; |
| pattern_4[1][5] = 0x23698dc0 ; |
| pattern_4[1][6] = 0x47458a33 ; |
| pattern_4[1][7] = 0xca1b327f ; |
| |
| pattern_4[2][0] = 0x51373f49 ; |
| pattern_4[2][1] = 0x2dbca62c ; |
| pattern_4[2][2] = 0x07884a0b ; |
| pattern_4[2][3] = 0x9c2d14e5 ; |
| pattern_4[2][4] = 0xc0be66d5 ; |
| pattern_4[2][5] = 0xdc6972c0 ; |
| pattern_4[2][6] = 0xb8457533 ; |
| pattern_4[2][7] = 0x351bcd7f ; |
| |
| |
| pattern_4[3][0] = 0x51c8c049 ; |
| pattern_4[3][1] = 0x2d43592c ; |
| pattern_4[3][2] = 0x0777b50b ; |
| pattern_4[3][3] = 0x9cd2ebe5 ; |
| pattern_4[3][4] = 0xc04199d5 ; |
| pattern_4[3][5] = 0xdc968dc0 ; |
| pattern_4[3][6] = 0xb8ba8a33 ; |
| pattern_4[3][7] = 0x35e4327f ; |
| |
| pattern_5[0][0] = 0xaec9c149 ; |
| pattern_5[0][1] = 0xd243592c ; |
| pattern_5[0][2] = 0xf877b50b ; |
| pattern_5[0][3] = 0x63d2ebe5 ; |
| pattern_5[0][4] = 0x3f439bd5 ; |
| pattern_5[0][5] = 0x23968dc0 ; |
| pattern_5[0][6] = 0x47ba8a33 ; |
| pattern_5[0][7] = 0xcae4327f ; |
| pattern_5[1][0] = 0xaeccc449 ; |
| pattern_5[1][1] = 0xd243592c ; |
| pattern_5[1][2] = 0xf877b50b ; |
| pattern_5[1][3] = 0x63d2ebe5 ; |
| pattern_5[1][4] = 0x3f4991d5 ; |
| pattern_5[1][5] = 0x23968dc0 ; |
| pattern_5[1][6] = 0x47ba8a33 ; |
| pattern_5[1][7] = 0xcae4327f ; |
| pattern_5[2][0] = 0xaed8d049 ; |
| pattern_5[2][1] = 0xd243592c ; |
| pattern_5[2][2] = 0xf877b50b ; |
| pattern_5[2][3] = 0x63d2ebe5 ; |
| pattern_5[2][4] = 0x3f61b9d5 ; |
| pattern_5[2][5] = 0x23968dc0 ; |
| pattern_5[2][6] = 0x47ba8a33 ; |
| pattern_5[2][7] = 0xcae4327f ; |
| pattern_5[3][0] = 0xae888049 ; |
| pattern_5[3][1] = 0xd243592c ; |
| pattern_5[3][2] = 0xf877b50b ; |
| pattern_5[3][3] = 0x63d2ebe5 ; |
| pattern_5[3][4] = 0x3fc119d5 ; |
| pattern_5[3][5] = 0x23968dc0 ; |
| pattern_5[3][6] = 0x47ba8a33 ; |
| pattern_5[3][7] = 0xcae4327f ; |
| |
| pattern_6[0][0] = 0xaec93f49 ; |
| pattern_6[0][1] = 0xd243a62c ; |
| pattern_6[0][2] = 0xf8774a0b ; |
| pattern_6[0][3] = 0x63d214e5 ; |
| pattern_6[0][4] = 0x3f4366d5 ; |
| pattern_6[0][5] = 0x239672c0 ; |
| pattern_6[0][6] = 0x47ba7533 ; |
| pattern_6[0][7] = 0xcae4cd7f ; |
| pattern_6[1][0] = 0xaecc3f49 ; |
| pattern_6[1][1] = 0xd243a62c ; |
| pattern_6[1][2] = 0xf8774a0b ; |
| pattern_6[1][3] = 0x63d214e5 ; |
| pattern_6[1][4] = 0x3f4966d5 ; |
| pattern_6[1][5] = 0x239672c0 ; |
| pattern_6[1][6] = 0x47ba7533 ; |
| pattern_6[1][7] = 0xcae4cd7f ; |
| pattern_6[2][0] = 0xaed83f49 ; |
| pattern_6[2][1] = 0xd243a62c ; |
| pattern_6[2][2] = 0xf8774a0b ; |
| pattern_6[2][3] = 0x63d214e5 ; |
| pattern_6[2][4] = 0x3f6166d5 ; |
| pattern_6[2][5] = 0x239672c0 ; |
| pattern_6[2][6] = 0x47ba7533 ; |
| pattern_6[2][7] = 0xcae4cd7f ; |
| pattern_6[3][0] = 0xae883f49 ; |
| pattern_6[3][1] = 0xd243a62c ; |
| pattern_6[3][2] = 0xf8774a0b ; |
| pattern_6[3][3] = 0x63d214e5 ; |
| pattern_6[3][4] = 0x3fc166d5 ; |
| pattern_6[3][5] = 0x239672c0 ; |
| pattern_6[3][6] = 0x47ba7533 ; |
| pattern_6[3][7] = 0xcae4cd7f ; |
| */ |
| //*/ |
| //*/ |
| start_addr=0x10000000; |
| unsigned int test_size = 0x20; |
| unsigned int test_addr; |
| unsigned int temp_i=0; |
| unsigned int temp_k=0; |
| unsigned int pattern_o[8]; |
| unsigned int pattern_d[8]; |
| { |
| // if(lflag) |
| // loop = 888; |
| |
| //if(old_pattern_flag==1) |
| { |
| |
| printf("\nStart writing at 0x%08x - 0x%08x...\n", start_addr, start_addr + test_size); |
| |
| /* |
| for ((temp_k=0);(temp_k<4);(temp_k++)) { |
| { |
| |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| flush_dcache_range(start_addr,start_addr + test_size); |
| |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_2[temp_k][temp_i]); |
| //printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| //printf("\n0x%08x",pattern_5[temp_k][temp_i]); |
| if (pattern_o[temp_i] != pattern_5[temp_k][temp_i]) |
| {error_count++; |
| printf("p5Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_5[temp_k][temp_i],pattern_2[temp_k][temp_i]); |
| } |
| } |
| } |
| } |
| */ |
| //if(pattern_flag1==1) |
| { |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]); |
| // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_4[temp_k][temp_i]); |
| if ((pattern_o[temp_i]) != (des_pattern(temp_i,1,temp_k,temp_i))) |
| {error_count++; |
| // printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), pattern_4[temp_k][temp_i],pattern_1[temp_k][temp_i]); |
| printf("p4Error data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n",pattern_o[temp_i], p_convter_int(test_addr), des_pattern(temp_i,1,temp_k,temp_i),pattern_1[temp_k][temp_i]); |
| } |
| |
| |
| } |
| } |
| } |
| |
| for ((temp_k=0);(temp_k<4);(temp_k++)) |
| { |
| { |
| ddr_udelay(10000); |
| for ((temp_i=0);(temp_i<8);(temp_i++)) |
| { |
| test_addr=start_addr+(temp_i<<2); |
| *(volatile uint32_t *)(int_convter_p(test_addr))=des_inv_pattern(temp_i,1,temp_k,temp_i);//des[temp_i]^pattern_2[temp_k][temp_i]; |
| // #define des_pattern(a,b,c,d) des[a]^pattern_##b[c][d] |
| //des[temp_i]^pattern_2[temp_k][temp_i] |
| } |
| // _clean_dcache_addr(0x10000000); |
| #ifdef DDR_PREFETCH_CACHE |
| flush_dcache_range(start_addr,start_addr + test_size); |
| #endif |
| for ((temp_i=0);(temp_i<8);(temp_i++)) { |
| test_addr=start_addr+(temp_i<<2); |
| pattern_o[temp_i]=*(volatile uint32_t *)(int_convter_p(test_addr)); |
| // printf("\n test_addr pattern_o pattern_d 0x%08x - 0x%08x - 0x%08x", test_addr,pattern_o[temp_i], pattern_1[temp_k][temp_i]); |
| // printf("\n0x%08x",(pattern_o[temp_i])^(des[temp_i])); |
| // printf("\n0x%08x",pattern_4[temp_k][temp_i]); |
| pattern_d[temp_i]=des_xor_pattern((des[temp_i]),(pattern_o[temp_i])); |
| if ((des_xor_pattern((des[temp_i]),des_inv_pattern(temp_i,1,temp_k,temp_i))) != pattern_d[temp_i]) |
| {error_count++; |
| printf("p4 invError data [0x%08x] at offset 0x%08x[0x%08x]-D0x%08x\n", |
| pattern_o[temp_i], p_convter_int(test_addr), ~(pattern_1[temp_k][temp_i]),pattern_d[temp_i]); |
| } |
| |
| } |
| } |
| } |
| |
| } |
| //if(pattern_flag2==1) |
| |
| |
| // if(pattern_flag3==1) |
| |
| |
| |
| |
| } |
| |
| printf("\Error count==0x%08x", error_count); |
| printf("\n \n"); |
| } |
| |
| |
| |
| |
| |
| |
| |
| if (error_count) |
| return 1; |
| else |
| return 0; |
| } |
| |
| |
| #endif |
| |
| static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length) |
| { |
| unsigned int *p; |
| // unsigned int i, j, n; |
| unsigned int i, n; |
| unsigned int m_len = m_length; |
| //#define ddr_pattern_loop 32 |
| p = ( unsigned int *)buff; |
| |
| while (m_len) |
| { |
| // for(j=0;j<32;j++) |
| { |
| if (m_len >= 128*4) |
| n = 32*4; |
| else |
| n = m_len>>2; |
| |
| for (i = 0; i < n; i++) |
| { |
| #ifdef DDR_PREFETCH_CACHE |
| ddr_pld_cache(p) ; |
| #endif |
| switch (i) |
| { |
| case 0: |
| case 1: |
| case 2: |
| case 3: |
| case 8: |
| case 9: |
| case 10: |
| case 11: |
| case 16: |
| case 17: |
| case 18: |
| case 19: |
| case 24: |
| case 25: |
| case 26: |
| case 27: |
| // case 30: |
| *(p+i) = TDATA32F; |
| break; |
| case 4: |
| case 5: |
| case 6: |
| case 7: |
| case 12: |
| case 13: |
| case 14: |
| case 15: |
| case 20: |
| case 21: |
| case 22: |
| case 23: |
| case 28: |
| case 29: |
| case 30: |
| case 31: |
| // case 22: |
| *(p+i) = 0; |
| break; |
| case DDR_PATTERN_LOOP_1+0: |
| case DDR_PATTERN_LOOP_1+1: |
| case DDR_PATTERN_LOOP_1+2: |
| case DDR_PATTERN_LOOP_1+3: |
| case DDR_PATTERN_LOOP_1+8: |
| case DDR_PATTERN_LOOP_1+9: |
| case DDR_PATTERN_LOOP_1+10: |
| case DDR_PATTERN_LOOP_1+11: |
| case DDR_PATTERN_LOOP_1+16: |
| case DDR_PATTERN_LOOP_1+17: |
| case DDR_PATTERN_LOOP_1+18: |
| case DDR_PATTERN_LOOP_1+19: |
| case DDR_PATTERN_LOOP_1+24: |
| case DDR_PATTERN_LOOP_1+25: |
| case DDR_PATTERN_LOOP_1+26: |
| case DDR_PATTERN_LOOP_1+27: |
| // case 30: |
| *(p+i) = TDATA32A; |
| break; |
| case DDR_PATTERN_LOOP_1+4: |
| case DDR_PATTERN_LOOP_1+5: |
| case DDR_PATTERN_LOOP_1+6: |
| case DDR_PATTERN_LOOP_1+7: |
| case DDR_PATTERN_LOOP_1+12: |
| case DDR_PATTERN_LOOP_1+13: |
| case DDR_PATTERN_LOOP_1+14: |
| case DDR_PATTERN_LOOP_1+15: |
| case DDR_PATTERN_LOOP_1+20: |
| case DDR_PATTERN_LOOP_1+21: |
| case DDR_PATTERN_LOOP_1+22: |
| case DDR_PATTERN_LOOP_1+23: |
| case DDR_PATTERN_LOOP_1+28: |
| case DDR_PATTERN_LOOP_1+29: |
| case DDR_PATTERN_LOOP_1+30: |
| case DDR_PATTERN_LOOP_1+31: |
| *(p+i) = TDATA325; |
| |
| |
| break; |
| case DDR_PATTERN_LOOP_2+0: |
| case DDR_PATTERN_LOOP_2+1: |
| case DDR_PATTERN_LOOP_2+2: |
| case DDR_PATTERN_LOOP_2+3: |
| *(p+i) =0xfe01fe01; |
| break; |
| case DDR_PATTERN_LOOP_2+4: |
| case DDR_PATTERN_LOOP_2+5: |
| case DDR_PATTERN_LOOP_2+6: |
| case DDR_PATTERN_LOOP_2+7: |
| *(p+i) =0xfd02fd02; |
| break; |
| case DDR_PATTERN_LOOP_2+8: |
| case DDR_PATTERN_LOOP_2+9: |
| case DDR_PATTERN_LOOP_2+10: |
| case DDR_PATTERN_LOOP_2+11: |
| *(p+i) =0xfb04fb04; |
| break; |
| case DDR_PATTERN_LOOP_2+12: |
| case DDR_PATTERN_LOOP_2+13: |
| case DDR_PATTERN_LOOP_2+14: |
| case DDR_PATTERN_LOOP_2+15: |
| *(p+i) =0xf708f708; |
| break; |
| case DDR_PATTERN_LOOP_2+16: |
| case DDR_PATTERN_LOOP_2+17: |
| case DDR_PATTERN_LOOP_2+18: |
| case DDR_PATTERN_LOOP_2+19: |
| *(p+i) =0xef10ef10; |
| break; |
| case DDR_PATTERN_LOOP_2+20: |
| case DDR_PATTERN_LOOP_2+21: |
| case DDR_PATTERN_LOOP_2+22: |
| case DDR_PATTERN_LOOP_2+23: |
| *(p+i) =0xdf20df20; |
| break; |
| case DDR_PATTERN_LOOP_2+24: |
| case DDR_PATTERN_LOOP_2+25: |
| case DDR_PATTERN_LOOP_2+26: |
| case DDR_PATTERN_LOOP_2+27: |
| *(p+i) =0xbf40bf40; |
| break; |
| case DDR_PATTERN_LOOP_2+28: |
| case DDR_PATTERN_LOOP_2+29: |
| case DDR_PATTERN_LOOP_2+30: |
| case DDR_PATTERN_LOOP_2+31: |
| *(p+i) =0x7f807f80; |
| break; |
| case DDR_PATTERN_LOOP_3+0: |
| case DDR_PATTERN_LOOP_3+1: |
| case DDR_PATTERN_LOOP_3+2<
|
