/*
 * arch/arm/dts/elaine-b1-panel.dtsi
 *
 * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 */

/ {
	lcd{
		compatible = "amlogic, lcd-sm1";
		mode = "tablet";
		status = "okay";
		key_valid = <0>;
		clocks = <&clkc CLKID_MIPI_DSI_HOST
			&clkc CLKID_MIPI_DSI_PHY
			&clkc CLKID_DSI_MEAS_COMP
			&clkc CLKID_VCLK2_ENCL
			&clkc CLKID_VCLK2_VENCL
			&clkc CLKID_GP0_PLL>;
		clock-names = "dsi_host_gate",
			"dsi_phy_gate",
			"dsi_meas",
			"encl_top_gate",
			"encl_int_gate",
			"gp0_pll";
		reg = <0x0 0xffd07000 0x0 0x400    /* dsi_host */
			0x0 0xff644000 0x0 0x200>; /* dsi_phy */
		interrupts = <0 3 1
			0 56 1>;
		interrupt-names = "vsync","vsync2";
		pinctrl_version = <2>; /* for uboot */

		/* power type:
		 *    (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
		 * power index:
		 *    (point gpios_index, or extern_index,0xff=invalid)
		 * power value:(0=output low, 1=output high, 2=input)
		 * power delay:(unit in ms)
		 */
		lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>;
		lcd_cpu_gpio_names = "GPIOZ_13";

		boe_fiti9364_7{
			model_name = "TV070WSM_FT9364";
			interface = "mipi";
			basic_setting = <600 1024 /*h_active, v_active*/
				700 1053 /*h_period, v_period*/
				8 /*lcd_bits*/
				95 163>; /*screen_widht, screen_height*/
			lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
				2 8 0>; /*vs_width,vs_bp,vs_pol*/
			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
				0 /*clk_ss_level*/
				1 /*clk_auto_generate*/
				44226000>; /*pixel_clk(unit in Hz)*/
			mipi_attr = <4 /*lane_num*/
				400 /*bit_rate_max(MHz)*/
				0 /*factor(*100, default 0 for auto)*/
				1 /*operation_mode_init(0=video, 1=command)*/
				0 /*operation_mode_display(0=video, 1=command)*/
				2 /*
				   *video_mode_type
				   *(0=sync_pulse,1=sync_event,2=burst)
				   */
				0 /*clk_always_hs(0=disable,1=enable)*/
				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
				/* dsi_init: data_type, num, data... */
			dsi_init_on = <
				0xff 10
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xf0 3 0 0 10 /* reset low, delay 10ms */
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xfc 2 0x04 3 /* check_reg, check_cnt */
				0xff 0xff>; /* ending flag */
			dsi_init_off = <
				0xff 5      /* delay 5ms */
				0xff 0xff>; /* ending flag */
				/* extern_init: 0xff for invalid */
			extern_init = <1>;
				/* power step: type,index,value,delay(ms) */
			power_on_step = <
					0 1 0 200
					2 0 0 0
					0xff 0 0 0>;
			power_off_step = <
					2 0 0 5   /* delay 5ms after mipi off */
					0 0 0 20  /* reset low */
					0 1 1 100 /* panel power off */
					0xff 0 0 0>;
			backlight_index = <0>;
		};

		inx_fiti9364_7{
			model_name = "P070ACB_FT9364";
			interface = "mipi";
			basic_setting = <600 1024 /*h_active, v_active*/
				770 1070 /*h_period, v_period*/
				8 /*lcd_bits*/
				3 5>; /*screen_widht, screen_height*/
			lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
				6 20 0>; /*vs_width,vs_bp,vs_pol*/
			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
				0 /*clk_ss_level*/
				1 /*clk_auto_generate*/
				49434000>; /*pixel_clk(unit in Hz)*/
			mipi_attr = <4 /*lane_num*/
				400 /*bit_rate_max(MHz)*/
				0 /*factor(*100, default 0 for auto)*/
				1 /*operation_mode_init(0=video, 1=command)*/
				0 /*operation_mode_display(0=video, 1=command)*/
				2 /*
				   *video_mode_type
				   *(0=sync_pulse,1=sync_event,2=burst)
				   */
				0 /*clk_always_hs(0=disable,1=enable)*/
				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
				/* dsi_init: data_type, num, data... */
			dsi_init_on = <
				0xff 10
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xf0 3 0 0 10 /* reset low, delay 10ms */
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xfc 2 0x04 3 /* check_reg, check_cnt */
				0xff 0xff>; /* ending flag */
			dsi_init_off = <
				0xff 5      /* delay 5ms */
				0xff 0xff>; /* ending flag */
				/* extern_init: 0xff for invalid */
			extern_init = <2>;
				/* power step: type,index,value,delay(ms) */
			power_on_step = <
					0 1 0 200 /* panel power on */
					2 0 0 0
					0xff 0 0 0>;
			power_off_step = <
					2 0 0 5   /* delay 5ms after mipi off */
					0 0 0 20  /* reset low */
					0 1 1 100 /* panel power off */
					0xff 0 0 0>;
			backlight_index = <0>;
		};

		kd_fiti9364_7{
			model_name = "KD070D82_FT9364";
			interface = "mipi";
			basic_setting = <600 1024 /*h_active, v_active*/
				770 1070 /*h_period, v_period*/
				8 /*lcd_bits*/
				3 5>; /*screen_widht, screen_height*/
			lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
				6 20 0>; /*vs_width,vs_bp,vs_pol*/
			clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
				0 /*clk_ss_level*/
				1 /*clk_auto_generate*/
				49434000>; /*pixel_clk(unit in Hz)*/
			mipi_attr = <4 /*lane_num*/
				400 /*bit_rate_max(MHz)*/
				0 /*factor(*100, default 0 for auto)*/
				1 /*operation_mode_init(0=video, 1=command)*/
				0 /*operation_mode_display(0=video, 1=command)*/
				2 /*
				   *video_mode_type
				   *(0=sync_pulse,1=sync_event,2=burst)
				   */
				0 /*clk_always_hs(0=disable,1=enable)*/
				0>; /*phy_switch(0=auto,1=standard,2=slow)*/
				/* dsi_init: data_type, num, data... */
			dsi_init_on = <
				0xff 10
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xf0 3 0 0 10 /* reset low, delay 10ms */
				0xf0 3 0 1 30 /* reset high, delay 30ms */
				0xfc 2 0x04 3 /* check_reg, check_cnt */
				0xff 0xff>; /* ending flag */
			dsi_init_off = <
				0xff 5      /* delay 5ms */
				0xff 0xff>; /* ending flag */
				/* extern_init: 0xff for invalid */
			extern_init = <3>;
				/* power step: type,index,value,delay(ms) */
			power_on_step = <
					0 1 0 200 /* panel power on */
					2 0 0 0
					0xff 0 0 0>;
			power_off_step = <
					2 0 0 5   /* delay 5ms after mipi off */
					0 0 0 20  /* reset low */
					0 1 1 100 /* panel power off */
					0xff 0 0 0>;
			backlight_index = <0>;
		};

	};

	lcd_extern{
		compatible = "amlogic, lcd_extern";
		dev_name = "lcd_extern";
		status = "okay";
		key_valid = <0>;

		extern_1{
			index = <1>;
			extern_name = "mipi_default"; // TV070WSM_FT9364
			status = "okay";
			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
			cmd_size = <0xff>;
			init_on = <
				0x23 2 0xE0 0x00
				0x23 2 0xE1 0x93
				0x23 2 0xE2 0x65
				0x23 2 0xE3 0xF8
				0x23 2 0xE0 0x01
				0x23 2 0x00 0x00
				0x23 2 0x01 0x90
				0x23 2 0x03 0x00
				0x23 2 0x04 0x90
				0x23 2 0x17 0x00
				0x23 2 0x18 0xB0
				0x23 2 0x19 0x01
				0x23 2 0x1A 0x00
				0x23 2 0x1B 0xB0
				0x23 2 0x1C 0x01
				0x23 2 0x1F 0x3E
				0x23 2 0x20 0x2F
				0x23 2 0x21 0x2F
				0x23 2 0x22 0x0E
				0x23 2 0x37 0x69
				0x23 2 0x38 0x05
				0x23 2 0x39 0x00
				0x23 2 0x3A 0x01
				0x23 2 0x3C 0x90
				0x23 2 0x3D 0xFF
				0x23 2 0x3E 0xFF
				0x23 2 0x3F 0xFF
				0x23 2 0x40 0x02
				0x23 2 0x41 0x80
				0x23 2 0x42 0x99
				0x23 2 0x43 0x06
				0x23 2 0x44 0x09
				0x23 2 0x45 0x3C
				0x23 2 0x4B 0x04
				0x23 2 0x55 0x0D
				0x23 2 0x56 0x01
				0x23 2 0x57 0x89
				0x23 2 0x58 0x0A
				0x23 2 0x59 0x0A
				0x23 2 0x5A 0x27
				0x23 2 0x5B 0x15
				0x23 2 0x5D 0x7C
				0x23 2 0x5E 0x67
				0x23 2 0x5F 0x58
				0x23 2 0x60 0x4C
				0x23 2 0x61 0x48
				0x23 2 0x62 0x38
				0x23 2 0x63 0x3C
				0x23 2 0x64 0x24
				0x23 2 0x65 0x3B
				0x23 2 0x66 0x38
				0x23 2 0x67 0x36
				0x23 2 0x68 0x53
				0x23 2 0x69 0x3F
				0x23 2 0x6A 0x44
				0x23 2 0x6B 0x35
				0x23 2 0x6C 0x2E
				0x23 2 0x6D 0x1F
				0x23 2 0x6E 0x0C
				0x23 2 0x6F 0x00
				0x23 2 0x70 0x7C
				0x23 2 0x71 0x67
				0x23 2 0x72 0x58
				0x23 2 0x73 0x4C
				0x23 2 0x74 0x48
				0x23 2 0x75 0x38
				0x23 2 0x76 0x3C
				0x23 2 0x77 0x24
				0x23 2 0x78 0x3B
				0x23 2 0x79 0x38
				0x23 2 0x7A 0x36
				0x23 2 0x7B 0x53
				0x23 2 0x7C 0x3F
				0x23 2 0x7D 0x44
				0x23 2 0x7E 0x35
				0x23 2 0x7F 0x2E
				0x23 2 0x80 0x1F
				0x23 2 0x81 0x0C
				0x23 2 0x82 0x00
				0x23 2 0xE0 0x02
				0x23 2 0x00 0x45
				0x23 2 0x01 0x45
				0x23 2 0x02 0x47
				0x23 2 0x03 0x47
				0x23 2 0x04 0x41
				0x23 2 0x05 0x41
				0x23 2 0x06 0x1F
				0x23 2 0x07 0x1F
				0x23 2 0x08 0x1F
				0x23 2 0x09 0x1F
				0x23 2 0x0A 0x1F
				0x23 2 0x0B 0x1F
				0x23 2 0x0C 0x1F
				0x23 2 0x0D 0x1D
				0x23 2 0x0E 0x1D
				0x23 2 0x0F 0x1D
				0x23 2 0x10 0x1F
				0x23 2 0x11 0x1F
				0x23 2 0x12 0x1F
				0x23 2 0x13 0x1F
				0x23 2 0x14 0x1F
				0x23 2 0x15 0x1F
				0x23 2 0x16 0x44
				0x23 2 0x17 0x44
				0x23 2 0x18 0x46
				0x23 2 0x19 0x46
				0x23 2 0x1A 0x40
				0x23 2 0x1B 0x40
				0x23 2 0x1C 0x1F
				0x23 2 0x1D 0x1F
				0x23 2 0x1E 0x1F
				0x23 2 0x1F 0x1F
				0x23 2 0x20 0x1F
				0x23 2 0x21 0x1F
				0x23 2 0x22 0x1F
				0x23 2 0x23 0x1D
				0x23 2 0x24 0x1D
				0x23 2 0x25 0x1D
				0x23 2 0x26 0x1F
				0x23 2 0x27 0x1F
				0x23 2 0x28 0x1F
				0x23 2 0x29 0x1F
				0x23 2 0x2A 0x1F
				0x23 2 0x2B 0x1F
				0x23 2 0x58 0x40
				0x23 2 0x59 0x00
				0x23 2 0x5A 0x00
				0x23 2 0x5B 0x10
				0x23 2 0x5C 0x07
				0x23 2 0x5D 0x20
				0x23 2 0x5E 0x00
				0x23 2 0x5F 0x00
				0x23 2 0x61 0x00
				0x23 2 0x62 0x00
				0x23 2 0x63 0x7A
				0x23 2 0x64 0x7A
				0x23 2 0x65 0x00
				0x23 2 0x66 0x00
				0x23 2 0x67 0x32
				0x23 2 0x68 0x08
				0x23 2 0x69 0x7A
				0x23 2 0x6A 0x7A
				0x23 2 0x6B 0x00
				0x23 2 0x6C 0x00
				0x23 2 0x6D 0x00
				0x23 2 0x6E 0x00
				0x23 2 0x6F 0x89
				0x23 2 0x70 0x00
				0x23 2 0x71 0x00
				0x23 2 0x72 0x06
				0x23 2 0x73 0x7B
				0x23 2 0x74 0x00
				0x23 2 0x75 0x07
				0x23 2 0x76 0x00
				0x23 2 0x77 0x5D
				0x23 2 0x78 0x17
				0x23 2 0x79 0x1F
				0x23 2 0x7A 0x00
				0x23 2 0x7B 0x00
				0x23 2 0x7C 0x00
				0x23 2 0x7D 0x03
				0x23 2 0x7E 0x7B
				0x23 2 0xE0 0x03
				0x23 2 0xAF 0x20
				0x23 2 0xE0 0x04
				0x23 2 0x09 0x11
				0x23 2 0x0E 0x48
				0x23 2 0x2B 0x2B
				0x23 2 0x2E 0x44
				0x23 2 0x41 0xFF
				0x23 2 0xE0 0x00
				0x23 2 0xE6 0x02
				0x23 2 0xE7 0x0C
				0x23 2 0x51 0xFF
				0x23 2 0x53 0x2C
				0x23 2 0x55 0x00
				0x05 1 0x11
				0xFF 125          /* Delay 125ms */
				0x05 1 0x29
				0xFF 0xFF         /* Ending Flag */
				>;
			init_off = <
				0xff 5
				0x05 1 0x28   /* display off */
				0xff 60       /* delay 60ms */
				0x05 1 0x10   /* sleep in */
				0xff 110      /* delay 110ms */
				0xff 0xff>;   /* ending */
		};

		extern_2{
			index = <2>;
			extern_name = "mipi_default"; // P070ACB_FT9364
			status = "okay";
			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
			cmd_size = <0xff>;
			init_on = <
				0x23 2 0xE0 0x00 /* Page 0 */
				0x23 2 0xE1 0x93 /* PASSWORD */
				0x23 2 0xE2 0x65
				0x23 2 0xE3 0xF8
				0x23 2 0x80 0x03 /* DSI 4 lane */
				0x23 2 0xE0 0x01 /* Page 01 */
				0x23 2 0x0C 0x74 /* Set PWRIC */
				0x23 2 0x17 0x00 /* Set Gamma Power */
				0x23 2 0x18 0xEF /* VGMP=5.1V */
				0x23 2 0x19 0x00 /* VGSP=0V */
				0x23 2 0x1A 0x00
				0x23 2 0x1B 0xEF /* VGMN=-5.1V */
				0x23 2 0x1C 0x00 /* VGSN=0V */
				0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
				0x23 2 0x20 0x2D /* VGL_REG=-12V */
				0x23 2 0x21 0x2D /* VGL_REG2=-12V */
				0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */
				0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */
				0x23 2 0x37 0x09 /* SS=1 BGR=1 */
				0x23 2 0x38 0x04 /* JDT=100 column inversion */
				0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */
				0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */
				0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */
				0x23 2 0x3D 0xFF /* SET Source OP on time */
				0x23 2 0x3E 0xFF /* SET Source OP off time */
				0x23 2 0x3F 0xFF /* SET Source OP off time */
				0x23 2 0x40 0x02 /* RSO=640 RGB */
				0x23 2 0x41 0x80 /* LN=512->1024 line */
				0x23 2 0x42 0x99 /* SLT internal line period */
				0x23 2 0x43 0x14 /* VFP */
				0x23 2 0x44 0x19 /* VBP */
				0x23 2 0x45 0x5A /* HBP */
				0x23 2 0x4B 0x04
				0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */
				0x23 2 0x56 0x01 /* No auto Ratio function */
				0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */
				0x23 2 0x58 0x0A /* AVDD_S */
				0x23 2 0x59 0x0A /* VCL = -2.5V */
				0x23 2 0x5A 0x2E /* VGH = 16.2V */
				0x23 2 0x5B 0x19 /* VGL = -12V */
				0x23 2 0x5C 0x15 /* pump clk */
				0x23 2 0x5D 0x71  /* V255 positive voltage from 4.888V to 4.888V */
				0x23 2 0x5E 0x65  /* V251 positive voltage from 4.533V to 4.718V */
				0x23 2 0x5F 0x55  /* V247 positive voltage from 4.349V to 4.491V */
				0x23 2 0x60 0x49  /* V243 positive voltage from 4.179V to 4.321V */
				0x23 2 0x61 0x46  /* V235 positive voltage from 3.910V to 4.052V */
				0x23 2 0x62 0x38  /* V227 positive voltage from 3.726V to 3.853V */
				0x23 2 0x63 0x3D  /* V211 positive voltage from 3.428V to 3.528V */
				0x23 2 0x64 0x29  /* V191 positive voltage from 3.159V to 3.244V */
				0x23 2 0x65 0x43  /* V159 positive voltage from 2.805V to 2.876V */
				0x23 2 0x66 0x42  /* V128 positive voltage from 2.522V to 2.578V */
				0x23 2 0x67 0x44  /* V96 positive voltage from 2.267V to 2.323V */
				0x23 2 0x68 0x63  /* V64 positive voltage from 1.941V to 2.026V */
				0x23 2 0x69 0x53  /* V44 positive voltage from 1.686V to 1.799V */
				0x23 2 0x6A 0x5B  /* V28 positive voltage from 1.431V to 1.516V */
				0x23 2 0x6B 0x4E  /* V20 positive voltage from 1.275V to 1.322V */
				0x23 2 0x6C 0x4C  /* V12 positive voltage from 1.077V to 1.077V */
				0x23 2 0x6D 0x41  /* V8 positive voltage from 0.949V to 0.921V */
				0x23 2 0x6E 0x2D  /* V4 positive voltage from 0.723V to 0.638V */
				0x23 2 0x6F 0x23  /* V0 positive voltage from 0.496V to 0.496V */
				0x23 2 0x70 0x71  /* V255 negative voltage from -4.888V to -4.888V */
				0x23 2 0x71 0x4C  /* V251 negative voltage from -4.179V to -4.363V */
				0x23 2 0x72 0x3B  /* V247 negative voltage from -3.995V to -4.123V */
				0x23 2 0x73 0x30  /* V243 negative voltage from -3.825V to -3.967V */
				0x23 2 0x74 0x2D  /* V233 negative voltage from -3.556V to -3.698V */
				0x23 2 0x75 0x1F  /* V227 negative voltage from -3.372V to -3.499V */
				0x23 2 0x76 0x25  /* V211 negative voltage from -3.088V to -3.188V */
				0x23 2 0x77 0x10  /* V191 negative voltage from -2.805V to -2.890V */
				0x23 2 0x78 0x2A  /* V159 negative voltage from -2.451V to -2.522V */
				0x23 2 0x79 0x2A  /* V128 negative voltage from -2.182V to -2.238V */
				0x23 2 0x7A 0x2B  /* V96 negative voltage from -1.913V to -1.969V */
				0x23 2 0x7B 0x4A  /* V64 negative voltage from -1.587V to -1.672V */
				0x23 2 0x7C 0x3A  /* V44 negative voltage from -1.332V to -1.445V */
				0x23 2 0x7D 0x43  /* V28 negative voltage from -1.091V to -1.176V */
				0x23 2 0x7E 0x36  /* V20 negative voltage from -0.935V to -0.992V */
				0x23 2 0x7F 0x33  /* V12 negative voltage from -0.723V to -0.723V */
				0x23 2 0x80 0x28  /* V8 negative voltage from -0.595V to -0.567V */
				0x23 2 0x81 0x14  /* V4 negative voltage from -0.368V to -0.283V */
				0x23 2 0x82 0x0B  /* V0 negative voltage from -0.156V to -0.156V */
				0x23 2 0xE0 0x02 /* Page2 */
				0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */
				0x23 2 0x01 0x55 /* VSSG_EVEN */
				0x23 2 0x02 0x55 /* VSSA_EVEN */
				0x23 2 0x03 0x51 /* STV2_EVEN */
				0x23 2 0x04 0x77 /* VDD2_EVEN */
				0x23 2 0x05 0x57 /* VDD1_EVEN */
				0x23 2 0x06 0x1F /* VGL */
				0x23 2 0x07 0x4F /* CK12 */
				0x23 2 0x08 0x4D /* CK10 */
				0x23 2 0x09 0x1F /* VGL */
				0x23 2 0x0A 0x4B /* CK8 */
				0x23 2 0x0B 0x49 /* CK6 */
				0x23 2 0x0C 0x1F /* VGL */
				0x23 2 0x0D 0x47 /* CK4 */
				0x23 2 0x0E 0x45 /* CK2 */
				0x23 2 0x0F 0x41 /* STV1_EVEN */
				0x23 2 0x10 0x1F /* VGL */
				0x23 2 0x11 0x1F /* VGL */
				0x23 2 0x12 0x1F /* VGL */
				0x23 2 0x13 0x55 /* VGG */
				0x23 2 0x14 0x1F /* VGL */
				0x23 2 0x15 0x1F /* VGL */
				0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */
				0x23 2 0x17 0x55 /* VSSG_ODD */
				0x23 2 0x18 0x55 /* VSSA_ODD */
				0x23 2 0x19 0x50 /* STV2_ODD */
				0x23 2 0x1A 0x77 /* VDD2_ODD */
				0x23 2 0x1B 0x57 /* VDD1_ODD */
				0x23 2 0x1C 0x1F /* VGL */
				0x23 2 0x1D 0x4E /* CK11 */
				0x23 2 0x1E 0x4C /* CK9 */
				0x23 2 0x1F 0x1F /* VGL */
				0x23 2 0x20 0x4A /* CK7 */
				0x23 2 0x21 0x48 /* CK5 */
				0x23 2 0x22 0x1F /* VGL */
				0x23 2 0x23 0x46 /* CK3 */
				0x23 2 0x24 0x44 /* CK1 */
				0x23 2 0x25 0x40 /* STV1_ODD */
				0x23 2 0x26 0x1F /* VGL */
				0x23 2 0x27 0x1F /* VGL */
				0x23 2 0x28 0x1F /* VGL */
				0x23 2 0x29 0x1F /* VGL */
				0x23 2 0x2A 0x1F /* VGL */
				0x23 2 0x2B 0x55 /* VGG */
				0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */
				0x23 2 0x2D 0x15 /* VSSG_EVEN */
				0x23 2 0x2E 0x15 /* VSSA_EVEN */
				0x23 2 0x2F 0x00 /* STV2_EVEN */
				0x23 2 0x30 0x17 /* VDD2_EVEN */
				0x23 2 0x31 0x17 /* VDD1_EVEN */
				0x23 2 0x32 0x1F /* VGL */
				0x23 2 0x33 0x08 /* CK12 */
				0x23 2 0x34 0x0A /* CK10 */
				0x23 2 0x35 0x1F /* VGL */
				0x23 2 0x36 0x0C /* CK8 */
				0x23 2 0x37 0x0E /* CK6 */
				0x23 2 0x38 0x1F /* VGL */
				0x23 2 0x39 0x04 /* CK4 */
				0x23 2 0x3A 0x06 /* CK2 */
				0x23 2 0x3B 0x10 /* STV1_EVEN */
				0x23 2 0x3C 0x1F /* VGL */
				0x23 2 0x3D 0x1F /* VGL */
				0x23 2 0x3E 0x1F /* VGL */
				0x23 2 0x3F 0x15 /* VGG */
				0x23 2 0x40 0x1F /* VGL */
				0x23 2 0x41 0x1F /* VGL */
				0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */
				0x23 2 0x43 0x15 /* VSSG_ODD */
				0x23 2 0x44 0x15 /* VSSA_ODD */
				0x23 2 0x45 0x01 /* STV2_ODD */
				0x23 2 0x46 0x37 /* VDD2_ODD */
				0x23 2 0x47 0x17 /* VDD1_ODD */
				0x23 2 0x48 0x1F /* VGL */
				0x23 2 0x49 0x09 /* CK11 */
				0x23 2 0x4A 0x0B /* CK9 */
				0x23 2 0x4B 0x1F /* VGL */
				0x23 2 0x4C 0x0D /* CK7 */
				0x23 2 0x4D 0x0F /* CK5 */
				0x23 2 0x4E 0x1F /* VGL */
				0x23 2 0x4F 0x05 /* CK3 */
				0x23 2 0x50 0x07 /* CK1 */
				0x23 2 0x51 0x11 /* STV1_ODD */
				0x23 2 0x52 0x1F /* VGL */
				0x23 2 0x53 0x1F /* VGL */
				0x23 2 0x54 0x1F /* VGL */
				0x23 2 0x55 0x1F /* VGL */
				0x23 2 0x56 0x1F /* VGL */
				0x23 2 0x57 0x15 /* VGG */
				0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */
				0x23 2 0x59 0x00 /* INIT_W */
				0x23 2 0x5A 0x00 /* INIT[7:0] */
				0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */
				0x23 2 0x5C 0x14 /* STV_S0[7:0] */
				0x23 2 0x5D 0x40 /* STV_W STV_S1 */
				0x23 2 0x5E 0x01 /* STV_S2 */
				0x23 2 0x5F 0x02 /* STV_S3 */
				0x23 2 0x60 0x40 /* ETV_W ETV_S1 */
				0x23 2 0x61 0x03 /* ETV_S2 */
				0x23 2 0x62 0x04 /* ETV_S3 */
				0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */
				0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */
				0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */
				0x23 2 0x66 0x16 /* ETV_S0 */
				0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */
				0x23 2 0x68 0x16 /* CKV0_S0 */
				0x23 2 0x69 0x7A /* CKV0_on */
				0x23 2 0x6A 0x7A /* CKV0_off time */
				0x23 2 0x6B 0x0C /* CKV0_DUM */
				0x23 2 0x6C 0x00 /* GIP Line EQ option */
				0x23 2 0x6D 0x04 /* GIP rising EQ */
				0x23 2 0x6E 0x04 /* GIP fallig EQ */
				0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */
				0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */
				0x23 2 0x71 0x00 /* CKV1_S0 */
				0x23 2 0x72 0x06 /* CKV1_on */
				0x23 2 0x73 0x7B /* CKV1_off time */
				0x23 2 0x74 0x00 /* CKV1_DUM */
				0x23 2 0x75 0xBC /* FLM_EN FLM_W */
				0x23 2 0x76 0x00 /* FLM on time */
				0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */
				0x23 2 0x78 0x2C /* FLM_OFF */
				0x23 2 0x79 0x00 /* VEN_W */
				0x23 2 0x7A 0x00 /* VEN_S0 */
				0x23 2 0x7B 0x00 /* VEN_S1 */
				0x23 2 0x7C 0x00 /* VEN_DUM */
				0x23 2 0x7D 0x03 /* VEN on time */
				0x23 2 0x7E 0x7B /* VEN off time */
				0x23 2 0xE0 0x03 /* Page3 */
				0x23 2 0xAF 0x20 /* Set CABC */
				0x23 2 0xE0 0x04 /* Page4 */
				0x23 2 0x09 0x11 /* Source level at blanking period */
				0x23 2 0x0E 0x48 /* Source EQ option */
				0x23 2 0x2B 0x2B /* ESD Protect */
				0x23 2 0x2E 0x44 /* Special Packet disable */
				0x23 2 0x41 0xFF /* Set CABC */
				0x23 2 0xE0 0x00 /* Page0 */
				0x23 2 0xE6 0x02 /* Enable Watch Dog */
				0x23 2 0xE7 0x0C /* Watch Dog timer setting */
				0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */
				0x23 2 0x53 0x2C
				0x23 2 0x55 0x00
				0x05 1 0x11      /* Sleep Out */
				0xFF 125         /* Delay 125ms */
				0x05 1 0x29      /* Display On */
				0xFF 0xFF        /* Ending */
				>;
			init_off = <
				0xff 5
				0x05 1 0x28   /* display off */
				0xff 60       /* delay 60ms */
				0x05 1 0x10   /* sleep in */
				0xff 110      /* delay 110ms */
				0xff 0xff>;   /* ending */
		};

		extern_3{
			index = <3>;
			extern_name = "mipi_default"; // KD070D82_FT9364
			status = "okay";
			type = <2>; /* 0=i2c, 1=spi, 2=mipi */
			cmd_size = <0xff>;
			init_on = <
				0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
				0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */
				0x23 2 0xE2 0x65
				0x23 2 0xE3 0xF8
				0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */
				0x23 2 0xE0 0x01 /* Register setting change to Page 1 */
				0x23 2 0x00 0x00 /* Set VCOM_Forward */
				0x23 2 0x01 0x9E /* VCOM=0x09F */
				0x23 2 0x03 0x00 /* Set VCOM_Reverse */
				0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */
				0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */
				0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */
				0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */
				0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */
				0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */
				0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */
				0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */
				0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
				0x23 2 0x20 0x2D /* VGL_REG=-12V */
				0x23 2 0x21 0x2D /* VGL_REG2=-12V */
				0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */
				0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */
				0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */
				0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */
				0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */
				0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */
				0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */
				0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */
				0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */
				0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */
				0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */
				0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */
				0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */
				0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */
				0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */
				0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */
				0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */
				0x23 2 0x56 0x01 /* No auto Ratio function */
				0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */
				0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */
				0x23 2 0x59 0x0A /* VCL = -2.5V */
				0x23 2 0x5A 0x2E /* VGH = 16.2V */
				0x23 2 0x5B 0x19 /* VGL = -12V */
				0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */
				0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */
				0x23 2 0x5E 0x5C /* VP251 */
				0x23 2 0x5F 0x4D /* VP247 */
				0x23 2 0x60 0x40 /* VP243 */
				0x23 2 0x61 0x3D /* VP235 */
				0x23 2 0x62 0x2F /* VP227 */
				0x23 2 0x63 0x34 /* VP211 */
				0x23 2 0x64 0x1F /* VP191 */
				0x23 2 0x65 0x38 /* VP159 */
				0x23 2 0x66 0x38 /* VP128 */
				0x23 2 0x67 0x39 /* VP96 */
				0x23 2 0x68 0x58 /* VP64 */
				0x23 2 0x69 0x48 /* VP44 */
				0x23 2 0x6A 0x51 /* VP28 */
				0x23 2 0x6B 0x44 /* VP20 */
				0x23 2 0x6C 0x41 /* VP12 */
				0x23 2 0x6D 0x35 /* VP8 */
				0x23 2 0x6E 0x24 /* VP4 */
				0x23 2 0x6F 0x02 /* VP0 */
				0x23 2 0x70 0x77 /* VN255 */
				0x23 2 0x71 0x5C /* VN251 */
				0x23 2 0x72 0x4D /* VN247 */
				0x23 2 0x73 0x40 /* VN243 */
				0x23 2 0x74 0x3D /* VN235 */
				0x23 2 0x75 0x2F /* VN227 */
				0x23 2 0x76 0x34 /* VN211 */
				0x23 2 0x77 0x1F /* VN191 */
				0x23 2 0x78 0x38 /* VN159 */
				0x23 2 0x79 0x38 /* VN128 */
				0x23 2 0x7A 0x39 /* VN96 */
				0x23 2 0x7B 0x58 /* VN64 */
				0x23 2 0x7C 0x48 /* VN44 */
				0x23 2 0x7D 0x51 /* VN28 */
				0x23 2 0x7E 0x44 /* VN20 */
				0x23 2 0x7F 0x41 /* VN12 */
				0x23 2 0x80 0x35 /* VN8 */
				0x23 2 0x81 0x24 /* VN4 */
				0x23 2 0x82 0x02 /* VN0 */
				0x23 2 0xE0 0x02 /* Register setting change to Page 2 */
				0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */
				0x23 2 0x01 0x55 /* assign as VSSG_EVEN */
				0x23 2 0x02 0x55 /* assign as VSSA_EVEN */
				0x23 2 0x03 0x51 /* assign as STV2_EVEN */
				0x23 2 0x04 0x77 /* assign as VDD2_EVEN */
				0x23 2 0x05 0x57 /* assign as VDD1_EVEN */
				0x23 2 0x06 0x1F /* assign as VGL */
				0x23 2 0x07 0x4F /* assign as CK12 */
				0x23 2 0x08 0x4D /* assign as CK10 */
				0x23 2 0x09 0x1F /* assign as VGL */
				0x23 2 0x0A 0x4B /* assign as CK8 */
				0x23 2 0x0B 0x49 /* assign as CK6 */
				0x23 2 0x0C 0x1F /* assign as VGL */
				0x23 2 0x0D 0x47 /* assign as CK4 */
				0x23 2 0x0E 0x45 /* assign as CK2 */
				0x23 2 0x0F 0x41 /* assign as STV1_EVEN */
				0x23 2 0x10 0x1F /* assign as VGL */
				0x23 2 0x11 0x1F /* assign as VGL */
				0x23 2 0x12 0x1F /* assign as VGL */
				0x23 2 0x13 0x55 /* assign as VGG */
				0x23 2 0x14 0x1F /* assign as VGL */
				0x23 2 0x15 0x1F /* assign as VGL */
				0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */
				0x23 2 0x17 0x55 /* assign as VSSG_ODD */
				0x23 2 0x18 0x55 /* assign as VSSA_ODD */
				0x23 2 0x19 0x50 /* assign as STV2_ODD */
				0x23 2 0x1A 0x77 /* assign as VDD2_ODD */
				0x23 2 0x1B 0x57 /* assign as VDD1_ODD */
				0x23 2 0x1C 0x1F /* assign as VGL */
				0x23 2 0x1D 0x4E /* assign as CK11 */
				0x23 2 0x1E 0x4C /* assign as CK9 */
				0x23 2 0x1F 0x1F /* assign as VGL */
				0x23 2 0x20 0x4A /* assign as CK7 */
				0x23 2 0x21 0x48 /* assign as CK5 */
				0x23 2 0x22 0x1F /* assign as VGL */
				0x23 2 0x23 0x46 /* assign as CK3 */
				0x23 2 0x24 0x44 /* assign as CK1 */
				0x23 2 0x25 0x40 /* assign as STV1_ODD */
				0x23 2 0x26 0x1F /* assign as VGL */
				0x23 2 0x27 0x1F /* assign as VGL */
				0x23 2 0x28 0x1F /* assign as VGL */
				0x23 2 0x29 0x1F /* assign as VGL */
				0x23 2 0x2A 0x1F /* assign as VGL */
				0x23 2 0x2B 0x55 /* assign as VGG */
				0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */
				0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */
				0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */
				0x23 2 0x2F 0x00 /* assign as STV2_EVEN */
				0x23 2 0x30 0x17 /* assign as VDD2_EVEN */
				0x23 2 0x31 0x17 /* assign as VDD1_EVEN */
				0x23 2 0x32 0x1F /* assign as VGL */
				0x23 2 0x33 0x08 /* assign as CK12 */
				0x23 2 0x34 0x0A /* assign as CK10 */
				0x23 2 0x35 0x1F /* assign as VGL */
				0x23 2 0x36 0x0C /* assign as CK8 */
				0x23 2 0x37 0x0E /* assign as CK6 */
				0x23 2 0x38 0x1F /* assign as VGL */
				0x23 2 0x39 0x04 /* assign as CK4 */
				0x23 2 0x3A 0x06 /* assign as CK2 */
				0x23 2 0x3B 0x10 /* assign as STV1_EVEN */
				0x23 2 0x3C 0x1F /* assign as VGL */
				0x23 2 0x3D 0x1F /* assign as VGL */
				0x23 2 0x3E 0x1F /* assign as VGL */
				0x23 2 0x3F 0x15 /* assign as VGG */
				0x23 2 0x40 0x1F /* assign as VGL */
				0x23 2 0x41 0x1F /* assign as VGL */
				0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */
				0x23 2 0x43 0x15 /* assign as VSSG_ODD */
				0x23 2 0x44 0x15 /* assign as VSSA_ODD */
				0x23 2 0x45 0x01 /* assign as STV2_ODD */
				0x23 2 0x46 0x17 /* assign as VDD2_ODD */
				0x23 2 0x47 0x17 /* assign as VDD1_ODD */
				0x23 2 0x48 0x1F /* assign as VGL */
				0x23 2 0x49 0x09 /* assign as CK11 */
				0x23 2 0x4A 0x0B /* assign as CK9 */
				0x23 2 0x4B 0x1F /* assign as VGL */
				0x23 2 0x4C 0x0D /* assign as CK7 */
				0x23 2 0x4D 0x0F /* assign as CK5 */
				0x23 2 0x4E 0x1F /* assign as VGL */
				0x23 2 0x4F 0x05 /* assign as CK3 */
				0x23 2 0x50 0x07 /* assign as CK1 */
				0x23 2 0x51 0x11 /* assign as STV1_ODD */
				0x23 2 0x52 0x1F /* assign as VGL */
				0x23 2 0x53 0x1F /* assign as VGL */
				0x23 2 0x54 0x1F /* assign as VGL */
				0x23 2 0x55 0x1F /* assign as VGL */
				0x23 2 0x56 0x1F /* assign as VGL */
				0x23 2 0x57 0x15 /* assign as VGG */
				0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */
				0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */
				0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */
				0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */
				0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */
				0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */
				0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */
				0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */
				0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */
				0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */
				0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */
				0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */
				0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */
				0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */
				0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */
				0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */
				0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */
				0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */
				0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */
				0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */
				0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */
				0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */
				0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */
				0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */
				0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */
				0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */
				0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */
				0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */
				0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */
				0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */
				0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */
				0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */
				0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */
				0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */
				0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */
				0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */
				0x23 2 0x7C 0x00 /* VEN_DUM  , no VEN function in this panel, don't care */
				0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */
				0x23 2 0x7E 0x7B /* VEN off time  , no VEN function in this panel, don't care */
				0x23 2 0xE0 0x03 /* Register setting change to Page 3 */
				0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */
				0x23 2 0xE0 0x04 /* Register setting change to Page 4 */
				0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */
				0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */
				0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */
				0x23 2 0x2E 0x44 /* ESD protect, disable special packet */
				0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */
				0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
				0x23 2 0xE6 0x02 /* Enable Watch Dog */
				0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */
				0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */
				0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */
				0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */
				0x05 1 0x11      /* SLPOUT */
				0xFF 125         /* Delay 125ms */
				0x05 1 0x29      /* Display On */
				0xFF 0xFF        /* Ending */
				>;
			init_off = <
				0xff 5
				0x05 1 0x28   /* display off */
				0xff 60       /* delay 60ms */
				0x05 1 0x10   /* sleep in */
				0xff 110      /* delay 110ms */
				0xff 0xff>;   /* ending */
		};
	};

	backlight{
		compatible = "amlogic, backlight-g12a";
		status = "okay";
		key_valid = <0>;
		pinctrl-names = "pwm_on","pwm_off";
		pinctrl-0 = <&pwm_f_pins2>;
		pinctrl-1 = <&bl_pwm_off_pins>;
		pinctrl_version = <2>; /* for uboot */
		bl_pwm_config = <&bl_pwm_conf>;
		bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
			&gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
		bl_gpio_names = "GPIOH_4","GPIOH_5";

		/* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
		/* power index:(point gpios_index, 0xff=invalid)
		 * power value:(0=output low, 1=output high, 2=input)
		 * power delay:(unit in ms)
		 */

		backlight_0{
			index = <0>;
			bl_name = "backlight_pwm";
			bl_level_default_uboot_kernel = <100 100>;
			bl_level_attr = <255 10 /*max, min*/
				128 128>; /*mid, mid_mapping*/
			bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
			bl_power_attr = <0 /*en_gpio_index*/
				1 0 /*on_value, off_value*/
				200 200>; /*on_delay(ms), off_delay(ms)*/
			bl_pwm_port = "PWM_F";
			bl_pwm_attr = <0 /*pwm_method*/
				180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
				100 25>; /*duty_max(%), duty_min(%)*/
			bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
				10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
			bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
		};
		backlight_1{
			index = <1>;
			bl_name = "bl_extern";
			bl_level_default_uboot_kernel = <100 100>;
			bl_level_attr = <255 10 /*max, min*/
				128 128>; /*mid, mid_mapping*/
			bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
			bl_power_attr = <1 /*en_gpio_index*/
				1 0 /*on_value, off_value*/
				200 200>; /*on_delay(ms), off_delay(ms)*/
			bl_extern_index = <0>;
		};
	};
	bl_pwm_conf:bl_pwm_conf{
		pwm_channel_0 {
			pwm_port_index = <5>;
			pwms = <&pwm_ef MESON_PWM_1 30040 0>;
		};
	};

	bl_extern{
		compatible = "amlogic, bl_extern";
		status = "disabled";
		i2c_bus = "i2c_bus_3";

		extern_0{
			index = <0>;
			extern_name = "i2c_lp8556";
			type = <0>; /*0=i2c, 1=spi, 2=mipi*/
			i2c_address = <0x2c>; /*7bit i2c address*/
			dim_max_min = <255 10>;
		};

		extern_1{
			index = <1>;
			extern_name = "mipi_lt070me05";
			type = <2>; /*0=i2c, 1=spi, 2=mipi*/
			dim_max_min = <255 10>;
		};
	};
};/* end of panel */