Initial revision
diff --git a/include/bedbug/bedbug.h b/include/bedbug/bedbug.h
new file mode 100644
index 0000000..471215e
--- /dev/null
+++ b/include/bedbug/bedbug.h
@@ -0,0 +1,42 @@
+/* $Id$ */
+
+#ifndef _BEDBUG_H
+#define _BEDBUG_H
+
+#ifndef NULL
+#define NULL 0
+#endif
+
+#define _USE_PROTOTYPES
+
+#ifndef isblank
+#define isblank(c) isspace((int)(c))
+#endif
+
+#ifndef __P
+#if defined(_USE_PROTOTYPES) && (defined(__STDC__) || defined(__cplusplus))
+#define __P(protos) protos /* full-blown ANSI C */
+#else
+#define __P(protos) () /* traditional C preprocessor */
+#endif
+#endif
+
+#define assert( condition ) if( (condition) ) _exit(0)
+
+#endif /* _BEDBUG_H */
+
+
+/*
+ * Copyright (c) 2001 William L. Pitts
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/ppc.h b/include/bedbug/ppc.h
new file mode 100644
index 0000000..9cc8f9f
--- /dev/null
+++ b/include/bedbug/ppc.h
@@ -0,0 +1,413 @@
+/* $Id$ */
+
+#ifndef _PPC_H
+#define _PPC_H
+
+/*======================================================================
+ *
+ * OPERANDS
+ *
+ *======================================================================*/
+
+enum OP_FIELD {
+ O_AA = 1, O_BD, O_BI, O_BO, O_crbD, O_crbA, O_crbB, O_CRM, O_d, O_frC, O_frD,
+ O_frS, O_IMM, O_LI, O_LK, O_MB, O_ME, O_NB, O_OE, O_rA, O_rB, O_Rc, O_rD,
+ O_rS, O_SH, O_SIMM, O_SR, O_TO, O_UIMM, O_crfD, O_crfS, O_L, O_spr, O_tbr,
+ O_cr2 };
+
+struct operand {
+ enum OP_FIELD field; /* The operand identifier from the
+ enum above */
+
+ char * name; /* Symbolic name of this operand */
+
+ unsigned int bits; /* The number of bits used by this
+ operand */
+
+ unsigned int shift; /* How far to the right the operand
+ should be shifted so that it is
+ aligned at the beginning of the
+ word */
+
+ unsigned int hint; /* A bitwise-inclusive-OR of the
+ values shown below. These are used
+ tell the disassembler how to print
+ this operand */
+};
+
+/* Values for operand hint */
+#define OH_SILENT 0x01 /* dont print this operand */
+#define OH_ADDR 0x02 /* this operand is an address */
+#define OH_REG 0x04 /* this operand is a register */
+#define OH_SPR 0x08 /* this operand is an SPR */
+#define OH_TBR 0x10 /* this operand is a TBR */
+#define OH_OFFSET 0x20 /* this operand is an offset */
+#define OH_LITERAL 0x40 /* a literal string */
+
+
+/*======================================================================
+ *
+ * OPCODES
+ *
+ *======================================================================*/
+
+/* From the MPCxxx instruction set documentation, all instructions are
+ * 32 bits long and word aligned. Bits 0-5 always specify the primary
+ * opcode. Many instructions also have an extended opcode.
+ */
+
+#define GET_OPCD(i) (((unsigned long)(i) >> 26) & 0x3f)
+#define MAKE_OPCODE(i) ((((unsigned long)(i)) & 0x3f) << 26)
+
+/* The MPC860 User's Manual, Appendix D.4 contains the definitions of the
+ * instruction forms
+ */
+
+
+/*-------------------------------------------------
+ * I-Form Instructions:
+ * bX
+ *-------------------------------------------------
+ * OPCD | LI |AA|LK
+ *-------------------------------------------------*/
+
+#define I_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define I_MASK I_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ * B-Form Instructions:
+ * bcX
+ *-------------------------------------------------
+ * OPCD | BO | BI | BD |AA|LK
+ *-------------------------------------------------*/
+
+#define B_OPCODE(i,aa,lk) (MAKE_OPCODE(i) | (((aa) & 0x1) << 1) | ((lk) & 0x1))
+#define B_MASK B_OPCODE(0x3f,0x1,0x1)
+
+
+/*-------------------------------------------------
+ * SC-Form Instructions:
+ * sc
+ *-------------------------------------------------
+ * OPCD | 00000 | 00000 | 00000000000000 |1|0
+ *-------------------------------------------------*/
+
+#define SC_OPCODE(i) (MAKE_OPCODE(i) | 0x2)
+#define SC_MASK SC_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ * D-Form Instructions:
+ * addi addic addic. addis andi. andis. cmpi cmpli
+ * lbz lbzu lha lhau lhz lhzu lmw lwz lwzu mulli
+ * ori oris stb stbu sth sthu stmw stw stwu subfic
+ * twi xori xoris
+ *-------------------------------------------------
+ * OPCD | D | A | d
+ * OPCD | D | A | SIMM
+ * OPCD | S | A | d
+ * OPCD | S | A | UIMM
+ * OPCD |crfD|0|L| A | SIMM
+ * OPCD |crfD|0|L| A | UIMM
+ * OPCD | TO | A | SIMM
+ *-------------------------------------------------*/
+
+#define D_OPCODE(i) MAKE_OPCODE(i)
+#define D_MASK MAKE_OPCODE(0x3f)
+
+
+/*-------------------------------------------------
+ * DS-Form Instructions:
+ * (none supported by MPC860)
+ *-------------------------------------------------
+ * OPCD | D | A | ds |XO
+ * OPCD | S | A | ds |XO
+ *-------------------------------------------------*/
+
+#define DS_OPCODE(i,xo) (MAKE_OPCODE(i) | ((xo) & 0x3))
+#define DS_MASK DS_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ * X-Form Instructions:
+ * andX andcX cmp cmpl cntlzwX dcbf dcbi dcbst dcbt
+ * dcbtst dcbz eciwx ecowx eieio eqvX extsbX extshX
+ * icbi lbzux lbxz lhaux lhax lhbrx lhzux lhxz lswi
+ * lswx lwarx lwbrx lwzux lwxz mcrfs mcrxr mfcr
+ * mfmsr mfsr mfsrin mtmsr mtsr mtsrin nandX norX
+ * orX orcX slwX srawX srawiX srwX stbux stbx
+ * sthbrx sthuxsthx stswi stswx stwbrx stwcx. stwux
+ * stwx sync tlbie tlbld tlbli tlbsync tw xorX
+ *---------------------------------------------------
+ * OPCD | D | A | B | XO |0
+ * OPCD | D | A | NB | XO |0
+ * OPCD | D | 00000 | B | XO |0
+ * OPCD | D | 00000 | 00000 | XO |0
+ * OPCD | D |0| SR | 00000 | XO |0
+ * OPCD | S | A | B | XO |Rc
+ * OPCD | S | A | B | XO |1
+ * OPCD | S | A | B | XO |0
+ * OPCD | S | A | NB | XO |0
+ * OPCD | S | A | 00000 | XO |Rc
+ * OPCD | S | 00000 | B | XO |0
+ * OPCD | S | 00000 | 00000 | XO |0
+ * OPCD | S |0| SR | 00000 | XO |0
+ * OPCD | S | A | SH | XO |Rc
+ * OPCD |crfD|0|L| A | SH | XO |0
+ * OPCD |crfD |00| A | B | XO |0
+ * OPCD |crfD |00|crfS |00| 00000 | XO |0
+ * OPCD |crfD |00| 00000 | 00000 | XO |0
+ * OPCD |crfD |00| 00000 | IMM |0| XO |Rc
+ * OPCD | TO | A | B | XO |0
+ * OPCD | D | 00000 | B | XO |Rc
+ * OPCD | D | 00000 | 00000 | XO |Rc
+ * OPCD | crbD | 00000 | 00000 | XO |Rc
+ * OPCD | 00000 | A | B | XO |0
+ * OPCD | 00000 | 00000 | B | XO |0
+ * OPCD | 00000 | 00000 | 00000 | XO |0
+ *---------------------------------------------------*/
+
+#define X_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+ ((rc) & 0x1))
+#define X_MASK X_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ * XL-Form Instructions:
+ * bcctrX bclrX crand crandc creqv crnand crnor cror
+ * croc crxorisync mcrf rfi
+ *---------------------------------------------------
+ * OPCD | BO | BI | 00000 | XO |LK
+ * OPCD | crbD | crbA | crbB | XO |0
+ * OPCD |crfD |00|crfS |00| 00000 | XO |0
+ * OPCD | 00000 | 00000 | 00000 | XO |0
+ *---------------------------------------------------*/
+
+#define XL_OPCODE(i,xo,lk) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+ ((lk) & 0x1))
+#define XL_MASK XL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ * XFX-Form Instructions:
+ * mfspr mftb mtcrf mtspr
+ *---------------------------------------------------
+ * OPCD | D | spr | XO |0
+ * OPCD | D |0| CRM |0| XO |0
+ * OPCD | S | spr | XO |0
+ * OPCD | D | tbr | XO |0
+ *---------------------------------------------------*/
+
+#define XFX_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+ ((rc) & 0x1))
+#define XFX_MASK XFX_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ * XFL-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD |0| FM |0| B | XO |0
+ *---------------------------------------------------*/
+
+#define XFL_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x3ff) << 1) | \
+ ((rc) & 0x1))
+#define XFL_MASK XFL_OPCODE(0x3f,0x3ff,0x1)
+
+
+/*---------------------------------------------------
+ * XS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD | S | A | sh | XO |sh|LK
+ *---------------------------------------------------*/
+
+#define XS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1ff) << 2) | \
+ ((rc) & 0x1))
+#define XS_MASK XS_OPCODE(0x3f,0x1ff,0x1)
+
+
+/*---------------------------------------------------
+ * XO-Form Instructions:
+ * addX addcXaddeX addmeX addzeX divwX divwuX mulhwX
+ * mulhwuX mullwX negX subfX subfcX subfeX subfmeX
+ * subfzeX
+ *---------------------------------------------------
+ * OPCD | D | A | B |OE| XO |Rc
+ * OPCD | D | A | B |0 | XO |Rc
+ * OPCD | D | A | 00000 |OE| XO |Rc
+ *---------------------------------------------------*/
+
+#define XO_OPCODE(i,xo,oe,rc) (MAKE_OPCODE(i) | (((oe) & 0x1) << 10) | \
+ (((xo) & 0x1ff) << 1) | ((rc) & 0x1))
+#define XO_MASK XO_OPCODE(0x3f,0x1ff,0x1,0x1)
+
+
+/*---------------------------------------------------
+ * A-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD | D | A | B |00000| XO |Rc
+ * OPCD | D | A | B | C | XO |Rc
+ * OPCD | D | A | 00000 | C | XO |Rc
+ * OPCD | D | 00000 | B |00000| XO |Rc
+ *---------------------------------------------------*/
+
+#define A_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x1f) << 1) | \
+ ((rc) & 0x1))
+#define A_MASK A_OPCODE(0x3f,0x1f,0x1)
+
+
+/*---------------------------------------------------
+ * M-Form Instructions:
+ * rlwimiX rlwinmX rlwnmX
+ *---------------------------------------------------
+ * OPCD | S | A | SH | MB | ME |Rc
+ * OPCD | S | A | B | MB | ME |Rc
+ *---------------------------------------------------*/
+
+#define M_OPCODE(i,rc) (MAKE_OPCODE(i) | ((rc) & 0x1))
+#define M_MASK M_OPCODE(0x3f,0x1)
+
+
+/*---------------------------------------------------
+ * MD-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD | S | A | sh | mb | XO |sh|Rc
+ * OPCD | S | A | sh | me | XO |sh|Rc
+ *---------------------------------------------------*/
+
+#define MD_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0x7) << 2) | \
+ ((rc) & 0x1))
+#define MD_MASK MD_OPCODE(0x3f,0x7,0x1)
+
+
+/*---------------------------------------------------
+ * MDS-Form Instructions:
+ * (none supported by MPC860)
+ *---------------------------------------------------
+ * OPCD | S | A | B | mb | XO |Rc
+ * OPCD | S | A | B | me | XO |Rc
+ *---------------------------------------------------*/
+
+#define MDS_OPCODE(i,xo,rc) (MAKE_OPCODE(i) | (((xo) & 0xf) << 1) | \
+ ((rc) & 0x1))
+#define MDS_MASK MDS_OPCODE(0x3f,0xf,0x1)
+
+#ifndef FALSE
+#define FALSE 0
+#define TRUE (!FALSE)
+#endif
+
+#define INSTRUCTION( memaddr ) ntohl(*(unsigned long *)(memaddr))
+
+#define MAX_OPERANDS 8
+
+struct ppc_ctx;
+
+struct opcode {
+ unsigned long opcode; /* The complete opcode as produced by
+ one of the XXX_OPCODE macros above */
+
+ unsigned long mask; /* The mask to use on an instruction
+ before comparing with the opcode
+ field to see if it matches */
+
+ enum OP_FIELD fields[MAX_OPERANDS];
+ /* An array defining the operands for
+ this opcode. The values of the
+ array are the operand identifiers */
+
+ int (*hfunc)(struct ppc_ctx *);
+ /* Address of a function to handle the given
+ mnemonic */
+
+ char * name; /* The symbolic name of this opcode */
+
+ unsigned int hint; /* A bitwise-inclusive-OR of the
+ values shown below. These are used
+ tell the disassembler how to print
+ some operands for this opcode */
+};
+
+/* values for opcode hints */
+#define H_RELATIVE 0x1 /* The address operand is relative */
+#define H_IMM_HIGH 0x2 /* [U|S]IMM field shifted high */
+#define H_RA0_IS_0 0x4 /* If rA = 0 then treat as literal 0 */
+
+struct ppc_ctx {
+ struct opcode * op;
+ unsigned long instr;
+ unsigned int flags;
+ int datalen;
+ char data[ 256 ];
+ char radix_fmt[ 8 ];
+ unsigned char * virtual;
+};
+
+
+/*======================================================================
+ *
+ * FUNCTIONS
+ *
+ *======================================================================*/
+
+/* Values for flags as passed to various ppc routines */
+#define F_RADOCTAL 0x1 /* output radix = unsigned octal */
+#define F_RADUDECIMAL 0x2 /* output radix = unsigned decimal */
+#define F_RADSDECIMAL 0x4 /* output radix = signed decimal */
+#define F_RADHEX 0x8 /* output radix = unsigned hex */
+#define F_SIMPLE 0x10 /* use simplified mnemonics */
+#define F_SYMBOL 0x20 /* use symbol lookups for addresses */
+#define F_INSTR 0x40 /* output the raw instruction */
+#define F_LOCALMEM 0x80 /* retrieve opcodes from local memory
+ rather than from the HMI */
+#define F_LINENO 0x100 /* show line number info if available */
+#define F_VALIDONLY 0x200 /* cache: valid entries only */
+
+/* Values for assembler error codes */
+#define E_ASM_BAD_OPCODE 1
+#define E_ASM_NUM_OPERANDS 2
+#define E_ASM_BAD_REGISTER 3
+#define E_ASM_BAD_SPR 4
+#define E_ASM_BAD_TBR 5
+
+extern int disppc __P((unsigned char *,unsigned char *,int,
+ int (*)(const char *), unsigned long));
+extern int print_source_line __P((char *,char *,int,
+ int (*pfunc)(const char *)));
+extern int find_next_address __P((unsigned char *,int,struct pt_regs *));
+extern int handle_bc __P((struct ppc_ctx *));
+extern unsigned long asmppc __P((unsigned long,char*,int*));
+extern char *asm_error_str __P((int));
+
+/*======================================================================
+ *
+ * GLOBAL VARIABLES
+ *
+ *======================================================================*/
+
+extern struct operand operands[];
+extern const unsigned int n_operands;
+extern struct opcode opcodes[];
+extern const unsigned int n_opcodes;
+
+#endif /* _PPC_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/bedbug/regs.h b/include/bedbug/regs.h
new file mode 100644
index 0000000..938e435
--- /dev/null
+++ b/include/bedbug/regs.h
@@ -0,0 +1,403 @@
+/* $Id$ */
+
+#ifndef _REGS_H
+#define _REGS_H
+
+/* Special Purpose Registers */
+
+#define SPR_CR -1
+#define SPR_MSR -2
+
+#define SPR_XER 1
+#define SPR_LR 8
+#define SPR_CTR 9
+#define SPR_DSISR 18
+#define SPR_DAR 19
+#define SPR_DEC 22
+#define SPR_SRR0 26
+#define SPR_SRR1 27
+#define SPR_EIE 80
+#define SPR_EID 81
+#define SPR_CMPA 144
+#define SPR_CMPB 145
+#define SPR_CMPC 146
+#define SPR_CMPD 147
+#define SPR_ICR 148
+#define SPR_DER 149
+#define SPR_COUNTA 150
+#define SPR_COUNTB 151
+#define SPR_CMPE 152
+#define SPR_CMPF 153
+#define SPR_CMPG 154
+#define SPR_CMPH 155
+#define SPR_LCTRL1 156
+#define SPR_LCTRL2 157
+#define SPR_ICTRL 158
+#define SPR_BAR 159
+#define SPR_USPRG0 256
+#define SPR_SPRG4_RO 260
+#define SPR_SPRG5_RO 261
+#define SPR_SPRG6_RO 262
+#define SPR_SPRG7_RO 263
+#define SPR_SPRG0 272
+#define SPR_SPRG1 273
+#define SPR_SPRG2 274
+#define SPR_SPRG3 275
+#define SPR_SPRG4 276
+#define SPR_SPRG5 277
+#define SPR_SPRG6 278
+#define SPR_SPRG7 279
+#define SPR_EAR 282 /* MPC603e core */
+#define SPR_TBL 284
+#define SPR_TBU 285
+#define SPR_PVR 287
+#define SPR_IC_CST 560
+#define SPR_IC_ADR 561
+#define SPR_IC_DAT 562
+#define SPR_DC_CST 568
+#define SPR_DC_ADR 569
+#define SPR_DC_DAT 570
+#define SPR_DPDR 630
+#define SPR_IMMR 638
+#define SPR_MI_CTR 784
+#define SPR_MI_AP 786
+#define SPR_MI_EPN 787
+#define SPR_MI_TWC 789
+#define SPR_MI_RPN 790
+#define SPR_MD_CTR 792
+#define SPR_M_CASID 793
+#define SPR_MD_AP 794
+#define SPR_MD_EPN 795
+#define SPR_M_TWB 796
+#define SPR_MD_TWC 797
+#define SPR_MD_RPN 798
+#define SPR_M_TW 799
+#define SPR_MI_DBCAM 816
+#define SPR_MI_DBRAM0 817
+#define SPR_MI_DBRAM1 818
+#define SPR_MD_DBCAM 824
+#define SPR_MD_DBRAM0 825
+#define SPR_MD_DBRAM1 826
+#define SPR_ZPR 944
+#define SPR_PID 945
+#define SPR_CCR0 947
+#define SPR_IAC3 948
+#define SPR_IAC4 949
+#define SPR_DVC1 950
+#define SPR_DVC2 951
+#define SPR_SGR 953
+#define SPR_DCWR 954
+#define SPR_SLER 955
+#define SPR_SU0R 956
+#define SPR_DBCR1 957
+#define SPR_ICDBDR 979
+#define SPR_ESR 980
+#define SPR_DEAR 981
+#define SPR_EVPR 982
+#define SPR_TSR 984
+#define SPR_TCR 986
+#define SPR_PIT 987
+#define SPR_SRR2 990
+#define SPR_SRR3 991
+#define SPR_DBSR 1008
+#define SPR_DBCR0 1010
+#define SPR_IABR 1010 /* MPC603e core */
+#define SPR_IAC1 1012
+#define SPR_IAC2 1013
+#define SPR_DAC1 1014
+#define SPR_DAC2 1015
+#define SPR_DCCR 1018
+#define SPR_ICCR 1019
+
+/* Bits for the DBCR0 register */
+#define DBCR0_EDM 0x80000000
+#define DBCR0_IDM 0x40000000
+#define DBCR0_RST 0x30000000
+#define DBCR0_IC 0x08000000
+#define DBCR0_BT 0x04000000
+#define DBCR0_EDE 0x02000000
+#define DBCR0_TDE 0x01000000
+#define DBCR0_IA1 0x00800000
+#define DBCR0_IA2 0x00400000
+#define DBCR0_IA12 0x00200000
+#define DBCR0_IA12X 0x00100000
+#define DBCR0_IA3 0x00080000
+#define DBCR0_IA4 0x00040000
+#define DBCR0_IA34 0x00020000
+#define DBCR0_IA34X 0x00010000
+#define DBCR0_IA12T 0x00008000
+#define DBCR0_IA34T 0x00004000
+#define DBCR0_FT 0x00000001
+
+/* Bits for the DBCR1 register */
+#define DBCR1_D1R 0x80000000
+#define DBCR1_D2R 0x40000000
+#define DBCR1_D1W 0x20000000
+#define DBCR1_D2W 0x10000000
+#define DBCR1_D1S 0x0C000000
+#define DBCR1_D2S 0x03000000
+#define DBCR1_DA12 0x00800000
+#define DBCR1_DA12X 0x00400000
+#define DBCR1_DV1M 0x000C0000
+#define DBCR1_DV2M 0x00030000
+#define DBCR1_DV1BE 0x0000F000
+#define DBCR1_DV2BE 0x00000F00
+
+/* Bits for the DBSR register */
+#define DBSR_IC 0x80000000
+#define DBSR_BT 0x40000000
+#define DBSR_EDE 0x20000000
+#define DBSR_TIE 0x10000000
+#define DBSR_UDE 0x08000000
+#define DBSR_IA1 0x04000000
+#define DBSR_IA2 0x02000000
+#define DBSR_DR1 0x01000000
+#define DBSR_DW1 0x00800000
+#define DBSR_DR2 0x00400000
+#define DBSR_DW2 0x00200000
+#define DBSR_IDE 0x00100000
+#define DBSR_IA3 0x00080000
+#define DBSR_IA4 0x00040000
+#define DBSR_MRR 0x00000300
+
+struct spr_info {
+ int spr_val;
+ char spr_name[ 10 ];
+};
+
+extern struct spr_info spr_map[];
+extern const unsigned int n_sprs;
+
+
+#define SET_REGISTER( str, val ) \
+({ unsigned long __value = (val); \
+ asm volatile( str : : "r" (__value)); \
+ __value; })
+
+#define GET_REGISTER( str ) \
+({ unsigned long __value; \
+ asm volatile( str : "=r" (__value) : ); \
+ __value; })
+
+#define GET_CR() GET_REGISTER( "mfcr %0" )
+#define SET_CR(val) SET_REGISTER( "mtcr %0", val )
+#define GET_MSR() GET_REGISTER( "mfmsr %0" )
+#define SET_MSR(val) SET_REGISTER( "mtmsr %0", val )
+#define GET_XER() GET_REGISTER( "mfspr %0,1" )
+#define SET_XER(val) SET_REGISTER( "mtspr 1,%0", val )
+#define GET_LR() GET_REGISTER( "mfspr %0,8" )
+#define SET_LR(val) SET_REGISTER( "mtspr 8,%0", val )
+#define GET_CTR() GET_REGISTER( "mfspr %0,9" )
+#define SET_CTR(val) SET_REGISTER( "mtspr 9,%0", val )
+#define GET_DSISR() GET_REGISTER( "mfspr %0,18" )
+#define SET_DSISR(val) SET_REGISTER( "mtspr 18,%0", val )
+#define GET_DAR() GET_REGISTER( "mfspr %0,19" )
+#define SET_DAR(val) SET_REGISTER( "mtspr 19,%0", val )
+#define GET_DEC() GET_REGISTER( "mfspr %0,22" )
+#define SET_DEC(val) SET_REGISTER( "mtspr 22,%0", val )
+#define GET_SRR0() GET_REGISTER( "mfspr %0,26" )
+#define SET_SRR0(val) SET_REGISTER( "mtspr 26,%0", val )
+#define GET_SRR1() GET_REGISTER( "mfspr %0,27" )
+#define SET_SRR1(val) SET_REGISTER( "mtspr 27,%0", val )
+#define GET_EIE() GET_REGISTER( "mfspr %0,80" )
+#define SET_EIE(val) SET_REGISTER( "mtspr 80,%0", val )
+#define GET_EID() GET_REGISTER( "mfspr %0,81" )
+#define SET_EID(val) SET_REGISTER( "mtspr 81,%0", val )
+#define GET_CMPA() GET_REGISTER( "mfspr %0,144" )
+#define SET_CMPA(val) SET_REGISTER( "mtspr 144,%0", val )
+#define GET_CMPB() GET_REGISTER( "mfspr %0,145" )
+#define SET_CMPB(val) SET_REGISTER( "mtspr 145,%0", val )
+#define GET_CMPC() GET_REGISTER( "mfspr %0,146" )
+#define SET_CMPC(val) SET_REGISTER( "mtspr 146,%0", val )
+#define GET_CMPD() GET_REGISTER( "mfspr %0,147" )
+#define SET_CMPD(val) SET_REGISTER( "mtspr 147,%0", val )
+#define GET_ICR() GET_REGISTER( "mfspr %0,148" )
+#define SET_ICR(val) SET_REGISTER( "mtspr 148,%0", val )
+#define GET_DER() GET_REGISTER( "mfspr %0,149" )
+#define SET_DER(val) SET_REGISTER( "mtspr 149,%0", val )
+#define GET_COUNTA() GET_REGISTER( "mfspr %0,150" )
+#define SET_COUNTA(val) SET_REGISTER( "mtspr 150,%0", val )
+#define GET_COUNTB() GET_REGISTER( "mfspr %0,151" )
+#define SET_COUNTB(val) SET_REGISTER( "mtspr 151,%0", val )
+#define GET_CMPE() GET_REGISTER( "mfspr %0,152" )
+#define SET_CMPE(val) SET_REGISTER( "mtspr 152,%0", val )
+#define GET_CMPF() GET_REGISTER( "mfspr %0,153" )
+#define SET_CMPF(val) SET_REGISTER( "mtspr 153,%0", val )
+#define GET_CMPG() GET_REGISTER( "mfspr %0,154" )
+#define SET_CMPG(val) SET_REGISTER( "mtspr 154,%0", val )
+#define GET_CMPH() GET_REGISTER( "mfspr %0,155" )
+#define SET_CMPH(val) SET_REGISTER( "mtspr 155,%0", val )
+#define GET_LCTRL1() GET_REGISTER( "mfspr %0,156" )
+#define SET_LCTRL1(val) SET_REGISTER( "mtspr 156,%0", val )
+#define GET_LCTRL2() GET_REGISTER( "mfspr %0,157" )
+#define SET_LCTRL2(val) SET_REGISTER( "mtspr 157,%0", val )
+#define GET_ICTRL() GET_REGISTER( "mfspr %0,158" )
+#define SET_ICTRL(val) SET_REGISTER( "mtspr 158,%0", val )
+#define GET_BAR() GET_REGISTER( "mfspr %0,159" )
+#define SET_BAR(val) SET_REGISTER( "mtspr 159,%0", val )
+#define GET_USPRG0() GET_REGISTER( "mfspr %0,256" )
+#define SET_USPRG0(val) SET_REGISTER( "mtspr 256,%0", val )
+#define GET_SPRG4_RO() GET_REGISTER( "mfspr %0,260" )
+#define SET_SPRG4_RO(val) SET_REGISTER( "mtspr 260,%0", val )
+#define GET_SPRG5_RO() GET_REGISTER( "mfspr %0,261" )
+#define SET_SPRG5_RO(val) SET_REGISTER( "mtspr 261,%0", val )
+#define GET_SPRG6_RO() GET_REGISTER( "mfspr %0,262" )
+#define SET_SPRG6_RO(val) SET_REGISTER( "mtspr 262,%0", val )
+#define GET_SPRG7_RO() GET_REGISTER( "mfspr %0,263" )
+#define SET_SPRG7_RO(val) SET_REGISTER( "mtspr 263,%0", val )
+#define GET_SPRG0() GET_REGISTER( "mfspr %0,272" )
+#define SET_SPRG0(val) SET_REGISTER( "mtspr 272,%0", val )
+#define GET_SPRG1() GET_REGISTER( "mfspr %0,273" )
+#define SET_SPRG1(val) SET_REGISTER( "mtspr 273,%0", val )
+#define GET_SPRG2() GET_REGISTER( "mfspr %0,274" )
+#define SET_SPRG2(val) SET_REGISTER( "mtspr 274,%0", val )
+#define GET_SPRG3() GET_REGISTER( "mfspr %0,275" )
+#define SET_SPRG3(val) SET_REGISTER( "mtspr 275,%0", val )
+#define GET_SPRG4() GET_REGISTER( "mfspr %0,276" )
+#define SET_SPRG4(val) SET_REGISTER( "mtspr 276,%0", val )
+#define GET_SPRG5() GET_REGISTER( "mfspr %0,277" )
+#define SET_SPRG5(val) SET_REGISTER( "mtspr 277,%0", val )
+#define GET_SPRG6() GET_REGISTER( "mfspr %0,278" )
+#define SET_SPRG6(val) SET_REGISTER( "mtspr 278,%0", val )
+#define GET_SPRG7() GET_REGISTER( "mfspr %0,279" )
+#define SET_SPRG7(val) SET_REGISTER( "mtspr 279,%0", val )
+#define GET_EAR() GET_REGISTER( "mfspr %0,282" )
+#define SET_EAR(val) SET_REGISTER( "mtspr 282,%0", val )
+#define GET_TBL() GET_REGISTER( "mfspr %0,284" )
+#define SET_TBL(val) SET_REGISTER( "mtspr 284,%0", val )
+#define GET_TBU() GET_REGISTER( "mfspr %0,285" )
+#define SET_TBU(val) SET_REGISTER( "mtspr 285,%0", val )
+#define GET_PVR() GET_REGISTER( "mfspr %0,287" )
+#define SET_PVR(val) SET_REGISTER( "mtspr 287,%0", val )
+#define GET_IC_CST() GET_REGISTER( "mfspr %0,560" )
+#define SET_IC_CST(val) SET_REGISTER( "mtspr 560,%0", val )
+#define GET_IC_ADR() GET_REGISTER( "mfspr %0,561" )
+#define SET_IC_ADR(val) SET_REGISTER( "mtspr 561,%0", val )
+#define GET_IC_DAT() GET_REGISTER( "mfspr %0,562" )
+#define SET_IC_DAT(val) SET_REGISTER( "mtspr 562,%0", val )
+#define GET_DC_CST() GET_REGISTER( "mfspr %0,568" )
+#define SET_DC_CST(val) SET_REGISTER( "mtspr 568,%0", val )
+#define GET_DC_ADR() GET_REGISTER( "mfspr %0,569" )
+#define SET_DC_ADR(val) SET_REGISTER( "mtspr 569,%0", val )
+#define GET_DC_DAT() GET_REGISTER( "mfspr %0,570" )
+#define SET_DC_DAT(val) SET_REGISTER( "mtspr 570,%0", val )
+#define GET_DPDR() GET_REGISTER( "mfspr %0,630" )
+#define SET_DPDR(val) SET_REGISTER( "mtspr 630,%0", val )
+#define GET_IMMR() GET_REGISTER( "mfspr %0,638" )
+#define SET_IMMR(val) SET_REGISTER( "mtspr 638,%0", val )
+#define GET_MI_CTR() GET_REGISTER( "mfspr %0,784" )
+#define SET_MI_CTR(val) SET_REGISTER( "mtspr 784,%0", val )
+#define GET_MI_AP() GET_REGISTER( "mfspr %0,786" )
+#define SET_MI_AP(val) SET_REGISTER( "mtspr 786,%0", val )
+#define GET_MI_EPN() GET_REGISTER( "mfspr %0,787" )
+#define SET_MI_EPN(val) SET_REGISTER( "mtspr 787,%0", val )
+#define GET_MI_TWC() GET_REGISTER( "mfspr %0,789" )
+#define SET_MI_TWC(val) SET_REGISTER( "mtspr 789,%0", val )
+#define GET_MI_RPN() GET_REGISTER( "mfspr %0,790" )
+#define SET_MI_RPN(val) SET_REGISTER( "mtspr 790,%0", val )
+#define GET_MD_CTR() GET_REGISTER( "mfspr %0,792" )
+#define SET_MD_CTR(val) SET_REGISTER( "mtspr 792,%0", val )
+#define GET_M_CASID() GET_REGISTER( "mfspr %0,793" )
+#define SET_M_CASID(val) SET_REGISTER( "mtspr 793,%0", val )
+#define GET_MD_AP() GET_REGISTER( "mfspr %0,794" )
+#define SET_MD_AP(val) SET_REGISTER( "mtspr ,794%0", val )
+#define GET_MD_EPN() GET_REGISTER( "mfspr %0,795" )
+#define SET_MD_EPN(val) SET_REGISTER( "mtspr 795,%0", val )
+#define GET_M_TWB() GET_REGISTER( "mfspr %0,796" )
+#define SET_M_TWB(val) SET_REGISTER( "mtspr 796,%0", val )
+#define GET_MD_TWC() GET_REGISTER( "mfspr %0,797" )
+#define SET_MD_TWC(val) SET_REGISTER( "mtspr 797,%0", val )
+#define GET_MD_RPN() GET_REGISTER( "mfspr %0,798" )
+#define SET_MD_RPN(val) SET_REGISTER( "mtspr 798,%0", val )
+#define GET_M_TW() GET_REGISTER( "mfspr %0,799" )
+#define SET_M_TW(val) SET_REGISTER( "mtspr 799,%0", val )
+#define GET_MI_DBCAM() GET_REGISTER( "mfspr %0,816" )
+#define SET_MI_DBCAM(val) SET_REGISTER( "mtspr 816,%0", val )
+#define GET_MI_DBRAM0() GET_REGISTER( "mfspr %0,817" )
+#define SET_MI_DBRAM0(val) SET_REGISTER( "mtspr 817,%0", val )
+#define GET_MI_DBRAM1() GET_REGISTER( "mfspr %0,818" )
+#define SET_MI_DBRAM1(val) SET_REGISTER( "mtspr 818,%0", val )
+#define GET_MD_DBCAM() GET_REGISTER( "mfspr %0,824" )
+#define SET_MD_DBCA(val) SET_REGISTER( "mtspr 824,%0", val )
+#define GET_MD_DBRAM0() GET_REGISTER( "mfspr %0,825" )
+#define SET_MD_DBRAM0(val) SET_REGISTER( "mtspr 825,%0", val )
+#define GET_MD_DBRAM1() GET_REGISTER( "mfspr %0,826" )
+#define SET_MD_DBRAM1(val) SET_REGISTER( "mtspr 826,%0", val )
+#define GET_ZPR() GET_REGISTER( "mfspr %0,944" )
+#define SET_ZPR(val) SET_REGISTER( "mtspr 944,%0", val )
+#define GET_PID() GET_REGISTER( "mfspr %0,945" )
+#define SET_PID(val) SET_REGISTER( "mtspr 945,%0", val )
+#define GET_CCR0() GET_REGISTER( "mfspr %0,947" )
+#define SET_CCR0(val) SET_REGISTER( "mtspr 947,%0", val )
+#define GET_IAC3() GET_REGISTER( "mfspr %0,948" )
+#define SET_IAC3(val) SET_REGISTER( "mtspr 948,%0", val )
+#define GET_IAC4() GET_REGISTER( "mfspr %0,949" )
+#define SET_IAC4(val) SET_REGISTER( "mtspr 949,%0", val )
+#define GET_DVC1() GET_REGISTER( "mfspr %0,950" )
+#define SET_DVC1(val) SET_REGISTER( "mtspr 950,%0", val )
+#define GET_DVC2() GET_REGISTER( "mfspr %0,951" )
+#define SET_DVC2(val) SET_REGISTER( "mtspr 951,%0", val )
+#define GET_SGR() GET_REGISTER( "mfspr %0,953" )
+#define SET_SGR(val) SET_REGISTER( "mtspr 953,%0", val )
+#define GET_DCWR() GET_REGISTER( "mfspr %0,954" )
+#define SET_DCWR(val) SET_REGISTER( "mtspr 954,%0", val )
+#define GET_SLER() GET_REGISTER( "mfspr %0,955" )
+#define SET_SLER(val) SET_REGISTER( "mtspr 955,%0", val )
+#define GET_SU0R() GET_REGISTER( "mfspr %0,956" )
+#define SET_SU0R(val) SET_REGISTER( "mtspr 956,%0", val )
+#define GET_DBCR1() GET_REGISTER( "mfspr %0,957" )
+#define SET_DBCR1(val) SET_REGISTER( "mtspr 957,%0", val )
+#define GET_ICDBDR() GET_REGISTER( "mfspr %0,979" )
+#define SET_ICDBDR(val) SET_REGISTER( "mtspr 979,%0", val )
+#define GET_ESR() GET_REGISTER( "mfspr %0,980" )
+#define SET_ESR(val) SET_REGISTER( "mtspr 980,%0", val )
+#define GET_DEAR() GET_REGISTER( "mfspr %0,981" )
+#define SET_DEAR(val) SET_REGISTER( "mtspr 981,%0", val )
+#define GET_EVPR() GET_REGISTER( "mfspr %0,982" )
+#define SET_EVPR(val) SET_REGISTER( "mtspr 982,%0", val )
+#define GET_TSR() GET_REGISTER( "mfspr %0,984" )
+#define SET_TSR(val) SET_REGISTER( "mtspr 984,%0", val )
+#define GET_TCR() GET_REGISTER( "mfspr %0,986" )
+#define SET_TCR(val) SET_REGISTER( "mtspr 986,%0", val )
+#define GET_PIT() GET_REGISTER( "mfspr %0,987" )
+#define SET_PIT(val) SET_REGISTER( "mtspr 987,%0", val )
+#define GET_SRR2() GET_REGISTER( "mfspr %0,990" )
+#define SET_SRR2(val) SET_REGISTER( "mtspr 990,%0", val )
+#define GET_SRR3() GET_REGISTER( "mfspr %0,991" )
+#define SET_SRR3(val) SET_REGISTER( "mtspr 991,%0", val )
+#define GET_DBSR() GET_REGISTER( "mfspr %0,1008" )
+#define SET_DBSR(val) SET_REGISTER( "mtspr 1008,%0", val )
+#define GET_DBCR0() GET_REGISTER( "mfspr %0,1010" )
+#define SET_DBCR0(val) SET_REGISTER( "mtspr 1010,%0", val )
+#define GET_IABR() GET_REGISTER( "mfspr %0,1010" )
+#define SET_IABR(val) SET_REGISTER( "mtspr 1010,%0", val )
+#define GET_IAC1() GET_REGISTER( "mfspr %0,1012" )
+#define SET_IAC1(val) SET_REGISTER( "mtspr 1012,%0", val )
+#define GET_IAC2() GET_REGISTER( "mfspr %0,1013" )
+#define SET_IAC2(val) SET_REGISTER( "mtspr 1013,%0", val )
+#define GET_DAC1() GET_REGISTER( "mfspr %0,1014" )
+#define SET_DAC1(val) SET_REGISTER( "mtspr 1014,%0", val )
+#define GET_DAC2() GET_REGISTER( "mfspr %0,1015" )
+#define SET_DAC2(val) SET_REGISTER( "mtspr 1015,%0", val )
+#define GET_DCCR() GET_REGISTER( "mfspr %0,1018" )
+#define SET_DCCR(val) SET_REGISTER( "mtspr 1018,%0", val )
+#define GET_ICCR() GET_REGISTER( "mfspr %0,1019" )
+#define SET_ICCR(val) SET_REGISTER( "mtspr 1019,%0", val )
+
+#endif /* _REGS_H */
+
+
+/*
+ * Copyright (c) 2000 William L. Pitts and W. Gerald Hicks
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms are freely
+ * permitted provided that the above copyright notice and this
+ * paragraph and the following disclaimer are duplicated in all
+ * such forms.
+ *
+ * This software is provided "AS IS" and without any express or
+ * implied warranties, including, without limitation, the implied
+ * warranties of merchantability and fitness for a particular
+ * purpose.
+ */
diff --git a/include/galileo/gt64260R.h b/include/galileo/gt64260R.h
new file mode 100644
index 0000000..1e6f58b
--- /dev/null
+++ b/include/galileo/gt64260R.h
@@ -0,0 +1,1197 @@
+/* gt64260R.h - GT64260 Internal registers definition file */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCgt64260rh
+#define __INCgt64260rh
+
+#ifndef GT64260
+#define GT64260
+#endif
+
+/* CPU MASTER CONTROL REGISTER */
+#define CPU_CONFIGURATION 0x0
+#define CPU_MASTER_CONTROL 0x160
+
+/****************************************/
+/* Processor Address Space */
+/****************************************/
+
+/* Sdram's BAR'S */
+#define SCS_0_LOW_DECODE_ADDRESS 0x008
+#define SCS_0_HIGH_DECODE_ADDRESS 0x010
+#define SCS_1_LOW_DECODE_ADDRESS 0x208
+#define SCS_1_HIGH_DECODE_ADDRESS 0x210
+#define SCS_2_LOW_DECODE_ADDRESS 0x018
+#define SCS_2_HIGH_DECODE_ADDRESS 0x020
+#define SCS_3_LOW_DECODE_ADDRESS 0x218
+#define SCS_3_HIGH_DECODE_ADDRESS 0x220
+/* Devices BAR'S */
+#define CS_0_LOW_DECODE_ADDRESS 0x028
+#define CS_0_HIGH_DECODE_ADDRESS 0x030
+#define CS_1_LOW_DECODE_ADDRESS 0x228
+#define CS_1_HIGH_DECODE_ADDRESS 0x230
+#define CS_2_LOW_DECODE_ADDRESS 0x248
+#define CS_2_HIGH_DECODE_ADDRESS 0x250
+#define CS_3_LOW_DECODE_ADDRESS 0x038
+#define CS_3_HIGH_DECODE_ADDRESS 0x040
+#define BOOTCS_LOW_DECODE_ADDRESS 0x238
+#define BOOTCS_HIGH_DECODE_ADDRESS 0x240
+
+#define PCI_0I_O_LOW_DECODE_ADDRESS 0x048
+#define PCI_0I_O_HIGH_DECODE_ADDRESS 0x050
+#define PCI_0MEMORY0_LOW_DECODE_ADDRESS 0x058
+#define PCI_0MEMORY0_HIGH_DECODE_ADDRESS 0x060
+#define PCI_0MEMORY1_LOW_DECODE_ADDRESS 0x080
+#define PCI_0MEMORY1_HIGH_DECODE_ADDRESS 0x088
+#define PCI_0MEMORY2_LOW_DECODE_ADDRESS 0x258
+#define PCI_0MEMORY2_HIGH_DECODE_ADDRESS 0x260
+#define PCI_0MEMORY3_LOW_DECODE_ADDRESS 0x280
+#define PCI_0MEMORY3_HIGH_DECODE_ADDRESS 0x288
+
+#define PCI_1I_O_LOW_DECODE_ADDRESS 0x090
+#define PCI_1I_O_HIGH_DECODE_ADDRESS 0x098
+#define PCI_1MEMORY0_LOW_DECODE_ADDRESS 0x0a0
+#define PCI_1MEMORY0_HIGH_DECODE_ADDRESS 0x0a8
+#define PCI_1MEMORY1_LOW_DECODE_ADDRESS 0x0b0
+#define PCI_1MEMORY1_HIGH_DECODE_ADDRESS 0x0b8
+#define PCI_1MEMORY2_LOW_DECODE_ADDRESS 0x2a0
+#define PCI_1MEMORY2_HIGH_DECODE_ADDRESS 0x2a8
+#define PCI_1MEMORY3_LOW_DECODE_ADDRESS 0x2b0
+#define PCI_1MEMORY3_HIGH_DECODE_ADDRESS 0x2b8
+
+
+#define INTERNAL_SPACE_DECODE 0x068
+
+#define CPU_0_LOW_DECODE_ADDRESS 0x290
+#define CPU_0_HIGH_DECODE_ADDRESS 0x298
+#define CPU_1_LOW_DECODE_ADDRESS 0x2c0
+#define CPU_1_HIGH_DECODE_ADDRESS 0x2c8
+
+#define PCI_0I_O_ADDRESS_REMAP 0x0f0
+#define PCI_0MEMORY0_ADDRESS_REMAP 0x0f8
+#define PCI_0MEMORY0_HIGH_ADDRESS_REMAP 0x320
+#define PCI_0MEMORY1_ADDRESS_REMAP 0x100
+#define PCI_0MEMORY1_HIGH_ADDRESS_REMAP 0x328
+#define PCI_0MEMORY2_ADDRESS_REMAP 0x2f8
+#define PCI_0MEMORY2_HIGH_ADDRESS_REMAP 0x330
+#define PCI_0MEMORY3_ADDRESS_REMAP 0x300
+#define PCI_0MEMORY3_HIGH_ADDRESS_REMAP 0x338
+
+#define PCI_1I_O_ADDRESS_REMAP 0x108
+#define PCI_1MEMORY0_ADDRESS_REMAP 0x110
+#define PCI_1MEMORY0_HIGH_ADDRESS_REMAP 0x340
+#define PCI_1MEMORY1_ADDRESS_REMAP 0x118
+#define PCI_1MEMORY1_HIGH_ADDRESS_REMAP 0x348
+#define PCI_1MEMORY2_ADDRESS_REMAP 0x310
+#define PCI_1MEMORY2_HIGH_ADDRESS_REMAP 0x350
+#define PCI_1MEMORY3_ADDRESS_REMAP 0x318
+#define PCI_1MEMORY3_HIGH_ADDRESS_REMAP 0x358
+
+
+
+
+/****************************************/
+/* CPU Sync Barrier */
+/****************************************/
+
+#define PCI_0SYNC_BARIER_VIRTUAL_REGISTER 0x0c0
+#define PCI_1SYNC_BARIER_VIRTUAL_REGISTER 0x0c8
+
+
+/****************************************/
+/* CPU Access Protect */
+/****************************************/
+
+#define CPU_LOW_PROTECT_ADDRESS_0 0x180
+#define CPU_HIGH_PROTECT_ADDRESS_0 0x188
+#define CPU_LOW_PROTECT_ADDRESS_1 0x190
+#define CPU_HIGH_PROTECT_ADDRESS_1 0x198
+#define CPU_LOW_PROTECT_ADDRESS_2 0x1a0
+#define CPU_HIGH_PROTECT_ADDRESS_2 0x1a8
+#define CPU_LOW_PROTECT_ADDRESS_3 0x1b0
+#define CPU_HIGH_PROTECT_ADDRESS_3 0x1b8
+#define CPU_LOW_PROTECT_ADDRESS_4 0x1c0
+#define CPU_HIGH_PROTECT_ADDRESS_4 0x1c8
+#define CPU_LOW_PROTECT_ADDRESS_5 0x1d0
+#define CPU_HIGH_PROTECT_ADDRESS_5 0x1d8
+#define CPU_LOW_PROTECT_ADDRESS_6 0x1e0
+#define CPU_HIGH_PROTECT_ADDRESS_6 0x1e8
+#define CPU_LOW_PROTECT_ADDRESS_7 0x1f0
+#define CPU_HIGH_PROTECT_ADDRESS_7 0x1f8
+
+
+/****************************************/
+/* Snoop Control */
+/****************************************/
+
+#define SNOOP_BASE_ADDRESS_0 0x380
+#define SNOOP_TOP_ADDRESS_0 0x388
+#define SNOOP_BASE_ADDRESS_1 0x390
+#define SNOOP_TOP_ADDRESS_1 0x398
+#define SNOOP_BASE_ADDRESS_2 0x3a0
+#define SNOOP_TOP_ADDRESS_2 0x3a8
+#define SNOOP_BASE_ADDRESS_3 0x3b0
+#define SNOOP_TOP_ADDRESS_3 0x3b8
+
+/****************************************/
+/* CPU Error Report */
+/****************************************/
+
+#define CPU_ERROR_ADDRESS_LOW 0x070
+#define CPU_ERROR_ADDRESS_HIGH 0x078
+#define CPU_ERROR_DATA_LOW 0x128
+#define CPU_ERROR_DATA_HIGH 0x130
+#define CPU_ERROR_PARITY 0x138
+#define CPU_ERROR_CAUSE 0x140
+#define CPU_ERROR_MASK 0x148
+
+/****************************************/
+/* Pslave Debug */
+/****************************************/
+
+#define X_0_ADDRESS 0x360
+#define X_0_COMMAND_ID 0x368
+#define X_1_ADDRESS 0x370
+#define X_1_COMMAND_ID 0x378
+#define WRITE_DATA_LOW 0x3c0
+#define WRITE_DATA_HIGH 0x3c8
+#define WRITE_BYTE_ENABLE 0x3e0
+#define READ_DATA_LOW 0x3d0
+#define READ_DATA_HIGH 0x3d8
+#define READ_ID 0x3e8
+
+
+/****************************************/
+/* SDRAM and Device Address Space */
+/****************************************/
+
+
+/****************************************/
+/* SDRAM Configuration */
+/****************************************/
+
+
+#define SDRAM_CONFIGURATION 0x448
+#define SDRAM_OPERATION_MODE 0x474
+#define SDRAM_ADDRESS_DECODE 0x47c
+#define SDRAM_UMA_CONTROL 0x4a4
+#define SDRAM_CROSS_BAR_CONTROL_LOW 0x4a8
+#define SDRAM_CROSS_BAR_CONTROL_HIGH 0x4ac
+#define SDRAM_CROSS_BAR_TIMEOUT 0x4b0
+#define SDRAM_TIMING 0x4b4
+
+
+/****************************************/
+/* SDRAM Parameters */
+/****************************************/
+
+#define SDRAM_BANK0PARAMETERS 0x44C
+#define SDRAM_BANK1PARAMETERS 0x450
+#define SDRAM_BANK2PARAMETERS 0x454
+#define SDRAM_BANK3PARAMETERS 0x458
+
+
+/****************************************/
+/* SDRAM Error Report */
+/****************************************/
+
+#define SDRAM_ERROR_DATA_LOW 0x484
+#define SDRAM_ERROR_DATA_HIGH 0x480
+#define SDRAM_AND_DEVICE_ERROR_ADDRESS 0x490
+#define SDRAM_RECEIVED_ECC 0x488
+#define SDRAM_CALCULATED_ECC 0x48c
+#define SDRAM_ECC_CONTROL 0x494
+#define SDRAM_ECC_ERROR_COUNTER 0x498
+
+
+/****************************************/
+/* SDunit Debug (for internal use) */
+/****************************************/
+
+#define X0_ADDRESS 0x500
+#define X0_COMMAND_AND_ID 0x504
+#define X0_WRITE_DATA_LOW 0x508
+#define X0_WRITE_DATA_HIGH 0x50c
+#define X0_WRITE_BYTE_ENABLE 0x518
+#define X0_READ_DATA_LOW 0x510
+#define X0_READ_DATA_HIGH 0x514
+#define X0_READ_ID 0x51c
+#define X1_ADDRESS 0x520
+#define X1_COMMAND_AND_ID 0x524
+#define X1_WRITE_DATA_LOW 0x528
+#define X1_WRITE_DATA_HIGH 0x52c
+#define X1_WRITE_BYTE_ENABLE 0x538
+#define X1_READ_DATA_LOW 0x530
+#define X1_READ_DATA_HIGH 0x534
+#define X1_READ_ID 0x53c
+#define X0_SNOOP_ADDRESS 0x540
+#define X0_SNOOP_COMMAND 0x544
+#define X1_SNOOP_ADDRESS 0x548
+#define X1_SNOOP_COMMAND 0x54c
+
+
+
+/****************************************/
+/* Device Parameters */
+/****************************************/
+
+#define DEVICE_BANK0PARAMETERS 0x45c
+#define DEVICE_BANK1PARAMETERS 0x460
+#define DEVICE_BANK2PARAMETERS 0x464
+#define DEVICE_BANK3PARAMETERS 0x468
+#define DEVICE_BOOT_BANK_PARAMETERS 0x46c
+#define DEVICE_CONTROL 0x4c0
+#define DEVICE_CROSS_BAR_CONTROL_LOW 0x4c8
+#define DEVICE_CROSS_BAR_CONTROL_HIGH 0x4cc
+#define DEVICE_CROSS_BAR_TIMEOUT 0x4c4
+
+
+/****************************************/
+/* Device Interrupt */
+/****************************************/
+
+#define DEVICE_INTERRUPT_CAUSE 0x4d0
+#define DEVICE_INTERRUPT_MASK 0x4d4
+#define DEVICE_ERROR_ADDRESS 0x4d8
+
+/****************************************/
+/* DMA Record */
+/****************************************/
+
+#define CHANNEL0_DMA_BYTE_COUNT 0x800
+#define CHANNEL1_DMA_BYTE_COUNT 0x804
+#define CHANNEL2_DMA_BYTE_COUNT 0x808
+#define CHANNEL3_DMA_BYTE_COUNT 0x80C
+#define CHANNEL4_DMA_BYTE_COUNT 0x900
+#define CHANNEL5_DMA_BYTE_COUNT 0x904
+#define CHANNEL6_DMA_BYTE_COUNT 0x908
+#define CHANNEL7_DMA_BYTE_COUNT 0x90C
+#define CHANNEL0_DMA_SOURCE_ADDRESS 0x810
+#define CHANNEL1_DMA_SOURCE_ADDRESS 0x814
+#define CHANNEL2_DMA_SOURCE_ADDRESS 0x818
+#define CHANNEL3_DMA_SOURCE_ADDRESS 0x81C
+#define CHANNEL4_DMA_SOURCE_ADDRESS 0x910
+#define CHANNEL5_DMA_SOURCE_ADDRESS 0x914
+#define CHANNEL6_DMA_SOURCE_ADDRESS 0x918
+#define CHANNEL7_DMA_SOURCE_ADDRESS 0x91C
+#define CHANNEL0_DMA_DESTINATION_ADDRESS 0x820
+#define CHANNEL1_DMA_DESTINATION_ADDRESS 0x824
+#define CHANNEL2_DMA_DESTINATION_ADDRESS 0x828
+#define CHANNEL3_DMA_DESTINATION_ADDRESS 0x82C
+#define CHANNEL4_DMA_DESTINATION_ADDRESS 0x920
+#define CHANNEL5_DMA_DESTINATION_ADDRESS 0x924
+#define CHANNEL6_DMA_DESTINATION_ADDRESS 0x928
+#define CHANNEL7_DMA_DESTINATION_ADDRESS 0x92C
+#define CHANNEL0NEXT_RECORD_POINTER 0x830
+#define CHANNEL1NEXT_RECORD_POINTER 0x834
+#define CHANNEL2NEXT_RECORD_POINTER 0x838
+#define CHANNEL3NEXT_RECORD_POINTER 0x83C
+#define CHANNEL4NEXT_RECORD_POINTER 0x930
+#define CHANNEL5NEXT_RECORD_POINTER 0x934
+#define CHANNEL6NEXT_RECORD_POINTER 0x938
+#define CHANNEL7NEXT_RECORD_POINTER 0x93C
+#define CHANNEL0CURRENT_DESCRIPTOR_POINTER 0x870
+#define CHANNEL1CURRENT_DESCRIPTOR_POINTER 0x874
+#define CHANNEL2CURRENT_DESCRIPTOR_POINTER 0x878
+#define CHANNEL3CURRENT_DESCRIPTOR_POINTER 0x87C
+#define CHANNEL4CURRENT_DESCRIPTOR_POINTER 0x970
+#define CHANNEL5CURRENT_DESCRIPTOR_POINTER 0x974
+#define CHANNEL6CURRENT_DESCRIPTOR_POINTER 0x978
+#define CHANNEL7CURRENT_DESCRIPTOR_POINTER 0x97C
+#define CHANNEL0_DMA_SOURCE_HIGH_PCI_ADDRESS 0x890
+#define CHANNEL1_DMA_SOURCE_HIGH_PCI_ADDRESS 0x894
+#define CHANNEL2_DMA_SOURCE_HIGH_PCI_ADDRESS 0x898
+#define CHANNEL3_DMA_SOURCE_HIGH_PCI_ADDRESS 0x89c
+#define CHANNEL4_DMA_SOURCE_HIGH_PCI_ADDRESS 0x990
+#define CHANNEL5_DMA_SOURCE_HIGH_PCI_ADDRESS 0x994
+#define CHANNEL6_DMA_SOURCE_HIGH_PCI_ADDRESS 0x998
+#define CHANNEL7_DMA_SOURCE_HIGH_PCI_ADDRESS 0x99c
+#define CHANNEL0_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a0
+#define CHANNEL1_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a4
+#define CHANNEL2_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8a8
+#define CHANNEL3_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x8ac
+#define CHANNEL4_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a0
+#define CHANNEL5_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a4
+#define CHANNEL6_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9a8
+#define CHANNEL7_DMA_DESTINATION_HIGH_PCI_ADDRESS 0x9ac
+#define CHANNEL0_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b0
+#define CHANNEL1_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b4
+#define CHANNEL2_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8b8
+#define CHANNEL3_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x8bc
+#define CHANNEL4_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b0
+#define CHANNEL5_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b4
+#define CHANNEL6_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9b8
+#define CHANNEL7_DMA_NEXT_RECORD_POINTER_HIGH_PCI_ADDRESS 0x9bc
+
+/****************************************/
+/* DMA Channel Control */
+/****************************************/
+
+#define CHANNEL0CONTROL 0x840
+#define CHANNEL0CONTROL_HIGH 0x880
+#define CHANNEL1CONTROL 0x844
+#define CHANNEL1CONTROL_HIGH 0x884
+#define CHANNEL2CONTROL 0x848
+#define CHANNEL2CONTROL_HIGH 0x888
+#define CHANNEL3CONTROL 0x84C
+#define CHANNEL3CONTROL_HIGH 0x88C
+
+#define CHANNEL4CONTROL 0x940
+#define CHANNEL4CONTROL_HIGH 0x980
+#define CHANNEL5CONTROL 0x944
+#define CHANNEL5CONTROL_HIGH 0x984
+#define CHANNEL6CONTROL 0x948
+#define CHANNEL6CONTROL_HIGH 0x988
+#define CHANNEL7CONTROL 0x94C
+#define CHANNEL7CONTROL_HIGH 0x98C
+
+
+/****************************************/
+/* DMA Arbiter */
+/****************************************/
+
+#define ARBITER_CONTROL_0_3 0x860
+#define ARBITER_CONTROL_4_7 0x960
+
+
+/****************************************/
+/* DMA Interrupt */
+/****************************************/
+
+#define CHANELS0_3_INTERRUPT_CAUSE 0x8c0
+#define CHANELS0_3_INTERRUPT_MASK 0x8c4
+#define CHANELS0_3_ERROR_ADDRESS 0x8c8
+#define CHANELS0_3_ERROR_SELECT 0x8cc
+#define CHANELS4_7_INTERRUPT_CAUSE 0x9c0
+#define CHANELS4_7_INTERRUPT_MASK 0x9c4
+#define CHANELS4_7_ERROR_ADDRESS 0x9c8
+#define CHANELS4_7_ERROR_SELECT 0x9cc
+
+
+/****************************************/
+/* DMA Debug (for internal use) */
+/****************************************/
+
+#define DMA_X0_ADDRESS 0x8e0
+#define DMA_X0_COMMAND_AND_ID 0x8e4
+#define DMA_X0_WRITE_DATA_LOW 0x8e8
+#define DMA_X0_WRITE_DATA_HIGH 0x8ec
+#define DMA_X0_WRITE_BYTE_ENABLE 0x8f8
+#define DMA_X0_READ_DATA_LOW 0x8f0
+#define DMA_X0_READ_DATA_HIGH 0x8f4
+#define DMA_X0_READ_ID 0x8fc
+#define DMA_X1_ADDRESS 0x9e0
+#define DMA_X1_COMMAND_AND_ID 0x9e4
+#define DMA_X1_WRITE_DATA_LOW 0x9e8
+#define DMA_X1_WRITE_DATA_HIGH 0x9ec
+#define DMA_X1_WRITE_BYTE_ENABLE 0x9f8
+#define DMA_X1_READ_DATA_LOW 0x9f0
+#define DMA_X1_READ_DATA_HIGH 0x9f4
+#define DMA_X1_READ_ID 0x9fc
+
+/****************************************/
+/* Timer_Counter */
+/****************************************/
+
+#define TIMER_COUNTER0 0x850
+#define TIMER_COUNTER1 0x854
+#define TIMER_COUNTER2 0x858
+#define TIMER_COUNTER3 0x85C
+#define TIMER_COUNTER_0_3_CONTROL 0x864
+#define TIMER_COUNTER_0_3_INTERRUPT_CAUSE 0x868
+#define TIMER_COUNTER_0_3_INTERRUPT_MASK 0x86c
+#define TIMER_COUNTER4 0x950
+#define TIMER_COUNTER5 0x954
+#define TIMER_COUNTER6 0x958
+#define TIMER_COUNTER7 0x95C
+#define TIMER_COUNTER_4_7_CONTROL 0x964
+#define TIMER_COUNTER_4_7_INTERRUPT_CAUSE 0x968
+#define TIMER_COUNTER_4_7_INTERRUPT_MASK 0x96c
+
+/****************************************/
+/* PCI Slave Address Decoding */
+/****************************************/
+
+#define PCI_0SCS_0_BANK_SIZE 0xc08
+#define PCI_1SCS_0_BANK_SIZE 0xc88
+#define PCI_0SCS_1_BANK_SIZE 0xd08
+#define PCI_1SCS_1_BANK_SIZE 0xd88
+#define PCI_0SCS_2_BANK_SIZE 0xc0c
+#define PCI_1SCS_2_BANK_SIZE 0xc8c
+#define PCI_0SCS_3_BANK_SIZE 0xd0c
+#define PCI_1SCS_3_BANK_SIZE 0xd8c
+#define PCI_0CS_0_BANK_SIZE 0xc10
+#define PCI_1CS_0_BANK_SIZE 0xc90
+#define PCI_0CS_1_BANK_SIZE 0xd10
+#define PCI_1CS_1_BANK_SIZE 0xd90
+#define PCI_0CS_2_BANK_SIZE 0xd18
+#define PCI_1CS_2_BANK_SIZE 0xd98
+#define PCI_0CS_3_BANK_SIZE 0xc14
+#define PCI_1CS_3_BANK_SIZE 0xc94
+#define PCI_0CS_BOOT_BANK_SIZE 0xd14
+#define PCI_1CS_BOOT_BANK_SIZE 0xd94
+#define PCI_0P2P_MEM0_BAR_SIZE 0xd1c
+#define PCI_1P2P_MEM0_BAR_SIZE 0xd9c
+#define PCI_0P2P_MEM1_BAR_SIZE 0xd20
+#define PCI_1P2P_MEM1_BAR_SIZE 0xda0
+#define PCI_0P2P_I_O_BAR_SIZE 0xd24
+#define PCI_1P2P_I_O_BAR_SIZE 0xda4
+#define PCI_0CPU_BAR_SIZE 0xd28
+#define PCI_1CPU_BAR_SIZE 0xda8
+#define PCI_0DAC_SCS_0_BANK_SIZE 0xe00
+#define PCI_1DAC_SCS_0_BANK_SIZE 0xe80
+#define PCI_0DAC_SCS_1_BANK_SIZE 0xe04
+#define PCI_1DAC_SCS_1_BANK_SIZE 0xe84
+#define PCI_0DAC_SCS_2_BANK_SIZE 0xe08
+#define PCI_1DAC_SCS_2_BANK_SIZE 0xe88
+#define PCI_0DAC_SCS_3_BANK_SIZE 0xe0c
+#define PCI_1DAC_SCS_3_BANK_SIZE 0xe8c
+#define PCI_0DAC_CS_0_BANK_SIZE 0xe10
+#define PCI_1DAC_CS_0_BANK_SIZE 0xe90
+#define PCI_0DAC_CS_1_BANK_SIZE 0xe14
+#define PCI_1DAC_CS_1_BANK_SIZE 0xe94
+#define PCI_0DAC_CS_2_BANK_SIZE 0xe18
+#define PCI_1DAC_CS_2_BANK_SIZE 0xe98
+#define PCI_0DAC_CS_3_BANK_SIZE 0xe1c
+#define PCI_1DAC_CS_3_BANK_SIZE 0xe9c
+#define PCI_0DAC_BOOTCS_BANK_SIZE 0xe20
+#define PCI_1DAC_BOOTCS_BANK_SIZE 0xea0
+#define PCI_0DAC_P2P_MEM0_BAR_SIZE 0xe24
+#define PCI_1DAC_P2P_MEM0_BAR_SIZE 0xea4
+#define PCI_0DAC_P2P_MEM1_BAR_SIZE 0xe28
+#define PCI_1DAC_P2P_MEM1_BAR_SIZE 0xea8
+#define PCI_0DAC_CPU_BAR_SIZE 0xe2c
+#define PCI_1DAC_CPU_BAR_SIZE 0xeac
+#define PCI_0EXPANSION_ROM_BAR_SIZE 0xd2c
+#define PCI_1EXPANSION_ROM_BAR_SIZE 0xdac
+#define PCI_0BASE_ADDRESS_REGISTERS_ENABLE 0xc3c
+#define PCI_1BASE_ADDRESS_REGISTERS_ENABLE 0xcbc
+#define PCI_0SCS_0_BASE_ADDRESS_REMAP 0xc48
+#define PCI_1SCS_0_BASE_ADDRESS_REMAP 0xcc8
+#define PCI_0SCS_1_BASE_ADDRESS_REMAP 0xd48
+#define PCI_1SCS_1_BASE_ADDRESS_REMAP 0xdc8
+#define PCI_0SCS_2_BASE_ADDRESS_REMAP 0xc4c
+#define PCI_1SCS_2_BASE_ADDRESS_REMAP 0xccc
+#define PCI_0SCS_3_BASE_ADDRESS_REMAP 0xd4c
+#define PCI_1SCS_3_BASE_ADDRESS_REMAP 0xdcc
+#define PCI_0CS_0_BASE_ADDRESS_REMAP 0xc50
+#define PCI_1CS_0_BASE_ADDRESS_REMAP 0xcd0
+#define PCI_0CS_1_BASE_ADDRESS_REMAP 0xd50
+#define PCI_1CS_1_BASE_ADDRESS_REMAP 0xdd0
+#define PCI_0CS_2_BASE_ADDRESS_REMAP 0xd58
+#define PCI_1CS_2_BASE_ADDRESS_REMAP 0xdd8
+#define PCI_0CS_3_BASE_ADDRESS_REMAP 0xc54
+#define PCI_1CS_3_BASE_ADDRESS_REMAP 0xcd4
+#define PCI_0CS_BOOTCS_BASE_ADDRESS_REMAP 0xd54
+#define PCI_1CS_BOOTCS_BASE_ADDRESS_REMAP 0xdd4
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xd5c
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xddc
+#define PCI_0P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xd60
+#define PCI_1P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xde0
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xd64
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xde4
+#define PCI_0P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xd68
+#define PCI_1P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xde8
+#define PCI_0P2P_I_O_BASE_ADDRESS_REMAP 0xd6c
+#define PCI_1P2P_I_O_BASE_ADDRESS_REMAP 0xdec
+#define PCI_0CPU_BASE_ADDRESS_REMAP 0xd70
+#define PCI_1CPU_BASE_ADDRESS_REMAP 0xdf0
+#define PCI_0DAC_SCS_0_BASE_ADDRESS_REMAP 0xf00
+#define PCI_1DAC_SCS_0_BASE_ADDRESS_REMAP 0xff0
+#define PCI_0DAC_SCS_1_BASE_ADDRESS_REMAP 0xf04
+#define PCI_1DAC_SCS_1_BASE_ADDRESS_REMAP 0xf84
+#define PCI_0DAC_SCS_2_BASE_ADDRESS_REMAP 0xf08
+#define PCI_1DAC_SCS_2_BASE_ADDRESS_REMAP 0xf88
+#define PCI_0DAC_SCS_3_BASE_ADDRESS_REMAP 0xf0c
+#define PCI_1DAC_SCS_3_BASE_ADDRESS_REMAP 0xf8c
+#define PCI_0DAC_CS_0_BASE_ADDRESS_REMAP 0xf10
+#define PCI_1DAC_CS_0_BASE_ADDRESS_REMAP 0xf90
+#define PCI_0DAC_CS_1_BASE_ADDRESS_REMAP 0xf14
+#define PCI_1DAC_CS_1_BASE_ADDRESS_REMAP 0xf94
+#define PCI_0DAC_CS_2_BASE_ADDRESS_REMAP 0xf18
+#define PCI_1DAC_CS_2_BASE_ADDRESS_REMAP 0xf98
+#define PCI_0DAC_CS_3_BASE_ADDRESS_REMAP 0xf1c
+#define PCI_1DAC_CS_3_BASE_ADDRESS_REMAP 0xf9c
+#define PCI_0DAC_BOOTCS_BASE_ADDRESS_REMAP 0xf20
+#define PCI_1DAC_BOOTCS_BASE_ADDRESS_REMAP 0xfa0
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xf24
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_LOW 0xfa4
+#define PCI_0DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xf28
+#define PCI_1DAC_P2P_MEM0_BASE_ADDRESS_REMAP_HIGH 0xfa8
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xf2c
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_LOW 0xfac
+#define PCI_0DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xf30
+#define PCI_1DAC_P2P_MEM1_BASE_ADDRESS_REMAP_HIGH 0xfb0
+#define PCI_0DAC_CPU_BASE_ADDRESS_REMAP 0xf34
+#define PCI_1DAC_CPU_BASE_ADDRESS_REMAP 0xfb4
+#define PCI_0EXPANSION_ROM_BASE_ADDRESS_REMAP 0xf38
+#define PCI_1EXPANSION_ROM_BASE_ADDRESS_REMAP 0xfb8
+#define PCI_0ADDRESS_DECODE_CONTROL 0xd3c
+#define PCI_1ADDRESS_DECODE_CONTROL 0xdbc
+
+/****************************************/
+/* PCI Control */
+/****************************************/
+
+#define PCI_0COMMAND 0xc00
+#define PCI_1COMMAND 0xc80
+#define PCI_0MODE 0xd00
+#define PCI_1MODE 0xd80
+#define PCI_0TIMEOUT_RETRY 0xc04
+#define PCI_1TIMEOUT_RETRY 0xc84
+#define PCI_0READ_BUFFER_DISCARD_TIMER 0xd04
+#define PCI_1READ_BUFFER_DISCARD_TIMER 0xd84
+#define MSI_0TRIGGER_TIMER 0xc38
+#define MSI_1TRIGGER_TIMER 0xcb8
+#define PCI_0ARBITER_CONTROL 0x1d00
+#define PCI_1ARBITER_CONTROL 0x1d80
+/* changing untill here */
+#define PCI_0CROSS_BAR_CONTROL_LOW 0x1d08
+#define PCI_0CROSS_BAR_CONTROL_HIGH 0x1d0c
+#define PCI_0CROSS_BAR_TIMEOUT 0x1d04
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d18
+#define PCI_0READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d1c
+#define PCI_0SYNC_BARRIER_VIRTUAL_REGISTER 0x1d10
+#define PCI_0P2P_CONFIGURATION 0x1d14
+#define PCI_0ACCESS_CONTROL_BASE_0_LOW 0x1e00
+#define PCI_0ACCESS_CONTROL_BASE_0_HIGH 0x1e04
+#define PCI_0ACCESS_CONTROL_TOP_0 0x1e08
+#define PCI_0ACCESS_CONTROL_BASE_1_LOW 0x1e10
+#define PCI_0ACCESS_CONTROL_BASE_1_HIGH 0x1e14
+#define PCI_0ACCESS_CONTROL_TOP_1 0x1e18
+#define PCI_0ACCESS_CONTROL_BASE_2_LOW 0x1e20
+#define PCI_0ACCESS_CONTROL_BASE_2_HIGH 0x1e24
+#define PCI_0ACCESS_CONTROL_TOP_2 0x1e28
+#define PCI_0ACCESS_CONTROL_BASE_3_LOW 0x1e30
+#define PCI_0ACCESS_CONTROL_BASE_3_HIGH 0x1e34
+#define PCI_0ACCESS_CONTROL_TOP_3 0x1e38
+#define PCI_0ACCESS_CONTROL_BASE_4_LOW 0x1e40
+#define PCI_0ACCESS_CONTROL_BASE_4_HIGH 0x1e44
+#define PCI_0ACCESS_CONTROL_TOP_4 0x1e48
+#define PCI_0ACCESS_CONTROL_BASE_5_LOW 0x1e50
+#define PCI_0ACCESS_CONTROL_BASE_5_HIGH 0x1e54
+#define PCI_0ACCESS_CONTROL_TOP_5 0x1e58
+#define PCI_0ACCESS_CONTROL_BASE_6_LOW 0x1e60
+#define PCI_0ACCESS_CONTROL_BASE_6_HIGH 0x1e64
+#define PCI_0ACCESS_CONTROL_TOP_6 0x1e68
+#define PCI_0ACCESS_CONTROL_BASE_7_LOW 0x1e70
+#define PCI_0ACCESS_CONTROL_BASE_7_HIGH 0x1e74
+#define PCI_0ACCESS_CONTROL_TOP_7 0x1e78
+#define PCI_1CROSS_BAR_CONTROL_LOW 0x1d88
+#define PCI_1CROSS_BAR_CONTROL_HIGH 0x1d8c
+#define PCI_1CROSS_BAR_TIMEOUT 0x1d84
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_LOW 0x1d98
+#define PCI_1READ_RESPONSE_CROSS_BAR_CONTROL_HIGH 0x1d9c
+#define PCI_1SYNC_BARRIER_VIRTUAL_REGISTER 0x1d90
+#define PCI_1P2P_CONFIGURATION 0x1d94
+#define PCI_1ACCESS_CONTROL_BASE_0_LOW 0x1e80
+#define PCI_1ACCESS_CONTROL_BASE_0_HIGH 0x1e84
+#define PCI_1ACCESS_CONTROL_TOP_0 0x1e88
+#define PCI_1ACCESS_CONTROL_BASE_1_LOW 0x1e90
+#define PCI_1ACCESS_CONTROL_BASE_1_HIGH 0x1e94
+#define PCI_1ACCESS_CONTROL_TOP_1 0x1e98
+#define PCI_1ACCESS_CONTROL_BASE_2_LOW 0x1ea0
+#define PCI_1ACCESS_CONTROL_BASE_2_HIGH 0x1ea4
+#define PCI_1ACCESS_CONTROL_TOP_2 0x1ea8
+#define PCI_1ACCESS_CONTROL_BASE_3_LOW 0x1eb0
+#define PCI_1ACCESS_CONTROL_BASE_3_HIGH 0x1eb4
+#define PCI_1ACCESS_CONTROL_TOP_3 0x1eb8
+#define PCI_1ACCESS_CONTROL_BASE_4_LOW 0x1ec0
+#define PCI_1ACCESS_CONTROL_BASE_4_HIGH 0x1ec4
+#define PCI_1ACCESS_CONTROL_TOP_4 0x1ec8
+#define PCI_1ACCESS_CONTROL_BASE_5_LOW 0x1ed0
+#define PCI_1ACCESS_CONTROL_BASE_5_HIGH 0x1ed4
+#define PCI_1ACCESS_CONTROL_TOP_5 0x1ed8
+#define PCI_1ACCESS_CONTROL_BASE_6_LOW 0x1ee0
+#define PCI_1ACCESS_CONTROL_BASE_6_HIGH 0x1ee4
+#define PCI_1ACCESS_CONTROL_TOP_6 0x1ee8
+#define PCI_1ACCESS_CONTROL_BASE_7_LOW 0x1ef0
+#define PCI_1ACCESS_CONTROL_BASE_7_HIGH 0x1ef4
+#define PCI_1ACCESS_CONTROL_TOP_7 0x1ef8
+
+/****************************************/
+/* PCI Snoop Control */
+/****************************************/
+
+#define PCI_0SNOOP_CONTROL_BASE_0_LOW 0x1f00
+#define PCI_0SNOOP_CONTROL_BASE_0_HIGH 0x1f04
+#define PCI_0SNOOP_CONTROL_TOP_0 0x1f08
+#define PCI_0SNOOP_CONTROL_BASE_1_0_LOW 0x1f10
+#define PCI_0SNOOP_CONTROL_BASE_1_0_HIGH 0x1f14
+#define PCI_0SNOOP_CONTROL_TOP_1 0x1f18
+#define PCI_0SNOOP_CONTROL_BASE_2_0_LOW 0x1f20
+#define PCI_0SNOOP_CONTROL_BASE_2_0_HIGH 0x1f24
+#define PCI_0SNOOP_CONTROL_TOP_2 0x1f28
+#define PCI_0SNOOP_CONTROL_BASE_3_0_LOW 0x1f30
+#define PCI_0SNOOP_CONTROL_BASE_3_0_HIGH 0x1f34
+#define PCI_0SNOOP_CONTROL_TOP_3 0x1f38
+#define PCI_1SNOOP_CONTROL_BASE_0_LOW 0x1f80
+#define PCI_1SNOOP_CONTROL_BASE_0_HIGH 0x1f84
+#define PCI_1SNOOP_CONTROL_TOP_0 0x1f88
+#define PCI_1SNOOP_CONTROL_BASE_1_0_LOW 0x1f90
+#define PCI_1SNOOP_CONTROL_BASE_1_0_HIGH 0x1f94
+#define PCI_1SNOOP_CONTROL_TOP_1 0x1f98
+#define PCI_1SNOOP_CONTROL_BASE_2_0_LOW 0x1fa0
+#define PCI_1SNOOP_CONTROL_BASE_2_0_HIGH 0x1fa4
+#define PCI_1SNOOP_CONTROL_TOP_2 0x1fa8
+#define PCI_1SNOOP_CONTROL_BASE_3_0_LOW 0x1fb0
+#define PCI_1SNOOP_CONTROL_BASE_3_0_HIGH 0x1fb4
+#define PCI_1SNOOP_CONTROL_TOP_3 0x1fb8
+
+/****************************************/
+/* PCI Configuration Address */
+/****************************************/
+
+#define PCI_0CONFIGURATION_ADDRESS 0xcf8
+#define PCI_0CONFIGURATION_DATA_VIRTUAL_REGISTER 0xcfc
+#define PCI_1CONFIGURATION_ADDRESS 0xc78
+#define PCI_1CONFIGURATION_DATA_VIRTUAL_REGISTER 0xc7c
+#define PCI_0INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xc34
+#define PCI_1INTERRUPT_ACKNOWLEDGE_VIRTUAL_REGISTER 0xcb4
+
+/****************************************/
+/* PCI Error Report */
+/****************************************/
+
+#define PCI_0SERR_MASK 0xc28
+#define PCI_0ERROR_ADDRESS_LOW 0x1d40
+#define PCI_0ERROR_ADDRESS_HIGH 0x1d44
+#define PCI_0ERROR_DATA_LOW 0x1d48
+#define PCI_0ERROR_DATA_HIGH 0x1d4c
+#define PCI_0ERROR_COMMAND 0x1d50
+#define PCI_0ERROR_CAUSE 0x1d58
+#define PCI_0ERROR_MASK 0x1d5c
+#define PCI_1SERR_MASK 0xca8
+#define PCI_1ERROR_ADDRESS_LOW 0x1dc0
+#define PCI_1ERROR_ADDRESS_HIGH 0x1dc4
+#define PCI_1ERROR_DATA_LOW 0x1dc8
+#define PCI_1ERROR_DATA_HIGH 0x1dcc
+#define PCI_1ERROR_COMMAND 0x1dd0
+#define PCI_1ERROR_CAUSE 0x1dd8
+#define PCI_1ERROR_MASK 0x1ddc
+
+
+/****************************************/
+/* Lslave Debug (for internal use) */
+/****************************************/
+
+#define L_SLAVE_X0_ADDRESS 0x1d20
+#define L_SLAVE_X0_COMMAND_AND_ID 0x1d24
+#define L_SLAVE_X1_ADDRESS 0x1d28
+#define L_SLAVE_X1_COMMAND_AND_ID 0x1d2c
+#define L_SLAVE_WRITE_DATA_LOW 0x1d30
+#define L_SLAVE_WRITE_DATA_HIGH 0x1d34
+#define L_SLAVE_WRITE_BYTE_ENABLE 0x1d60
+#define L_SLAVE_READ_DATA_LOW 0x1d38
+#define L_SLAVE_READ_DATA_HIGH 0x1d3c
+#define L_SLAVE_READ_ID 0x1d64
+
+/****************************************/
+/* PCI Configuration Function 0 */
+/****************************************/
+
+#define PCI_DEVICE_AND_VENDOR_ID 0x000
+#define PCI_STATUS_AND_COMMAND 0x004
+#define PCI_CLASS_CODE_AND_REVISION_ID 0x008
+#define PCI_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE 0x00C
+#define PCI_SCS_0_BASE_ADDRESS 0x010
+#define PCI_SCS_1_BASE_ADDRESS 0x014
+#define PCI_SCS_2_BASE_ADDRESS 0x018
+#define PCI_SCS_3_BASE_ADDRESS 0x01C
+#define PCI_INTERNAL_REGISTERS_MEMORY_MAPPED_BASE_ADDRESS 0x020
+#define PCI_INTERNAL_REGISTERS_I_OMAPPED_BASE_ADDRESS 0x024
+#define PCI_SUBSYSTEM_ID_AND_SUBSYSTEM_VENDOR_ID 0x02C
+#define PCI_EXPANSION_ROM_BASE_ADDRESS_REGISTER 0x030
+#define PCI_CAPABILTY_LIST_POINTER 0x034
+#define PCI_INTERRUPT_PIN_AND_LINE 0x03C
+#define PCI_POWER_MANAGEMENT_CAPABILITY 0x040
+#define PCI_POWER_MANAGEMENT_STATUS_AND_CONTROL 0x044
+#define PCI_VPD_ADDRESS 0x048
+#define PCI_VPD_DATA 0x04c
+#define PCI_MSI_MESSAGE_CONTROL 0x050
+#define PCI_MSI_MESSAGE_ADDRESS 0x054
+#define PCI_MSI_MESSAGE_UPPER_ADDRESS 0x058
+#define PCI_MSI_MESSAGE_DATA 0x05c
+#define PCI_COMPACT_PCI_HOT_SWAP_CAPABILITY 0x058
+
+/****************************************/
+/* PCI Configuration Function 1 */
+/****************************************/
+
+#define PCI_CS_0_BASE_ADDRESS 0x110
+#define PCI_CS_1_BASE_ADDRESS 0x114
+#define PCI_CS_2_BASE_ADDRESS 0x118
+#define PCI_CS_3_BASE_ADDRESS 0x11c
+#define PCI_BOOTCS_BASE_ADDRESS 0x120
+
+/****************************************/
+/* PCI Configuration Function 2 */
+/****************************************/
+
+#define PCI_P2P_MEM0_BASE_ADDRESS 0x210
+#define PCI_P2P_MEM1_BASE_ADDRESS 0x214
+#define PCI_P2P_I_O_BASE_ADDRESS 0x218
+#define PCI_CPU_BASE_ADDRESS 0x21c
+
+/****************************************/
+/* PCI Configuration Function 4 */
+/****************************************/
+
+#define PCI_DAC_SCS_0_BASE_ADDRESS_LOW 0x410
+#define PCI_DAC_SCS_0_BASE_ADDRESS_HIGH 0x414
+#define PCI_DAC_SCS_1_BASE_ADDRESS_LOW 0x418
+#define PCI_DAC_SCS_1_BASE_ADDRESS_HIGH 0x41c
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_LOW 0x420
+#define PCI_DAC_P2P_MEM0_BASE_ADDRESS_HIGH 0x424
+
+
+/****************************************/
+/* PCI Configuration Function 5 */
+/****************************************/
+
+#define PCI_DAC_SCS_2_BASE_ADDRESS_LOW 0x510
+#define PCI_DAC_SCS_2_BASE_ADDRESS_HIGH 0x514
+#define PCI_DAC_SCS_3_BASE_ADDRESS_LOW 0x518
+#define PCI_DAC_SCS_3_BASE_ADDRESS_HIGH 0x51c
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_LOW 0x520
+#define PCI_DAC_P2P_MEM1_BASE_ADDRESS_HIGH 0x524
+
+
+/****************************************/
+/* PCI Configuration Function 6 */
+/****************************************/
+
+#define PCI_DAC_CS_0_BASE_ADDRESS_LOW 0x610
+#define PCI_DAC_CS_0_BASE_ADDRESS_HIGH 0x614
+#define PCI_DAC_CS_1_BASE_ADDRESS_LOW 0x618
+#define PCI_DAC_CS_1_BASE_ADDRESS_HIGH 0x61c
+#define PCI_DAC_CS_2_BASE_ADDRESS_LOW 0x620
+#define PCI_DAC_CS_2_BASE_ADDRESS_HIGH 0x624
+
+/****************************************/
+/* PCI Configuration Function 7 */
+/****************************************/
+
+#define PCI_DAC_CS_3_BASE_ADDRESS_LOW 0x710
+#define PCI_DAC_CS_3_BASE_ADDRESS_HIGH 0x714
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_LOW 0x718
+#define PCI_DAC_BOOTCS_BASE_ADDRESS_HIGH 0x71c
+#define PCI_DAC_CPU_BASE_ADDRESS_LOW 0x720
+#define PCI_DAC_CPU_BASE_ADDRESS_HIGH 0x724
+
+/****************************************/
+/* Interrupts */
+/****************************************/
+
+#define LOW_INTERRUPT_CAUSE_REGISTER 0xc18
+#define HIGH_INTERRUPT_CAUSE_REGISTER 0xc68
+#define CPU_INTERRUPT_MASK_REGISTER_LOW 0xc1c
+#define CPU_INTERRUPT_MASK_REGISTER_HIGH 0xc6c
+#define CPU_SELECT_CAUSE_REGISTER 0xc70
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xc24
+#define PCI_0INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xc64
+#define PCI_0SELECT_CAUSE 0xc74
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_LOW 0xca4
+#define PCI_1INTERRUPT_CAUSE_MASK_REGISTER_HIGH 0xce4
+#define PCI_1SELECT_CAUSE 0xcf4
+#define CPU_INT_0_MASK 0xe60
+#define CPU_INT_1_MASK 0xe64
+#define CPU_INT_2_MASK 0xe68
+#define CPU_INT_3_MASK 0xe6c
+
+/****************************************/
+/* I20 Support registers */
+/****************************************/
+
+#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x010
+#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x014
+#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE 0x018
+#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE 0x01C
+#define INBOUND_DOORBELL_REGISTER_PCI_SIDE 0x020
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x024
+#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x028
+#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE 0x02C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE 0x030
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE 0x034
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x040
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE 0x044
+#define QUEUE_CONTROL_REGISTER_PCI_SIDE 0x050
+#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE 0x054
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x060
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x064
+#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x068
+#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x06C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE 0x070
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE 0x074
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE 0x078
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE 0x07C
+
+#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C10
+#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C14
+#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE 0x1C18
+#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE 0x1C1C
+#define INBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C20
+#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C24
+#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C28
+#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE 0x1C2C
+#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE 0x1C30
+#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE 0x1C34
+#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C40
+#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE 0x1C44
+#define QUEUE_CONTROL_REGISTER_CPU_SIDE 0x1C50
+#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE 0x1C54
+#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C60
+#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C64
+#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C68
+#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C6C
+#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C70
+#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C74
+#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE 0x1C78
+#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE 0x1C7C
+
+/****************************************/
+/* Communication Unit Registers */
+/****************************************/
+
+#define ETHERNET_0_ADDRESS_CONTROL_LOW 0xf200
+#define ETHERNET_0_ADDRESS_CONTROL_HIGH 0xf204
+#define ETHERNET_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf208
+#define ETHERNET_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf20c
+#define ETHERNET_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf210
+#define ETHERNET_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf214
+#define ETHERNET_0_HASH_TABLE_PCI_HIGH_ADDRESS 0xf218
+#define ETHERNET_1_ADDRESS_CONTROL_LOW 0xf220
+#define ETHERNET_1_ADDRESS_CONTROL_HIGH 0xf224
+#define ETHERNET_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf228
+#define ETHERNET_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf22c
+#define ETHERNET_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf230
+#define ETHERNET_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf234
+#define ETHERNET_1_HASH_TABLE_PCI_HIGH_ADDRESS 0xf238
+#define ETHERNET_2_ADDRESS_CONTROL_LOW 0xf240
+#define ETHERNET_2_ADDRESS_CONTROL_HIGH 0xf244
+#define ETHERNET_2_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf248
+#define ETHERNET_2_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf24c
+#define ETHERNET_2_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf250
+#define ETHERNET_2_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf254
+#define ETHERNET_2_HASH_TABLE_PCI_HIGH_ADDRESS 0xf258
+#define MPSC_0_ADDRESS_CONTROL_LOW 0xf280
+#define MPSC_0_ADDRESS_CONTROL_HIGH 0xf284
+#define MPSC_0_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf288
+#define MPSC_0_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf28c
+#define MPSC_0_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf290
+#define MPSC_0_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf294
+#define MPSC_1_ADDRESS_CONTROL_LOW 0xf2c0
+#define MPSC_1_ADDRESS_CONTROL_HIGH 0xf2c4
+#define MPSC_1_RECEIVE_BUFFER_PCI_HIGH_ADDRESS 0xf2c8
+#define MPSC_1_TRANSMIT_BUFFER_PCI_HIGH_ADDRESS 0xf2cc
+#define MPSC_1_RECEIVE_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d0
+#define MPSC_1_TRANSMIT_DESCRIPTOR_PCI_HIGH_ADDRESS 0xf2d4
+#define SERIAL_INIT_PCI_HIGH_ADDRESS 0xf320
+#define SERIAL_INIT_LAST_DATA 0xf324
+#define SERIAL_INIT_STATUS_AND_CONTROL 0xf328
+#define COMM_UNIT_ARBITER_CONTROL 0xf300
+#define COMM_UNIT_CROSS_BAR_TIMEOUT 0xf304
+#define COMM_UNIT_INTERRUPT_CAUSE 0xf310
+#define COMM_UNIT_INTERRUPT_MASK 0xf314
+#define COMM_UNIT_ERROR_ADDRESS 0xf314
+
+/****************************************/
+/* Cunit Debug (for internal use) */
+/****************************************/
+
+#define CUNIT_ADDRESS 0xf340
+#define CUNIT_COMMAND_AND_ID 0xf344
+#define CUNIT_WRITE_DATA_LOW 0xf348
+#define CUNIT_WRITE_DATA_HIGH 0xf34c
+#define CUNIT_WRITE_BYTE_ENABLE 0xf358
+#define CUNIT_READ_DATA_LOW 0xf350
+#define CUNIT_READ_DATA_HIGH 0xf354
+#define CUNIT_READ_ID 0xf35c
+
+/****************************************/
+/* Fast Ethernet Unit Registers */
+/****************************************/
+
+/* Ethernet */
+
+#define ETHERNET_PHY_ADDRESS_REGISTER 0x2000
+#define ETHERNET_SMI_REGISTER 0x2010
+
+/* Ethernet 0 */
+
+#define ETHERNET0_PORT_CONFIGURATION_REGISTER 0x2400
+#define ETHERNET0_PORT_CONFIGURATION_EXTEND_REGISTER 0x2408
+#define ETHERNET0_PORT_COMMAND_REGISTER 0x2410
+#define ETHERNET0_PORT_STATUS_REGISTER 0x2418
+#define ETHERNET0_SERIAL_PARAMETRS_REGISTER 0x2420
+#define ETHERNET0_HASH_TABLE_POINTER_REGISTER 0x2428
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2430
+#define ETHERNET0_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2438
+#define ETHERNET0_SDMA_CONFIGURATION_REGISTER 0x2440
+#define ETHERNET0_SDMA_COMMAND_REGISTER 0x2448
+#define ETHERNET0_INTERRUPT_CAUSE_REGISTER 0x2450
+#define ETHERNET0_INTERRUPT_MASK_REGISTER 0x2458
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER0 0x2480
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER1 0x2484
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER2 0x2488
+#define ETHERNET0_FIRST_RX_DESCRIPTOR_POINTER3 0x248c
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER0 0x24a0
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER1 0x24a4
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER2 0x24a8
+#define ETHERNET0_CURRENT_RX_DESCRIPTOR_POINTER3 0x24ac
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER0 0x24e0
+#define ETHERNET0_CURRENT_TX_DESCRIPTOR_POINTER1 0x24e4
+#define ETHERNET0_MIB_COUNTER_BASE 0x2500
+
+/* Ethernet 1 */
+
+#define ETHERNET1_PORT_CONFIGURATION_REGISTER 0x2800
+#define ETHERNET1_PORT_CONFIGURATION_EXTEND_REGISTER 0x2808
+#define ETHERNET1_PORT_COMMAND_REGISTER 0x2810
+#define ETHERNET1_PORT_STATUS_REGISTER 0x2818
+#define ETHERNET1_SERIAL_PARAMETRS_REGISTER 0x2820
+#define ETHERNET1_HASH_TABLE_POINTER_REGISTER 0x2828
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2830
+#define ETHERNET1_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2838
+#define ETHERNET1_SDMA_CONFIGURATION_REGISTER 0x2840
+#define ETHERNET1_SDMA_COMMAND_REGISTER 0x2848
+#define ETHERNET1_INTERRUPT_CAUSE_REGISTER 0x2850
+#define ETHERNET1_INTERRUPT_MASK_REGISTER 0x2858
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER0 0x2880
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER1 0x2884
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER2 0x2888
+#define ETHERNET1_FIRST_RX_DESCRIPTOR_POINTER3 0x288c
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER0 0x28a0
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER1 0x28a4
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER2 0x28a8
+#define ETHERNET1_CURRENT_RX_DESCRIPTOR_POINTER3 0x28ac
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER0 0x28e0
+#define ETHERNET1_CURRENT_TX_DESCRIPTOR_POINTER1 0x28e4
+#define ETHERNET1_MIB_COUNTER_BASE 0x2900
+
+/* Ethernet 2 */
+
+#define ETHERNET2_PORT_CONFIGURATION_REGISTER 0x2c00
+#define ETHERNET2_PORT_CONFIGURATION_EXTEND_REGISTER 0x2c08
+#define ETHERNET2_PORT_COMMAND_REGISTER 0x2c10
+#define ETHERNET2_PORT_STATUS_REGISTER 0x2c18
+#define ETHERNET2_SERIAL_PARAMETRS_REGISTER 0x2c20
+#define ETHERNET2_HASH_TABLE_POINTER_REGISTER 0x2c28
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_LOW 0x2c30
+#define ETHERNET2_FLOW_CONTROL_SOURCE_ADDRESS_HIGH 0x2c38
+#define ETHERNET2_SDMA_CONFIGURATION_REGISTER 0x2c40
+#define ETHERNET2_SDMA_COMMAND_REGISTER 0x2c48
+#define ETHERNET2_INTERRUPT_CAUSE_REGISTER 0x2c50
+#define ETHERNET2_INTERRUPT_MASK_REGISTER 0x2c58
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER0 0x2c80
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER1 0x2c84
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER2 0x2c88
+#define ETHERNET2_FIRST_RX_DESCRIPTOR_POINTER3 0x2c8c
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER0 0x2ca0
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER1 0x2ca4
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER2 0x2ca8
+#define ETHERNET2_CURRENT_RX_DESCRIPTOR_POINTER3 0x2cac
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER0 0x2ce0
+#define ETHERNET2_CURRENT_TX_DESCRIPTOR_POINTER1 0x2ce4
+#define ETHERNET2_MIB_COUNTER_BASE 0x2d00
+
+/****************************************/
+/* SDMA Registers */
+/****************************************/
+
+#define SDMA_GROUP_CONFIGURATION_REGISTER 0xb1f0
+#define CHANNEL0_CONFIGURATION_REGISTER 0x4000
+#define CHANNEL0_COMMAND_REGISTER 0x4008
+#define CHANNEL0_RX_CMD_STATUS 0x4800
+#define CHANNEL0_RX_PACKET_AND_BUFFER_SIZES 0x4804
+#define CHANNEL0_RX_BUFFER_POINTER 0x4808
+#define CHANNEL0_RX_NEXT_POINTER 0x480c
+#define CHANNEL0_CURRENT_RX_DESCRIPTOR_POINTER 0x4810
+#define CHANNEL0_TX_CMD_STATUS 0x4C00
+#define CHANNEL0_TX_PACKET_SIZE 0x4C04
+#define CHANNEL0_TX_BUFFER_POINTER 0x4C08
+#define CHANNEL0_TX_NEXT_POINTER 0x4C0c
+#define CHANNEL0_CURRENT_TX_DESCRIPTOR_POINTER 0x4c10
+#define CHANNEL0_FIRST_TX_DESCRIPTOR_POINTER 0x4c14
+#define CHANNEL1_CONFIGURATION_REGISTER 0x5000
+#define CHANNEL1_COMMAND_REGISTER 0x5008
+#define CHANNEL1_RX_CMD_STATUS 0x5800
+#define CHANNEL1_RX_PACKET_AND_BUFFER_SIZES 0x5804
+#define CHANNEL1_RX_BUFFER_POINTER 0x5808
+#define CHANNEL1_RX_NEXT_POINTER 0x580c
+#define CHANNEL1_TX_CMD_STATUS 0x5C00
+#define CHANNEL1_TX_PACKET_SIZE 0x5C04
+#define CHANNEL1_TX_BUFFER_POINTER 0x5C08
+#define CHANNEL1_TX_NEXT_POINTER 0x5C0c
+#define CHANNEL1_CURRENT_RX_DESCRIPTOR_POINTER 0x5810
+#define CHANNEL1_CURRENT_TX_DESCRIPTOR_POINTER 0x5c10
+#define CHANNEL1_FIRST_TX_DESCRIPTOR_POINTER 0x5c14
+#define CHANNEL2_CONFIGURATION_REGISTER 0x6000
+#define CHANNEL2_COMMAND_REGISTER 0x6008
+#define CHANNEL2_RX_CMD_STATUS 0x6800
+#define CHANNEL2_RX_PACKET_AND_BUFFER_SIZES 0x6804
+#define CHANNEL2_RX_BUFFER_POINTER 0x6808
+#define CHANNEL2_RX_NEXT_POINTER 0x680c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
+#define CHANNEL2_TX_CMD_STATUS 0x6C00
+#define CHANNEL2_TX_PACKET_SIZE 0x6C04
+#define CHANNEL2_TX_BUFFER_POINTER 0x6C08
+#define CHANNEL2_TX_NEXT_POINTER 0x6C0c
+#define CHANNEL2_CURRENT_RX_DESCRIPTOR_POINTER 0x6810
+#define CHANNEL2_CURRENT_TX_DESCRIPTOR_POINTER 0x6c10
+#define CHANNEL2_FIRST_TX_DESCRIPTOR_POINTER 0x6c14
+
+/* SDMA Interrupt */
+
+#define SDMA_CAUSE 0xb820
+#define SDMA_MASK 0xb8a0
+
+
+/****************************************/
+/* Baude Rate Generators Registers */
+/****************************************/
+
+/* BRG 0 */
+
+#define BRG0_CONFIGURATION_REGISTER 0xb200
+#define BRG0_BAUDE_TUNING_REGISTER 0xb204
+
+/* BRG 1 */
+
+#define BRG1_CONFIGURATION_REGISTER 0xb208
+#define BRG1_BAUDE_TUNING_REGISTER 0xb20c
+
+/* BRG 2 */
+
+#define BRG2_CONFIGURATION_REGISTER 0xb210
+#define BRG2_BAUDE_TUNING_REGISTER 0xb214
+
+/* BRG Interrupts */
+
+#define BRG_CAUSE_REGISTER 0xb834
+#define BRG_MASK_REGISTER 0xb8b4
+
+/* MISC */
+
+#define MAIN_ROUTING_REGISTER 0xb400
+#define RECEIVE_CLOCK_ROUTING_REGISTER 0xb404
+#define TRANSMIT_CLOCK_ROUTING_REGISTER 0xb408
+#define COMM_UNIT_ARBITER_CONFIGURATION_REGISTER 0xb40c
+#define WATCHDOG_CONFIGURATION_REGISTER 0xb410
+#define WATCHDOG_VALUE_REGISTER 0xb414
+
+
+/****************************************/
+/* Flex TDM Registers */
+/****************************************/
+
+/* FTDM Port */
+
+#define FLEXTDM_TRANSMIT_READ_POINTER 0xa800
+#define FLEXTDM_RECEIVE_READ_POINTER 0xa804
+#define FLEXTDM_CONFIGURATION_REGISTER 0xa808
+#define FLEXTDM_AUX_CHANNELA_TX_REGISTER 0xa80c
+#define FLEXTDM_AUX_CHANNELA_RX_REGISTER 0xa810
+#define FLEXTDM_AUX_CHANNELB_TX_REGISTER 0xa814
+#define FLEXTDM_AUX_CHANNELB_RX_REGISTER 0xa818
+
+/* FTDM Interrupts */
+
+#define FTDM_CAUSE_REGISTER 0xb830
+#define FTDM_MASK_REGISTER 0xb8b0
+
+
+/****************************************/
+/* GPP Interface Registers */
+/****************************************/
+
+#define GPP_IO_CONTROL 0xf100
+#define GPP_LEVEL_CONTROL 0xf110
+#define GPP_VALUE 0xf104
+#define GPP_INTERRUPT_CAUSE 0xf108
+#define GPP_INTERRUPT_MASK 0xf10c
+
+#define MPP_CONTROL0 0xf000
+#define MPP_CONTROL1 0xf004
+#define MPP_CONTROL2 0xf008
+#define MPP_CONTROL3 0xf00c
+#define DEBUG_PORT_MULTIPLEX 0xf014
+#define SERIAL_PORT_MULTIPLEX 0xf010
+
+/****************************************/
+/* I2C Registers */
+/****************************************/
+
+#define I2C_SLAVE_ADDRESS 0xc000
+#define I2C_EXTENDED_SLAVE_ADDRESS 0xc040
+#define I2C_DATA 0xc004
+#define I2C_CONTROL 0xc008
+#define I2C_STATUS_BAUDE_RATE 0xc00C
+#define I2C_SOFT_RESET 0xc01c
+
+/****************************************/
+/* MPSC Registers */
+/****************************************/
+
+/* MPSC0 */
+
+#define MPSC0_MAIN_CONFIGURATION_LOW 0x8000
+#define MPSC0_MAIN_CONFIGURATION_HIGH 0x8004
+#define MPSC0_PROTOCOL_CONFIGURATION 0x8008
+#define CHANNEL0_REGISTER1 0x800c
+#define CHANNEL0_REGISTER2 0x8010
+#define CHANNEL0_REGISTER3 0x8014
+#define CHANNEL0_REGISTER4 0x8018
+#define CHANNEL0_REGISTER5 0x801c
+#define CHANNEL0_REGISTER6 0x8020
+#define CHANNEL0_REGISTER7 0x8024
+#define CHANNEL0_REGISTER8 0x8028
+#define CHANNEL0_REGISTER9 0x802c
+#define CHANNEL0_REGISTER10 0x8030
+#define CHANNEL0_REGISTER11 0x8034
+
+/* MPSC1 */
+
+#define MPSC1_MAIN_CONFIGURATION_LOW 0x8840
+#define MPSC1_MAIN_CONFIGURATION_HIGH 0x8844
+#define MPSC1_PROTOCOL_CONFIGURATION 0x8848
+#define CHANNEL1_REGISTER1 0x884c
+#define CHANNEL1_REGISTER2 0x8850
+#define CHANNEL1_REGISTER3 0x8854
+#define CHANNEL1_REGISTER4 0x8858
+#define CHANNEL1_REGISTER5 0x885c
+#define CHANNEL1_REGISTER6 0x8860
+#define CHANNEL1_REGISTER7 0x8864
+#define CHANNEL1_REGISTER8 0x8868
+#define CHANNEL1_REGISTER9 0x886c
+#define CHANNEL1_REGISTER10 0x8870
+#define CHANNEL1_REGISTER11 0x8874
+
+/* MPSC2 */
+
+#define MPSC2_MAIN_CONFIGURATION_LOW 0x9040
+#define MPSC2_MAIN_CONFIGURATION_HIGH 0x9044
+#define MPSC2_PROTOCOL_CONFIGURATION 0x9048
+#define CHANNEL2_REGISTER1 0x904c
+#define CHANNEL2_REGISTER2 0x9050
+#define CHANNEL2_REGISTER3 0x9054
+#define CHANNEL2_REGISTER4 0x9058
+#define CHANNEL2_REGISTER5 0x905c
+#define CHANNEL2_REGISTER6 0x9060
+#define CHANNEL2_REGISTER7 0x9064
+#define CHANNEL2_REGISTER8 0x9068
+#define CHANNEL2_REGISTER9 0x906c
+#define CHANNEL2_REGISTER10 0x9070
+#define CHANNEL2_REGISTER11 0x9074
+
+/* MPSCs Interupts */
+
+#define MPSC0_CAUSE 0xb824
+#define MPSC0_MASK 0xb8a4
+#define MPSC1_CAUSE 0xb828
+#define MPSC1_MASK 0xb8a8
+#define MPSC2_CAUSE 0xb82c
+#define MPSC2_MASK 0xb8ac
+
+#endif /* __INCgt64260rh */
diff --git a/include/galileo/memory.h b/include/galileo/memory.h
new file mode 100644
index 0000000..99bd79b
--- /dev/null
+++ b/include/galileo/memory.h
@@ -0,0 +1,86 @@
+/* Memory.h - Memory mappings and remapping functions declarations */
+
+/* Copyright - Galileo technology. */
+
+#ifndef __INCmemoryh
+#define __INCmemoryh
+
+/* includes */
+
+#include "core.h"
+
+/* defines */
+
+#define DONT_MODIFY 0xffffffff
+#define PARITY_SUPPORT 0x40000000
+
+#define _8BIT 0x00000000
+#define _16BIT 0x00100000
+#define _32BIT 0x00200000
+#define _64BIT 0x00300000
+
+/* typedefs */
+
+ typedef struct deviceParam
+{ /* boundary values */
+ unsigned int turnOff; /* 0x0 - 0xf */
+ unsigned int acc2First; /* 0x0 - 0x1f */
+ unsigned int acc2Next; /* 0x0 - 0x1f */
+ unsigned int ale2Wr; /* 0x0 - 0xf */
+ unsigned int wrLow; /* 0x0 - 0xf */
+ unsigned int wrHigh; /* 0x0 - 0xf */
+ unsigned int deviceWidth; /* in Bytes */
+} DEVICE_PARAM;
+
+typedef enum __memBank{BANK0,BANK1,BANK2,BANK3} MEMORY_BANK;
+typedef enum __memDevice{DEVICE0,DEVICE1,DEVICE2,DEVICE3,BOOT_DEVICE} DEVICE;
+
+typedef enum __memoryProtectRegion{MEM_REGION0,MEM_REGION1,MEM_REGION2, \
+ MEM_REGION3,MEM_REGION4,MEM_REGION5, \
+ MEM_REGION6,MEM_REGION7} \
+ MEMORY_PROTECT_REGION;
+typedef enum __memoryAccess{MEM_ACCESS_ALLOWED,MEM_ACCESS_FORBIDEN} \
+ MEMORY_ACCESS;
+typedef enum __memoryWrite{MEM_WRITE_ALLOWED,MEM_WRITE_FORBIDEN} \
+ MEMORY_ACCESS_WRITE;
+typedef enum __memoryCacheProtect{MEM_CACHE_ALLOWED,MEM_CACHE_FORBIDEN} \
+ MEMORY_CACHE_PROTECT;
+typedef enum __memorySnoopType{MEM_NO_SNOOP,MEM_SNOOP_WT,MEM_SNOOP_WB} \
+ MEMORY_SNOOP_TYPE;
+typedef enum __memorySnoopRegion{MEM_SNOOP_REGION0,MEM_SNOOP_REGION1, \
+ MEM_SNOOP_REGION2,MEM_SNOOP_REGION3} \
+ MEMORY_SNOOP_REGION;
+
+/* functions */
+unsigned int memoryGetBankBaseAddress(MEMORY_BANK bank);
+unsigned int memoryGetDeviceBaseAddress(DEVICE device);
+unsigned int memoryGetBankSize(MEMORY_BANK bank);
+unsigned int memoryGetDeviceSize(DEVICE device);
+unsigned int memoryGetDeviceWidth(DEVICE device);
+
+/* when given base Address and size Set new WINDOW for SCS_X. (X = 0,1,2 or 3*/
+bool memoryMapBank(MEMORY_BANK bank, unsigned int bankBase,unsigned int bankLength);
+bool memoryMapDeviceSpace(DEVICE device, unsigned int deviceBase,unsigned int deviceLength);
+
+/* Change the Internal Register Base Address to a new given Address. */
+bool memoryMapInternalRegistersSpace(unsigned int internalRegBase);
+/* returns internal Register Space Base Address. */
+unsigned int memoryGetInternalRegistersSpace(void);
+/* Configurate the protection feature to a given space. */
+bool memorySetProtectRegion(MEMORY_PROTECT_REGION region,
+ MEMORY_ACCESS memoryAccess,
+ MEMORY_ACCESS_WRITE memoryWrite,
+ MEMORY_CACHE_PROTECT cacheProtection,
+ unsigned int baseAddress,
+ unsigned int regionLength);
+/* Configurate the snoop feature to a given space. */
+bool memorySetRegionSnoopMode(MEMORY_SNOOP_REGION region,
+ MEMORY_SNOOP_TYPE snoopType,
+ unsigned int baseAddress,
+ unsigned int regionLength);
+
+bool memoryRemapAddress(unsigned int remapReg, unsigned int remapValue);
+bool memoryGetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+bool memorySetDeviceParam(DEVICE_PARAM *deviceParam, DEVICE deviceNum);
+#endif /* __INCmemoryh */
+
diff --git a/include/jffs2/compr_rubin.h b/include/jffs2/compr_rubin.h
new file mode 100644
index 0000000..f26f476
--- /dev/null
+++ b/include/jffs2/compr_rubin.h
@@ -0,0 +1,11 @@
+/* Rubin encoder/decoder header */
+/* work started at : aug 3, 1994 */
+/* last modification : aug 15, 1994 */
+/* $Id: compr_rubin.h,v 1.1 2002/01/16 23:34:32 nyet Exp $ */
+
+#define RUBIN_REG_SIZE 16
+#define UPPER_BIT_RUBIN (((long) 1)<<(RUBIN_REG_SIZE-1))
+#define LOWER_BITS_RUBIN ((((long) 1)<<(RUBIN_REG_SIZE-1))-1)
+
+void dynrubin_decompress(unsigned char *data_in, unsigned char *cpage_out,
+ unsigned long sourcelen, unsigned long dstlen);
diff --git a/include/jffs2/mini_inflate.h b/include/jffs2/mini_inflate.h
new file mode 100644
index 0000000..f79aac7
--- /dev/null
+++ b/include/jffs2/mini_inflate.h
@@ -0,0 +1,82 @@
+/*-------------------------------------------------------------------------
+ * Filename: mini_inflate.h
+ * Version: $Id: mini_inflate.h,v 1.2 2002/01/17 00:53:20 nyet Exp $
+ * Copyright: Copyright (C) 2001, Russ Dill
+ * Author: Russ Dill <Russ.Dill@asu.edu>
+ * Description: Mini deflate implementation
+ *-----------------------------------------------------------------------*/
+/*
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+typedef __SIZE_TYPE__ size;
+
+#define NO_ERROR 0
+#define COMP_UNKNOWN 1 /* The specififed bytype is invalid */
+#define CODE_NOT_FOUND 2 /* a huffman code in the stream could not be decoded */
+#define TOO_MANY_BITS 3 /* pull_bits was passed an argument that is too
+ * large */
+
+/* This struct represents an entire huffman code set. It has various lookup
+ * tables to speed decoding */
+struct huffman_set {
+ int bits; /* maximum bit length */
+ int num_symbols; /* Number of symbols this code can represent */
+ int *lengths; /* The bit length of symbols */
+ int *symbols; /* All of the symbols, sorted by the huffman code */
+ int *count; /* the number of codes of this bit length */
+ int *first; /* the first code of this bit length */
+ int *pos; /* the symbol that first represents (in the symbols
+ * array) */
+};
+
+struct bitstream {
+ unsigned char *data; /* increments as we move from byte to byte */
+ unsigned char bit; /* 0 to 7 */
+ void *(*memcpy)(void *, const void *, size);
+ unsigned long decoded; /* The number of bytes decoded */
+ int error;
+
+ int distance_count[16];
+ int distance_first[16];
+ int distance_pos[16];
+ int distance_lengths[32];
+ int distance_symbols[32];
+
+ int code_count[8];
+ int code_first[8];
+ int code_pos[8];
+ int code_lengths[19];
+ int code_symbols[19];
+
+ int length_count[16];
+ int length_first[16];
+ int length_pos[16];
+ int length_lengths[288];
+ int length_symbols[288];
+
+ struct huffman_set codes;
+ struct huffman_set lengths;
+ struct huffman_set distance;
+};
+
+#define NO_COMP 0
+#define FIXED_COMP 1
+#define DYNAMIC_COMP 2
+
+long decompress_block(unsigned char *dest, unsigned char *source,
+ void *(*inflate_memcpy)(void *dest, const void *src, size n));
diff --git a/include/linux/mtd/doc2000.h b/include/linux/mtd/doc2000.h
new file mode 100644
index 0000000..c703f77
--- /dev/null
+++ b/include/linux/mtd/doc2000.h
@@ -0,0 +1,158 @@
+
+/* Linux driver for Disk-On-Chip 2000 */
+/* (c) 1999 Machine Vision Holdings, Inc. */
+/* Author: David Woodhouse <dwmw2@mvhi.com> */
+/* $Id: doc2000.h,v 1.15 2001/09/19 00:22:15 dwmw2 Exp $ */
+
+#ifndef __MTD_DOC2000_H__
+#define __MTD_DOC2000_H__
+
+struct DiskOnChip;
+
+#include <linux/mtd/nftl.h>
+
+#define DoC_Sig1 0
+#define DoC_Sig2 1
+
+#define DoC_ChipID 0x1000
+#define DoC_DOCStatus 0x1001
+#define DoC_DOCControl 0x1002
+#define DoC_FloorSelect 0x1003
+#define DoC_CDSNControl 0x1004
+#define DoC_CDSNDeviceSelect 0x1005
+#define DoC_ECCConf 0x1006
+#define DoC_2k_ECCStatus 0x1007
+
+#define DoC_CDSNSlowIO 0x100d
+#define DoC_ECCSyndrome0 0x1010
+#define DoC_ECCSyndrome1 0x1011
+#define DoC_ECCSyndrome2 0x1012
+#define DoC_ECCSyndrome3 0x1013
+#define DoC_ECCSyndrome4 0x1014
+#define DoC_ECCSyndrome5 0x1015
+#define DoC_AliasResolution 0x101b
+#define DoC_ConfigInput 0x101c
+#define DoC_ReadPipeInit 0x101d
+#define DoC_WritePipeTerm 0x101e
+#define DoC_LastDataRead 0x101f
+#define DoC_NOP 0x1020
+
+#define DoC_Mil_CDSN_IO 0x0800
+#define DoC_2k_CDSN_IO 0x1800
+
+#define ReadDOC_(adr, reg) ((volatile unsigned char)(*(volatile __u8 *)(((unsigned long)adr)+((reg)))))
+#define WriteDOC_(d, adr, reg) do{ *(volatile __u8 *)(((unsigned long)adr)+((reg))) = (__u8)d; eieio();} while(0)
+
+#define DOC_IOREMAP_LEN 0x4000
+
+/* These are provided to directly use the DoC_xxx defines */
+#define ReadDOC(adr, reg) ReadDOC_(adr,DoC_##reg)
+#define WriteDOC(d, adr, reg) WriteDOC_(d,adr,DoC_##reg)
+
+#define DOC_MODE_RESET 0
+#define DOC_MODE_NORMAL 1
+#define DOC_MODE_RESERVED1 2
+#define DOC_MODE_RESERVED2 3
+
+#define DOC_MODE_MDWREN 4
+#define DOC_MODE_CLR_ERR 0x80
+
+#define DOC_ChipID_UNKNOWN 0x00
+#define DOC_ChipID_Doc2k 0x20
+#define DOC_ChipID_DocMil 0x30
+
+#define CDSN_CTRL_FR_B 0x80
+#define CDSN_CTRL_ECC_IO 0x20
+#define CDSN_CTRL_FLASH_IO 0x10
+#define CDSN_CTRL_WP 0x08
+#define CDSN_CTRL_ALE 0x04
+#define CDSN_CTRL_CLE 0x02
+#define CDSN_CTRL_CE 0x01
+
+#define DOC_ECC_RESET 0
+#define DOC_ECC_ERROR 0x80
+#define DOC_ECC_RW 0x20
+#define DOC_ECC__EN 0x08
+#define DOC_TOGGLE_BIT 0x04
+#define DOC_ECC_RESV 0x02
+#define DOC_ECC_IGNORE 0x01
+
+/* We have to also set the reserved bit 1 for enable */
+#define DOC_ECC_EN (DOC_ECC__EN | DOC_ECC_RESV)
+#define DOC_ECC_DIS (DOC_ECC_RESV)
+
+struct Nand {
+ char floor, chip;
+ unsigned long curadr;
+ unsigned char curmode;
+ /* Also some erase/write/pipeline info when we get that far */
+};
+
+#define MAX_FLOORS 4
+#define MAX_CHIPS 4
+
+#define MAX_FLOORS_MIL 4
+#define MAX_CHIPS_MIL 1
+
+#define ADDR_COLUMN 1
+#define ADDR_PAGE 2
+#define ADDR_COLUMN_PAGE 3
+
+struct DiskOnChip {
+ unsigned long physadr;
+ unsigned long virtadr;
+ unsigned long totlen;
+ char* name;
+ char ChipID; /* Type of DiskOnChip */
+ int ioreg;
+
+ char* chips_name;
+ unsigned long mfr; /* Flash IDs - only one type of flash per device */
+ unsigned long id;
+ int chipshift;
+ char page256;
+ char pageadrlen;
+ unsigned long erasesize;
+
+ int curfloor;
+ int curchip;
+
+ int numchips;
+ struct Nand *chips;
+
+ int nftl_found;
+ struct NFTLrecord nftl;
+};
+
+#define SECTORSIZE 512
+
+/* Return codes from doc_write(), doc_read(), and doc_erase().
+ */
+#define DOC_OK 0
+#define DOC_EIO 1
+#define DOC_EINVAL 2
+#define DOC_EECC 3
+#define DOC_ETIMEOUT 4
+
+/*
+ * Function Prototypes
+ */
+int doc_decode_ecc(unsigned char sector[512], unsigned char ecc1[6]);
+
+int doc_rw(struct DiskOnChip* this, int cmd, loff_t from, size_t len,
+ size_t *retlen, u_char *buf);
+int doc_read_ecc(struct DiskOnChip* this, loff_t from, size_t len,
+ size_t *retlen, u_char *buf, u_char *eccbuf);
+int doc_write_ecc(struct DiskOnChip* this, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf, u_char *eccbuf);
+int doc_read_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
+ size_t *retlen, u_char *buf);
+int doc_write_oob(struct DiskOnChip* this, loff_t ofs, size_t len,
+ size_t *retlen, const u_char *buf);
+int doc_erase (struct DiskOnChip* this, loff_t ofs, size_t len);
+
+void doc_probe(unsigned long physadr);
+
+void doc_print(struct DiskOnChip*);
+
+#endif /* __MTD_DOC2000_H__ */
diff --git a/include/linux/time.h b/include/linux/time.h
new file mode 100644
index 0000000..bf12b99
--- /dev/null
+++ b/include/linux/time.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_TIME_H
+#define _LINUX_TIME_H
+
+#include <linux/types.h>
+
+#define _DEFUN(a,b,c) a(c)
+#define _CONST const
+#define _AND ,
+
+#define _REENT_ONLY
+
+#define SECSPERMIN 60L
+#define MINSPERHOUR 60L
+#define HOURSPERDAY 24L
+#define SECSPERHOUR (SECSPERMIN * MINSPERHOUR)
+#define SECSPERDAY (SECSPERHOUR * HOURSPERDAY)
+#define DAYSPERWEEK 7
+#define MONSPERYEAR 12
+
+#define YEAR_BASE 1900
+#define EPOCH_YEAR 1970
+#define EPOCH_WDAY 4
+
+#define isleap(y) ((((y) % 4) == 0 && ((y) % 100) != 0) || ((y) % 400) == 0)
+
+
+/* Used by other time functions. */
+struct tm {
+ int tm_sec; /* Seconds. [0-60] (1 leap second) */
+ int tm_min; /* Minutes. [0-59] */
+ int tm_hour; /* Hours. [0-23] */
+ int tm_mday; /* Day. [1-31] */
+ int tm_mon; /* Month. [0-11] */
+ int tm_year; /* Year - 1900. */
+ int tm_wday; /* Day of week. [0-6] */
+ int tm_yday; /* Days in year.[0-365] */
+ int tm_isdst; /* DST. [-1/0/1]*/
+
+# ifdef __USE_BSD
+ long int tm_gmtoff; /* Seconds east of UTC. */
+ __const char *tm_zone; /* Timezone abbreviation. */
+# else
+ long int __tm_gmtoff; /* Seconds east of UTC. */
+ __const char *__tm_zone; /* Timezone abbreviation. */
+# endif
+};
+
+static inline char *
+_DEFUN (asctime_r, (tim_p, result),
+ _CONST struct tm *tim_p _AND
+ char *result)
+{
+ static _CONST char day_name[7][3] = {
+ "Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"
+ };
+ static _CONST char mon_name[12][3] = {
+ "Jan", "Feb", "Mar", "Apr", "May", "Jun",
+ "Jul", "Aug", "Sep", "Oct", "Nov", "Dec"
+ };
+
+ sprintf (result, "%.3s %.3s %.2d %.2d:%.2d:%.2d %d\n",
+ day_name[tim_p->tm_wday],
+ mon_name[tim_p->tm_mon],
+ tim_p->tm_mday, tim_p->tm_hour, tim_p->tm_min,
+ tim_p->tm_sec, 1900 + tim_p->tm_year);
+ return result;
+}
+
+static inline struct tm *
+_DEFUN (localtime_r, (tim_p, res),
+ _CONST time_t * tim_p _AND
+ struct tm *res)
+{
+ static _CONST int mon_lengths[2][MONSPERYEAR] = {
+ {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31},
+ {31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}
+ } ;
+
+ static _CONST int year_lengths[2] = {
+ 365,
+ 366
+ } ;
+
+ long days, rem;
+ int y;
+ int yleap;
+ _CONST int *ip;
+
+ days = ((long) *tim_p) / SECSPERDAY;
+ rem = ((long) *tim_p) % SECSPERDAY;
+ while (rem < 0)
+ {
+ rem += SECSPERDAY;
+ --days;
+ }
+ while (rem >= SECSPERDAY)
+ {
+ rem -= SECSPERDAY;
+ ++days;
+ }
+
+ /* compute hour, min, and sec */
+ res->tm_hour = (int) (rem / SECSPERHOUR);
+ rem %= SECSPERHOUR;
+ res->tm_min = (int) (rem / SECSPERMIN);
+ res->tm_sec = (int) (rem % SECSPERMIN);
+
+ /* compute day of week */
+ if ((res->tm_wday = ((EPOCH_WDAY + days) % DAYSPERWEEK)) < 0)
+ res->tm_wday += DAYSPERWEEK;
+
+ /* compute year & day of year */
+ y = EPOCH_YEAR;
+ if (days >= 0)
+ {
+ for (;;)
+ {
+ yleap = isleap(y);
+ if (days < year_lengths[yleap])
+ break;
+ y++;
+ days -= year_lengths[yleap];
+ }
+ }
+ else
+ {
+ do
+ {
+ --y;
+ yleap = isleap(y);
+ days += year_lengths[yleap];
+ } while (days < 0);
+ }
+
+ res->tm_year = y - YEAR_BASE;
+ res->tm_yday = days;
+ ip = mon_lengths[yleap];
+ for (res->tm_mon = 0; days >= ip[res->tm_mon]; ++res->tm_mon)
+ days -= ip[res->tm_mon];
+ res->tm_mday = days + 1;
+
+ /* set daylight saving time flag */
+ res->tm_isdst = -1;
+
+ return (res);
+}
+
+static inline char *
+_DEFUN (ctime_r, (tim_p, result),
+ _CONST time_t * tim_p _AND
+ char * result)
+
+{
+ struct tm tm;
+ return asctime_r (localtime_r (tim_p, &tm), result);
+}
+
+#endif
diff --git a/include/mk48t59.h b/include/mk48t59.h
new file mode 100644
index 0000000..03c992e
--- /dev/null
+++ b/include/mk48t59.h
@@ -0,0 +1,64 @@
+/*
+ * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
+ * Andreas Heppel <aheppel@sysgo.de>
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Date & Time support for the MK48T59 RTC
+ */
+
+
+#if defined(CONFIG_RTC_MK48T59) && (CONFIG_COMMANDS & CFG_CMD_DATE)
+
+#define RTC_PORT_ADDR0 CFG_ISA_IO + 0x70
+#define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1
+#define RTC_PORT_DATA CFG_ISA_IO + 0x76
+
+/* RTC Offsets */
+#define RTC_SECONDS 0x1FF9
+#define RTC_MINUTES 0x1FFA
+#define RTC_HOURS 0x1FFB
+#define RTC_DAY_OF_WEEK 0x1FFC
+#define RTC_DAY_OF_MONTH 0x1FFD
+#define RTC_MONTH 0x1FFE
+#define RTC_YEAR 0x1FFF
+
+#define RTC_CONTROLA 0x1FF8
+#define RTC_CA_WRITE 0x80
+#define RTC_CA_READ 0x40
+#define RTC_CA_CALIB_SIGN 0x20
+#define RTC_CA_CALIB_MASK 0x1f
+
+#define RTC_CONTROLB 0x1FF9
+#define RTC_CB_STOP 0x80
+
+#define RTC_WATCHDOG 0x1FF7
+#define RTC_WDS 0x80
+#define RTC_WD_RB_16TH 0x0
+#define RTC_WD_RB_4TH 0x1
+#define RTC_WD_RB_1 0x2
+#define RTC_WD_RB_4 0x3
+
+void rtc_set_watchdog(short multi, short res);
+void *nvram_read(void *dest, const short src, size_t count);
+void nvram_write(short dest, const void *src, size_t count);
+
+#endif
diff --git a/include/part.h b/include/part.h
new file mode 100644
index 0000000..e43978c
--- /dev/null
+++ b/include/part.h
@@ -0,0 +1,99 @@
+/*
+ * (C) Copyright 2000, 2001
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PART_H
+#define _PART_H
+
+
+typedef struct block_dev_desc {
+ int if_type; /* type of the interface */
+ int dev; /* device number */
+ unsigned char part_type; /* partition type */
+ unsigned char target; /* target SCSI ID */
+ unsigned char lun; /* target LUN */
+ unsigned char type; /* device type */
+ unsigned long lba; /* number of blocks */
+ unsigned long blksz; /* block size */
+ unsigned char vendor[40]; /* IDE model, SCSI Vendor */
+ unsigned char product[20];/* IDE Serial no, SCSI product */
+ unsigned char revision[8];/* firmware revision */
+ unsigned char removable; /* removable device */
+ unsigned long (*block_read)(int dev,unsigned long start,unsigned long blkcnt, unsigned long *buffer);
+}block_dev_desc_t;
+/* Interface types: */
+#define IF_TYPE_UNKNOWN 0
+#define IF_TYPE_IDE 1
+#define IF_TYPE_SCSI 2
+#define IF_TYPE_ATAPI 3
+#define IF_TYPE_USB 4
+#define IF_TYPE_DOC 5
+/* Part types */
+#define PART_TYPE_UNKNOWN 0x00
+#define PART_TYPE_MAC 0x01
+#define PART_TYPE_DOS 0x02
+#define PART_TYPE_ISO 0x03
+/* device types */
+#define DEV_TYPE_UNKNOWN 0xff /* not connected */
+#define DEV_TYPE_HARDDISK 0x00 /* harddisk */
+#define DEV_TYPE_TAPE 0x01 /* Tape */
+#define DEV_TYPE_CDROM 0x05 /* CD-ROM */
+#define DEV_TYPE_OPDISK 0x07 /* optical disk */
+
+typedef struct disk_partition {
+ ulong start; /* # of first block in partition */
+ ulong size; /* number of blocks in partition */
+ ulong blksz; /* block size in bytes */
+ uchar name[32]; /* partition name */
+ uchar type[32]; /* string type description */
+} disk_partition_t;
+
+/* disk/part.c */
+int get_partition_info (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part (block_dev_desc_t *dev_desc);
+void init_part (block_dev_desc_t *dev_desc);
+void dev_print(block_dev_desc_t *dev_desc);
+
+
+#ifdef CONFIG_MAC_PARTITION
+/* disk/part_mac.c */
+int get_partition_info_mac (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_mac (block_dev_desc_t *dev_desc);
+int test_part_mac (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_DOS_PARTITION
+/* disk/part_dos.c */
+int get_partition_info_dos (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_dos (block_dev_desc_t *dev_desc);
+int test_part_dos (block_dev_desc_t *dev_desc);
+#endif
+
+#ifdef CONFIG_ISO_PARTITION
+/* disk/part_iso.c */
+int get_partition_info_iso (block_dev_desc_t * dev_desc, int part, disk_partition_t *info);
+void print_part_iso (block_dev_desc_t *dev_desc);
+int test_part_iso (block_dev_desc_t *dev_desc);
+#endif
+
+#endif /* _PART_H */
+
+
diff --git a/include/usb.h b/include/usb.h
new file mode 100644
index 0000000..c3cc890
--- /dev/null
+++ b/include/usb.h
@@ -0,0 +1,352 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_H_
+#define _USB_H_
+
+#include <usb_defs.h>
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC 4
+#define USB_MAXALTSETTING 128 /* Hard limit */
+
+#define USB_MAX_DEVICE 32
+#define USB_MAXCONFIG 8
+#define USB_MAXINTERFACES 8
+#define USB_MAXENDPOINTS 16
+#define USB_MAXCHILDREN 8 /* This is arbitrary */
+#define USB_MAX_HUB 16
+
+#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
+
+
+/* String descriptor */
+struct usb_string_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned short wData[1];
+} __attribute__ ((packed));
+
+/* device request (setup) */
+struct devrequest {
+ unsigned char requesttype;
+ unsigned char request;
+ unsigned short value;
+ unsigned short index;
+ unsigned short length;
+} __attribute__ ((packed));
+
+
+
+/* All standard descriptors have these 2 fields in common */
+struct usb_descriptor_header {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+} __attribute__ ((packed));
+
+/* Device descriptor */
+struct usb_device_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned short bcdUSB;
+ unsigned char bDeviceClass;
+ unsigned char bDeviceSubClass;
+ unsigned char bDeviceProtocol;
+ unsigned char bMaxPacketSize0;
+ unsigned short idVendor;
+ unsigned short idProduct;
+ unsigned short bcdDevice;
+ unsigned char iManufacturer;
+ unsigned char iProduct;
+ unsigned char iSerialNumber;
+ unsigned char bNumConfigurations;
+} __attribute__ ((packed));
+
+
+/* Endpoint descriptor */
+struct usb_endpoint_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned char bEndpointAddress;
+ unsigned char bmAttributes;
+ unsigned short wMaxPacketSize;
+ unsigned char bInterval;
+ unsigned char bRefresh;
+ unsigned char bSynchAddress;
+
+} __attribute__ ((packed));
+/* Interface descriptor */
+struct usb_interface_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned char bInterfaceNumber;
+ unsigned char bAlternateSetting;
+ unsigned char bNumEndpoints;
+ unsigned char bInterfaceClass;
+ unsigned char bInterfaceSubClass;
+ unsigned char bInterfaceProtocol;
+ unsigned char iInterface;
+
+ unsigned char no_of_ep;
+ unsigned char act_altsetting;
+ struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+} __attribute__ ((packed));
+
+
+/* Configuration descriptor information.. */
+struct usb_config_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned short wTotalLength;
+ unsigned char bNumInterfaces;
+ unsigned char bConfigurationValue;
+ unsigned char iConfiguration;
+ unsigned char bmAttributes;
+ unsigned char MaxPower;
+
+ unsigned char no_of_if; /* number of interfaces */
+ struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
+} __attribute__ ((packed));
+
+
+struct usb_device {
+ int devnum; /* Device number on USB bus */
+ int slow; /* Slow device? */
+ char mf[32]; /* manufacturer */
+ char prod[32]; /* product */
+ char serial[32]; /* serial number */
+
+ int maxpacketsize; /* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+ unsigned int toggle[2]; /* one bit for each endpoint ([0] = IN, [1] = OUT) */
+ unsigned int halted[2]; /* endpoint halts; one bit per endpoint # & direction; */
+ /* [0] = IN, [1] = OUT */
+ int epmaxpacketin[16]; /* INput endpoint specific maximums */
+ int epmaxpacketout[16]; /* OUTput endpoint specific maximums */
+
+ int configno; /* selected config number */
+ struct usb_device_descriptor descriptor; /* Device Descriptor */
+ struct usb_config_descriptor config; /* config descriptor */
+
+ int have_langid; /* whether string_langid is valid yet */
+ int string_langid; /* language ID for strings */
+ int (*irq_handle)(struct usb_device *dev);
+ unsigned long irq_status;
+ int irq_act_len; /* transfered bytes */
+ void *privptr;
+ /*
+ * Child devices - if this is a hub device
+ * Each instance needs its own set of data structures.
+ */
+ unsigned long status;
+ int act_len; /* transfered bytes */
+ int maxchild; /* Number of ports if hub */
+ struct usb_device *parent;
+ struct usb_device *children[USB_MAXCHILDREN];
+};
+
+/**********************************************************************
+ * this is how the lowlevel part communicate with the outer world
+ */
+
+#ifdef CONFIG_USB_UHCI
+int usb_lowlevel_init(void);
+int usb_lowlevel_stop(void);
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,int transfer_len);
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len,struct devrequest *setup);
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+ int transfer_len, int interval);
+
+/* Defines */
+#define USB_UHCI_VEND_ID 0x8086
+#define USB_UHCI_DEV_ID 0x7112
+
+#else
+#error USB Lowlevel not defined
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+
+#define USB_MAX_STOR_DEV 5
+block_dev_desc_t *usb_stor_get_dev(int index);
+int usb_stor_scan(int mode);
+
+#endif
+
+#ifdef CONFIG_USB_KEYBOARD
+
+int drv_usb_kbd_init(void);
+int usb_kbd_deregister(void);
+
+#endif
+/* routines */
+int usb_init(void); /* initialize the USB Controller */
+int usb_stop(void); /* stop the USB Controller */
+
+
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
+struct usb_device * usb_get_dev_index(int index);
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+ unsigned char request, unsigned char requesttype,
+ unsigned short value, unsigned short index,
+ void *data, unsigned short size, int timeout);
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+ void *data, int len, int *actual_length, int timeout);
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+ void *buffer,int transfer_len, int interval);
+void usb_disable_asynch(int disable);
+int usb_maxpacket(struct usb_device *dev,unsigned long pipe);
+void __inline__ wait_ms(unsigned long ms);
+int usb_get_configuration_no(struct usb_device *dev,unsigned char *buffer,int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type, unsigned char id, void *buf, int size);
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+ unsigned char type, unsigned char id, void *buf, int size);
+int usb_clear_halt(struct usb_device *dev, int pipe);
+int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
+int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+
+/* big endian -> little endian conversion */
+#define swap_16(x) \
+ ((unsigned short)( \
+ (((unsigned short)(x) & (unsigned short)0x00ffU) << 8) | \
+ (((unsigned short)(x) & (unsigned short)0xff00U) >> 8) ))
+#define swap_32(x) \
+ ((unsigned long)( \
+ (((unsigned long)(x) & (unsigned long)0x000000ffUL) << 24) | \
+ (((unsigned long)(x) & (unsigned long)0x0000ff00UL) << 8) | \
+ (((unsigned long)(x) & (unsigned long)0x00ff0000UL) >> 8) | \
+ (((unsigned long)(x) & (unsigned long)0xff000000UL) >> 24) ))
+
+/*
+ * Calling this entity a "pipe" is glorifying it. A USB pipe
+ * is something embarrassingly simple: it basically consists
+ * of the following information:
+ * - device number (7 bits)
+ * - endpoint number (4 bits)
+ * - current Data0/1 state (1 bit)
+ * - direction (1 bit)
+ * - speed (1 bit)
+ * - max packet size (2 bits: 8, 16, 32 or 64)
+ * - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *
+ * That's 18 bits. Really. Nothing more. And the USB people have
+ * documented these eighteen bits as some kind of glorious
+ * virtual data structure.
+ *
+ * Let's not fall in that trap. We'll just encode it as a simple
+ * unsigned int. The encoding is:
+ *
+ * - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ * - direction: bit 7 (0 = Host-to-Device [Out], 1 = Device-to-Host [In])
+ * - device: bits 8-14
+ * - endpoint: bits 15-18
+ * - Data0/1: bit 19
+ * - speed: bit 26 (0 = Full, 1 = Low Speed)
+ * - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt, 10 = control, 11 = bulk)
+ *
+ * Why? Because it's arbitrary, and whatever encoding we select is really
+ * up to us. This one happens to share a lot of bit positions with the UHCI
+ * specification, so that much of the uhci driver can just mask the bits
+ * appropriately.
+ */
+/* Create various pipes... */
+#define create_pipe(dev,endpoint) \
+ (((dev)->devnum << 8) | (endpoint << 15) | ((dev)->slow << 26) | (dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->slow <<26)
+
+#define usb_sndctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint))
+#define usb_rcvctrlpipe(dev,endpoint) ((PIPE_CONTROL << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndisocpipe(dev,endpoint) ((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint))
+#define usb_rcvisocpipe(dev,endpoint) ((PIPE_ISOCHRONOUS << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndbulkpipe(dev,endpoint) ((PIPE_BULK << 30) | create_pipe(dev,endpoint))
+#define usb_rcvbulkpipe(dev,endpoint) ((PIPE_BULK << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_sndintpipe(dev,endpoint) ((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint))
+#define usb_rcvintpipe(dev,endpoint) ((PIPE_INTERRUPT << 30) | create_pipe(dev,endpoint) | USB_DIR_IN)
+#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | default_pipe(dev))
+#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | default_pipe(dev) | USB_DIR_IN)
+
+/* The D0/D1 toggle bits */
+#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
+#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = ((dev)->toggle[out] & ~(1 << ep)) | ((bit) << ep))
+
+/* Endpoint halt control/status */
+#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1)
+#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
+#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
+#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
+
+#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : USB_PID_OUT)
+
+#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1)
+#define usb_pipein(pipe) (((pipe) >> 7) & 1)
+#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f)
+#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff)
+#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf)
+#define usb_pipedata(pipe) (((pipe) >> 19) & 1)
+#define usb_pipeslow(pipe) (((pipe) >> 26) & 1)
+#define usb_pipetype(pipe) (((pipe) >> 30) & 3)
+#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
+#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT)
+#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL)
+#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK)
+
+
+/*************************************************************************
+ * Hub Stuff
+ */
+struct usb_port_status {
+ unsigned short wPortStatus;
+ unsigned short wPortChange;
+} __attribute__ ((packed));
+
+struct usb_hub_status {
+ unsigned short wHubStatus;
+ unsigned short wHubChange;
+} __attribute__ ((packed));
+
+
+/* Hub descriptor */
+struct usb_hub_descriptor {
+ unsigned char bLength;
+ unsigned char bDescriptorType;
+ unsigned char bNbrPorts;
+ unsigned short wHubCharacteristics;
+ unsigned char bPwrOn2PwrGood;
+ unsigned char bHubContrCurrent;
+ unsigned char DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+ unsigned char PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+ /* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+ bitmaps that hold max 255 entries. (bit0 is ignored) */
+} __attribute__ ((packed));
+
+
+struct usb_hub_device {
+ struct usb_device *pusb_dev;
+ struct usb_hub_descriptor desc;
+};
+
+#endif /*_USB_H_ */
diff --git a/include/usb_defs.h b/include/usb_defs.h
new file mode 100644
index 0000000..00a31e9
--- /dev/null
+++ b/include/usb_defs.h
@@ -0,0 +1,256 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_DEFS_H_
+#define _USB_DEFS_H_
+
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC 4
+#define USB_MAXALTSETTING 128 /* Hard limit */
+
+#define USB_MAX_DEVICE 32
+#define USB_MAXCONFIG 8
+#define USB_MAXINTERFACES 8
+#define USB_MAXENDPOINTS 16
+#define USB_MAXCHILDREN 8 /* This is arbitrary */
+#define USB_MAX_HUB 16
+
+#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
+
+/* USB constants */
+
+/* Device and/or Interface Class codes */
+#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
+#define USB_CLASS_AUDIO 1
+#define USB_CLASS_COMM 2
+#define USB_CLASS_HID 3
+#define USB_CLASS_PRINTER 7
+#define USB_CLASS_MASS_STORAGE 8
+#define USB_CLASS_HUB 9
+#define USB_CLASS_DATA 10
+#define USB_CLASS_VENDOR_SPEC 0xff
+
+/* some HID sub classes */
+#define USB_SUB_HID_NONE 0
+#define USB_SUB_HID_BOOT 1
+
+/* some UID Protocols */
+#define USB_PROT_HID_NONE 0
+#define USB_PROT_HID_KEYBOARD 1
+#define USB_PROT_HID_MOUSE 2
+
+
+/* Sub STORAGE Classes */
+#define US_SC_RBC 1 /* Typically, flash devices */
+#define US_SC_8020 2 /* CD-ROM */
+#define US_SC_QIC 3 /* QIC-157 Tapes */
+#define US_SC_UFI 4 /* Floppy */
+#define US_SC_8070 5 /* Removable media */
+#define US_SC_SCSI 6 /* Transparent */
+#define US_SC_MIN US_SC_RBC
+#define US_SC_MAX US_SC_SCSI
+
+/* STORAGE Protocols */
+#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
+#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
+#define US_PR_BULK 0x50 /* bulk only */
+
+/* USB types */
+#define USB_TYPE_STANDARD (0x00 << 5)
+#define USB_TYPE_CLASS (0x01 << 5)
+#define USB_TYPE_VENDOR (0x02 << 5)
+#define USB_TYPE_RESERVED (0x03 << 5)
+
+/* USB recipients */
+#define USB_RECIP_DEVICE 0x00
+#define USB_RECIP_INTERFACE 0x01
+#define USB_RECIP_ENDPOINT 0x02
+#define USB_RECIP_OTHER 0x03
+
+/* USB directions */
+#define USB_DIR_OUT 0
+#define USB_DIR_IN 0x80
+
+/* Descriptor types */
+#define USB_DT_DEVICE 0x01
+#define USB_DT_CONFIG 0x02
+#define USB_DT_STRING 0x03
+#define USB_DT_INTERFACE 0x04
+#define USB_DT_ENDPOINT 0x05
+
+#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
+
+/* Descriptor sizes per descriptor type */
+#define USB_DT_DEVICE_SIZE 18
+#define USB_DT_CONFIG_SIZE 9
+#define USB_DT_INTERFACE_SIZE 9
+#define USB_DT_ENDPOINT_SIZE 7
+#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE 7
+#define USB_DT_HID_SIZE 9
+
+/* Endpoints */
+#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK 0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL 0
+#define USB_ENDPOINT_XFER_ISOC 1
+#define USB_ENDPOINT_XFER_BULK 2
+#define USB_ENDPOINT_XFER_INT 3
+
+/* USB Packet IDs (PIDs) */
+#define USB_PID_UNDEF_0 0xf0
+#define USB_PID_OUT 0xe1
+#define USB_PID_ACK 0xd2
+#define USB_PID_DATA0 0xc3
+#define USB_PID_UNDEF_4 0xb4
+#define USB_PID_SOF 0xa5
+#define USB_PID_UNDEF_6 0x96
+#define USB_PID_UNDEF_7 0x87
+#define USB_PID_UNDEF_8 0x78
+#define USB_PID_IN 0x69
+#define USB_PID_NAK 0x5a
+#define USB_PID_DATA1 0x4b
+#define USB_PID_PREAMBLE 0x3c
+#define USB_PID_SETUP 0x2d
+#define USB_PID_STALL 0x1e
+#define USB_PID_UNDEF_F 0x0f
+
+/* Standard requests */
+#define USB_REQ_GET_STATUS 0x00
+#define USB_REQ_CLEAR_FEATURE 0x01
+#define USB_REQ_SET_FEATURE 0x03
+#define USB_REQ_SET_ADDRESS 0x05
+#define USB_REQ_GET_DESCRIPTOR 0x06
+#define USB_REQ_SET_DESCRIPTOR 0x07
+#define USB_REQ_GET_CONFIGURATION 0x08
+#define USB_REQ_SET_CONFIGURATION 0x09
+#define USB_REQ_GET_INTERFACE 0x0A
+#define USB_REQ_SET_INTERFACE 0x0B
+#define USB_REQ_SYNCH_FRAME 0x0C
+
+/* HID requests */
+#define USB_REQ_GET_REPORT 0x01
+#define USB_REQ_GET_IDLE 0x02
+#define USB_REQ_GET_PROTOCOL 0x03
+#define USB_REQ_SET_REPORT 0x09
+#define USB_REQ_SET_IDLE 0x0A
+#define USB_REQ_SET_PROTOCOL 0x0B
+
+
+/* "pipe" definitions */
+
+#define PIPE_ISOCHRONOUS 0
+#define PIPE_INTERRUPT 1
+#define PIPE_CONTROL 2
+#define PIPE_BULK 3
+#define PIPE_DEVEP_MASK 0x0007ff00
+
+#define USB_ISOCHRONOUS 0
+#define USB_INTERRUPT 1
+#define USB_CONTROL 2
+#define USB_BULK 3
+
+/* USB-status codes: */
+#define USB_ST_ACTIVE 0x1 /* TD is active */
+#define USB_ST_STALLED 0x2 /* TD is stalled */
+#define USB_ST_BUF_ERR 0x4 /* buffer error */
+#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
+#define USB_ST_NAK_REC 0x10 /* NAK Received*/
+#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
+#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
+#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
+
+
+
+/*************************************************************************
+ * Hub defines
+ */
+
+/*
+ * Hub request types
+ */
+
+#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+/*
+ * Hub Class feature numbers
+ */
+#define C_HUB_LOCAL_POWER 0
+#define C_HUB_OVER_CURRENT 1
+
+/*
+ * Port feature numbers
+ */
+#define USB_PORT_FEAT_CONNECTION 0
+#define USB_PORT_FEAT_ENABLE 1
+#define USB_PORT_FEAT_SUSPEND 2
+#define USB_PORT_FEAT_OVER_CURRENT 3
+#define USB_PORT_FEAT_RESET 4
+#define USB_PORT_FEAT_POWER 8
+#define USB_PORT_FEAT_LOWSPEED 9
+#define USB_PORT_FEAT_C_CONNECTION 16
+#define USB_PORT_FEAT_C_ENABLE 17
+#define USB_PORT_FEAT_C_SUSPEND 18
+#define USB_PORT_FEAT_C_OVER_CURRENT 19
+#define USB_PORT_FEAT_C_RESET 20
+
+/* wPortStatus bits */
+#define USB_PORT_STAT_CONNECTION 0x0001
+#define USB_PORT_STAT_ENABLE 0x0002
+#define USB_PORT_STAT_SUSPEND 0x0004
+#define USB_PORT_STAT_OVERCURRENT 0x0008
+#define USB_PORT_STAT_RESET 0x0010
+#define USB_PORT_STAT_POWER 0x0100
+#define USB_PORT_STAT_LOW_SPEED 0x0200
+
+/* wPortChange bits */
+#define USB_PORT_STAT_C_CONNECTION 0x0001
+#define USB_PORT_STAT_C_ENABLE 0x0002
+#define USB_PORT_STAT_C_SUSPEND 0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET 0x0010
+
+/* wHubCharacteristics (masks) */
+#define HUB_CHAR_LPSM 0x0003
+#define HUB_CHAR_COMPOUND 0x0004
+#define HUB_CHAR_OCPM 0x0018
+
+/*
+ *Hub Status & Hub Change bit masks
+ */
+#define HUB_STATUS_LOCAL_POWER 0x0001
+#define HUB_STATUS_OVERCURRENT 0x0002
+
+#define HUB_CHANGE_LOCAL_POWER 0x0001
+#define HUB_CHANGE_OVERCURRENT 0x0002
+
+#endif /*_USB_DEFS_H_ */
diff --git a/include/w83c553f.h b/include/w83c553f.h
new file mode 100644
index 0000000..88ea9da
--- /dev/null
+++ b/include/w83c553f.h
@@ -0,0 +1,178 @@
+/*
+ * (C) Copyright 2000
+ * Rob Taylor, Flying Pig Systems. robt@flyingpig.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+ /* winbond access routines and defines*/
+
+/* from the winbond data sheet -
+ The W83C553F SIO controller with PCI arbiter is a multi-function PCI device.
+ Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller.
+*/
+
+/*ISA bridge configuration space*/
+
+#define W83C553F_VID 0x10AD
+#define W83C553F_DID 0x0565
+
+#define WINBOND_PCICONTR 0x40 /*pci control reg*/
+#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/
+#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/
+#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/
+#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/
+#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/
+#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/
+#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/
+#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/
+#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/
+#define WINBOND_CDR 0x4c /*Clock Divisor Register*/
+#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/
+#define WINBOND_ATSCR 0x4e /*AT System Control register*/
+#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/
+#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/
+#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/
+#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/
+#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/
+
+#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/
+
+#define IPADCR_MBE512 0x1
+#define IPADCR_MBE640 0x2
+#define IPADCR_IPATOM4 0x10
+#define IPADCR_IPATOM5 0x20
+#define IPADCR_IPATOM6 0x40
+#define IPADCR_IPATOM7 0x80
+
+#define CSCR_UBIOSCSE 0x10
+#define CSCR_BIOSWP 0x20
+
+#define IDECSR_P0EN 0x01
+#define IDECSR_P0F16 0x02
+#define IDECSR_P1EN 0x10
+#define IDECSR_P1F16 0x20
+#define IDECSR_LEGIRQ 0x800
+
+/*
+ * Interrupt controller
+ */
+#define W83C553F_PIC1_ICW1 CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_ICW2 CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW3 CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_ICW4 CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW1 CFG_ISA_IO + 0x21
+#define W83C553F_PIC1_OCW2 CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_OCW3 CFG_ISA_IO + 0x20
+#define W83C553F_PIC1_ELC CFG_ISA_IO + 0x4D0
+#define W83C553F_PIC2_ICW1 CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_ICW2 CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW3 CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_ICW4 CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW1 CFG_ISA_IO + 0xA1
+#define W83C553F_PIC2_OCW2 CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_OCW3 CFG_ISA_IO + 0xA0
+#define W83C553F_PIC2_ELC CFG_ISA_IO + 0x4D1
+
+#define W83C553F_TMR1_CMOD CFG_ISA_IO + 0x43
+
+/*
+ * DMA controller
+ */
+#define W83C553F_DMA1 CFG_ISA_IO + 0x000 /* channel 0 - 3 */
+#define W83C553F_DMA2 CFG_ISA_IO + 0x0C0 /* channel 4 - 7 */
+
+/* command/status register bit definitions */
+
+#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */
+#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */
+#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */
+#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */
+
+#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */
+#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */
+#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */
+#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */
+
+#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */
+#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */
+#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */
+#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */
+
+/* mode register bit definitions */
+
+#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */
+#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */
+#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */
+#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */
+#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */
+#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */
+#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */
+#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */
+#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */
+#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */
+#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */
+#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */
+#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */
+#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */
+
+/* request register bit definitions */
+
+#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */
+#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */
+#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */
+#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */
+#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */
+
+/* write single mask bit register bit definitions */
+
+#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */
+#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */
+#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */
+#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */
+#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */
+
+/* read/write all mask bits register bit definitions */
+
+#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */
+#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */
+#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */
+#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */
+
+/* typedefs */
+
+#define W83C553F_DMA1_CS 0x8
+#define W83C553F_DMA1_WR 0x9
+#define W83C553F_DMA1_WSMB 0xA
+#define W83C553F_DMA1_WM 0xB
+#define W83C553F_DMA1_CBP 0xC
+#define W83C553F_DMA1_MC 0xD
+#define W83C553F_DMA1_CM 0xE
+#define W83C553F_DMA1_RWAMB 0xF
+
+#define W83C553F_DMA2_CS 0x10
+#define W83C553F_DMA2_WR 0x12
+#define W83C553F_DMA2_WSMB 0x14
+#define W83C553F_DMA2_WM 0x16
+#define W83C553F_DMA2_CBP 0x18
+#define W83C553F_DMA2_MC 0x1A
+#define W83C553F_DMA2_CM 0x1C
+#define W83C553F_DMA2_RWAMB 0x1E
+
+void initialise_w83c553f(void);
diff --git a/include/watchdog.h b/include/watchdog.h
new file mode 100644
index 0000000..6a64409
--- /dev/null
+++ b/include/watchdog.h
@@ -0,0 +1,96 @@
+/*
+ * (C) Copyright 2001
+ * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+/*
+ * Watchdog functions and macros.
+ */
+#ifndef _WATCHDOG_H_
+#define _WATCHDOG_H_
+
+#if defined(CONFIG_HW_WATCHDOG) && defined(CONFIG_WATCHDOG)
+# error "Configuration error: CONFIG_HW_WATCHDOG and CONFIG_WATCHDOG can't be used together."
+#endif
+
+/*
+ * Hardware watchdog
+ */
+#ifdef CONFIG_HW_WATCHDOG
+ #if defined(__ASSEMBLY__)
+ #define WATCHDOG_RESET bl hw_watchdog_reset
+ #else
+ extern void hw_watchdog_reset(void);
+
+ #define WATCHDOG_RESET hw_watchdog_reset
+ #endif /* __ASSEMBLY__ */
+#else
+ /*
+ * Maybe a software watchdog?
+ */
+ #if defined(CONFIG_WATCHDOG)
+ #if defined(__ASSEMBLY__)
+ #define WATCHDOG_RESET bl watchdog_reset
+ #else
+ extern void watchdog_reset(void);
+
+ #define WATCHDOG_RESET watchdog_reset
+ #endif
+ #else
+ /*
+ * No hardware or software watchdog.
+ */
+ #if defined(__ASSEMBLY__)
+ #define WATCHDOG_RESET /*XXX DO_NOT_DEL_THIS_COMMENT*/
+ #else
+ #define WATCHDOG_RESET() {}
+ #endif /* __ASSEMBLY__ */
+ #endif /* CONFIG_WATCHDOG && !__ASSEMBLY__ */
+#endif /* CONFIG_HW_WATCHDOG */
+
+/*
+ * Prototypes from $(CPU)/cpu.c.
+ */
+
+/* MPC 8xx */
+#if (defined(CONFIG_8xx) || defined(CONFIG_MPC860)) && !defined(__ASSEMBLY__)
+ void reset_8xx_watchdog(volatile immap_t *immr);
+#endif
+
+/* IBM 4xx */
+#if defined(CONFIG_4xx) && !defined(__ASSEMBLY__)
+ void reset_4xx_watchdog(void);
+#endif
+
+/* MPC 8260 */
+#if defined(CONFIG_MPC8260) && !defined(__ASSEMBLY__)
+#if defined(CONFIG_WATCHDOG)
+extern __inline__ void
+reset_8260_watchdog(volatile immap_t *immr)
+{
+ immr->im_siu_conf.sc_swsr = 0x556c;
+ immr->im_siu_conf.sc_swsr = 0xaa39;
+}
+#endif /* !__ASSEMBLY__ && CONFIG_WATCHDOG */
+#endif /* CONFIG_MPC8260 && !__ASSEMBLY__ */
+
+#endif /* _WATCHDOG_H_ */
+
