Merge branch 'master' of git://git.denx.de/u-boot-arm

diff --git a/MAINTAINERS b/MAINTAINERS
index 439c1b8..e9db278 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS

@@ -928,6 +928,7 @@
 	CM-BF527	BF527
 	CM-BF533	BF533
 	CM-BF537E	BF537
+	CM-BF537U	BF537
 	CM-BF548	BF548
 	CM-BF561	BF561
 	TCM-BF537	BF537

diff --git a/MAKEALL b/MAKEALL
index 13f3f5e..f0ed8ea 100755
--- a/MAKEALL
+++ b/MAKEALL

@@ -843,6 +843,7 @@
 	cm-bf527	\
 	cm-bf533	\
 	cm-bf537e	\
+	cm-bf537u	\
 	cm-bf548	\
 	cm-bf561	\
 	ibf-dsp561	\

diff --git a/Makefile b/Makefile
index df22bff..0449a5b 100644
--- a/Makefile
+++ b/Makefile

@@ -3551,7 +3551,7 @@
 	bf537-pnav bf537-stamp bf538f-ezkit bf548-ezkit bf561-ezkit
 
 # Bluetechnix tinyboards
-BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf548 cm-bf561 tcm-bf537
+BFIN_BOARDS += cm-bf527 cm-bf533 cm-bf537e cm-bf537u cm-bf548 cm-bf561 tcm-bf537
 
 # Misc third party boards
 BFIN_BOARDS += bf537-minotaur bf537-srv1 blackstamp

diff --git a/README b/README
index 246ae2b..c90f6ee 100644
--- a/README
+++ b/README

@@ -3912,10 +3912,10 @@
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 
-On Blackfin, the normal C ABI (except for P5) is followed as documented here:
+On Blackfin, the normal C ABI (except for P3) is followed as documented here:
 	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
 
-    ==> U-Boot will use P5 to hold a pointer to the global data
+    ==> U-Boot will use P3 to hold a pointer to the global data
 
 On ARM, the following registers are used:
 

diff --git a/board/cm-bf537u/Makefile b/board/cm-bf537u/Makefile
new file mode 100644
index 0000000..3812ba1
--- /dev/null
+++ b/board/cm-bf537u/Makefile

@@ -0,0 +1,54 @@
+#
+# U-boot - Makefile
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2000-2006
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+include $(TOPDIR)/config.mk
+
+LIB	= $(obj)lib$(BOARD).a
+
+COBJS-y	:= $(BOARD).o flash.o gpio_cfi_flash.o
+
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(COBJS-y))
+SOBJS	:= $(addprefix $(obj),$(SOBJS-y))
+
+$(LIB):	$(obj).depend $(OBJS) $(SOBJS)
+	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)
+
+clean:
+	rm -f $(SOBJS) $(OBJS)
+
+distclean:	clean
+	rm -f $(LIB) core *.bak $(obj).depend
+
+#########################################################################
+
+# defines $(obj).depend target
+include $(SRCTREE)/rules.mk
+
+sinclude $(obj).depend
+
+#########################################################################

diff --git a/board/cm-bf537u/cm-bf537u.c b/board/cm-bf537u/cm-bf537u.c
new file mode 100644
index 0000000..9628e0f
--- /dev/null
+++ b/board/cm-bf537u/cm-bf537u.c

@@ -0,0 +1,66 @@
+/*
+ * U-boot - main board file
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <net.h>
+#include <netdev.h>
+#include <asm/blackfin.h>
+#include <asm/net.h>
+#include "gpio_cfi_flash.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int checkboard(void)
+{
+	printf("Board: Bluetechnix CM-BF537U board\n");
+	printf("       Support: http://www.bluetechnix.at/\n");
+	return 0;
+}
+
+phys_size_t initdram(int board_type)
+{
+	gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
+	gd->bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
+	return gd->bd->bi_memsize;
+}
+
+#ifdef CONFIG_BFIN_MAC
+static void board_init_enetaddr(uchar *mac_addr)
+{
+	puts("Warning: Generating 'random' MAC address\n");
+	bfin_gen_rand_mac(mac_addr);
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+}
+
+int board_eth_init(bd_t *bis)
+{
+	return bfin_EMAC_initialize(bis);
+}
+#endif
+
+#ifdef CONFIG_SMC911X
+int board_eth_init(bd_t *bis)
+{
+	return smc911x_initialize(0, CONFIG_SMC911X_BASE);
+}
+#endif
+
+int misc_init_r(void)
+{
+#ifdef CONFIG_BFIN_MAC
+	uchar enetaddr[6];
+	if (!eth_getenv_enetaddr("ethaddr", enetaddr))
+		board_init_enetaddr(enetaddr);
+#endif
+
+	gpio_cfi_flash_init();
+
+	return 0;
+}

diff --git a/board/cm-bf537u/config.mk b/board/cm-bf537u/config.mk
new file mode 100644
index 0000000..3c0b46f
--- /dev/null
+++ b/board/cm-bf537u/config.mk

@@ -0,0 +1,34 @@
+#
+# Copyright (c) 2005-2008 Analog Device Inc.
+#
+# (C) Copyright 2001
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+
+# This is not actually used for Blackfin boards so do not change it
+#TEXT_BASE = do-not-use-me
+
+CFLAGS_lib_generic += -O2
+CFLAGS_lzma += -O2
+
+# Set some default LDR flags based on boot mode.
+LDR_FLAGS-BFIN_BOOT_PARA := --bits 16 --dma 8
+LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))

diff --git a/board/cm-bf537u/flash.c b/board/cm-bf537u/flash.c
new file mode 100644
index 0000000..ebe17b6
--- /dev/null
+++ b/board/cm-bf537u/flash.c

@@ -0,0 +1,34 @@
+/*
+ * flash.c - helper commands for working with GPIO-assisted flash
+ *
+ * Copyright (c) 2005-2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/blackfin.h>
+#include "gpio_cfi_flash.h"
+
+int do_ph(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	ulong faddr = CONFIG_SYS_FLASH_BASE;
+	ushort data;
+	ulong dflg;
+
+	if (argc > 1) {
+		dflg = simple_strtoul(argv[1], NULL, 16);
+		faddr |= (dflg << 21);
+		gpio_cfi_flash_swizzle((void *)faddr);
+	} else {
+		data = bfin_read_PORTHIO();
+		printf("Port H data %04x (PH0:%i)\n", data, !!(data & PH0));
+	}
+
+	return 0;
+}
+
+U_BOOT_CMD(ph, 3, 0, do_ph,
+	"set/clear PH0 GPIO flash bank switch\n",
+	"<ph0> - set PH0 GPIO pin state\n");

diff --git a/board/cm-bf537u/gpio_cfi_flash.c b/board/cm-bf537u/gpio_cfi_flash.c
new file mode 100644
index 0000000..68633ec
--- /dev/null
+++ b/board/cm-bf537u/gpio_cfi_flash.c

@@ -0,0 +1,60 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+#include <common.h>
+#include <asm/blackfin.h>
+#include <asm/io.h>
+#include "gpio_cfi_flash.h"
+
+#define GPIO_PIN_1  PH0
+#define GPIO_MASK_1 (1 << 21)
+#define GPIO_MASK   (GPIO_MASK_1)
+
+void *gpio_cfi_flash_swizzle(void *vaddr)
+{
+	unsigned long addr = (unsigned long)vaddr;
+
+	if (addr & GPIO_MASK_1)
+		bfin_write_PORTHIO_SET(GPIO_PIN_1);
+	else
+		bfin_write_PORTHIO_CLEAR(GPIO_PIN_1);
+
+#ifdef GPIO_MASK_2
+	if (addr & GPIO_MASK_2)
+		bfin_write_PORTGIO_SET(GPIO_PIN_2);
+	else
+		bfin_write_PORTGIO_CLEAR(GPIO_PIN_2);
+#endif
+
+	SSYNC();
+
+	return (void *)(addr & ~GPIO_MASK);
+}
+
+#define __raw_writeq(value, addr) *(volatile u64 *)addr = value
+#define __raw_readq(addr) *(volatile u64 *)addr
+
+#define MAKE_FLASH(size, sfx) \
+void flash_write##size(u##size value, void *addr) \
+{ \
+	__raw_write##sfx(value, gpio_cfi_flash_swizzle(addr)); \
+} \
+u##size flash_read##size(void *addr) \
+{ \
+	return __raw_read##sfx(gpio_cfi_flash_swizzle(addr)); \
+}
+MAKE_FLASH(8, b)  /* flash_write8()  flash_read8() */
+MAKE_FLASH(16, w) /* flash_write16() flash_read16() */
+MAKE_FLASH(32, l) /* flash_write32() flash_read32() */
+MAKE_FLASH(64, q) /* flash_write64() flash_read64() */
+
+void gpio_cfi_flash_init(void)
+{
+	bfin_write_PORTHIO_DIR(bfin_read_PORTHIO_DIR() | GPIO_PIN_1);
+	gpio_cfi_flash_swizzle((void *)CONFIG_SYS_FLASH_BASE);
+}

diff --git a/board/cm-bf537u/gpio_cfi_flash.h b/board/cm-bf537u/gpio_cfi_flash.h
new file mode 100644
index 0000000..5211e97
--- /dev/null
+++ b/board/cm-bf537u/gpio_cfi_flash.h

@@ -0,0 +1,10 @@
+/*
+ * gpio_cfi_flash.c - GPIO-assisted Flash Chip Support
+ *
+ * Copyright (c) 2009 Analog Devices Inc.
+ *
+ * Licensed under the GPL-2 or later.
+ */
+
+void *gpio_cfi_flash_swizzle(void *vaddr);
+void gpio_cfi_flash_init(void);

diff --git a/board/cm-bf548/video.c b/board/cm-bf548/video.c
index 49dbe77..0787342 100644
--- a/board/cm-bf548/video.c
+++ b/board/cm-bf548/video.c

@@ -14,7 +14,7 @@
 #include <asm/mach-common/bits/dma.h>
 #include <i2c.h>
 #include <linux/types.h>
-#include <devices.h>
+#include <stdio_dev.h>
 
 int gunzip(void *, int, unsigned char *, unsigned long *);
 
@@ -291,7 +291,7 @@
 int drv_video_init(void)
 {
 	int error, devices = 1;
-	device_t videodev;
+	struct stdio_dev videodev;
 
 	u8 *dst;
 	u32 fbmem_size =
@@ -331,7 +331,7 @@
 	videodev.putc = video_putc;	/* 'putc' function */
 	videodev.puts = video_puts;	/* 'puts' function */
 
-	error = device_register(&videodev);
+	error = stdio_register(&videodev);
 
 	return (error == 0) ? devices : error;
 }

diff --git a/board/eNET/Makefile b/board/eNET/Makefile
index 4813b4b..588d21d 100644
--- a/board/eNET/Makefile
+++ b/board/eNET/Makefile

@@ -31,12 +31,13 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= eNET.o
-SOBJS	:= eNET_start16.o eNET_start.o
+COBJS-y	+= eNET.o
+COBJS-$(CONFIG_PCI) += eNET_pci.o
+SOBJS-y	+= eNET_start16.o
+SOBJS-y	+= eNET_start.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

diff --git a/board/eNET/eNET.c b/board/eNET/eNET.c
index 57dd635..29cf295 100644
--- a/board/eNET/eNET.c
+++ b/board/eNET/eNET.c

@@ -46,17 +46,17 @@
 void init_sc520_enet (void)
 {
 	/* Set CPU Speed to 100MHz */
-	write_mmcr_byte(SC520_CPUCTL, 1);
+	sc520_mmcr->cpuctl = 0x01;
 	gd->cpu_clk = 100000000;
 
 	/* wait at least one millisecond */
 	asm("movl	$0x2000,%%ecx\n"
-	    "wait_loop:	pushl %%ecx\n"
+	    "0:	pushl %%ecx\n"
 	    "popl	%%ecx\n"
-	    "loop wait_loop\n": : : "ecx");
+	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	write_mmcr_byte(SC520_DBCTL, 0x11);
+	sc520_mmcr->dbctl = 0x11;
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -71,51 +71,51 @@
 {
 	init_sc520_enet();
 
-	write_mmcr_byte(SC520_GPCSRT, 0x01);		/* GP Chip Select Recovery Time */
-	write_mmcr_byte(SC520_GPCSPW, 0x07);		/* GP Chip Select Pulse Width */
-	write_mmcr_byte(SC520_GPCSOFF, 0x00);		/* GP Chip Select Offset */
-	write_mmcr_byte(SC520_GPRDW, 0x05);		/* GP Read pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 0x01);		/* GP Read offset */
-	write_mmcr_byte(SC520_GPWRW, 0x05);		/* GP Write pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 0x01);		/* GP Write offset */
+	sc520_mmcr->gpcsrt = 0x01;		/* GP Chip Select Recovery Time */
+	sc520_mmcr->gpcspw = 0x07;		/* GP Chip Select Pulse Width */
+	sc520_mmcr->gpcsoff = 0x00;		/* GP Chip Select Offset */
+	sc520_mmcr->gprdw = 0x05;		/* GP Read pulse width */
+	sc520_mmcr->gprdoff = 0x01;		/* GP Read offset */
+	sc520_mmcr->gpwrw = 0x05;		/* GP Write pulse width */
+	sc520_mmcr->gpwroff = 0x01;		/* GP Write offset */
 
-	write_mmcr_word(SC520_PIODATA15_0, 0x0630);	/* PIO15_PIO0 Data */
-	write_mmcr_word(SC520_PIODATA31_16, 0x2000);	/* PIO31_PIO16 Data */
-	write_mmcr_word(SC520_PIODIR31_16, 0x2000);	/* GPIO Direction */
-	write_mmcr_word(SC520_PIODIR15_0, 0x87b5);	/* GPIO Direction */
-	write_mmcr_word(SC520_PIOPFS31_16, 0x0dfe);	/* GPIO pin function 31-16 reg */
-	write_mmcr_word(SC520_PIOPFS15_0, 0x200a);	/* GPIO pin function 15-0 reg */
-	write_mmcr_byte(SC520_CSPFS, 0x00f8);		/* Chip Select Pin Function Select */
+	sc520_mmcr->piodata15_0 = 0x0630;	/* PIO15_PIO0 Data */
+	sc520_mmcr->piodata31_16 = 0x2000;	/* PIO31_PIO16 Data */
+	sc520_mmcr->piodir31_16 = 0x2000;	/* GPIO Direction */
+	sc520_mmcr->piodir15_0 = 0x87b5;	/* GPIO Direction */
+	sc520_mmcr->piopfs31_16 = 0x0dfe;	/* GPIO pin function 31-16 reg */
+	sc520_mmcr->piopfs15_0 = 0x200a;	/* GPIO pin function 15-0 reg */
+	sc520_mmcr->cspfs = 0x00f8;		/* Chip Select Pin Function Select */
 
-	write_mmcr_long(SC520_PAR2, 0x200713f8);	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR3, 0x2c0712f8);	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR4, 0x300711f8);	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR5, 0x340710f8);	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
-	write_mmcr_long(SC520_PAR6, 0xe3ffc000);	/* SDRAM (0x00000000, 128MB) */
-	write_mmcr_long(SC520_PAR7, 0xaa3fd000);	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
-	write_mmcr_long(SC520_PAR8, 0xca3fd100);	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
-	write_mmcr_long(SC520_PAR9, 0x4203d900);	/* SRAM (GPCS0, 0x19000000, 1MB) */
-	write_mmcr_long(SC520_PAR10, 0x4e03d910);	/* SRAM (GPCS3, 0x19100000, 1MB) */
-	write_mmcr_long(SC520_PAR11, 0x50018100);	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
-	write_mmcr_long(SC520_PAR12, 0x54020000);	/* CFLASH1 (0x200000000, 4kB) */
-	write_mmcr_long(SC520_PAR13, 0x5c020001);	/* CFLASH2 (0x200010000, 4kB) */
-/*	write_mmcr_long(SC520_PAR14, 0x8bfff800); */	/* BOOTCS at  0x18000000 */
-/*	write_mmcr_long(SC520_PAR15, 0x38201000); */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
+	sc520_mmcr->par[2] = 0x200713f8;	/* Uart A (GPCS0, 0x013f8, 8 Bytes) */
+	sc520_mmcr->par[3] = 0x2c0712f8;	/* Uart B (GPCS3, 0x012f8, 8 Bytes) */
+	sc520_mmcr->par[4] = 0x300711f8;	/* Uart C (GPCS4, 0x011f8, 8 Bytes) */
+	sc520_mmcr->par[5] = 0x340710f8;	/* Uart D (GPCS5, 0x010f8, 8 Bytes) */
+	sc520_mmcr->par[6] =  0xe3ffc000;	/* SDRAM (0x00000000, 128MB) */
+	sc520_mmcr->par[7] = 0xaa3fd000;	/* StrataFlash (ROMCS1, 0x10000000, 16MB) */
+	sc520_mmcr->par[8] = 0xca3fd100;	/* StrataFlash (ROMCS2, 0x11000000, 16MB) */
+	sc520_mmcr->par[9] = 0x4203d900;	/* SRAM (GPCS0, 0x19000000, 1MB) */
+	sc520_mmcr->par[10] = 0x4e03d910;	/* SRAM (GPCS3, 0x19100000, 1MB) */
+	sc520_mmcr->par[11] = 0x50018100;	/* DP-RAM (GPCS4, 0x18100000, 4kB) */
+	sc520_mmcr->par[12] = 0x54020000;	/* CFLASH1 (0x200000000, 4kB) */
+	sc520_mmcr->par[13] = 0x5c020001;	/* CFLASH2 (0x200010000, 4kB) */
+/*	sc520_mmcr->par14 = 0x8bfff800; */	/* BOOTCS at  0x18000000 */
+/*	sc520_mmcr->par15 = 0x38201000; */	/* LEDs etc (GPCS6, 0x1000, 20 Bytes */
 
 	/* Disable Watchdog */
-	write_mmcr_word(0x0cb0, 0x3333);
-	write_mmcr_word(0x0cb0, 0xcccc);
-	write_mmcr_word(0x0cb0, 0x0000);
+	sc520_mmcr->wdtmrctl = 0x3333;
+	sc520_mmcr->wdtmrctl = 0xcccc;
+	sc520_mmcr->wdtmrctl = 0x0000;
 
 	/* Chip Select Configuration */
-	write_mmcr_word(SC520_BOOTCSCTL, 0x0033);
-	write_mmcr_word(SC520_ROMCS1CTL, 0x0615);
-	write_mmcr_word(SC520_ROMCS2CTL, 0x0615);
+	sc520_mmcr->bootcsctl = 0x0033;
+	sc520_mmcr->romcs1ctl = 0x0615;
+	sc520_mmcr->romcs2ctl = 0x0615;
 
-	write_mmcr_byte(SC520_ADDDECCTL, 0x02);
-	write_mmcr_byte(SC520_UART1CTL, 0x07);
-	write_mmcr_byte(SC520_SYSARBCTL,0x06);
-	write_mmcr_word(SC520_SYSARBMENB, 0x0003);
+	sc520_mmcr->adddecctl = 0x02;
+	sc520_mmcr->uart1ctl = 0x07;
+	sc520_mmcr->sysarbctl = 0x06;
+	sc520_mmcr->sysarbmenb = 0x0003;
 
 	/* Crystal is 33.000MHz */
 	gd->bus_clk = 33000000;

diff --git a/board/eNET/eNET_pci.c b/board/eNET/eNET_pci.c
new file mode 100644
index 0000000..e80a8fe
--- /dev/null
+++ b/board/eNET/eNET_pci.c

@@ -0,0 +1,95 @@
+/*
+ * (C) Copyright 2008
+ * Graeme Russ, graeme.russ@gmail.com.
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#include <common.h>
+#include <pci.h>
+#include <asm/pci.h>
+#include <asm/ic/pci.h>
+
+static void pci_enet_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of IRQs to steal when we need one */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin -= 1; /* PCI config space use 1-based numbering */
+	if (pin == -1) {
+		return; /* device use no irq */
+	}
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 12:	/* First Ethernet Chip */
+		pin += SC520_PCI_INTA;
+		break;
+
+	case 13:	/* Second Ethernet Chip */
+		pin += SC520_PCI_INTB;
+		break;
+
+	default:
+		return;
+	}
+
+	pin &= 3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+	if (-1 != sc520_pci_ints[pin]) {
+	pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller enet_hose = {
+	fixup_irq: pci_enet_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&enet_hose);
+}

diff --git a/board/lwmon/lwmon.c b/board/lwmon/lwmon.c
index 75b3209..8e27778 100644
--- a/board/lwmon/lwmon.c
+++ b/board/lwmon/lwmon.c

@@ -7,7 +7,6 @@
  * (C) Copyright 2001, 2002
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
 D* Design:        wd@denx.de
 C* Coding:        wd@denx.de

diff --git a/board/sc520_cdp/Makefile b/board/sc520_cdp/Makefile
index 0d2800d..7944a01 100644
--- a/board/sc520_cdp/Makefile
+++ b/board/sc520_cdp/Makefile

@@ -28,12 +28,14 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= sc520_cdp.o flash.o
-SOBJS	:= sc520_cdp_asm.o sc520_cdp_asm16.o
+COBJS-y	+= sc520_cdp.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_PCI) += sc520_cdp_pci.o
+SOBJS-y	+= sc520_cdp_asm.o
+SOBJS-y	+= sc520_cdp_asm16.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

diff --git a/board/sc520_cdp/flash.c b/board/sc520_cdp/flash.c
index dcb8c57..64831b7 100644
--- a/board/sc520_cdp/flash.c
+++ b/board/sc520_cdp/flash.c

@@ -337,12 +337,12 @@
 	unsigned micro; \
 	unsigned milli=0; \
 	\
-	micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
+	micro = sc520_mmcr->swtmrmilli; \
 	 \
 	for (;;) { \
 		\
-		milli += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); \
-		micro = *(volatile u16*)(0xfffef000+SC520_SWTMRMICRO); \
+		milli += sc520_mmcr->swtmrmilli; \
+		micro = sc520_mmcr->swtmrmicro; \
 		\
 		if ((delay) <= (micro + (milli * 1000))) { \
 			break; \
@@ -364,12 +364,12 @@
 	/* Sector erase command comes last */
 	*(volatile u32*)(addr + sector) = 0x30303030;
 
-	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
 	elapsed = 0;
 	__udelay(50);
 	while (((*(volatile u32*)(addr + sector)) & 0x80808080) != 0x80808080) {
 
-		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		elapsed += sc520_mmcr->swtmrmilli;
 		if (elapsed > ((CONFIG_SYS_FLASH_ERASE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			*(volatile u32*)(addr) = 0xf0f0f0f0;
 			return 1;
@@ -487,12 +487,12 @@
 
 	dest2[0] = data;
 
-	elapsed = *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI); /* dummy read */
+	elapsed = sc520_mmcr->swtmrmilli; /* dummy read */
 	elapsed = 0;
 
 	/* data polling for D7 */
 	while ((dest2[0] & 0x80808080) != (data2[0] & 0x80808080)) {
-		elapsed += *(volatile u16*)(0xfffef000+SC520_SWTMRMILLI);
+		elapsed += sc520_mmcr->swtmrmilli;
 		if (elapsed > ((CONFIG_SYS_FLASH_WRITE_TOUT/CONFIG_SYS_HZ) * 1000)) {
 			addr2[0] = 0xf0f0f0f0;
 			return 1;

diff --git a/board/sc520_cdp/sc520_cdp.c b/board/sc520_cdp/sc520_cdp.c
index 830ec37..4c44b24 100644
--- a/board/sc520_cdp/sc520_cdp.c
+++ b/board/sc520_cdp/sc520_cdp.c

@@ -23,9 +23,7 @@
  */
 
 #include <common.h>
-#include <pci.h>
 #include <asm/io.h>
-#include <asm/pci.h>
 #include <asm/ic/sc520.h>
 #include <ali512x.h>
 #include <spi.h>
@@ -57,144 +55,62 @@
 static void irq_init(void)
 {
 	/* disable global interrupt mode */
-	write_mmcr_byte(SC520_PICICR, 0x40);
+	sc520_mmcr->picicr = 0x40;
 
 	/* set all irqs to edge */
-	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
-	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	sc520_mmcr->pic_mode[0] = 0x00;
+	sc520_mmcr->pic_mode[1] = 0x00;
+	sc520_mmcr->pic_mode[2] = 0x00;
 
 	/* active low polarity on PIC interrupt pins,
 	 *  active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+	sc520_mmcr->intpinpol = 0x0000;
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
-	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
-	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
-	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
-	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
-	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
-	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
-	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ_DISABLED);      /* disable Synchronius serial INT */
-	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
-	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED;	/* disable GP timer 0 INT */
+	sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED;	/* disable GP timer 1 INT */
+	sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED;	/* disable GP timer 2 INT */
+	sc520_mmcr->pit_int_map[0] = SC520_IRQ0;		/* Set PIT timer 0 INT to IRQ0 */
+	sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED;	/* disable PIT timer 1 INT */
+	sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED;	/* disable PIT timer 2 INT */
+	sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED;	/* disable PCI INT A */
+	sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED;	/* disable PCI INT B */
+	sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED;	/* disable PCI INT C */
+	sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED;	/* disable PCI INT D */
+	sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED;		/* disable DMA INT */
+	sc520_mmcr->ssimap = SC520_IRQ_DISABLED;		/* disable Synchronius serial INT */
+	sc520_mmcr->wdtmap = SC520_IRQ_DISABLED;		/* disable Watchdog INT */
+	sc520_mmcr->rtcmap = SC520_IRQ8;			/* Set RTC int to 8 */
+	sc520_mmcr->wpvmap = SC520_IRQ_DISABLED;		/* disable write protect INT */
+	sc520_mmcr->icemap = SC520_IRQ1;			/* Set ICE Debug Serielport INT to IRQ1 */
+	sc520_mmcr->ferrmap = SC520_IRQ13; 			/* Set FP error INT to IRQ13 */
 
 	if (CONFIG_SYS_USE_SIO_UART) {
-		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ_DISABLED); /* disable internal UART1 INT */
-		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ_DISABLED); /* disable internal UART2 INT */
-		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ3);          /* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
-		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ4);          /* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
+		sc520_mmcr->uart_int_map[0] = SC520_IRQ_DISABLED;	/* disable internal UART1 INT */
+		sc520_mmcr->uart_int_map[1] = SC520_IRQ_DISABLED;	/* disable internal UART2 INT */
+		sc520_mmcr->gp_int_map[3] = SC520_IRQ3;		/* Set GPIRQ3 (ISA IRQ3) to IRQ3 */
+		sc520_mmcr->gp_int_map[4] = SC520_IRQ4;		/* Set GPIRQ4 (ISA IRQ4) to IRQ4 */
 	} else {
-		write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);         /* Set internal UART2 INT to IRQ4 */
-		write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);         /* Set internal UART2 INT to IRQ3 */
-		write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ3 (ISA IRQ3) */
-		write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);  /* disable GPIRQ4 (ISA IRQ4) */
+		sc520_mmcr->uart_int_map[0] = SC520_IRQ4;		/* Set internal UART2 INT to IRQ4 */
+		sc520_mmcr->uart_int_map[1] = SC520_IRQ3;		/* Set internal UART2 INT to IRQ3 */
+		sc520_mmcr->gp_int_map[3] = SC520_IRQ_DISABLED;	/* disable GPIRQ3 (ISA IRQ3) */
+		sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED;	/* disable GPIRQ4 (ISA IRQ4) */
 	}
 
-	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ1);             /* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
-	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ5);             /* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ6);             /* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ7);             /* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ8);             /* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ9);             /* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
-	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ11);            /* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
-	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ12);            /* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
-	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ14);            /* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
+	sc520_mmcr->gp_int_map[1] = SC520_IRQ1;			/* Set GPIRQ1 (SIO IRQ1) to IRQ1 */
+	sc520_mmcr->gp_int_map[5] = SC520_IRQ5;			/* Set GPIRQ5 (ISA IRQ5) to IRQ5 */
+	sc520_mmcr->gp_int_map[6] = SC520_IRQ6;			/* Set GPIRQ6 (ISA IRQ6) to IRQ6 */
+	sc520_mmcr->gp_int_map[7] = SC520_IRQ7;			/* Set GPIRQ7 (ISA IRQ7) to IRQ7 */
+	sc520_mmcr->gp_int_map[8] = SC520_IRQ8;			/* Set GPIRQ8 (SIO IRQ8) to IRQ8 */
+	sc520_mmcr->gp_int_map[9] = SC520_IRQ9;			/* Set GPIRQ9 (ISA IRQ2) to IRQ9 */
+	sc520_mmcr->gp_int_map[0] = SC520_IRQ11;		/* Set GPIRQ0 (ISA IRQ11) to IRQ10 */
+	sc520_mmcr->gp_int_map[2] = SC520_IRQ12;		/* Set GPIRQ2 (ISA IRQ12) to IRQ12 */
+	sc520_mmcr->gp_int_map[10] = SC520_IRQ14;		/* Set GPIRQ10 (ISA IRQ14) to IRQ14 */
 
-	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);                /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP, 0x100);                    /* Map SDRAM ECC failure INT to NMI */
-
+	sc520_mmcr->pcihostmap = 0x11f;				/* Map PCI hostbridge INT to NMI */
+	sc520_mmcr->eccmap = 0x100;				/* Map SDRAM ECC failure INT to NMI */
 }
 
-#ifdef CONFIG_PCI
-/* PCI stuff */
-static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* a configurable lists of irqs to steal
-	 * when we need one (a board with more pci interrupt pins
-	 * would use a larger table */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index=0;
-
-	uchar tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin-=1; /* pci config space use 1-based numbering */
-	if (-1 == pin) {
-		return; /* device use no irq */
-	}
-
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 20:
-		pin+=SC520_PCI_INTA;
-		break;
-
-	case 19:
-		pin+=SC520_PCI_INTB;
-		break;
-
-	case 18:
-		pin+=SC520_PCI_INTC;
-		break;
-
-	case 17:
-		pin+=SC520_PCI_INTD;
-		break;
-
-	default:
-		return;
-	}
-
-	pin&=3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3) {
-			return;
-		}
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
-			return;
-		}
-		next_irq_index++;
-	}
-
-
-	if (-1 != sc520_pci_ints[pin]) {
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-	}
-	PRINTF("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-}
-
-static struct pci_controller sc520_cdp_hose = {
-	fixup_irq: pci_sc520_cdp_fixup_irq,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&sc520_cdp_hose);
-}
-#endif
-
 static void silence_uart(int port)
 {
 	outb(0, port+1);
@@ -234,23 +150,22 @@
 {
 
 	/* set up the GP IO pins */
-	write_mmcr_word(SC520_PIOPFS31_16, 0xf7ff);	/* set the GPIO pin function 31-16 reg */
-	write_mmcr_word(SC520_PIOPFS15_0, 0xffff);	/* set the GPIO pin function 15-0 reg */
-	write_mmcr_byte(SC520_CSPFS, 0xf8);		/* set the CS pin function  reg */
-	write_mmcr_byte(SC520_CLKSEL, 0x70);
+	sc520_mmcr->piopfs31_16 = 0xf7ff;	/* set the GPIO pin function 31-16 reg */
+	sc520_mmcr->piopfs15_0 = 0xffff;	/* set the GPIO pin function 15-0 reg */
+	sc520_mmcr->cspfs = 0xf8;		/* set the CS pin function  reg */
+	sc520_mmcr->clksel = 0x70;
 
+	sc520_mmcr->gpcsrt = 1;   		/* set the GP CS offset */
+	sc520_mmcr->gpcspw = 3;   		/* set the GP CS pulse width */
+	sc520_mmcr->gpcsoff = 1;  		/* set the GP CS offset */
+	sc520_mmcr->gprdw = 3;    		/* set the RD pulse width */
+	sc520_mmcr->gprdoff = 1;  		/* set the GP RD offset */
+	sc520_mmcr->gpwrw = 3;   		 /* set the GP WR pulse width */
+	sc520_mmcr->gpwroff = 1; 		 /* set the GP WR offset */
 
-	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
-	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
-	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
-
-	write_mmcr_word(SC520_BOOTCSCTL, 0x1823);		/* set up timing of BOOTCS */
-	write_mmcr_word(SC520_ROMCS1CTL, 0x1823);		/* set up timing of ROMCS1 */
-	write_mmcr_word(SC520_ROMCS2CTL, 0x1823);		/* set up timing of ROMCS2 */
+	sc520_mmcr->bootcsctl = 0x1823;		/* set up timing of BOOTCS */
+	sc520_mmcr->romcs1ctl = 0x1823;		/* set up timing of ROMCS1 */
+	sc520_mmcr->romcs2ctl = 0x1823;		/* set up timing of ROMCS2 */
 
 	/* adjust the memory map:
 	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -259,31 +174,31 @@
 
 
 	/* SRAM = GPCS3 128k @ d0000-effff*/
-	write_mmcr_long(SC520_PAR2,  0x4e00400d);
+	sc520_mmcr->par[2] = 0x4e00400d;
 
 	/* IDE0 = GPCS6 1f0-1f7 */
-	write_mmcr_long(SC520_PAR3,  0x380801f0);
+	sc520_mmcr->par[3] = 0x380801f0;
 
 	/* IDE1 = GPCS7 3f6 */
-	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+	sc520_mmcr->par[4] = 0x3c0003f6;
 	/* bootcs */
-	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+	sc520_mmcr->par[12] = 0x8bffe800;
 	/* romcs2 */
-	write_mmcr_long(SC520_PAR13, 0xcbfff000);
+	sc520_mmcr->par[13] = 0xcbfff000;
 	/* romcs1 */
-	write_mmcr_long(SC520_PAR14, 0xabfff800);
+	sc520_mmcr->par[14] = 0xabfff800;
 	/* 680 LEDS */
-	write_mmcr_long(SC520_PAR15, 0x30000640);
+	sc520_mmcr->par[15] = 0x30000640;
 
-	write_mmcr_byte(SC520_ADDDECCTL, 0);
+	sc520_mmcr->adddecctl = 0;
 
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
 	if (CONFIG_SYS_USE_SIO_UART) {
-		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) | UART2_DIS|UART1_DIS);
+		sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | UART2_DIS | UART1_DIS;
 		setup_ali_sio(1);
 	} else {
-		write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+		sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
 		setup_ali_sio(0);
 		silence_uart(0x3e8);
 		silence_uart(0x2e8);
@@ -323,162 +238,6 @@
  */
 
 /*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
-	u32 par;
-
-	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
-	       size, bus_addr);
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 12;
-	par--;
-	par&=0x7f;
-	par <<= 18;
-	par |= (bus_addr>>12);
-	par |= 0x50000000;
-
-	PRINTF ("setting PAR11 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR11,  par);
-
-	return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
-	PRINTF("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
-		write_mmcr_long(SC520_PAR11, 0);
-		PRINTF(" done\n");
-		return;
-	}
-	PRINTF(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
-	u32 par;
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 16;
-	par--;
-	par&=0x7ff;
-	par <<= 14;
-	par |= (PCI_ROM_TEMP_SPACE>>16);
-	par |= 0x72000000;
-
-	PRINTF ("setting PAR1 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR1,  par);
-
-	return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
-	PRINTF("pci_remove_rom_window: %x", addr);
-	if (addr == PCI_ROM_TEMP_SPACE) {
-		write_mmcr_long(SC520_PAR1, 0);
-		PRINTF(" done\n");
-		return;
-	}
-	PRINTF(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
-	/* Map video memory to 0xa0000*/
-	write_mmcr_long(SC520_PAR0,  0x7200400a);
-
-	/* forward all I/O accesses to PCI */
-	write_mmcr_byte(SC520_ADDDECCTL,
-			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
-
-
-	/* so we map away all io ports to pci (only way to access pci io
-	 * below 0x400. But then we have to map back the portions that we dont
-	 * use so that the generate cycles on the GPIO bus where the sio and
-	 * ISA slots are connected, this requre the use of several PAR registers
-	 */
-
-	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
-	write_mmcr_long(SC520_PAR5, 0x30ef0100);
-
-	/* IDE use 1f0-1f7 */
-
-	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
-	write_mmcr_long(SC520_PAR6, 0x30ff01f8);
-
-	/* com2 use 2f8-2ff */
-
-	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	write_mmcr_long(SC520_PAR7, 0x30af0300);
-
-	/* vga use 3b0-3bb */
-
-	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	write_mmcr_long(SC520_PAR8, 0x300303bc);
-
-	/* vga use 3c0-3df */
-
-	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
-	write_mmcr_long(SC520_PAR9, 0x301503e0);
-
-	/* ide use 3f6 */
-
-	/* bring 0x3f7  back to ISA using PAR10 */
-	write_mmcr_long(SC520_PAR10, 0x300003f7);
-
-	/* com1 use 3f8-3ff */
-
-	return 0;
-}
-#endif
-
-/*
  * Miscelaneous platform dependent initialisations
  */
 
@@ -489,12 +248,12 @@
 	irq_init();
 
 	/* max drive current on SDRAM */
-	write_mmcr_word(SC520_DSCTL, 0x0100);
+	sc520_mmcr->dsctl = 0x0100;
 
 	/* enter debug mode after next reset (only if jumper is also set) */
-	write_mmcr_byte(SC520_RESCFG, 0x08);
+	sc520_mmcr->rescfg = 0x08;
 	/* configure the software timer to 33.333MHz */
-	write_mmcr_byte(SC520_SWTMRCFG, 0);
+	sc520_mmcr->swtmrcfg = 0;
 	gd->bus_clk = 33333000;
 
 	return 0;

diff --git a/board/sc520_cdp/sc520_cdp_pci.c b/board/sc520_cdp/sc520_cdp_pci.c
new file mode 100644
index 0000000..ccb7988
--- /dev/null
+++ b/board/sc520_cdp/sc520_cdp_pci.c

@@ -0,0 +1,271 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#undef SC520_CDP_DEBUG
+
+#ifdef	SC520_CDP_DEBUG
+#define	PRINTF(fmt,args...)	printf (fmt ,##args)
+#else
+#define PRINTF(fmt,args...)
+#endif
+
+static void pci_sc520_cdp_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 20:
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 19:
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 18:
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 17:
+		pin+=SC520_PCI_INTD;
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+	PRINTF("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+}
+
+static struct pci_controller sc520_cdp_hose = {
+	fixup_irq: pci_sc520_cdp_fixup_irq,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_cdp_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	PRINTF("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	PRINTF ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[11] = par;
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	PRINTF("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	PRINTF ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[1] = par;
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	PRINTF("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		sc520_mmcr->par[1] = 0;
+		PRINTF(" done\n");
+		return;
+	}
+	PRINTF(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	sc520_mmcr->par[0] = 0x7200400a;
+
+	/* forward all I/O accesses to PCI */
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x1ef back to ISA using PAR5 */
+	sc520_mmcr->par[5] = 0x30ef0100;
+
+	/* IDE use 1f0-1f7 */
+
+	/* bring 0x1f8 - 0x2f7 back to ISA using PAR6 */
+	sc520_mmcr->par[6] = 0x30ff01f8;
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	sc520_mmcr->par[7] = 0x30af0300;
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	sc520_mmcr->par[8] = 0x300303bc;
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f5 back to ISA using PAR9 */
+	sc520_mmcr->par[9] = 0x301503e0;
+
+	/* ide use 3f6 */
+
+	/* bring 0x3f7  back to ISA using PAR10 */
+	sc520_mmcr->par[10] = 0x300003f7;
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}

diff --git a/board/sc520_spunk/Makefile b/board/sc520_spunk/Makefile
index e04172e..06fa2f3 100644
--- a/board/sc520_spunk/Makefile
+++ b/board/sc520_spunk/Makefile

@@ -28,12 +28,14 @@
 
 LIB	= $(obj)lib$(BOARD).a
 
-COBJS	:= sc520_spunk.o flash.o
-SOBJS	:= sc520_spunk_asm.o sc520_spunk_asm16.o
+COBJS-y	+= sc520_spunk.o
+COBJS-y	+= flash.o
+COBJS-$(CONFIG_PCI) += sc520_spunk_pci.o
+SOBJS-y	+= sc520_spunk_asm.o
+SOBJS-y	+= sc520_spunk_asm16.o
 
-SRCS	:= $(SOBJS:.o=.S) $(COBJS:.o=.c)
-OBJS	:= $(addprefix $(obj),$(COBJS))
-SOBJS	:= $(addprefix $(obj),$(SOBJS))
+SRCS	:= $(SOBJS-y:.o=.S) $(COBJS-y:.o=.c)
+OBJS	:= $(addprefix $(obj),$(SOBJS-y) $(COBJS-y))
 
 $(LIB):	$(obj).depend $(OBJS) $(SOBJS)
 	$(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS)

diff --git a/board/sc520_spunk/sc520_spunk.c b/board/sc520_spunk/sc520_spunk.c
index d3bd869..09f11bb 100644
--- a/board/sc520_spunk/sc520_spunk.c
+++ b/board/sc520_spunk/sc520_spunk.c

@@ -23,12 +23,11 @@
  */
 
 #include <common.h>
-#include <pci.h>
-#include <ssi.h>
 #include <netdev.h>
+#include <ds1722.h>
 #include <asm/io.h>
-#include <asm/pci.h>
 #include <asm/ic/sc520.h>
+#include <asm/ic/ssi.h>
 
 DECLARE_GLOBAL_DATA_PTR;
 
@@ -45,206 +44,57 @@
 static void irq_init(void)
 {
 	/* disable global interrupt mode */
-	write_mmcr_byte(SC520_PICICR, 0x40);
+	sc520_mmcr->picicr = 0x40;
 
 	/* set all irqs to edge */
-	write_mmcr_byte(SC520_MPICMODE, 0x00);
-	write_mmcr_byte(SC520_SL1PICMODE, 0x00);
-	write_mmcr_byte(SC520_SL2PICMODE, 0x00);
+	sc520_mmcr->pic_mode[0] = 0x00;
+	sc520_mmcr->pic_mode[1] = 0x00;
+	sc520_mmcr->pic_mode[2] = 0x00;
 
 	/* active low polarity on PIC interrupt pins,
 	 *  active high polarity on all other irq pins */
-	write_mmcr_word(SC520_INTPINPOL, 0x0000);
+	sc520_mmcr->intpinpol = 0x0000;
 
 	/* set irq number mapping */
-	write_mmcr_byte(SC520_GPTMR0MAP, SC520_IRQ_DISABLED);   /* disable GP timer 0 INT */
-	write_mmcr_byte(SC520_GPTMR1MAP, SC520_IRQ_DISABLED);   /* disable GP timer 1 INT */
-	write_mmcr_byte(SC520_GPTMR2MAP, SC520_IRQ_DISABLED);   /* disable GP timer 2 INT */
-	write_mmcr_byte(SC520_PIT0MAP, SC520_IRQ0);             /* Set PIT timer 0 INT to IRQ0 */
-	write_mmcr_byte(SC520_PIT1MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 1 INT */
-	write_mmcr_byte(SC520_PIT2MAP, SC520_IRQ_DISABLED);     /* disable PIT timer 2 INT */
-	write_mmcr_byte(SC520_PCIINTAMAP, SC520_IRQ_DISABLED);  /* disable PCI INT A */
-	write_mmcr_byte(SC520_PCIINTBMAP, SC520_IRQ_DISABLED);  /* disable PCI INT B */
-	write_mmcr_byte(SC520_PCIINTCMAP, SC520_IRQ_DISABLED);  /* disable PCI INT C */
-	write_mmcr_byte(SC520_PCIINTDMAP, SC520_IRQ_DISABLED);  /* disable PCI INT D */
-	write_mmcr_byte(SC520_DMABCINTMAP, SC520_IRQ_DISABLED); /* disable DMA INT */
-	write_mmcr_byte(SC520_SSIMAP, SC520_IRQ6);              /* Set Synchronius serial INT to IRQ6*/
-	write_mmcr_byte(SC520_WDTMAP, SC520_IRQ_DISABLED);      /* disable Watchdog INT */
-	write_mmcr_byte(SC520_RTCMAP, SC520_IRQ8);              /* Set RTC int to 8 */
-	write_mmcr_byte(SC520_WPVMAP, SC520_IRQ_DISABLED);      /* disable write protect INT */
-	write_mmcr_byte(SC520_ICEMAP, SC520_IRQ1);              /* Set ICE Debug Serielport INT to IRQ1 */
-	write_mmcr_byte(SC520_FERRMAP,SC520_IRQ13);             /* Set FP error INT to IRQ13 */
+	sc520_mmcr->gp_tmr_int_map[0] = SC520_IRQ_DISABLED;	/* disable GP timer 0 INT */
+	sc520_mmcr->gp_tmr_int_map[1] = SC520_IRQ_DISABLED;	/* disable GP timer 1 INT */
+	sc520_mmcr->gp_tmr_int_map[2] = SC520_IRQ_DISABLED;	/* disable GP timer 2 INT */
+	sc520_mmcr->pit_int_map[0] = SC520_IRQ0;		/* Set PIT timer 0 INT to IRQ0 */
+	sc520_mmcr->pit_int_map[1] = SC520_IRQ_DISABLED;	/* disable PIT timer 1 INT */
+	sc520_mmcr->pit_int_map[2] = SC520_IRQ_DISABLED;	/* disable PIT timer 2 INT */
+	sc520_mmcr->pci_int_map[0] = SC520_IRQ_DISABLED;	/* disable PCI INT A */
+	sc520_mmcr->pci_int_map[1] = SC520_IRQ_DISABLED;	/* disable PCI INT B */
+	sc520_mmcr->pci_int_map[2] = SC520_IRQ_DISABLED;	/* disable PCI INT C */
+	sc520_mmcr->pci_int_map[3] = SC520_IRQ_DISABLED;	/* disable PCI INT D */
+	sc520_mmcr->dmabcintmap = SC520_IRQ_DISABLED;		/* disable DMA INT */
+	sc520_mmcr->ssimap = SC520_IRQ6;			/* Set Synchronius serial INT to IRQ6*/
+	sc520_mmcr->wdtmap = SC520_IRQ_DISABLED;		/* disable Watchdog INT */
+	sc520_mmcr->rtcmap = SC520_IRQ8;			/* Set RTC int to 8 */
+	sc520_mmcr->wpvmap = SC520_IRQ_DISABLED;		/* disable write protect INT */
+	sc520_mmcr->icemap = SC520_IRQ1;			/* Set ICE Debug Serielport INT to IRQ1 */
+	sc520_mmcr->ferrmap = SC520_IRQ13; 			/* Set FP error INT to IRQ13 */
 
-	write_mmcr_byte(SC520_UART1MAP, SC520_IRQ4);            /* Set internal UART2 INT to IRQ4 */
-	write_mmcr_byte(SC520_UART2MAP, SC520_IRQ3);            /* Set internal UART2 INT to IRQ3 */
 
-	write_mmcr_byte(SC520_GP0IMAP, SC520_IRQ7);             /* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
-	write_mmcr_byte(SC520_GP1IMAP, SC520_IRQ14);            /* Set GPIRQ1 (CF IRQ) to IRQ14 */
-	write_mmcr_byte(SC520_GP3IMAP, SC520_IRQ5);             /* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
-	write_mmcr_byte(SC520_GP4IMAP, SC520_IRQ_DISABLED);     /* disbale GIRQ4 ( IRR IRQ ) */
-	write_mmcr_byte(SC520_GP5IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ5 */
-	write_mmcr_byte(SC520_GP6IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ6 */
-	write_mmcr_byte(SC520_GP7IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ7 */
-	write_mmcr_byte(SC520_GP8IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ8 */
-	write_mmcr_byte(SC520_GP9IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ9 */
-	write_mmcr_byte(SC520_GP2IMAP, SC520_IRQ_DISABLED);     /* disable GPIRQ2 */
-	write_mmcr_byte(SC520_GP10IMAP,SC520_IRQ_DISABLED);     /* disable GPIRQ10 */
+	sc520_mmcr->uart_int_map[0] = SC520_IRQ4;		/* Set internal UART1 INT to IRQ4 */
+	sc520_mmcr->uart_int_map[1] = SC520_IRQ3;		/* Set internal UART2 INT to IRQ3 */
 
-	write_mmcr_word(SC520_PCIHOSTMAP, 0x11f);               /* Map PCI hostbridge INT to NMI */
-	write_mmcr_word(SC520_ECCMAP, 0x100);                   /* Map SDRAM ECC failure INT to NMI */
+	sc520_mmcr->gp_int_map[0] = SC520_IRQ7;			/* Set GPIRQ0 (PC-Card AUX IRQ) to IRQ7 */
+	sc520_mmcr->gp_int_map[1] = SC520_IRQ14;		/* Set GPIRQ1 (CF IRQ) to IRQ14 */
+	sc520_mmcr->gp_int_map[3] = SC520_IRQ5;			/* Set GPIRQ3 ( CAN IRQ ) ti IRQ5 */
+	sc520_mmcr->gp_int_map[4] = SC520_IRQ_DISABLED;		/* disbale GIRQ4 ( IRR IRQ ) */
+	sc520_mmcr->gp_int_map[5] = SC520_IRQ_DISABLED;		/* disable GPIRQ5 */
+	sc520_mmcr->gp_int_map[6] = SC520_IRQ_DISABLED;		/* disable GPIRQ6 */
+	sc520_mmcr->gp_int_map[7] = SC520_IRQ_DISABLED;		/* disable GPIRQ7 */
+	sc520_mmcr->gp_int_map[8] = SC520_IRQ_DISABLED;		/* disable GPIRQ8 */
+	sc520_mmcr->gp_int_map[9] = SC520_IRQ_DISABLED;		/* disable GPIRQ9 */
+	sc520_mmcr->gp_int_map[2] = SC520_IRQ_DISABLED;		/* disable GPIRQ2 */
+	sc520_mmcr->gp_int_map[10] = SC520_IRQ_DISABLED;	/* disable GPIRQ10 */
+
+	sc520_mmcr->pcihostmap = 0x11f;				/* Map PCI hostbridge INT to NMI */
+	sc520_mmcr->eccmap = 0x100;				/* Map SDRAM ECC failure INT to NMI */
 
 }
 
-
-/* PCI stuff */
-static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
-{
-	int version = read_mmcr_byte(SC520_SYSINFO);
-
-	/* a configurable lists of irqs to steal
-	 * when we need one (a board with more pci interrupt pins
-	 * would use a larger table */
-	static int irq_list[] = {
-		CONFIG_SYS_FIRST_PCI_IRQ,
-		CONFIG_SYS_SECOND_PCI_IRQ,
-		CONFIG_SYS_THIRD_PCI_IRQ,
-		CONFIG_SYS_FORTH_PCI_IRQ
-	};
-	static int next_irq_index=0;
-
-	char tmp_pin;
-	int pin;
-
-	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
-	pin = tmp_pin;
-
-	pin-=1; /* pci config space use 1-based numbering */
-	if (-1 == pin) {
-		return; /* device use no irq */
-	}
-
-
-	/* map device number +  pin to a pin on the sc520 */
-	switch (PCI_DEV(dev)) {
-	case 6:  /* ETH0 */
-		pin+=SC520_PCI_INTA;
-		break;
-
-	case 7:  /* ETH1 */
-		pin+=SC520_PCI_INTB;
-		break;
-
-	case 8:  /* Crypto */
-		pin+=SC520_PCI_INTC;
-		break;
-
-	case 9: /* PMC slot */
-		pin+=SC520_PCI_INTD;
-		break;
-
-	case 10: /* PC-Card */
-
-		if (version < 10) {
-			pin+=SC520_PCI_INTD;
-		} else {
-			pin+=SC520_PCI_INTC;
-		}
-		break;
-
-	default:
-		return;
-	}
-
-	pin&=3; /* wrap around */
-
-	if (sc520_pci_ints[pin] == -1) {
-		/* re-route one interrupt for us */
-		if (next_irq_index > 3) {
-			return;
-		}
-		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
-			return;
-		}
-		next_irq_index++;
-	}
-
-
-	if (-1 != sc520_pci_ints[pin]) {
-		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
-					   sc520_pci_ints[pin]);
-	}
-#if 0
-	printf("fixup_irq: device %d pin %c irq %d\n",
-	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
-#endif
-}
-
-
-static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
-					      pci_dev_t dev, struct pci_config_table *te)
-{
-	u32 io_base;
-	u32 temp;
-
-	pciauto_config_device(hose, dev);
-
-	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
-	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
-	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
-	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
-	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
-	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
-	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
-
-	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
-	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
-	/* route MF0 to ~INT and MF3 to IRQ7
-	 * reserve all others */
-	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
-	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
-	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
-
-	if (te->device != 0xac56) {
-		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
-		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
-		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
-	} else {
-		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
-	}
-	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
-
-
-	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
-	io_base &= ~0xfL;
-
-	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
-	writel(0, io_base+0x10);     /* CLKRUN default */
-	writel(0, io_base+0x20);     /* CLKRUN default */
-
-}
-
-
-static struct pci_config_table pci_sc520_spunk_config_table[] = {
-	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
-	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
-	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
-};
-
-static struct pci_controller sc520_spunk_hose = {
-	fixup_irq: pci_sc520_spunk_fixup_irq,
-	config_table: pci_sc520_spunk_config_table,
-	first_busno: 0x00,
-	last_busno: 0xff,
-};
-
-void pci_init_board(void)
-{
-	pci_sc520_init(&sc520_spunk_hose);
-}
-
-
 /* set up the ISA bus timing and system address mappings */
 static void bus_init(void)
 {
@@ -253,41 +103,41 @@
 	 * ??  Hyglo version 0.97 (small board)
 	 * 10  Spunk board
 	 */
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (version) {
 		/* set up the GP IO pins (for the Spunk board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xfff0);	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0,  0x000f);	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x000f);	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0,  0x1ff0);	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0xc0);		/* set the CS pin function reg */
-		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		sc520_mmcr->piopfs31_16 = 0xfff0;	/* set the GPIO pin function 31-16 reg */
+		sc520_mmcr->piopfs15_0 = 0x000f;	/* set the GPIO pin function 15-0 reg */
+		sc520_mmcr->piodir31_16 = 0x000f;	/* set the GPIO direction 31-16 reg */
+		sc520_mmcr->piodir15_0 = 0x1ff0;	/* set the GPIO direction 15-0 reg */
+		sc520_mmcr->cspfs = 0xc0;		/* set the CS pin function reg */
+		sc520_mmcr->clksel = 0x70;
 
-		write_mmcr_word(SC520_PIOCLR31_16, 0x0003);     /* reset SSI chip-selects */
-		write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+		sc520_mmcr->pioclr31_16 = 0x0003;	/* reset SSI chip-selects */
+		sc520_mmcr->pioset31_16 = 0x000c;
 
 	} else {
 		/* set up the GP IO pins (for the Hyglo board) */
-		write_mmcr_word(SC520_PIOPFS31_16, 0xffc0);	/* set the GPIO pin function 31-16 reg */
-		write_mmcr_word(SC520_PIOPFS15_0, 0x1e7f);	/* set the GPIO pin function 15-0 reg */
-		write_mmcr_word(SC520_PIODIR31_16, 0x003f);	/* set the GPIO direction 31-16 reg */
-		write_mmcr_word(SC520_PIODIR15_0, 0xe180);	/* set the GPIO direction 15-0 reg */
-		write_mmcr_byte(SC520_CSPFS, 0x00);		/* set the CS pin function reg */
-		write_mmcr_byte(SC520_CLKSEL, 0x70);
+		sc520_mmcr->piopfs31_16 = 0xffc0;	/* set the GPIO pin function 31-16 reg */
+		sc520_mmcr->piopfs15_0 = 0x1e7f;	/* set the GPIO pin function 15-0 reg */
+		sc520_mmcr->piodir31_16 = 0x003f;	/* set the GPIO direction 31-16 reg */
+		sc520_mmcr->piodir15_0 = 0xe180;	/* set the GPIO direction 15-0 reg */
+		sc520_mmcr->cspfs = 0x00;		/* set the CS pin function reg */
+		sc520_mmcr->clksel = 0x70;
 
-		write_mmcr_word(SC520_PIOCLR15_0, 0x0180);      /* reset SSI chip-selects */
+		sc520_mmcr->pioclr15_0 = 0x0180;	/* reset SSI chip-selects */
 	}
 
-	write_mmcr_byte(SC520_GPCSRT, 1);   /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPCSPW, 3);   /* set the GP CS pulse width */
-	write_mmcr_byte(SC520_GPCSOFF, 1);  /* set the GP CS offset */
-	write_mmcr_byte(SC520_GPRDW, 3);    /* set the RD pulse width */
-	write_mmcr_byte(SC520_GPRDOFF, 1);  /* set the GP RD offset */
-	write_mmcr_byte(SC520_GPWRW, 3);    /* set the GP WR pulse width */
-	write_mmcr_byte(SC520_GPWROFF, 1);  /* set the GP WR offset */
+	sc520_mmcr->gpcsrt = 1;		/* set the GP CS offset */
+	sc520_mmcr->gpcspw = 3;		/* set the GP CS pulse width */
+	sc520_mmcr->gpcsoff = 1;	/* set the GP CS offset */
+	sc520_mmcr->gprdw = 3;		/* set the RD pulse width */
+	sc520_mmcr->gprdoff = 1;	/* set the GP RD offset */
+	sc520_mmcr->gpwrw = 3;		/* set the GP WR pulse width */
+	sc520_mmcr->gpwroff = 1;	/* set the GP WR offset */
 
-	write_mmcr_word(SC520_BOOTCSCTL, 0x0407);		/* set up timing of BOOTCS */
+	sc520_mmcr->bootcsctl = 0x0407;	/* set up timing of BOOTCS */
 
 	/* adjust the memory map:
 	 * by default the first 256MB (0x00000000 - 0x0fffffff) is mapped to SDRAM
@@ -296,17 +146,17 @@
 
 
 	/* bootcs */
-	write_mmcr_long(SC520_PAR12, 0x8bffe800);
+	sc520_mmcr->par[12] = 0x8bffe800;
 
 	/* IDE0 = GPCS6 1f0-1f7 */
-	write_mmcr_long(SC520_PAR3,  0x380801f0);
+	sc520_mmcr->par[3] = 0x380801f0;
 
 	/* IDE1 = GPCS7 3f6 */
-	write_mmcr_long(SC520_PAR4,  0x3c0003f6);
+	sc520_mmcr->par[4] = 0x3c0003f6;
 
 	asm ("wbinvd\n"); /* Flush cache, req. after setting the unchached attribute ona PAR */
 
-	write_mmcr_byte(SC520_ADDDECCTL, read_mmcr_byte(SC520_ADDDECCTL) & ~(UART2_DIS|UART1_DIS));
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl & ~(UART2_DIS|UART1_DIS);
 
 }
 
@@ -331,152 +181,6 @@
  */
 
 /*
- * This function should map a chunk of size bytes
- * of the system address space to the ISA bus
- *
- * The function will return the memory address
- * as seen by the host (which may very will be the
- * same as the bus address)
- */
-u32 isa_map_rom(u32 bus_addr, int size)
-{
-	u32 par;
-
-	printf("isa_map_rom asked to map %d bytes at %x\n",
-	       size, bus_addr);
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 12;
-	par--;
-	par&=0x7f;
-	par <<= 18;
-	par |= (bus_addr>>12);
-	par |= 0x50000000;
-
-	printf ("setting PAR11 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR11,  par);
-
-	return bus_addr;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void isa_unmap_rom(u32 addr)
-{
-	printf("isa_unmap_rom asked to unmap %x", addr);
-	if ((addr>>12) == (read_mmcr_long(SC520_PAR11)&0x3ffff)) {
-		write_mmcr_long(SC520_PAR11, 0);
-		printf(" done\n");
-		return;
-	}
-	printf(" not ours\n");
-}
-
-#ifdef CONFIG_PCI
-#define PCI_ROM_TEMP_SPACE 0x10000
-/*
- * This function should map a chunk of size bytes
- * of the system address space to the PCI bus,
- * suitable to map PCI ROMS (bus address < 16M)
- * the function will return the host memory address
- * which should be converted into a bus address
- * before used to configure the PCI rom address
- * decoder
- */
-u32 pci_get_rom_window(struct pci_controller *hose, int size)
-{
-	u32 par;
-
-	par = size;
-	if (par < 0x80000) {
-		par = 0x80000;
-	}
-	par >>= 16;
-	par--;
-	par&=0x7ff;
-	par <<= 14;
-	par |= (PCI_ROM_TEMP_SPACE>>16);
-	par |= 0x72000000;
-
-	printf ("setting PAR1 to %x\n", par);
-
-	/* Map rom 0x10000 with PAR1 */
-	write_mmcr_long(SC520_PAR1,  par);
-
-	return PCI_ROM_TEMP_SPACE;
-}
-
-/*
- * this function removed any mapping created
- * with pci_get_rom_window()
- */
-void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
-{
-	printf("pci_remove_rom_window: %x", addr);
-	if (addr == PCI_ROM_TEMP_SPACE) {
-		write_mmcr_long(SC520_PAR1, 0);
-		printf(" done\n");
-		return;
-	}
-	printf(" not ours\n");
-
-}
-
-/*
- * This function is called in order to provide acces to the
- * legacy video I/O ports on the PCI bus.
- * After this function accesses to I/O ports 0x3b0-0x3bb and
- * 0x3c0-0x3df shuld result in transactions on the PCI bus.
- *
- */
-int pci_enable_legacy_video_ports(struct pci_controller *hose)
-{
-	/* Map video memory to 0xa0000*/
-	write_mmcr_long(SC520_PAR0,  0x7200400a);
-
-	/* forward all I/O accesses to PCI */
-	write_mmcr_byte(SC520_ADDDECCTL,
-			read_mmcr_byte(SC520_ADDDECCTL) | IO_HOLE_DEST_PCI);
-
-
-	/* so we map away all io ports to pci (only way to access pci io
-	 * below 0x400. But then we have to map back the portions that we dont
-	 * use so that the generate cycles on the GPIO bus where the sio and
-	 * ISA slots are connected, this requre the use of several PAR registers
-	 */
-
-	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
-	write_mmcr_long(SC520_PAR5, 0x31f70100);
-
-	/* com2 use 2f8-2ff */
-
-	/* bring 0x300 - 0x3af back to ISA using PAR7 */
-	write_mmcr_long(SC520_PAR7, 0x30af0300);
-
-	/* vga use 3b0-3bb */
-
-	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
-	write_mmcr_long(SC520_PAR8, 0x300303bc);
-
-	/* vga use 3c0-3df */
-
-	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
-	write_mmcr_long(SC520_PAR9, 0x301703e0);
-
-	/* com1 use 3f8-3ff */
-
-	return 0;
-}
-#endif
-
-/*
  * Miscelaneous platform dependent initialisations
  */
 
@@ -487,12 +191,12 @@
 	irq_init();
 
 	/* max drive current on SDRAM */
-	write_mmcr_word(SC520_DSCTL, 0x0100);
+	sc520_mmcr->dsctl = 0x0100;
 
 	/* enter debug mode after next reset (only if jumper is also set) */
-	write_mmcr_byte(SC520_RESCFG, 0x08);
+	sc520_mmcr->rescfg = 0x08;
 	/* configure the software timer to 33.000MHz */
-	write_mmcr_byte(SC520_SWTMRCFG, 1);
+	sc520_mmcr->swtmrcfg = 1;
 	gd->bus_clk = 33000000;
 
 	return 0;
@@ -506,17 +210,15 @@
 
 void show_boot_progress(int val)
 {
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (val < -32) val = -1;  /* let things compatible */
 	if (version == 0) {
 		/* PIO31-PIO16 Data */
-		write_mmcr_word(SC520_PIODATA31_16,
-				(read_mmcr_word(SC520_PIODATA31_16) & 0xffc0)| ((val&0x7e)>>1)); /* 0x1f8 >> 3 */
+		sc520_mmcr->piodata31_16 = (sc520_mmcr->piodata31_16 & 0xffc0) | ((val&0x7e)>>1); /* 0x1f8 >> 3 */
 
 		/* PIO0-PIO15 Data */
-		write_mmcr_word(SC520_PIODATA15_0,
-				(read_mmcr_word(SC520_PIODATA15_0) & 0x1fff)| ((val&0x7)<<13));
+		sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0x1fff)| ((val&0x7)<<13);
 	} else {
 		/* newer boards use PIO4-PIO12 */
 		/* PIO0-PIO15 Data */
@@ -525,8 +227,7 @@
 #else
 		val = (val & 0x007) | ((val & 0x07e) << 2);
 #endif
-		write_mmcr_word(SC520_PIODATA15_0,
-				(read_mmcr_word(SC520_PIODATA15_0) & 0xe00f) | ((val&0x01ff)<<4));
+		sc520_mmcr->piodata15_0 = (sc520_mmcr->piodata15_0 & 0xe00f) | ((val&0x01ff)<<4);
 	}
 }
 
@@ -534,7 +235,7 @@
 int last_stage_init(void)
 {
 
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	printf("Omicron Ceti SC520 Spunk revision %x\n", version);
 
@@ -585,30 +286,30 @@
 
 void ssi_chip_select(int dev)
 {
-	int version = read_mmcr_byte(SC520_SYSINFO);
+	int version = sc520_mmcr->sysinfo;
 
 	if (version) {
 		/* Spunk board: EEPROM and CAN are actove-low, TEMP and AUX are active high */
 		switch (dev) {
 		case 1: /* EEPROM */
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0004);
+			sc520_mmcr->pioclr31_16 = 0x0004;
 			break;
 
 		case 2: /* Temp Probe */
-			write_mmcr_word(SC520_PIOSET31_16, 0x0002);
+			sc520_mmcr->pioset31_16 = 0x0002;
 			break;
 
 		case 3: /* CAN */
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0008);
+			sc520_mmcr->pioclr31_16 = 0x0008;
 			break;
 
 		case 4: /* AUX */
-			write_mmcr_word(SC520_PIOSET31_16, 0x0001);
+			sc520_mmcr->pioset31_16 = 0x0001;
 			break;
 
 		case 0:
-			write_mmcr_word(SC520_PIOCLR31_16, 0x0003);
-			write_mmcr_word(SC520_PIOSET31_16, 0x000c);
+			sc520_mmcr->pioclr31_16 = 0x0003;
+			sc520_mmcr->pioset31_16 = 0x000c;
 			break;
 
 		default:
@@ -620,15 +321,15 @@
 
 		switch (dev) {
 		case 1: /* EEPROM */
-			write_mmcr_word(SC520_PIOSET15_0, 0x0100);
+			sc520_mmcr->pioset15_0 = 0x0100;
 			break;
 
 		case 2: /* Temp Probe */
-			write_mmcr_word(SC520_PIOSET15_0, 0x0080);
+			sc520_mmcr->pioset15_0 = 0x0080;
 			break;
 
 		case 0:
-			write_mmcr_word(SC520_PIOCLR15_0, 0x0180);
+			sc520_mmcr->pioclr15_0 = 0x0180;
 			break;
 
 		default:
@@ -637,12 +338,37 @@
 	}
 }
 
+void spi_eeprom_probe(int x)
+{
+}
+
+int spi_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+int spi_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+void mw_eeprom_probe(int x)
+{
+}
+
+int mw_eeprom_read(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
+
+int mw_eeprom_write(int x, int offset, uchar *buffer, int len)
+{
+       return 0;
+}
 
 void spi_init_f(void)
 {
-	read_mmcr_byte(SC520_SYSINFO) ?
-		spi_eeprom_probe(1) :
-	mw_eeprom_probe(1);
+	sc520_mmcr->sysinfo ? spi_eeprom_probe(1) : mw_eeprom_probe(1);
 
 }
 
@@ -657,7 +383,7 @@
 		offset |= addr[i];
 	}
 
-	return	read_mmcr_byte(SC520_SYSINFO) ?
+	return	sc520_mmcr->sysinfo ?
 		spi_eeprom_read(1, offset, buffer, len) :
 	mw_eeprom_read(1, offset, buffer, len);
 }
@@ -673,7 +399,7 @@
 		offset |= addr[i];
 	}
 
-	return	read_mmcr_byte(SC520_SYSINFO) ?
+	return	sc520_mmcr->sysinfo ?
 		spi_eeprom_write(1, offset, buffer, len) :
 	mw_eeprom_write(1, offset, buffer, len);
 }

diff --git a/board/sc520_spunk/sc520_spunk_pci.c b/board/sc520_spunk/sc520_spunk_pci.c
new file mode 100644
index 0000000..1b5d0f1
--- /dev/null
+++ b/board/sc520_spunk/sc520_spunk_pci.c

@@ -0,0 +1,323 @@
+/*
+ *
+ * (C) Copyright 2002
+ * Daniel Engström, Omicron Ceti AB <daniel@omicron.se>.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#include <common.h>
+#include <pci.h>
+#include <ds1722.h>
+#include <asm/io.h>
+#include <asm/pci.h>
+#include <asm/ic/sc520.h>
+#include <asm/ic/pci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static void pci_sc520_spunk_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
+{
+	int version = sc520_mmcr->sysinfo;
+
+	/* a configurable lists of irqs to steal
+	 * when we need one (a board with more pci interrupt pins
+	 * would use a larger table */
+	static int irq_list[] = {
+		CONFIG_SYS_FIRST_PCI_IRQ,
+		CONFIG_SYS_SECOND_PCI_IRQ,
+		CONFIG_SYS_THIRD_PCI_IRQ,
+		CONFIG_SYS_FORTH_PCI_IRQ
+	};
+	static int next_irq_index=0;
+
+	uchar tmp_pin;
+	int pin;
+
+	pci_hose_read_config_byte(hose, dev, PCI_INTERRUPT_PIN, &tmp_pin);
+	pin = tmp_pin;
+
+	pin-=1; /* pci config space use 1-based numbering */
+	if (-1 == pin) {
+		return; /* device use no irq */
+	}
+
+
+	/* map device number +  pin to a pin on the sc520 */
+	switch (PCI_DEV(dev)) {
+	case 6:  /* ETH0 */
+		pin+=SC520_PCI_INTA;
+		break;
+
+	case 7:  /* ETH1 */
+		pin+=SC520_PCI_INTB;
+		break;
+
+	case 8:  /* Crypto */
+		pin+=SC520_PCI_INTC;
+		break;
+
+	case 9: /* PMC slot */
+		pin+=SC520_PCI_INTD;
+		break;
+
+	case 10: /* PC-Card */
+
+		if (version < 10) {
+			pin+=SC520_PCI_INTD;
+		} else {
+			pin+=SC520_PCI_INTC;
+		}
+		break;
+
+	default:
+		return;
+	}
+
+	pin&=3; /* wrap around */
+
+	if (sc520_pci_ints[pin] == -1) {
+		/* re-route one interrupt for us */
+		if (next_irq_index > 3) {
+			return;
+		}
+		if (pci_sc520_set_irq(pin, irq_list[next_irq_index])) {
+			return;
+		}
+		next_irq_index++;
+	}
+
+
+	if (-1 != sc520_pci_ints[pin]) {
+		pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE,
+					   sc520_pci_ints[pin]);
+	}
+#if 0
+	printf("fixup_irq: device %d pin %c irq %d\n",
+	       PCI_DEV(dev), 'A' + pin, sc520_pci_ints[pin]);
+#endif
+}
+
+
+static void pci_sc520_spunk_configure_cardbus(struct pci_controller *hose,
+					      pci_dev_t dev, struct pci_config_table *te)
+{
+	u32 io_base;
+	u32 temp;
+
+	pciauto_config_device(hose, dev);
+
+	pci_hose_write_config_word(hose, dev, PCI_COMMAND, 0x07);  /* enable device */
+	pci_hose_write_config_byte(hose, dev, 0x0c, 0x10);         /* cacheline size */
+	pci_hose_write_config_byte(hose, dev, 0x0d, 0x40);         /* latency timer */
+	pci_hose_write_config_byte(hose, dev, 0x1b, 0x40);         /* cardbus latency timer */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0040);  /* reset cardbus */
+	pci_hose_write_config_word(hose, dev, PCI_BRIDGE_CONTROL, 0x0080);  /* route interrupts though ExCA */
+	pci_hose_write_config_word(hose, dev,  0x44, 0x3e0); /* map legacy I/O port to 0x3e0 */
+
+	pci_hose_read_config_dword(hose, dev,  0x80, &temp); /* System control */
+	pci_hose_write_config_dword(hose, dev,  0x80, temp | 0x60); /* System control: disable clockrun */
+	/* route MF0 to ~INT and MF3 to IRQ7
+	 * reserve all others */
+	pci_hose_write_config_dword(hose, dev, 0x8c, 0x00007002);
+	pci_hose_write_config_byte(hose, dev, 0x91, 0x00);    /* card control */
+	pci_hose_write_config_byte(hose, dev, 0x92, 0x62);    /* device control */
+
+	if (te->device != 0xac56) {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x21);    /* async interrupt enable */
+		pci_hose_write_config_word(hose, dev, 0xa8, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xac, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xaa, 0x0000);  /* reset GPIO */
+		pci_hose_write_config_word(hose, dev, 0xae, 0x0000);  /* reset GPIO */
+	} else {
+		pci_hose_write_config_byte(hose, dev, 0x93, 0x20);    /*  */
+	}
+	pci_hose_write_config_word(hose, dev, 0xa4, 0x8000);  /* reset power management */
+
+
+	pci_hose_read_config_dword(hose, dev, PCI_BASE_ADDRESS_0, &io_base);
+	io_base &= ~0xfL;
+
+	writeb(0x07, io_base+0x803); /* route CSC irq though ExCA and enable IRQ7 */
+	writel(0, io_base+0x10);     /* CLKRUN default */
+	writel(0, io_base+0x20);     /* CLKRUN default */
+
+}
+
+
+static struct pci_config_table pci_sc520_spunk_config_table[] = {
+	{ 0x104c, 0xac50, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0x104c, 0xac56, PCI_ANY_ID, 0, 0x0a, 0, pci_sc520_spunk_configure_cardbus, { 0, 0, 0} },
+	{ 0, 0, 0, 0, 0, 0, NULL, {0,0,0}}
+};
+
+static struct pci_controller sc520_spunk_hose = {
+	fixup_irq: pci_sc520_spunk_fixup_irq,
+	config_table: pci_sc520_spunk_config_table,
+	first_busno: 0x00,
+	last_busno: 0xff,
+};
+
+void pci_init_board(void)
+{
+	pci_sc520_init(&sc520_spunk_hose);
+}
+
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the ISA bus
+ *
+ * The function will return the memory address
+ * as seen by the host (which may very will be the
+ * same as the bus address)
+ */
+u32 isa_map_rom(u32 bus_addr, int size)
+{
+	u32 par;
+
+	printf("isa_map_rom asked to map %d bytes at %x\n",
+	       size, bus_addr);
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 12;
+	par--;
+	par&=0x7f;
+	par <<= 18;
+	par |= (bus_addr>>12);
+	par |= 0x50000000;
+
+	printf ("setting PAR11 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[11] = par;
+
+	return bus_addr;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void isa_unmap_rom(u32 addr)
+{
+	printf("isa_unmap_rom asked to unmap %x", addr);
+	if ((addr>>12) == (sc520_mmcr->par[11] & 0x3ffff)) {
+		sc520_mmcr->par[11] = 0;
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+}
+
+#define PCI_ROM_TEMP_SPACE 0x10000
+/*
+ * This function should map a chunk of size bytes
+ * of the system address space to the PCI bus,
+ * suitable to map PCI ROMS (bus address < 16M)
+ * the function will return the host memory address
+ * which should be converted into a bus address
+ * before used to configure the PCI rom address
+ * decoder
+ */
+u32 pci_get_rom_window(struct pci_controller *hose, int size)
+{
+	u32 par;
+
+	par = size;
+	if (par < 0x80000) {
+		par = 0x80000;
+	}
+	par >>= 16;
+	par--;
+	par&=0x7ff;
+	par <<= 14;
+	par |= (PCI_ROM_TEMP_SPACE>>16);
+	par |= 0x72000000;
+
+	printf ("setting PAR1 to %x\n", par);
+
+	/* Map rom 0x10000 with PAR1 */
+	sc520_mmcr->par[1] = par;
+
+	return PCI_ROM_TEMP_SPACE;
+}
+
+/*
+ * this function removed any mapping created
+ * with pci_get_rom_window()
+ */
+void pci_remove_rom_window(struct pci_controller *hose, u32 addr)
+{
+	printf("pci_remove_rom_window: %x", addr);
+	if (addr == PCI_ROM_TEMP_SPACE) {
+		sc520_mmcr->par[1] = 0;
+		printf(" done\n");
+		return;
+	}
+	printf(" not ours\n");
+
+}
+
+/*
+ * This function is called in order to provide acces to the
+ * legacy video I/O ports on the PCI bus.
+ * After this function accesses to I/O ports 0x3b0-0x3bb and
+ * 0x3c0-0x3df shuld result in transactions on the PCI bus.
+ *
+ */
+int pci_enable_legacy_video_ports(struct pci_controller *hose)
+{
+	/* Map video memory to 0xa0000*/
+	sc520_mmcr->par[0] = 0x7200400a;
+
+	/* forward all I/O accesses to PCI */
+	sc520_mmcr->adddecctl = sc520_mmcr->adddecctl | IO_HOLE_DEST_PCI;
+
+
+	/* so we map away all io ports to pci (only way to access pci io
+	 * below 0x400. But then we have to map back the portions that we dont
+	 * use so that the generate cycles on the GPIO bus where the sio and
+	 * ISA slots are connected, this requre the use of several PAR registers
+	 */
+
+	/* bring 0x100 - 0x2f7 back to ISA using PAR5 */
+	sc520_mmcr->par[5] = 0x31f70100;
+
+	/* com2 use 2f8-2ff */
+
+	/* bring 0x300 - 0x3af back to ISA using PAR7 */
+	sc520_mmcr->par[7] = 0x30af0300;
+
+	/* vga use 3b0-3bb */
+
+	/* bring 0x3bc - 0x3bf back to ISA using PAR8 */
+	sc520_mmcr->par[8] = 0x300303bc;
+
+	/* vga use 3c0-3df */
+
+	/* bring 0x3e0 - 0x3f7 back to ISA using PAR9 */
+	sc520_mmcr->par[9] = 0x301703e0;
+
+	/* com1 use 3f8-3ff */
+
+	return 0;
+}

diff --git a/board/tqc/tqm5200/Makefile b/board/tqc/tqm5200/Makefile
index ce125e2..55c4d99 100644
--- a/board/tqc/tqm5200/Makefile
+++ b/board/tqc/tqm5200/Makefile

@@ -41,7 +41,7 @@
 	rm -f $(LIB) core *.bak $(obj).depend
 
 cam5200_flash.o:	cam5200_flash.c
-	$(CC) $(CFLAGS) -fno-strict-aliasing -c -o $@ $<
+	$(CC) $(CFLAGS) -c -o $@ $<
 
 #########################################################################
 

diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c
index 86c8122..365ceeb 100644
--- a/common/cmd_bootm.c
+++ b/common/cmd_bootm.c

@@ -166,6 +166,13 @@
 }
 void arch_lmb_reserve(struct lmb *lmb) __attribute__((weak, alias("__arch_lmb_reserve")));
 
+/* Allow for arch specific config before we boot */
+void __arch_preboot_os(void)
+{
+	/* please define platform specific arch_preboot_os() */
+}
+void arch_preboot_os(void) __attribute__((weak, alias("__arch_preboot_os")));
+
 #if defined(__ARM__)
   #define IH_INITRD_ARCH IH_ARCH_ARM
 #elif defined(__avr32__)
@@ -543,6 +550,7 @@
 			break;
 		case BOOTM_STATE_OS_GO:
 			disable_interrupts();
+			arch_preboot_os();
 			boot_fn(BOOTM_STATE_OS_GO, argc, argv, &images);
 			break;
 	}
@@ -673,6 +681,8 @@
 		return 1;
 	}
 
+	arch_preboot_os();
+
 	boot_fn(0, argc, argv, &images);
 
 	show_boot_progress (-9);

diff --git a/common/cmd_mtdparts.c b/common/cmd_mtdparts.c
index 665995d..b375fea 100644
--- a/common/cmd_mtdparts.c
+++ b/common/cmd_mtdparts.c

@@ -1336,7 +1336,7 @@
 
 	if (find_dev_and_part(id, &dev, &pnum, &part) == 0) {
 
-		DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08lx@0x%08lx\n",
+		DEBUGF("delete_partition: device = %s%d, partition %d = (%s) 0x%08x@0x%08x\n",
 				MTD_DEV_TYPE(dev->id->type), dev->id->num, pnum,
 				part->name, part->size, part->offset);
 

diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index 4a18562..241db8c 100644
--- a/common/dlmalloc.c
+++ b/common/dlmalloc.c

@@ -1502,7 +1502,38 @@
 		*p++ += gd->reloc_off;
 	}
 }
-
+
+ulong mem_malloc_start = 0;
+ulong mem_malloc_end = 0;
+ulong mem_malloc_brk = 0;
+
+void *sbrk(ptrdiff_t increment)
+{
+	ulong old = mem_malloc_brk;
+	ulong new = old + increment;
+
+	if ((new < mem_malloc_start) || (new > mem_malloc_end))
+		return NULL;
+
+	mem_malloc_brk = new;
+
+	return (void *)old;
+}
+
+#ifndef CONFIG_X86
+/*
+ * x86 boards use a slightly different init sequence thus they implement
+ * their own version of mem_malloc_init()
+ */
+void mem_malloc_init(ulong start, ulong size)
+{
+	mem_malloc_start = start;
+	mem_malloc_end = start + size;
+	mem_malloc_brk = start;
+
+	memset((void *)mem_malloc_start, 0, size);
+}
+#endif
 
 /* field-extraction macros */
 

diff --git a/cpu/74xx_7xx/config.mk b/cpu/74xx_7xx/config.mk
index 324f62b..d589210 100644
--- a/cpu/74xx_7xx/config.mk
+++ b/cpu/74xx_7xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_74xx_7xx -ffixed-r2 -mstring

diff --git a/cpu/arm1136/config.mk b/cpu/arm1136/config.mk
index 61d5a38..3e68535 100644
--- a/cpu/arm1136/config.mk
+++ b/cpu/arm1136/config.mk

@@ -20,8 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5

diff --git a/cpu/arm1176/config.mk b/cpu/arm1176/config.mk
index a31c7b0..14346cf 100644
--- a/cpu/arm1176/config.mk
+++ b/cpu/arm1176/config.mk

@@ -20,8 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t

diff --git a/cpu/arm1176/s3c64xx/config.mk b/cpu/arm1176/s3c64xx/config.mk
index a31c7b0..14346cf 100644
--- a/cpu/arm1176/s3c64xx/config.mk
+++ b/cpu/arm1176/s3c64xx/config.mk

@@ -20,8 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v6.
 PLATFORM_CPPFLAGS += -march=armv5t

diff --git a/cpu/arm720t/config.mk b/cpu/arm720t/config.mk
index 74d5283..3844c62 100644
--- a/cpu/arm720t/config.mk
+++ b/cpu/arm720t/config.mk

@@ -22,8 +22,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS +=  -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi
 # =========================================================================

diff --git a/cpu/arm920t/config.mk b/cpu/arm920t/config.mk
index a43b156..8f6c1a3 100644
--- a/cpu/arm920t/config.mk
+++ b/cpu/arm920t/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================

diff --git a/cpu/arm925t/config.mk b/cpu/arm925t/config.mk
index a43b156..8f6c1a3 100644
--- a/cpu/arm925t/config.mk
+++ b/cpu/arm925t/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================

diff --git a/cpu/arm926ejs/config.mk b/cpu/arm926ejs/config.mk
index 90eb3c0..f8ef90f 100644
--- a/cpu/arm926ejs/config.mk
+++ b/cpu/arm926ejs/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv5te
 # =========================================================================

diff --git a/cpu/arm926ejs/davinci/config.mk b/cpu/arm926ejs/davinci/config.mk
index 7757be3..565adda 100644
--- a/cpu/arm926ejs/davinci/config.mk
+++ b/cpu/arm926ejs/davinci/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv5te
 # =========================================================================

diff --git a/cpu/arm946es/config.mk b/cpu/arm946es/config.mk
index a81321b..e783f69 100644
--- a/cpu/arm946es/config.mk
+++ b/cpu/arm946es/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	 -msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================

diff --git a/cpu/arm_cortexa8/config.mk b/cpu/arm_cortexa8/config.mk
index da5ee16..49ac9c7 100644
--- a/cpu/arm_cortexa8/config.mk
+++ b/cpu/arm_cortexa8/config.mk

@@ -20,8 +20,7 @@
 # Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 # MA 02111-1307 USA
 #
-PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \
-		     -msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 # Make ARMv5 to allow more compilers to work, even though its v7a.
 PLATFORM_CPPFLAGS += -march=armv5

diff --git a/cpu/arm_intcm/config.mk b/cpu/arm_intcm/config.mk
index a81321b..e783f69 100644
--- a/cpu/arm_intcm/config.mk
+++ b/cpu/arm_intcm/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	 -msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS +=  -march=armv4
 # =========================================================================

diff --git a/cpu/blackfin/interrupt.S b/cpu/blackfin/interrupt.S
index dd2cc53..71e0fc6 100644
--- a/cpu/blackfin/interrupt.S
+++ b/cpu/blackfin/interrupt.S

@@ -5,6 +5,7 @@
  * Licensed under the GPL-2 or later.
  */
 
+#include <config.h>
 #include <asm/blackfin.h>
 #include <asm/entry.h>
 
@@ -12,12 +13,16 @@
 
 /* default entry point for exceptions */
 ENTRY(_trap)
+	CONFIG_BFIN_SCRATCH_REG = sp;
+	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
+	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
 	SAVE_ALL_SYS
 	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
 	sp += -12;
 	call _trap_c;
 	sp += 12;
 	RESTORE_ALL_SYS
+	sp = CONFIG_BFIN_SCRATCH_REG;
 	rtx;
 ENDPROC(_trap)
 

diff --git a/cpu/i386/sc520/sc520.c b/cpu/i386/sc520/sc520.c
index ae3b500..4b566a7 100644
--- a/cpu/i386/sc520/sc520.c
+++ b/cpu/i386/sc520/sc520.c

@@ -33,75 +33,35 @@
 /*
  * utility functions for boards based on the AMD sc520
  *
- * void write_mmcr_byte(u16 mmcr, u8 data)
- * void write_mmcr_word(u16 mmcr, u16 data)
- * void write_mmcr_long(u16 mmcr, u32 data)
- *
- * u8   read_mmcr_byte(u16 mmcr)
- * u16  read_mmcr_word(u16 mmcr)
- * u32  read_mmcr_long(u16 mmcr)
- *
  * void init_sc520(void)
  * unsigned long init_sc520_dram(void)
  */
 
-static u32 mmcr_base= 0xfffef000;
-
-void write_mmcr_byte(u16 mmcr, u8 data)
-{
-	writeb(data, mmcr+mmcr_base);
-}
-
-void write_mmcr_word(u16 mmcr, u16 data)
-{
-	writew(data, mmcr+mmcr_base);
-}
-
-void write_mmcr_long(u16 mmcr, u32 data)
-{
-	writel(data, mmcr+mmcr_base);
-}
-
-u8 read_mmcr_byte(u16 mmcr)
-{
-	return readb(mmcr+mmcr_base);
-}
-
-u16 read_mmcr_word(u16 mmcr)
-{
-	return readw(mmcr+mmcr_base);
-}
-
-u32 read_mmcr_long(u16 mmcr)
-{
-	return readl(mmcr+mmcr_base);
-}
-
+volatile sc520_mmcr_t *sc520_mmcr = (sc520_mmcr_t *)0xfffef000;
 
 void init_sc520(void)
 {
 	/* Set the UARTxCTL register at it's slower,
 	 * baud clock giving us a 1.8432 MHz reference
 	 */
-	write_mmcr_byte(SC520_UART1CTL, 7);
-	write_mmcr_byte(SC520_UART2CTL, 7);
+	sc520_mmcr->uart1ctl = 0x07;
+	sc520_mmcr->uart2ctl = 0x07;
 
 	/* first set the timer pin mapping */
-	write_mmcr_byte(SC520_CLKSEL, 0x72);	/* no clock frequency selected, use 1.1892MHz */
+	sc520_mmcr->clksel = 0x72;	/* no clock frequency selected, use 1.1892MHz */
 
 	/* enable PCI bus arbitrer */
-	write_mmcr_byte(SC520_SYSARBCTL,0x02);  /* enable concurrent mode */
+	sc520_mmcr->sysarbctl = 0x02;	/* enable concurrent mode */
 
-	write_mmcr_word(SC520_SYSARBMENB,0x1f); /* enable external grants */
-	write_mmcr_word(SC520_HBCTL,0x04);      /* enable posted-writes */
-
+	sc520_mmcr->sysarbmenb = 0x1f;	/* enable external grants */
+	sc520_mmcr->hbctl = 0x04;	/* enable posted-writes */
 
 	if (CONFIG_SYS_SC520_HIGH_SPEED) {
-		write_mmcr_byte(SC520_CPUCTL, 0x2);	/* set it to 133 MHz and write back */
+		sc520_mmcr->cpuctl = 0x02;	/* set it to 133 MHz and write back */
 		gd->cpu_clk = 133000000;
 		printf("## CPU Speed set to 133MHz\n");
 	} else {
-		write_mmcr_byte(SC520_CPUCTL, 1);	/* set CPU to 100 MHz and write back cache */
+		sc520_mmcr->cpuctl = 0x01;	/* set it to 100 MHz and write back */
 		printf("## CPU Speed set to 100MHz\n");
 		gd->cpu_clk = 100000000;
 	}
@@ -109,12 +69,12 @@
 
 	/* wait at least one millisecond */
 	asm("movl	$0x2000,%%ecx\n"
-	    "wait_loop:	pushl %%ecx\n"
+	    "0:		pushl %%ecx\n"
 	    "popl	%%ecx\n"
-	    "loop wait_loop\n": : : "ecx");
+	    "loop 0b\n": : : "ecx");
 
 	/* turn on the SDRAM write buffer */
-	write_mmcr_byte(SC520_DBCTL, 0x11);
+	sc520_mmcr->dbctl = 0x11;
 
 	/* turn on the cache and disable write through */
 	asm("movl	%%cr0, %%eax\n"
@@ -156,10 +116,9 @@
 		val = 3;  /* 62.4us */
 	}
 
-	write_mmcr_byte(SC520_DRCCTL, (read_mmcr_byte(SC520_DRCCTL) & 0xcf) | (val<<4));
+	sc520_mmcr->drcctl = (sc520_mmcr->drcctl & 0xcf) | (val<<4);
 
-	val = read_mmcr_byte(SC520_DRCTMCTL);
-	val &= 0xf0;
+	val = sc520_mmcr->drctmctl & 0xf0;
 
 	if (cas_precharge_delay==3) {
 		val |= 0x04;   /* 3T */
@@ -174,12 +133,12 @@
 	} else {
 		val |= 1;
 	}
-	write_mmcr_byte(SC520_DRCTMCTL, val);
+	sc520_mmcr->drctmctl = val;
 #endif
 
 	/* We read-back the configuration of the dram
 	 * controller that the assembly code wrote */
-	dram_ctrl = read_mmcr_long(SC520_DRCBENDADR);
+	dram_ctrl = sc520_mmcr->drcbendadr;
 
 	bd->bi_dram[0].start = 0;
 	if (dram_ctrl & 0x80) {
@@ -232,7 +191,7 @@
 {
 	printf("Resetting using SC520 MMCR\n");
 	/* Write a '1' to the SYS_RST of the RESCFG MMCR */
-	write_mmcr_word(SC520_RESCFG, 0x0001);
+	sc520_mmcr->rescfg = 0x01;
 
 	/* NOTREACHED */
 }

diff --git a/cpu/i386/sc520/sc520_pci.c b/cpu/i386/sc520/sc520_pci.c
index 38b837e..f446c6d 100644
--- a/cpu/i386/sc520/sc520_pci.c
+++ b/cpu/i386/sc520/sc520_pci.c

@@ -33,23 +33,23 @@
 	u16 level_reg;
 	u8 level_bit;
 } sc520_irq[] = {
-	{ SC520_IRQ0,  SC520_MPICMODE,  0x01 },
-	{ SC520_IRQ1,  SC520_MPICMODE,  0x02 },
-	{ SC520_IRQ2,  SC520_SL1PICMODE, 0x02 },
-	{ SC520_IRQ3,  SC520_MPICMODE,  0x08 },
-	{ SC520_IRQ4,  SC520_MPICMODE,  0x10 },
-	{ SC520_IRQ5,  SC520_MPICMODE,  0x20 },
-	{ SC520_IRQ6,  SC520_MPICMODE,  0x40 },
-	{ SC520_IRQ7,  SC520_MPICMODE,  0x80 },
+	{ SC520_IRQ0,  0, 0x01 },
+	{ SC520_IRQ1,  0, 0x02 },
+	{ SC520_IRQ2,  1, 0x02 },
+	{ SC520_IRQ3,  0, 0x08 },
+	{ SC520_IRQ4,  0, 0x10 },
+	{ SC520_IRQ5,  0, 0x20 },
+	{ SC520_IRQ6,  0, 0x40 },
+	{ SC520_IRQ7,  0, 0x80 },
 
-	{ SC520_IRQ8,  SC520_SL1PICMODE, 0x01 },
-	{ SC520_IRQ9,  SC520_SL1PICMODE, 0x02 },
-	{ SC520_IRQ10, SC520_SL1PICMODE, 0x04 },
-	{ SC520_IRQ11, SC520_SL1PICMODE, 0x08 },
-	{ SC520_IRQ12, SC520_SL1PICMODE, 0x10 },
-	{ SC520_IRQ13, SC520_SL1PICMODE, 0x20 },
-	{ SC520_IRQ14, SC520_SL1PICMODE, 0x40 },
-	{ SC520_IRQ15, SC520_SL1PICMODE, 0x80 }
+	{ SC520_IRQ8,  1, 0x01 },
+	{ SC520_IRQ9,  1, 0x02 },
+	{ SC520_IRQ10, 1, 0x04 },
+	{ SC520_IRQ11, 1, 0x08 },
+	{ SC520_IRQ12, 1, 0x10 },
+	{ SC520_IRQ13, 1, 0x20 },
+	{ SC520_IRQ14, 1, 0x40 },
+	{ SC520_IRQ15, 1, 0x80 }
 };
 
 
@@ -77,34 +77,34 @@
 
 	/* first disable any non-pci interrupt source that use
 	 * this level */
-	for (i=SC520_GPTMR0MAP;i<=SC520_GP10IMAP;i++) {
-		if (i>=SC520_PCIINTAMAP&&i<=SC520_PCIINTDMAP) {
-			continue;
-		}
-		if (read_mmcr_byte(i) == sc520_irq[irq].priority) {
-			write_mmcr_byte(i, SC520_IRQ_DISABLED);
-		}
+
+	/* PCI interrupt mapping (A through D)*/
+	for (i=0; i<=3 ;i++) {
+		if (sc520_mmcr->pci_int_map[i] == sc520_irq[irq].priority)
+			sc520_mmcr->pci_int_map[i] = SC520_IRQ_DISABLED;
+	}
+
+	/* GP IRQ interrupt mapping */
+	for (i=0; i<=10 ;i++) {
+		if (sc520_mmcr->gp_int_map[i] == sc520_irq[irq].priority)
+			sc520_mmcr->gp_int_map[i] = SC520_IRQ_DISABLED;
 	}
 
 	/* Set the trigger to level */
-	write_mmcr_byte(sc520_irq[irq].level_reg,
-			read_mmcr_byte(sc520_irq[irq].level_reg) | sc520_irq[irq].level_bit);
+	sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] =
+		sc520_mmcr->pic_mode[sc520_irq[irq].level_reg] | sc520_irq[irq].level_bit;
 
 
 	if (pci_pin < 4) {
 		/* PCI INTA-INTD */
 		/* route the interrupt */
-		write_mmcr_byte(SC520_PCIINTAMAP + pci_pin, sc520_irq[irq].priority);
-
-
+		sc520_mmcr->pci_int_map[pci_pin] = sc520_irq[irq].priority;
 	} else {
 		/* GPIRQ0-GPIRQ10 used for additional PCI INTS */
-		write_mmcr_byte(SC520_GP0IMAP + pci_pin - 4, sc520_irq[irq].priority);
+		sc520_mmcr->gp_int_map[pci_pin - 4] = sc520_irq[irq].priority;
 
 		/* also set the polarity in this case */
-		write_mmcr_word(SC520_INTPINPOL,
-				read_mmcr_word(SC520_INTPINPOL) | (1 << (pci_pin-4)));
-
+		sc520_mmcr->intpinpol = sc520_mmcr->intpinpol | (1 << (pci_pin-4));
 	}
 
 	/* register the pin */
@@ -124,7 +124,7 @@
 		       SC520_PCI_MEMORY_BUS,
 		       SC520_PCI_MEMORY_PHYS,
 		       SC520_PCI_MEMORY_SIZE,
-		       PCI_REGION_MEM | PCI_REGION_MEMORY);
+		       PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
 
 	/* PCI memory space */
 	pci_set_region(hose->regions + 1,

diff --git a/cpu/i386/sc520/sc520_ssi.c b/cpu/i386/sc520/sc520_ssi.c
index dd667ca..8dbe17a 100644
--- a/cpu/i386/sc520/sc520_ssi.c
+++ b/cpu/i386/sc520/sc520_ssi.c

@@ -61,32 +61,34 @@
 		temp |= PHS_INV_ENB;
 	}
 
-	write_mmcr_byte(SC520_SSICTL, temp);
+	sc520_mmcr->ssictl = temp;
 
 	return 0;
 }
 
 u8 ssi_txrx_byte(u8 data)
 {
-	write_mmcr_byte(SC520_SSIXMIT, data);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMITRCV);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	return read_mmcr_byte(SC520_SSIRCV);
+	sc520_mmcr->ssixmit = data;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMITRCV;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+
+	return sc520_mmcr->ssircv;
 }
 
 
 void ssi_tx_byte(u8 data)
 {
-	write_mmcr_byte(SC520_SSIXMIT, data);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_XMIT);
+	sc520_mmcr->ssixmit = data;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_XMIT;
 }
 
 u8 ssi_rx_byte(void)
 {
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	write_mmcr_byte(SC520_SSICMD, SSICMD_CMD_SEL_RCV);
-	while ((read_mmcr_byte(SC520_SSISTA)) & SSISTA_BSY);
-	return read_mmcr_byte(SC520_SSIRCV);
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+	sc520_mmcr->ssicmd = SSICMD_CMD_SEL_RCV;
+	while (sc520_mmcr->ssista & SSISTA_BSY);
+
+	return sc520_mmcr->ssircv;
 }

diff --git a/cpu/i386/sc520/sc520_timer.c b/cpu/i386/sc520/sc520_timer.c
index 2cb8656..23de14b 100644
--- a/cpu/i386/sc520/sc520_timer.c
+++ b/cpu/i386/sc520/sc520_timer.c

@@ -30,32 +30,29 @@
 void sc520_timer_isr(void)
 {
 	/* Ack the GP Timer Interrupt */
-	write_mmcr_byte (SC520_GPTMRSTA, 0x02);
+	sc520_mmcr->gptmrsta = 0x02;
 }
 
 int timer_init(void)
 {
 	/* Map GP Timer 1 to Master PIC IR0  */
-	write_mmcr_byte (SC520_GPTMR1MAP, 0x01);
+	sc520_mmcr->gp_tmr_int_map[1] = 0x01;
 
 	/* Disable GP Timers 1 & 2 - Allow configuration writes */
-	write_mmcr_word (SC520_GPTMR1CTL, 0x4000);
-	write_mmcr_word (SC520_GPTMR2CTL, 0x4000);
+	sc520_mmcr->gptmr1ctl = 0x4000;
+	sc520_mmcr->gptmr2ctl = 0x4000;
 
 	/* Reset GP Timers 1 & 2 */
-	write_mmcr_word (SC520_GPTMR1CNT, 0x0000);
-	write_mmcr_word (SC520_GPTMR2CNT, 0x0000);
+	sc520_mmcr->gptmr1cnt = 0x0000;
+	sc520_mmcr->gptmr2cnt = 0x0000;
 
 	/* Setup GP Timer 2 as a 100kHz (10us) prescaler */
-	write_mmcr_word (SC520_GPTMR2MAXCMPA, 83);
-	write_mmcr_word (SC520_GPTMR2CTL, 0xc001);
+	sc520_mmcr->gptmr2maxcmpa = 83;
+	sc520_mmcr->gptmr2ctl = 0xc001;
 
 	/* Setup GP Timer 1 as a 1000 Hz (1ms) interrupt generator */
-	write_mmcr_word (SC520_GPTMR1MAXCMPA, 100);
-	write_mmcr_word (SC520_GPTMR1CTL, 0xe009);
-
-	/* Clear the GP Timers status register */
-	write_mmcr_byte (SC520_GPTMRSTA, 0x07);
+	sc520_mmcr->gptmr1maxcmpa = 100;
+	sc520_mmcr->gptmr1ctl = 0xe009;
 
 	/* Register the SC520 specific timer interrupt handler */
 	register_timer_isr (sc520_timer_isr);
@@ -64,6 +61,9 @@
 	irq_install_handler (0, timer_isr, NULL);
 	unmask_irq (0);
 
+	/* Clear the GP Timer 1 status register to get the show rolling*/
+	sc520_mmcr->gptmrsta = 0x02;
+
 	return 0;
 }
 
@@ -71,12 +71,13 @@
 {
 	int m = 0;
 	long u;
+	long temp;
 
-	read_mmcr_word (SC520_SWTMRMILLI);
-	read_mmcr_word (SC520_SWTMRMICRO);
+	temp = sc520_mmcr->swtmrmilli;
+	temp = sc520_mmcr->swtmrmicro;
 
 	do {
-		m += read_mmcr_word (SC520_SWTMRMILLI);
-		u = read_mmcr_word (SC520_SWTMRMICRO) + (m * 1000);
+		m += sc520_mmcr->swtmrmilli;
+		u = sc520_mmcr->swtmrmicro + (m * 1000);
 	} while (u < usec);
 }

diff --git a/cpu/ixp/config.mk b/cpu/ixp/config.mk
index 2c33b40..deca3f4 100644
--- a/cpu/ixp/config.mk
+++ b/cpu/ixp/config.mk

@@ -24,8 +24,7 @@
 
 BIG_ENDIAN = y
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float -mbig-endian
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float -mbig-endian
 
 PLATFORM_CPPFLAGS += -mbig-endian -march=armv5te -mtune=strongarm1100
 # =========================================================================

diff --git a/cpu/lh7a40x/config.mk b/cpu/lh7a40x/config.mk
index 27bc481..47b2b7b 100644
--- a/cpu/lh7a40x/config.mk
+++ b/cpu/lh7a40x/config.mk

@@ -21,8 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4
 # =========================================================================

diff --git a/cpu/mpc824x/config.mk b/cpu/mpc824x/config.mk
index 1bb0487..b607fee 100644
--- a/cpu/mpc824x/config.mk
+++ b/cpu/mpc824x/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_MPC824X -ffixed-r2 -mstring -mcpu=603e -msoft-float
 

diff --git a/cpu/mpc83xx/serdes.c b/cpu/mpc83xx/serdes.c
index 283cc3f..64033fe 100644
--- a/cpu/mpc83xx/serdes.c
+++ b/cpu/mpc83xx/serdes.c

@@ -2,7 +2,7 @@
  * Freescale SerDes initialization routine
  *
  * Copyright (C) 2007 Freescale Semicondutor, Inc.
- * Copyright (C) 2008 MontaVista Software, Inc. All rights reserved.
+ * Copyright (C) 2008 MontaVista Software, Inc.
  *
  * Author: Li Yang <leoli@freescale.com>
  *

diff --git a/cpu/mpc8xx/config.mk b/cpu/mpc8xx/config.mk
index 6031e7f..2b3d545 100644
--- a/cpu/mpc8xx/config.mk
+++ b/cpu/mpc8xx/config.mk

@@ -21,6 +21,6 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 
 PLATFORM_CPPFLAGS += -DCONFIG_8xx -ffixed-r2 -mstring -mcpu=860 -msoft-float

diff --git a/cpu/ppc4xx/config.mk b/cpu/ppc4xx/config.mk
index baa97a4..00ad39b 100644
--- a/cpu/ppc4xx/config.mk
+++ b/cpu/ppc4xx/config.mk

@@ -21,7 +21,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi -fno-strict-aliasing
+PLATFORM_RELFLAGS += -fPIC -ffixed-r14 -meabi
 PLATFORM_CPPFLAGS += -DCONFIG_4xx -ffixed-r2 -mstring -msoft-float
 
 cfg=$(shell grep configs $(OBJTREE)/include/config.h | sed 's/.*<\(configs.*\)>/\1/')

diff --git a/cpu/pxa/config.mk b/cpu/pxa/config.mk
index f360478..a05d69c 100644
--- a/cpu/pxa/config.mk
+++ b/cpu/pxa/config.mk

@@ -22,8 +22,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv5te -mtune=xscale
 # =========================================================================

diff --git a/cpu/s3c44b0/config.mk b/cpu/s3c44b0/config.mk
index 3623f25..7454d72 100644
--- a/cpu/s3c44b0/config.mk
+++ b/cpu/s3c44b0/config.mk

@@ -22,8 +22,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=arm7tdmi -msoft-float
 # =========================================================================

diff --git a/cpu/sa1100/config.mk b/cpu/sa1100/config.mk
index 553cd0c..6f21f41 100644
--- a/cpu/sa1100/config.mk
+++ b/cpu/sa1100/config.mk

@@ -22,8 +22,7 @@
 # MA 02111-1307 USA
 #
 
-PLATFORM_RELFLAGS += -fno-strict-aliasing  -fno-common -ffixed-r8 \
-	-msoft-float
+PLATFORM_RELFLAGS += -fno-common -ffixed-r8 -msoft-float
 
 PLATFORM_CPPFLAGS += -march=armv4 -mtune=strongarm1100
 # =========================================================================

diff --git a/doc/README.standalone b/doc/README.standalone
index 81b949a..885c92f 100644
--- a/doc/README.standalone
+++ b/doc/README.standalone

@@ -21,7 +21,7 @@
 2. The pointer to the jump table is passed to the application in a
    machine-dependent way. PowerPC, ARM, MIPS and Blackfin architectures
    use a dedicated register to hold the pointer to the 'global_data'
-   structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P5 on Blackfin.
+   structure: r2 on PowerPC, r8 on ARM, k0 on MIPS, and P3 on Blackfin.
    The x86 architecture does not use such a register; instead, the
    pointer to the 'global_data' structure is passed as 'argv[-1]'
    pointer.

diff --git a/drivers/block/ata_piix.c b/drivers/block/ata_piix.c
index 549de31..c81d11a 100644
--- a/drivers/block/ata_piix.c
+++ b/drivers/block/ata_piix.c

@@ -310,7 +310,7 @@
 	}
 
 	if (status & ATA_BUSY)
-		printf ("ata%u is slow to respond,plz be patient\n", port);
+		printf ("ata%u is slow to respond,plz be patient\n", num);
 
 	while ((status & ATA_BUSY)) {
 		msleep (100);
@@ -318,7 +318,7 @@
 	}
 
 	if (status & ATA_BUSY) {
-		printf ("ata%u failed to respond : ", port);
+		printf ("ata%u failed to respond : ", num);
 		printf ("bus reset failed\n");
 		return 1;
 	}
@@ -389,11 +389,11 @@
 		return;
 	}
 
-	sata_cpy (sata_dev_desc[devno].revision, iop->fw_rev,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].revision, iop->fw_rev,
 		  sizeof (sata_dev_desc[devno].revision));
-	sata_cpy (sata_dev_desc[devno].vendor, iop->model,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].vendor, iop->model,
 		  sizeof (sata_dev_desc[devno].vendor));
-	sata_cpy (sata_dev_desc[devno].product, iop->serial_no,
+	sata_cpy ((unsigned char *)sata_dev_desc[devno].product, iop->serial_no,
 		  sizeof (sata_dev_desc[devno].product));
 	strswab (sata_dev_desc[devno].revision);
 	strswab (sata_dev_desc[devno].vendor);

diff --git a/drivers/block/ata_piix.h b/drivers/block/ata_piix.h
index 11885af..9157cf8 100644
--- a/drivers/block/ata_piix.h
+++ b/drivers/block/ata_piix.h

@@ -37,20 +37,7 @@
 
 /***********SATA LIBRARY SPECIFIC DEFINITIONS AND DECLARATIONS**************/
 #ifdef SATA_DECL		/*SATA library specific declarations */
-#define ata_id_has_lba48(id)    ((id)[83] & (1 << 10))
-#define ata_id_has_lba(id)      ((id)[49] & (1 << 9))
-#define ata_id_has_dma(id)      ((id)[49] & (1 << 8))
-#define ata_id_u32(id,n)        \
-	(((u32) (id)[(n) + 1] << 16) | ((u32) (id)[(n)]))
-#define ata_id_u64(id,n)        \
-	(((u64) (id)[(n) + 3] << 48) | \
-	((u64) (id)[(n) + 2] << 32) | \
-	((u64) (id)[(n) + 1] << 16) | \
-	((u64) (id)[(n) + 0]) )
-#endif
-
-#ifdef SATA_DECL		/*SATA library specific declarations */
-static inline void
+inline void
 ata_dump_id (u16 * id)
 {
 	PRINTF ("49 = 0x%04x  "

diff --git a/drivers/hwmon/ds1722.c b/drivers/hwmon/ds1722.c
index 7e2f1ed..a46cd4d 100644
--- a/drivers/hwmon/ds1722.c
+++ b/drivers/hwmon/ds1722.c

@@ -1,6 +1,7 @@
 
 #include <common.h>
-#include <ssi.h>
+#include <asm/ic/ssi.h>
+#include <ds1722.h>
 
 static void ds1722_select(int dev)
 {

diff --git a/drivers/input/keyboard.c b/drivers/input/keyboard.c
index a5fbd5f..614592e 100644
--- a/drivers/input/keyboard.c
+++ b/drivers/input/keyboard.c

@@ -3,7 +3,6 @@
  * (C) Copyright 2004
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * Keyboard driver
  *

diff --git a/drivers/input/pc_keyb.c b/drivers/input/pc_keyb.c
index 25ad3e4..1606ab3 100644
--- a/drivers/input/pc_keyb.c
+++ b/drivers/input/pc_keyb.c

@@ -3,7 +3,6 @@
  * (C) Copyright 2004
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * PS/2 keyboard driver
  *

diff --git a/drivers/input/ps2mult.c b/drivers/input/ps2mult.c
index ecd5853..ab74933 100644
--- a/drivers/input/ps2mult.c
+++ b/drivers/input/ps2mult.c

@@ -3,7 +3,6 @@
  * (C) Copyright 2004
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * PS/2 multiplexer driver
  *

diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c
index 1a5e2d4..1b20a76 100644
--- a/drivers/input/ps2ser.c
+++ b/drivers/input/ps2ser.c

@@ -3,7 +3,6 @@
  * (C) Copyright 2004-2009
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * Simple 16550A serial driver
  *

diff --git a/drivers/mtd/nand/mxc_nand.c b/drivers/mtd/nand/mxc_nand.c
index 647be0b..eb0323f 100644
--- a/drivers/mtd/nand/mxc_nand.c
+++ b/drivers/mtd/nand/mxc_nand.c

@@ -1,5 +1,5 @@
 /*
- * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
+ * Copyright 2004-2007 Freescale Semiconductor, Inc.
  * Copyright 2008 Sascha Hauer, kernel@pengutronix.de
  * Copyright 2009 Ilya Yanok, <yanok@emcraft.com>
  *

diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c
index b8dd9f2..7f9f783 100644
--- a/drivers/net/e1000.c
+++ b/drivers/net/e1000.c

@@ -50,7 +50,8 @@
 #define bus_to_phys(devno, a)	pci_mem_to_phys(devno, a)
 #define mdelay(n)	udelay((n)*1000)
 
-#define E1000_DEFAULT_PBA    0x000a0026
+#define E1000_DEFAULT_PCI_PBA	0x00000030
+#define E1000_DEFAULT_PCIE_PBA	0x000a0026
 
 /* NIC specific static variables go here */
 
@@ -1349,9 +1350,16 @@
 	uint32_t ctrl_ext;
 	uint32_t icr;
 	uint32_t manc;
+	uint32_t pba = 0;
 
 	DEBUGFUNC();
 
+	/* get the correct pba value for both PCI and PCIe*/
+	if (hw->mac_type <  e1000_82571)
+		pba = E1000_DEFAULT_PCI_PBA;
+	else
+		pba = E1000_DEFAULT_PCIE_PBA;
+
 	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
 	if (hw->mac_type == e1000_82542_rev2_0) {
 		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
@@ -1419,7 +1427,7 @@
 	if (hw->mac_type == e1000_82542_rev2_0) {
 		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
 	}
-	E1000_WRITE_REG(hw, PBA, E1000_DEFAULT_PBA);
+	E1000_WRITE_REG(hw, PBA, pba);
 }
 
 /******************************************************************************

diff --git a/drivers/pcmcia/ti_pci1410a.c b/drivers/pcmcia/ti_pci1410a.c
index 6ab9759..4ac2e0f 100644
--- a/drivers/pcmcia/ti_pci1410a.c
+++ b/drivers/pcmcia/ti_pci1410a.c

@@ -68,13 +68,12 @@
 
 int pcmcia_on(int ide_base_bus);
 
-static int  pcmcia_off(void);
 static int  hardware_disable(int slot);
 static int  hardware_enable(int slot);
 static int  voltage_set(int slot, int vcc, int vpp);
 static void print_funcid(int func);
-static void print_fixed(volatile uchar *p);
-static int  identify(volatile uchar *p);
+static void print_fixed(volatile char *p);
+static int  identify(volatile char *p);
 static int  check_ide_device(int slot, int ide_base_bus);
 
 
@@ -86,33 +85,6 @@
 /* ------------------------------------------------------------------------- */
 
 
-int do_pinit(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
-{
-#ifndef CONFIG_SYS_FIRST_PCMCIA_BUS
-# define CONFIG_SYS_FIRST_PCMCIA_BUS 0
-#endif
-
-	int rcode = 0;
-
-	if (argc != 2) {
-		printf ("Usage: pinit {on | off}\n");
-		return 1;
-	}
-	if (strcmp(argv[1],"on") == 0) {
-		rcode = pcmcia_on(CONFIG_SYS_FIRST_PCMCIA_BUS);
-	} else if (strcmp(argv[1],"off") == 0) {
-		rcode = pcmcia_off();
-	} else {
-		printf ("Usage: pinit {on | off}\n");
-		return 1;
-	}
-
-	return rcode;
-}
-
-/* ------------------------------------------------------------------------- */
-
-
 static struct pci_device_id supported[] = {
 	{ PCI_VENDOR_ID_TI, 0xac50 }, /* Ti PCI1410A */
 	{ PCI_VENDOR_ID_TI, 0xac56 }, /* Ti PCI1510 */
@@ -245,7 +217,8 @@
 /* ------------------------------------------------------------------------- */
 
 
-static int pcmcia_off (void)
+#if defined(CONFIG_CMD_PCMCIA)
+int pcmcia_off (void)
 {
 	int slot = 0;
 
@@ -285,6 +258,7 @@
 	return 0;
 }
 
+#endif
 
 /* ------------------------------------------------------------------------- */
 
@@ -294,9 +268,9 @@
 int ide_devices_found;
 static int check_ide_device(int slot, int ide_base_bus)
 {
-	volatile uchar *ident = NULL;
-	volatile uchar *feature_p[MAX_FEATURES];
-	volatile uchar *p, *start;
+	volatile char *ident = NULL;
+	volatile char *feature_p[MAX_FEATURES];
+	volatile char *p, *start;
 	int n_features = 0;
 	uchar func_id = ~0;
 	uchar code, len;
@@ -314,7 +288,7 @@
 		return 1;
 	}
 
-	start = p = (volatile uchar *) pcmcia_cis_ptr;
+	start = p = (volatile char *) pcmcia_cis_ptr;
 
 	while ((p - start) < MAX_TUPEL_SZ) {
 
@@ -417,7 +391,7 @@
 		socket_control |= 0x30;
 		break;
 	case 0:
-	default:
+	default: ;
 	}
 
 	switch (vpp) {
@@ -431,7 +405,7 @@
 		socket_control |= 0x3;
 		break;
 	case 0:
-	default:
+	default: ;
 	}
 
 	writel(socket_control, reg);
@@ -537,7 +511,7 @@
 
 /* ------------------------------------------------------------------------- */
 
-static void print_fixed(volatile uchar *p)
+static void print_fixed(volatile char *p)
 {
 	if (p == NULL)
 		return;
@@ -605,17 +579,17 @@
 #define MAX_IDENT_CHARS		64
 #define	MAX_IDENT_FIELDS	4
 
-static uchar *known_cards[] = {
+static char *known_cards[] = {
 	"ARGOSY PnPIDE D5",
 	NULL
 };
 
-static int identify(volatile uchar *p)
+static int identify(volatile char *p)
 {
-	uchar id_str[MAX_IDENT_CHARS];
-	uchar data;
-	uchar *t;
-	uchar **card;
+	char id_str[MAX_IDENT_CHARS];
+	char data;
+	char *t;
+	char **card;
 	int i, done;
 
 	if (p == NULL)

diff --git a/examples/standalone/.gitignore b/examples/standalone/.gitignore
index 0d1864c..7b783fc 100644
--- a/examples/standalone/.gitignore
+++ b/examples/standalone/.gitignore

@@ -1,4 +1,5 @@
 /82559_eeprom
+/atmel_df_pow2
 /hello_world
 /interrupt
 /mem_to_mem_idma2intr

diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index d2e811a..bc98120 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile

@@ -21,71 +21,16 @@
 # MA 02111-1307 USA
 #
 
-ifeq ($(ARCH),ppc)
-LOAD_ADDR = 0x40000
-endif
-
-ifeq ($(ARCH),i386)
-LOAD_ADDR = 0x40000
-endif
-
-ifeq ($(ARCH),arm)
-ifeq ($(BOARD),omap2420h4)
-LOAD_ADDR = 0x80300000
-else
-ifeq ($(SOC),omap3)
-LOAD_ADDR = 0x80300000
-else
-LOAD_ADDR = 0xc100000
-endif
-endif
-endif
-
-ifeq ($(ARCH),mips)
-LOAD_ADDR = 0x80200000 -T mips.lds
-endif
-
-ifeq ($(ARCH),nios)
-LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
-endif
-
-ifeq ($(ARCH),nios2)
-LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds
-endif
-
-ifeq ($(ARCH),m68k)
-LOAD_ADDR = 0x20000  -L $(clibdir)
-endif
-
-ifeq ($(ARCH),microblaze)
-LOAD_ADDR = 0x80F00000
-endif
-
-ifeq ($(ARCH),blackfin)
-LOAD_ADDR = 0x1000
-endif
-
-ifeq ($(ARCH),avr32)
-LOAD_ADDR = 0x00000000
-endif
-
-ifeq ($(ARCH),sh)
-LOAD_ADDR = 0x8C000000
-ifeq ($(CPU),sh2)
-BIG_ENDIAN=y
-endif
-endif
-
-ifeq ($(ARCH),sparc)
-LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds
-endif
-
 include $(TOPDIR)/config.mk
 
 ELF	= hello_world
 SREC	= hello_world.srec
 BIN	= hello_world.bin
 
+ELF	+= atmel_df_pow2
+SREC	+= atmel_df_pow2.srec
+BIN	+= atmel_df_pow2.bin
+
 ifeq ($(CPU),mpc8xx)
 ELF	+= test_burst
 SREC	+= test_burst.srec
@@ -139,9 +84,6 @@
 BIN	+= eepro100_eeprom.bin
 endif
 
-ifeq ($(BIG_ENDIAN),y)
-EX_LDFLAGS += -EB
-endif
 
 COBJS	:= $(SREC:.srec=.o)
 
@@ -164,7 +106,6 @@
 SREC	:= $(addprefix $(obj),$(SREC))
 
 gcclibdir := $(shell dirname `$(CC) -print-libgcc-file-name`)
-clibdir := $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
 
 CPPFLAGS += -I..
 
@@ -176,7 +117,7 @@
 
 $(ELF):
 $(obj)%:	$(obj)%.o $(LIB)
-		$(LD) -g $(EX_LDFLAGS) -Ttext $(LOAD_ADDR) \
+		$(LD) -g -Ttext $(STANDALONE_LOAD_ADDR) \
 			-o $@ -e $(SYM_PREFIX)$(notdir $(<:.o=)) $< $(LIB) \
 			-L$(gcclibdir) -lgcc
 

diff --git a/examples/standalone/atmel_df_pow2.c b/examples/standalone/atmel_df_pow2.c
new file mode 100644
index 0000000..db0cd69
--- /dev/null
+++ b/examples/standalone/atmel_df_pow2.c

@@ -0,0 +1,209 @@
+/*
+ * atmel_df_pow2.c - convert Atmel Dataflashes to Power of 2 mode
+ *
+ * Copyright 2009 Analog Devices Inc.
+ *
+ * Licensed under the 2-clause BSD.
+ */
+
+#include <common.h>
+#include <exports.h>
+
+#define CMD_ID    0x9f
+#define CMD_STAT  0xd7
+#define CMD_CFG   0x3d
+
+static int flash_cmd(struct spi_slave *slave, uchar cmd, uchar *buf, int len)
+{
+	buf[0] = cmd;
+	return spi_xfer(slave, 8 * len, buf, buf, SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static int flash_status(struct spi_slave *slave)
+{
+	uchar buf[2];
+	if (flash_cmd(slave, CMD_STAT, buf, sizeof(buf)))
+		return -1;
+	return buf[1];
+}
+
+static int flash_set_pow2(struct spi_slave *slave)
+{
+	int ret;
+	uchar buf[4];
+
+	buf[1] = 0x2a;
+	buf[2] = 0x80;
+	buf[3] = 0xa6;
+
+	ret = flash_cmd(slave, CMD_CFG, buf, sizeof(buf));
+	if (ret)
+		return ret;
+
+	/* wait Tp, or 6 msec */
+	udelay(6000);
+
+	ret = flash_status(slave);
+	if (ret == -1)
+		return 1;
+
+	return ret & 0x1 ? 0 : 1;
+}
+
+static int flash_check(struct spi_slave *slave)
+{
+	int ret;
+	uchar buf[4];
+
+	ret = flash_cmd(slave, CMD_ID, buf, sizeof(buf));
+	if (ret)
+		return ret;
+
+	if (buf[1] != 0x1F) {
+		printf("atmel flash not found (id[0] = %#x)\n", buf[1]);
+		return 1;
+	}
+
+	if ((buf[2] >> 5) != 0x1) {
+		printf("AT45 flash not found (id[0] = %#x)\n", buf[2]);
+		return 2;
+	}
+
+	return 0;
+}
+
+static char *getline(void)
+{
+	static char buffer[100];
+	char c;
+	size_t i;
+
+	i = 0;
+	while (1) {
+		buffer[i] = '\0';
+
+		c = getc();
+
+		switch (c) {
+		case '\r':	/* Enter/Return key */
+		case '\n':
+			puts("\n");
+			return buffer;
+
+		case 0x03:	/* ^C - break */
+			return NULL;
+
+		case 0x5F:
+		case 0x08:	/* ^H  - backspace */
+		case 0x7F:	/* DEL - backspace */
+			if (i) {
+				puts("\b \b");
+				i--;
+			}
+			break;
+
+		default:
+			/* Ignore control characters */
+			if (c < 0x20)
+				break;
+			/* Queue up all other characters */
+			buffer[i++] = c;
+			printf("%c", c);
+			break;
+		}
+	}
+}
+
+int atmel_df_pow2(int argc, char *argv[])
+{
+	/* Print the ABI version */
+	app_startup(argv);
+	if (XF_VERSION != get_version()) {
+		printf("Expects ABI version %d\n", XF_VERSION);
+		printf("Actual U-Boot ABI version %lu\n", get_version());
+		printf("Can't run\n\n");
+		return 1;
+	}
+
+	spi_init();
+
+	while (1) {
+		struct spi_slave *slave;
+		char *line, *p;
+		int bus, cs, status;
+
+		puts("\nenter the [BUS:]CS of the SPI flash: ");
+		line = getline();
+
+		/* CTRL+C */
+		if (!line)
+			return 0;
+		if (line[0] == '\0')
+			continue;
+
+		bus = cs = simple_strtoul(line, &p, 10);
+		if (*p) {
+			if (*p == ':') {
+				++p;
+				cs = simple_strtoul(p, &p, 10);
+			}
+			if (*p) {
+				puts("invalid format, please try again\n");
+				continue;
+			}
+		} else
+			bus = 0;
+
+		printf("\ngoing to work with dataflash at %i:%i\n", bus, cs);
+
+		/* use a low speed -- it'll work with all devices, and
+		 * speed here doesn't really matter.
+		 */
+		slave = spi_setup_slave(bus, cs, 1000, SPI_MODE_3);
+		if (!slave) {
+			puts("unable to setup slave\n");
+			continue;
+		}
+
+		if (spi_claim_bus(slave)) {
+			spi_free_slave(slave);
+			continue;
+		}
+
+		if (flash_check(slave)) {
+			puts("no flash found\n");
+			goto done;
+		}
+
+		status = flash_status(slave);
+		if (status == -1) {
+			puts("unable to read status register\n");
+			goto done;
+		}
+		if (status & 0x1) {
+			puts("flash is already in power-of-2 mode!\n");
+			goto done;
+		}
+
+		puts("are you sure you wish to set power-of-2 mode?\n");
+		puts("this operation is permanent and irreversible\n");
+		printf("enter YES to continue: ");
+		line = getline();
+		if (!line || strcmp(line, "YES"))
+			goto done;
+
+		if (flash_set_pow2(slave)) {
+			puts("setting pow2 mode failed\n");
+			goto done;
+		}
+
+		puts(
+			"Configuration should be updated now.  You will have to\n"
+			"power cycle the part in order to finish the conversion.\n"
+		);
+
+ done:
+		spi_release_bus(slave);
+		spi_free_slave(slave);
+	}
+}

diff --git a/examples/standalone/stubs.c b/examples/standalone/stubs.c
index a8cb954..339bbf9 100644
--- a/examples/standalone/stubs.c
+++ b/examples/standalone/stubs.c

@@ -127,14 +127,14 @@
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "r5");
 #elif defined(CONFIG_BLACKFIN)
 /*
- * P5 holds the pointer to the global_data, P0 is a call-clobbered
+ * P3 holds the pointer to the global_data, P0 is a call-clobbered
  * register
  */
 #define EXPORT_FUNC(x)			\
 	asm volatile (			\
 "	.globl _" #x "\n_"		\
 #x ":\n"				\
-"	P0 = [P5 + %0]\n"		\
+"	P0 = [P3 + %0]\n"		\
 "	P0 = [P0 + %1]\n"		\
 "	JUMP (P0)\n"			\
 	: : "i"(offsetof(gd_t, jt)), "i"(XF_ ## x * sizeof(void *)) : "P0");

diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h
index 5293d67..6c1f5ac 100644
--- a/include/asm-arm/mach-types.h
+++ b/include/asm-arm/mach-types.h

@@ -1,6 +1,9 @@
 /*
- * This was automagically generated from arch/arm/tools/mach-types!
+ * This was automagically generated from mach-types!
  * Do NOT edit
+ *
+ * Last update: Fri Sep 4 22:16:22 2009
+ *
  */
 
 #ifndef __ASM_ARM_MACH_TYPE_H
@@ -1451,7 +1454,7 @@
 #define MACH_TYPE_H6044                1458
 #define MACH_TYPE_APP                  1459
 #define MACH_TYPE_TCT_HAMMER           1460
-#define MACH_TYPE_HERMES               1461
+#define MACH_TYPE_HERALD               1461
 #define MACH_TYPE_ARTEMIS              1462
 #define MACH_TYPE_HTCTITAN             1463
 #define MACH_TYPE_QRANIUM              1464
@@ -1765,7 +1768,7 @@
 #define MACH_TYPE_MI424WR              1778
 #define MACH_TYPE_AXS_ULTRAX           1779
 #define MACH_TYPE_AT572D940DEB         1780
-#define MACH_TYPE_DAVINCI_DA8XX_EVM    1781
+#define MACH_TYPE_DAVINCI_DA830_EVM    1781
 #define MACH_TYPE_EP9302               1782
 #define MACH_TYPE_AT572D940HFEB        1783
 #define MACH_TYPE_CYBOOK3              1784
@@ -2241,6 +2244,163 @@
 #define MACH_TYPE_OMAP3_WL_FF          2258
 #define MACH_TYPE_SIMCOM               2259
 #define MACH_TYPE_MCWEBIO              2260
+#define MACH_TYPE_OMAP3_PHRAZER        2261
+#define MACH_TYPE_DARWIN               2262
+#define MACH_TYPE_ORATISCOMU           2263
+#define MACH_TYPE_RTSBC20              2264
+#define MACH_TYPE_I780                 2265
+#define MACH_TYPE_GEMINI324            2266
+#define MACH_TYPE_ORATISLAN            2267
+#define MACH_TYPE_ORATISALOG           2268
+#define MACH_TYPE_ORATISMADI           2269
+#define MACH_TYPE_ORATISOT16           2270
+#define MACH_TYPE_ORATISDESK           2271
+#define MACH_TYPE_V2P_CA9              2272
+#define MACH_TYPE_SINTEXO              2273
+#define MACH_TYPE_CM3389               2274
+#define MACH_TYPE_OMAP3_CIO            2275
+#define MACH_TYPE_SGH_I900             2276
+#define MACH_TYPE_BST100               2277
+#define MACH_TYPE_PASSION              2278
+#define MACH_TYPE_INDESIGN_AT91SAM     2279
+#define MACH_TYPE_C4_BADGER            2280
+#define MACH_TYPE_C4_VIPER             2281
+#define MACH_TYPE_D2NET                2282
+#define MACH_TYPE_BIGDISK              2283
+#define MACH_TYPE_NOTALVISION          2284
+#define MACH_TYPE_OMAP3_KBOC           2285
+#define MACH_TYPE_CYCLONE              2286
+#define MACH_TYPE_NINJA                2287
+#define MACH_TYPE_AT91SAM9G20EK_2MMC   2288
+#define MACH_TYPE_BCMRING              2289
+#define MACH_TYPE_RESOL_DL2            2290
+#define MACH_TYPE_IFOSW                2291
+#define MACH_TYPE_HTCRHODIUM           2292
+#define MACH_TYPE_HTCTOPAZ             2293
+#define MACH_TYPE_MATRIX504            2294
+#define MACH_TYPE_MRFSA                2295
+#define MACH_TYPE_SC_P270              2296
+#define MACH_TYPE_ATLAS5_EVB           2297
+#define MACH_TYPE_PELCO_LOBOX          2298
+#define MACH_TYPE_DILAX_PCU200         2299
+#define MACH_TYPE_LEONARDO             2300
+#define MACH_TYPE_ZORAN_APPROACH7      2301
+#define MACH_TYPE_DP6XX                2302
+#define MACH_TYPE_BCM2153_VESPER       2303
+#define MACH_TYPE_MAHIMAHI             2304
+#define MACH_TYPE_CLICKC               2305
+#define MACH_TYPE_ZB_GATEWAY           2306
+#define MACH_TYPE_TAZCARD              2307
+#define MACH_TYPE_TAZDEV               2308
+#define MACH_TYPE_ANNAX_CB_ARM         2309
+#define MACH_TYPE_ANNAX_DM3            2310
+#define MACH_TYPE_CEREBRIC             2311
+#define MACH_TYPE_ORCA                 2312
+#define MACH_TYPE_PC9260               2313
+#define MACH_TYPE_EMS285A              2314
+#define MACH_TYPE_GEC2410              2315
+#define MACH_TYPE_GEC2440              2316
+#define MACH_TYPE_ARCH_MW903           2317
+#define MACH_TYPE_MW2440               2318
+#define MACH_TYPE_ECAC2378             2319
+#define MACH_TYPE_TAZKIOSK             2320
+#define MACH_TYPE_WHITERABBIT_MCH      2321
+#define MACH_TYPE_SBOX9263             2322
+#define MACH_TYPE_OREO                 2323
+#define MACH_TYPE_SMDK6442             2324
+#define MACH_TYPE_OPENRD_BASE          2325
+#define MACH_TYPE_INCREDIBLE           2326
+#define MACH_TYPE_INCREDIBLEC          2327
+#define MACH_TYPE_HEROCT               2328
+#define MACH_TYPE_MMNET1000            2329
+#define MACH_TYPE_DEVKIT8000           2330
+#define MACH_TYPE_DEVKIT9000           2331
+#define MACH_TYPE_MX31TXTR             2332
+#define MACH_TYPE_U380                 2333
+#define MACH_TYPE_HUALU_BOARD          2334
+#define MACH_TYPE_NPCMX50              2335
+#define MACH_TYPE_MX51_LANGE51         2336
+#define MACH_TYPE_MX51_LANGE52         2337
+#define MACH_TYPE_RIOM                 2338
+#define MACH_TYPE_COMCAS               2339
+#define MACH_TYPE_WSI_MX27             2340
+#define MACH_TYPE_CM_T35               2341
+#define MACH_TYPE_NET2BIG              2342
+#define MACH_TYPE_MOTOROLA_A1600       2343
+#define MACH_TYPE_IGEP0020             2344
+#define MACH_TYPE_IGEP0010             2345
+#define MACH_TYPE_MV6281GTWGE2         2346
+#define MACH_TYPE_SCAT100              2347
+#define MACH_TYPE_SANMINA              2348
+#define MACH_TYPE_MOMENTO              2349
+#define MACH_TYPE_NUC9XX               2350
+#define MACH_TYPE_NUC910EVB            2351
+#define MACH_TYPE_NUC920EVB            2352
+#define MACH_TYPE_NUC950EVB            2353
+#define MACH_TYPE_NUC945EVB            2354
+#define MACH_TYPE_NUC960EVB            2355
+#define MACH_TYPE_NUC932EVB            2356
+#define MACH_TYPE_NUC900               2357
+#define MACH_TYPE_SD1SOC               2358
+#define MACH_TYPE_LN2440BC             2359
+#define MACH_TYPE_RSBC                 2360
+#define MACH_TYPE_OPENRD_CLIENT        2361
+#define MACH_TYPE_HPIPAQ11X            2362
+#define MACH_TYPE_WAYLAND              2363
+#define MACH_TYPE_ACNBSX102            2364
+#define MACH_TYPE_HWAT91               2365
+#define MACH_TYPE_AT91SAM9263CS        2366
+#define MACH_TYPE_CSB732               2367
+#define MACH_TYPE_U8500                2368
+#define MACH_TYPE_HUQIU                2369
+#define MACH_TYPE_MX51_KUNLUN          2370
+#define MACH_TYPE_PMT1G                2371
+#define MACH_TYPE_HTCELF               2372
+#define MACH_TYPE_ARMADILLO420         2373
+#define MACH_TYPE_ARMADILLO440         2374
+#define MACH_TYPE_U_CHIP_DUAL_ARM      2375
+#define MACH_TYPE_CSR_BDB3             2376
+#define MACH_TYPE_DOLBY_CAT1018        2377
+#define MACH_TYPE_HY9307               2378
+#define MACH_TYPE_A_ES                 2379
+#define MACH_TYPE_DAVINCI_IRIF         2380
+#define MACH_TYPE_AGAMA9263            2381
+#define MACH_TYPE_MARVELL_JASPER       2382
+#define MACH_TYPE_FLINT                2383
+#define MACH_TYPE_TAVOREVB3            2384
+#define MACH_TYPE_SCH_M490             2386
+#define MACH_TYPE_RBL01                2387
+#define MACH_TYPE_OMNIFI               2388
+#define MACH_TYPE_OTAVALO              2389
+#define MACH_TYPE_SIENNA               2390
+#define MACH_TYPE_HTC_EXCALIBUR_S620   2391
+#define MACH_TYPE_HTC_OPAL             2392
+#define MACH_TYPE_TOUCHBOOK            2393
+#define MACH_TYPE_LATTE                2394
+#define MACH_TYPE_XA200                2395
+#define MACH_TYPE_NIMROD               2396
+#define MACH_TYPE_CC9P9215_3G          2397
+#define MACH_TYPE_CC9P9215_3GJS        2398
+#define MACH_TYPE_TK71                 2399
+#define MACH_TYPE_COMHAM3525           2400
+#define MACH_TYPE_MX31EREBUS           2401
+#define MACH_TYPE_MCARDMX27            2402
+#define MACH_TYPE_PARADISE             2403
+#define MACH_TYPE_TIDE                 2404
+#define MACH_TYPE_WZL2440              2405
+#define MACH_TYPE_SDRDEMO              2406
+#define MACH_TYPE_ETHERCAN2            2407
+#define MACH_TYPE_ECMIMG20             2408
+#define MACH_TYPE_OMAP_DRAGON          2409
+#define MACH_TYPE_HALO                 2410
+#define MACH_TYPE_HUANGSHAN            2411
+#define MACH_TYPE_VL_MA2SC             2412
+#define MACH_TYPE_RAUMFELD_RC          2413
+#define MACH_TYPE_RAUMFELD_CONNECTOR   2414
+#define MACH_TYPE_RAUMFELD_SPEAKER     2415
+#define MACH_TYPE_MULTIBUS_MASTER      2416
+#define MACH_TYPE_MULTIBUS_PBK         2417
+#define MACH_TYPE_TNETV107X            2418
 
 #ifdef CONFIG_ARCH_EBSA110
 # ifdef machine_arch_type
@@ -19510,14 +19670,14 @@
 # define machine_is_tct_hammer()	(0)
 #endif
 
-#ifdef CONFIG_MACH_HERMES
+#ifdef CONFIG_MACH_HERALD
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_HERMES
+#  define machine_arch_type	MACH_TYPE_HERALD
 # endif
-# define machine_is_herald()	(machine_arch_type == MACH_TYPE_HERMES)
+# define machine_is_herald()	(machine_arch_type == MACH_TYPE_HERALD)
 #else
 # define machine_is_herald()	(0)
 #endif
@@ -23278,16 +23438,16 @@
 # define machine_is_at572d940deb()	(0)
 #endif
 
-#ifdef CONFIG_MACH_DAVINCI_DA8XX_EVM
+#ifdef CONFIG_MACH_DAVINCI_DA830_EVM
 # ifdef machine_arch_type
 #  undef machine_arch_type
 #  define machine_arch_type	__machine_arch_type
 # else
-#  define machine_arch_type	MACH_TYPE_DAVINCI_DA8XX_EVM
+#  define machine_arch_type	MACH_TYPE_DAVINCI_DA830_EVM
 # endif
-# define machine_is_davinci_da8xx_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA8XX_EVM)
+# define machine_is_davinci_da830_evm()	(machine_arch_type == MACH_TYPE_DAVINCI_DA830_EVM)
 #else
-# define machine_is_davinci_da8xx_evm()	(0)
+# define machine_is_davinci_da830_evm()	(0)
 #endif
 
 #ifdef CONFIG_MACH_EP9302
@@ -25601,9 +25761,9 @@
 # else
 #  define machine_arch_type	MACH_TYPE_CPUIMX27
 # endif
-# define machine_is_cpuimx27()	(machine_arch_type == MACH_TYPE_CPUIMX27)
+# define machine_is_eukrea_cpuimx27()	(machine_arch_type == MACH_TYPE_CPUIMX27)
 #else
-# define machine_is_cpuimx27()	(0)
+# define machine_is_eukrea_cpuimx27()	(0)
 #endif
 
 #ifdef CONFIG_MACH_CHEFLUX
@@ -28990,6 +29150,1890 @@
 # define machine_is_mcwebio()	(0)
 #endif
 
+#ifdef CONFIG_MACH_OMAP3_PHRAZER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_PHRAZER
+# endif
+# define machine_is_omap3_phrazer()	(machine_arch_type == MACH_TYPE_OMAP3_PHRAZER)
+#else
+# define machine_is_omap3_phrazer()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DARWIN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DARWIN
+# endif
+# define machine_is_darwin()	(machine_arch_type == MACH_TYPE_DARWIN)
+#else
+# define machine_is_darwin()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISCOMU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISCOMU
+# endif
+# define machine_is_oratiscomu()	(machine_arch_type == MACH_TYPE_ORATISCOMU)
+#else
+# define machine_is_oratiscomu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RTSBC20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RTSBC20
+# endif
+# define machine_is_rtsbc20()	(machine_arch_type == MACH_TYPE_RTSBC20)
+#else
+# define machine_is_rtsbc20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_I780
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_I780
+# endif
+# define machine_is_sgh_i780()	(machine_arch_type == MACH_TYPE_I780)
+#else
+# define machine_is_sgh_i780()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GEMINI324
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEMINI324
+# endif
+# define machine_is_gemini324()	(machine_arch_type == MACH_TYPE_GEMINI324)
+#else
+# define machine_is_gemini324()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISLAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISLAN
+# endif
+# define machine_is_oratislan()	(machine_arch_type == MACH_TYPE_ORATISLAN)
+#else
+# define machine_is_oratislan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISALOG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISALOG
+# endif
+# define machine_is_oratisalog()	(machine_arch_type == MACH_TYPE_ORATISALOG)
+#else
+# define machine_is_oratisalog()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISMADI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISMADI
+# endif
+# define machine_is_oratismadi()	(machine_arch_type == MACH_TYPE_ORATISMADI)
+#else
+# define machine_is_oratismadi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISOT16
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISOT16
+# endif
+# define machine_is_oratisot16()	(machine_arch_type == MACH_TYPE_ORATISOT16)
+#else
+# define machine_is_oratisot16()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORATISDESK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORATISDESK
+# endif
+# define machine_is_oratisdesk()	(machine_arch_type == MACH_TYPE_ORATISDESK)
+#else
+# define machine_is_oratisdesk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_V2P_CA9
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_V2P_CA9
+# endif
+# define machine_is_v2_ca9()	(machine_arch_type == MACH_TYPE_V2P_CA9)
+#else
+# define machine_is_v2_ca9()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SINTEXO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SINTEXO
+# endif
+# define machine_is_sintexo()	(machine_arch_type == MACH_TYPE_SINTEXO)
+#else
+# define machine_is_sintexo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM3389
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM3389
+# endif
+# define machine_is_cm3389()	(machine_arch_type == MACH_TYPE_CM3389)
+#else
+# define machine_is_cm3389()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_CIO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_CIO
+# endif
+# define machine_is_omap3_cio()	(machine_arch_type == MACH_TYPE_OMAP3_CIO)
+#else
+# define machine_is_omap3_cio()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SGH_I900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SGH_I900
+# endif
+# define machine_is_sgh_i900()	(machine_arch_type == MACH_TYPE_SGH_I900)
+#else
+# define machine_is_sgh_i900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BST100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BST100
+# endif
+# define machine_is_bst100()	(machine_arch_type == MACH_TYPE_BST100)
+#else
+# define machine_is_bst100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PASSION
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PASSION
+# endif
+# define machine_is_passion()	(machine_arch_type == MACH_TYPE_PASSION)
+#else
+# define machine_is_passion()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INDESIGN_AT91SAM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INDESIGN_AT91SAM
+# endif
+# define machine_is_indesign_at91sam()	(machine_arch_type == MACH_TYPE_INDESIGN_AT91SAM)
+#else
+# define machine_is_indesign_at91sam()	(0)
+#endif
+
+#ifdef CONFIG_MACH_C4_BADGER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_C4_BADGER
+# endif
+# define machine_is_c4_badger()	(machine_arch_type == MACH_TYPE_C4_BADGER)
+#else
+# define machine_is_c4_badger()	(0)
+#endif
+
+#ifdef CONFIG_MACH_C4_VIPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_C4_VIPER
+# endif
+# define machine_is_c4_viper()	(machine_arch_type == MACH_TYPE_C4_VIPER)
+#else
+# define machine_is_c4_viper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_D2NET
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_D2NET
+# endif
+# define machine_is_d2net()	(machine_arch_type == MACH_TYPE_D2NET)
+#else
+# define machine_is_d2net()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BIGDISK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BIGDISK
+# endif
+# define machine_is_bigdisk()	(machine_arch_type == MACH_TYPE_BIGDISK)
+#else
+# define machine_is_bigdisk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NOTALVISION
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NOTALVISION
+# endif
+# define machine_is_notalvision()	(machine_arch_type == MACH_TYPE_NOTALVISION)
+#else
+# define machine_is_notalvision()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP3_KBOC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP3_KBOC
+# endif
+# define machine_is_omap3_kboc()	(machine_arch_type == MACH_TYPE_OMAP3_KBOC)
+#else
+# define machine_is_omap3_kboc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CYCLONE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CYCLONE
+# endif
+# define machine_is_cyclone()	(machine_arch_type == MACH_TYPE_CYCLONE)
+#else
+# define machine_is_cyclone()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NINJA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NINJA
+# endif
+# define machine_is_ninja()	(machine_arch_type == MACH_TYPE_NINJA)
+#else
+# define machine_is_ninja()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9G20EK_2MMC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9G20EK_2MMC
+# endif
+# define machine_is_at91sam9g20ek_2mmc()	(machine_arch_type == MACH_TYPE_AT91SAM9G20EK_2MMC)
+#else
+# define machine_is_at91sam9g20ek_2mmc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCMRING
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCMRING
+# endif
+# define machine_is_bcmring()	(machine_arch_type == MACH_TYPE_BCMRING)
+#else
+# define machine_is_bcmring()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RESOL_DL2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RESOL_DL2
+# endif
+# define machine_is_resol_dl2()	(machine_arch_type == MACH_TYPE_RESOL_DL2)
+#else
+# define machine_is_resol_dl2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IFOSW
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IFOSW
+# endif
+# define machine_is_ifosw()	(machine_arch_type == MACH_TYPE_IFOSW)
+#else
+# define machine_is_ifosw()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCRHODIUM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCRHODIUM
+# endif
+# define machine_is_htcrhodium()	(machine_arch_type == MACH_TYPE_HTCRHODIUM)
+#else
+# define machine_is_htcrhodium()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCTOPAZ
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCTOPAZ
+# endif
+# define machine_is_htctopaz()	(machine_arch_type == MACH_TYPE_HTCTOPAZ)
+#else
+# define machine_is_htctopaz()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MATRIX504
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MATRIX504
+# endif
+# define machine_is_matrix504()	(machine_arch_type == MACH_TYPE_MATRIX504)
+#else
+# define machine_is_matrix504()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MRFSA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MRFSA
+# endif
+# define machine_is_mrfsa()	(machine_arch_type == MACH_TYPE_MRFSA)
+#else
+# define machine_is_mrfsa()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SC_P270
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SC_P270
+# endif
+# define machine_is_sc_p270()	(machine_arch_type == MACH_TYPE_SC_P270)
+#else
+# define machine_is_sc_p270()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ATLAS5_EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ATLAS5_EVB
+# endif
+# define machine_is_atlas5_evb()	(machine_arch_type == MACH_TYPE_ATLAS5_EVB)
+#else
+# define machine_is_atlas5_evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PELCO_LOBOX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PELCO_LOBOX
+# endif
+# define machine_is_pelco_lobox()	(machine_arch_type == MACH_TYPE_PELCO_LOBOX)
+#else
+# define machine_is_pelco_lobox()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DILAX_PCU200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DILAX_PCU200
+# endif
+# define machine_is_dilax_pcu200()	(machine_arch_type == MACH_TYPE_DILAX_PCU200)
+#else
+# define machine_is_dilax_pcu200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LEONARDO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LEONARDO
+# endif
+# define machine_is_leonardo()	(machine_arch_type == MACH_TYPE_LEONARDO)
+#else
+# define machine_is_leonardo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZORAN_APPROACH7
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZORAN_APPROACH7
+# endif
+# define machine_is_zoran_approach7()	(machine_arch_type == MACH_TYPE_ZORAN_APPROACH7)
+#else
+# define machine_is_zoran_approach7()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DP6XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DP6XX
+# endif
+# define machine_is_dp6xx()	(machine_arch_type == MACH_TYPE_DP6XX)
+#else
+# define machine_is_dp6xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_BCM2153_VESPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_BCM2153_VESPER
+# endif
+# define machine_is_bcm2153_vesper()	(machine_arch_type == MACH_TYPE_BCM2153_VESPER)
+#else
+# define machine_is_bcm2153_vesper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MAHIMAHI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MAHIMAHI
+# endif
+# define machine_is_mahimahi()	(machine_arch_type == MACH_TYPE_MAHIMAHI)
+#else
+# define machine_is_mahimahi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CLICKC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CLICKC
+# endif
+# define machine_is_clickc()	(machine_arch_type == MACH_TYPE_CLICKC)
+#else
+# define machine_is_clickc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ZB_GATEWAY
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ZB_GATEWAY
+# endif
+# define machine_is_zb_gateway()	(machine_arch_type == MACH_TYPE_ZB_GATEWAY)
+#else
+# define machine_is_zb_gateway()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAZCARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAZCARD
+# endif
+# define machine_is_tazcard()	(machine_arch_type == MACH_TYPE_TAZCARD)
+#else
+# define machine_is_tazcard()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAZDEV
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAZDEV
+# endif
+# define machine_is_tazdev()	(machine_arch_type == MACH_TYPE_TAZDEV)
+#else
+# define machine_is_tazdev()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANNAX_CB_ARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANNAX_CB_ARM
+# endif
+# define machine_is_annax_cb_arm()	(machine_arch_type == MACH_TYPE_ANNAX_CB_ARM)
+#else
+# define machine_is_annax_cb_arm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ANNAX_DM3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ANNAX_DM3
+# endif
+# define machine_is_annax_dm3()	(machine_arch_type == MACH_TYPE_ANNAX_DM3)
+#else
+# define machine_is_annax_dm3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CEREBRIC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CEREBRIC
+# endif
+# define machine_is_cerebric()	(machine_arch_type == MACH_TYPE_CEREBRIC)
+#else
+# define machine_is_cerebric()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ORCA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ORCA
+# endif
+# define machine_is_orca()	(machine_arch_type == MACH_TYPE_ORCA)
+#else
+# define machine_is_orca()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PC9260
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PC9260
+# endif
+# define machine_is_pc9260()	(machine_arch_type == MACH_TYPE_PC9260)
+#else
+# define machine_is_pc9260()	(0)
+#endif
+
+#ifdef CONFIG_MACH_EMS285A
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_EMS285A
+# endif
+# define machine_is_ems285a()	(machine_arch_type == MACH_TYPE_EMS285A)
+#else
+# define machine_is_ems285a()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GEC2410
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEC2410
+# endif
+# define machine_is_gec2410()	(machine_arch_type == MACH_TYPE_GEC2410)
+#else
+# define machine_is_gec2410()	(0)
+#endif
+
+#ifdef CONFIG_MACH_GEC2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_GEC2440
+# endif
+# define machine_is_gec2440()	(machine_arch_type == MACH_TYPE_GEC2440)
+#else
+# define machine_is_gec2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARCH_MW903
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARCH_MW903
+# endif
+# define machine_is_mw903()	(machine_arch_type == MACH_TYPE_ARCH_MW903)
+#else
+# define machine_is_mw903()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MW2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MW2440
+# endif
+# define machine_is_mw2440()	(machine_arch_type == MACH_TYPE_MW2440)
+#else
+# define machine_is_mw2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECAC2378
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECAC2378
+# endif
+# define machine_is_ecac2378()	(machine_arch_type == MACH_TYPE_ECAC2378)
+#else
+# define machine_is_ecac2378()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAZKIOSK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAZKIOSK
+# endif
+# define machine_is_tazkiosk()	(machine_arch_type == MACH_TYPE_TAZKIOSK)
+#else
+# define machine_is_tazkiosk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WHITERABBIT_MCH
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WHITERABBIT_MCH
+# endif
+# define machine_is_whiterabbit_mch()	(machine_arch_type == MACH_TYPE_WHITERABBIT_MCH)
+#else
+# define machine_is_whiterabbit_mch()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SBOX9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SBOX9263
+# endif
+# define machine_is_sbox9263()	(machine_arch_type == MACH_TYPE_SBOX9263)
+#else
+# define machine_is_sbox9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OREO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OREO
+# endif
+# define machine_is_oreo()	(machine_arch_type == MACH_TYPE_OREO)
+#else
+# define machine_is_oreo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SMDK6442
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SMDK6442
+# endif
+# define machine_is_smdk6442()	(machine_arch_type == MACH_TYPE_SMDK6442)
+#else
+# define machine_is_smdk6442()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPENRD_BASE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_BASE
+# endif
+# define machine_is_openrd_base()	(machine_arch_type == MACH_TYPE_OPENRD_BASE)
+#else
+# define machine_is_openrd_base()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INCREDIBLE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INCREDIBLE
+# endif
+# define machine_is_incredible()	(machine_arch_type == MACH_TYPE_INCREDIBLE)
+#else
+# define machine_is_incredible()	(0)
+#endif
+
+#ifdef CONFIG_MACH_INCREDIBLEC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_INCREDIBLEC
+# endif
+# define machine_is_incrediblec()	(machine_arch_type == MACH_TYPE_INCREDIBLEC)
+#else
+# define machine_is_incrediblec()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HEROCT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HEROCT
+# endif
+# define machine_is_heroct()	(machine_arch_type == MACH_TYPE_HEROCT)
+#else
+# define machine_is_heroct()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MMNET1000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MMNET1000
+# endif
+# define machine_is_mmnet1000()	(machine_arch_type == MACH_TYPE_MMNET1000)
+#else
+# define machine_is_mmnet1000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEVKIT8000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEVKIT8000
+# endif
+# define machine_is_devkit8000()	(machine_arch_type == MACH_TYPE_DEVKIT8000)
+#else
+# define machine_is_devkit8000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DEVKIT9000
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DEVKIT9000
+# endif
+# define machine_is_devkit9000()	(machine_arch_type == MACH_TYPE_DEVKIT9000)
+#else
+# define machine_is_devkit9000()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31TXTR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31TXTR
+# endif
+# define machine_is_mx31txtr()	(machine_arch_type == MACH_TYPE_MX31TXTR)
+#else
+# define machine_is_mx31txtr()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U380
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U380
+# endif
+# define machine_is_u380()	(machine_arch_type == MACH_TYPE_U380)
+#else
+# define machine_is_u380()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUALU_BOARD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUALU_BOARD
+# endif
+# define machine_is_oamp3_hualu()	(machine_arch_type == MACH_TYPE_HUALU_BOARD)
+#else
+# define machine_is_oamp3_hualu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NPCMX50
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NPCMX50
+# endif
+# define machine_is_npcmx50()	(machine_arch_type == MACH_TYPE_NPCMX50)
+#else
+# define machine_is_npcmx50()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_LANGE51
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_LANGE51
+# endif
+# define machine_is_mx51_lange51()	(machine_arch_type == MACH_TYPE_MX51_LANGE51)
+#else
+# define machine_is_mx51_lange51()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_LANGE52
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_LANGE52
+# endif
+# define machine_is_mx51_lange52()	(machine_arch_type == MACH_TYPE_MX51_LANGE52)
+#else
+# define machine_is_mx51_lange52()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RIOM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RIOM
+# endif
+# define machine_is_riom()	(machine_arch_type == MACH_TYPE_RIOM)
+#else
+# define machine_is_riom()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COMCAS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMCAS
+# endif
+# define machine_is_comcas()	(machine_arch_type == MACH_TYPE_COMCAS)
+#else
+# define machine_is_comcas()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WSI_MX27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WSI_MX27
+# endif
+# define machine_is_wsi_mx27()	(machine_arch_type == MACH_TYPE_WSI_MX27)
+#else
+# define machine_is_wsi_mx27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CM_T35
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CM_T35
+# endif
+# define machine_is_cm_t35()	(machine_arch_type == MACH_TYPE_CM_T35)
+#else
+# define machine_is_cm_t35()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NET2BIG
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NET2BIG
+# endif
+# define machine_is_net2big()	(machine_arch_type == MACH_TYPE_NET2BIG)
+#else
+# define machine_is_net2big()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MOTOROLA_A1600
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MOTOROLA_A1600
+# endif
+# define machine_is_motorola_a1600()	(machine_arch_type == MACH_TYPE_MOTOROLA_A1600)
+#else
+# define machine_is_motorola_a1600()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0020
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0020
+# endif
+# define machine_is_igep0020()	(machine_arch_type == MACH_TYPE_IGEP0020)
+#else
+# define machine_is_igep0020()	(0)
+#endif
+
+#ifdef CONFIG_MACH_IGEP0010
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_IGEP0010
+# endif
+# define machine_is_igep0010()	(machine_arch_type == MACH_TYPE_IGEP0010)
+#else
+# define machine_is_igep0010()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MV6281GTWGE2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MV6281GTWGE2
+# endif
+# define machine_is_mv6281gtwge2()	(machine_arch_type == MACH_TYPE_MV6281GTWGE2)
+#else
+# define machine_is_mv6281gtwge2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCAT100
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCAT100
+# endif
+# define machine_is_scat100()	(machine_arch_type == MACH_TYPE_SCAT100)
+#else
+# define machine_is_scat100()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SANMINA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SANMINA
+# endif
+# define machine_is_sanmina()	(machine_arch_type == MACH_TYPE_SANMINA)
+#else
+# define machine_is_sanmina()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MOMENTO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MOMENTO
+# endif
+# define machine_is_momento()	(machine_arch_type == MACH_TYPE_MOMENTO)
+#else
+# define machine_is_momento()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC9XX
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC9XX
+# endif
+# define machine_is_nuc9xx()	(machine_arch_type == MACH_TYPE_NUC9XX)
+#else
+# define machine_is_nuc9xx()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC910EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC910EVB
+# endif
+# define machine_is_nuc910evb()	(machine_arch_type == MACH_TYPE_NUC910EVB)
+#else
+# define machine_is_nuc910evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC920EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC920EVB
+# endif
+# define machine_is_nuc920evb()	(machine_arch_type == MACH_TYPE_NUC920EVB)
+#else
+# define machine_is_nuc920evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC950EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC950EVB
+# endif
+# define machine_is_nuc950evb()	(machine_arch_type == MACH_TYPE_NUC950EVB)
+#else
+# define machine_is_nuc950evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC945EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC945EVB
+# endif
+# define machine_is_nuc945evb()	(machine_arch_type == MACH_TYPE_NUC945EVB)
+#else
+# define machine_is_nuc945evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC960EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC960EVB
+# endif
+# define machine_is_nuc960evb()	(machine_arch_type == MACH_TYPE_NUC960EVB)
+#else
+# define machine_is_nuc960evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC932EVB
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC932EVB
+# endif
+# define machine_is_nuc932evb()	(machine_arch_type == MACH_TYPE_NUC932EVB)
+#else
+# define machine_is_nuc932evb()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NUC900
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NUC900
+# endif
+# define machine_is_nuc900()	(machine_arch_type == MACH_TYPE_NUC900)
+#else
+# define machine_is_nuc900()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SD1SOC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SD1SOC
+# endif
+# define machine_is_sd1soc()	(machine_arch_type == MACH_TYPE_SD1SOC)
+#else
+# define machine_is_sd1soc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LN2440BC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LN2440BC
+# endif
+# define machine_is_ln2440bc()	(machine_arch_type == MACH_TYPE_LN2440BC)
+#else
+# define machine_is_ln2440bc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RSBC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RSBC
+# endif
+# define machine_is_rsbc()	(machine_arch_type == MACH_TYPE_RSBC)
+#else
+# define machine_is_rsbc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OPENRD_CLIENT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OPENRD_CLIENT
+# endif
+# define machine_is_openrd_client()	(machine_arch_type == MACH_TYPE_OPENRD_CLIENT)
+#else
+# define machine_is_openrd_client()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HPIPAQ11X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HPIPAQ11X
+# endif
+# define machine_is_hpipaq11x()	(machine_arch_type == MACH_TYPE_HPIPAQ11X)
+#else
+# define machine_is_hpipaq11x()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WAYLAND
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WAYLAND
+# endif
+# define machine_is_wayland()	(machine_arch_type == MACH_TYPE_WAYLAND)
+#else
+# define machine_is_wayland()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ACNBSX102
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ACNBSX102
+# endif
+# define machine_is_acnbsx102()	(machine_arch_type == MACH_TYPE_ACNBSX102)
+#else
+# define machine_is_acnbsx102()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HWAT91
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HWAT91
+# endif
+# define machine_is_hwat91()	(machine_arch_type == MACH_TYPE_HWAT91)
+#else
+# define machine_is_hwat91()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AT91SAM9263CS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AT91SAM9263CS
+# endif
+# define machine_is_at91sam9263cs()	(machine_arch_type == MACH_TYPE_AT91SAM9263CS)
+#else
+# define machine_is_at91sam9263cs()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSB732
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSB732
+# endif
+# define machine_is_csb732()	(machine_arch_type == MACH_TYPE_CSB732)
+#else
+# define machine_is_csb732()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U8500
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U8500
+# endif
+# define machine_is_u8500()	(machine_arch_type == MACH_TYPE_U8500)
+#else
+# define machine_is_u8500()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUQIU
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUQIU
+# endif
+# define machine_is_huqiu()	(machine_arch_type == MACH_TYPE_HUQIU)
+#else
+# define machine_is_huqiu()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX51_KUNLUN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX51_KUNLUN
+# endif
+# define machine_is_mx51_kunlun()	(machine_arch_type == MACH_TYPE_MX51_KUNLUN)
+#else
+# define machine_is_mx51_kunlun()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PMT1G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PMT1G
+# endif
+# define machine_is_pmt1g()	(machine_arch_type == MACH_TYPE_PMT1G)
+#else
+# define machine_is_pmt1g()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTCELF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTCELF
+# endif
+# define machine_is_htcelf()	(machine_arch_type == MACH_TYPE_HTCELF)
+#else
+# define machine_is_htcelf()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO420
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO420
+# endif
+# define machine_is_armadillo420()	(machine_arch_type == MACH_TYPE_ARMADILLO420)
+#else
+# define machine_is_armadillo420()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ARMADILLO440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ARMADILLO440
+# endif
+# define machine_is_armadillo440()	(machine_arch_type == MACH_TYPE_ARMADILLO440)
+#else
+# define machine_is_armadillo440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_U_CHIP_DUAL_ARM
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_U_CHIP_DUAL_ARM
+# endif
+# define machine_is_u_chip_dual_arm()	(machine_arch_type == MACH_TYPE_U_CHIP_DUAL_ARM)
+#else
+# define machine_is_u_chip_dual_arm()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CSR_BDB3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CSR_BDB3
+# endif
+# define machine_is_csr_bdb3()	(machine_arch_type == MACH_TYPE_CSR_BDB3)
+#else
+# define machine_is_csr_bdb3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DOLBY_CAT1018
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DOLBY_CAT1018
+# endif
+# define machine_is_dolby_cat1018()	(machine_arch_type == MACH_TYPE_DOLBY_CAT1018)
+#else
+# define machine_is_dolby_cat1018()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HY9307
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HY9307
+# endif
+# define machine_is_hy9307()	(machine_arch_type == MACH_TYPE_HY9307)
+#else
+# define machine_is_hy9307()	(0)
+#endif
+
+#ifdef CONFIG_MACH_A_ES
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_A_ES
+# endif
+# define machine_is_aspire_easystore()	(machine_arch_type == MACH_TYPE_A_ES)
+#else
+# define machine_is_aspire_easystore()	(0)
+#endif
+
+#ifdef CONFIG_MACH_DAVINCI_IRIF
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_DAVINCI_IRIF
+# endif
+# define machine_is_davinci_irif()	(machine_arch_type == MACH_TYPE_DAVINCI_IRIF)
+#else
+# define machine_is_davinci_irif()	(0)
+#endif
+
+#ifdef CONFIG_MACH_AGAMA9263
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_AGAMA9263
+# endif
+# define machine_is_agama9263()	(machine_arch_type == MACH_TYPE_AGAMA9263)
+#else
+# define machine_is_agama9263()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MARVELL_JASPER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MARVELL_JASPER
+# endif
+# define machine_is_marvell_jasper()	(machine_arch_type == MACH_TYPE_MARVELL_JASPER)
+#else
+# define machine_is_marvell_jasper()	(0)
+#endif
+
+#ifdef CONFIG_MACH_FLINT
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_FLINT
+# endif
+# define machine_is_flint()	(machine_arch_type == MACH_TYPE_FLINT)
+#else
+# define machine_is_flint()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TAVOREVB3
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TAVOREVB3
+# endif
+# define machine_is_tavorevb3()	(machine_arch_type == MACH_TYPE_TAVOREVB3)
+#else
+# define machine_is_tavorevb3()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SCH_M490
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SCH_M490
+# endif
+# define machine_is_sch_m490()	(machine_arch_type == MACH_TYPE_SCH_M490)
+#else
+# define machine_is_sch_m490()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RBL01
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RBL01
+# endif
+# define machine_is_rbl01()	(machine_arch_type == MACH_TYPE_RBL01)
+#else
+# define machine_is_rbl01()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMNIFI
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMNIFI
+# endif
+# define machine_is_omnifi()	(machine_arch_type == MACH_TYPE_OMNIFI)
+#else
+# define machine_is_omnifi()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OTAVALO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OTAVALO
+# endif
+# define machine_is_otavalo()	(machine_arch_type == MACH_TYPE_OTAVALO)
+#else
+# define machine_is_otavalo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SIENNA
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SIENNA
+# endif
+# define machine_is_sienna()	(machine_arch_type == MACH_TYPE_SIENNA)
+#else
+# define machine_is_sienna()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTC_EXCALIBUR_S620
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTC_EXCALIBUR_S620
+# endif
+# define machine_is_htc_excalibur_s620()	(machine_arch_type == MACH_TYPE_HTC_EXCALIBUR_S620)
+#else
+# define machine_is_htc_excalibur_s620()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HTC_OPAL
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HTC_OPAL
+# endif
+# define machine_is_htc_opal()	(machine_arch_type == MACH_TYPE_HTC_OPAL)
+#else
+# define machine_is_htc_opal()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TOUCHBOOK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TOUCHBOOK
+# endif
+# define machine_is_touchbook()	(machine_arch_type == MACH_TYPE_TOUCHBOOK)
+#else
+# define machine_is_touchbook()	(0)
+#endif
+
+#ifdef CONFIG_MACH_LATTE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_LATTE
+# endif
+# define machine_is_latte()	(machine_arch_type == MACH_TYPE_LATTE)
+#else
+# define machine_is_latte()	(0)
+#endif
+
+#ifdef CONFIG_MACH_XA200
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_XA200
+# endif
+# define machine_is_xa200()	(machine_arch_type == MACH_TYPE_XA200)
+#else
+# define machine_is_xa200()	(0)
+#endif
+
+#ifdef CONFIG_MACH_NIMROD
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_NIMROD
+# endif
+# define machine_is_nimrod()	(machine_arch_type == MACH_TYPE_NIMROD)
+#else
+# define machine_is_nimrod()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CC9P9215_3G
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CC9P9215_3G
+# endif
+# define machine_is_cc9p9215_3g()	(machine_arch_type == MACH_TYPE_CC9P9215_3G)
+#else
+# define machine_is_cc9p9215_3g()	(0)
+#endif
+
+#ifdef CONFIG_MACH_CC9P9215_3GJS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_CC9P9215_3GJS
+# endif
+# define machine_is_cc9p9215_3gjs()	(machine_arch_type == MACH_TYPE_CC9P9215_3GJS)
+#else
+# define machine_is_cc9p9215_3gjs()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TK71
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TK71
+# endif
+# define machine_is_tk71()	(machine_arch_type == MACH_TYPE_TK71)
+#else
+# define machine_is_tk71()	(0)
+#endif
+
+#ifdef CONFIG_MACH_COMHAM3525
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_COMHAM3525
+# endif
+# define machine_is_comham3525()	(machine_arch_type == MACH_TYPE_COMHAM3525)
+#else
+# define machine_is_comham3525()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MX31EREBUS
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MX31EREBUS
+# endif
+# define machine_is_mx31erebus()	(machine_arch_type == MACH_TYPE_MX31EREBUS)
+#else
+# define machine_is_mx31erebus()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MCARDMX27
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MCARDMX27
+# endif
+# define machine_is_mcardmx27()	(machine_arch_type == MACH_TYPE_MCARDMX27)
+#else
+# define machine_is_mcardmx27()	(0)
+#endif
+
+#ifdef CONFIG_MACH_PARADISE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_PARADISE
+# endif
+# define machine_is_paradise()	(machine_arch_type == MACH_TYPE_PARADISE)
+#else
+# define machine_is_paradise()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TIDE
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TIDE
+# endif
+# define machine_is_tide()	(machine_arch_type == MACH_TYPE_TIDE)
+#else
+# define machine_is_tide()	(0)
+#endif
+
+#ifdef CONFIG_MACH_WZL2440
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_WZL2440
+# endif
+# define machine_is_wzl2440()	(machine_arch_type == MACH_TYPE_WZL2440)
+#else
+# define machine_is_wzl2440()	(0)
+#endif
+
+#ifdef CONFIG_MACH_SDRDEMO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_SDRDEMO
+# endif
+# define machine_is_sdrdemo()	(machine_arch_type == MACH_TYPE_SDRDEMO)
+#else
+# define machine_is_sdrdemo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ETHERCAN2
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ETHERCAN2
+# endif
+# define machine_is_ethercan2()	(machine_arch_type == MACH_TYPE_ETHERCAN2)
+#else
+# define machine_is_ethercan2()	(0)
+#endif
+
+#ifdef CONFIG_MACH_ECMIMG20
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_ECMIMG20
+# endif
+# define machine_is_ecmimg20()	(machine_arch_type == MACH_TYPE_ECMIMG20)
+#else
+# define machine_is_ecmimg20()	(0)
+#endif
+
+#ifdef CONFIG_MACH_OMAP_DRAGON
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_OMAP_DRAGON
+# endif
+# define machine_is_omap_dragon()	(machine_arch_type == MACH_TYPE_OMAP_DRAGON)
+#else
+# define machine_is_omap_dragon()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HALO
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HALO
+# endif
+# define machine_is_halo()	(machine_arch_type == MACH_TYPE_HALO)
+#else
+# define machine_is_halo()	(0)
+#endif
+
+#ifdef CONFIG_MACH_HUANGSHAN
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_HUANGSHAN
+# endif
+# define machine_is_huangshan()	(machine_arch_type == MACH_TYPE_HUANGSHAN)
+#else
+# define machine_is_huangshan()	(0)
+#endif
+
+#ifdef CONFIG_MACH_VL_MA2SC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_VL_MA2SC
+# endif
+# define machine_is_vl_ma2sc()	(machine_arch_type == MACH_TYPE_VL_MA2SC)
+#else
+# define machine_is_vl_ma2sc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_RC
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_RC
+# endif
+# define machine_is_raumfeld_rc()	(machine_arch_type == MACH_TYPE_RAUMFELD_RC)
+#else
+# define machine_is_raumfeld_rc()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_CONNECTOR
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_CONNECTOR
+# endif
+# define machine_is_raumfeld_connector()	(machine_arch_type == MACH_TYPE_RAUMFELD_CONNECTOR)
+#else
+# define machine_is_raumfeld_connector()	(0)
+#endif
+
+#ifdef CONFIG_MACH_RAUMFELD_SPEAKER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_RAUMFELD_SPEAKER
+# endif
+# define machine_is_raumfeld_speaker()	(machine_arch_type == MACH_TYPE_RAUMFELD_SPEAKER)
+#else
+# define machine_is_raumfeld_speaker()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MULTIBUS_MASTER
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MULTIBUS_MASTER
+# endif
+# define machine_is_multibus_master()	(machine_arch_type == MACH_TYPE_MULTIBUS_MASTER)
+#else
+# define machine_is_multibus_master()	(0)
+#endif
+
+#ifdef CONFIG_MACH_MULTIBUS_PBK
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_MULTIBUS_PBK
+# endif
+# define machine_is_multibus_pbk()	(machine_arch_type == MACH_TYPE_MULTIBUS_PBK)
+#else
+# define machine_is_multibus_pbk()	(0)
+#endif
+
+#ifdef CONFIG_MACH_TNETV107X
+# ifdef machine_arch_type
+#  undef machine_arch_type
+#  define machine_arch_type	__machine_arch_type
+# else
+#  define machine_arch_type	MACH_TYPE_TNETV107X
+# endif
+# define machine_is_tnetv107x()	(machine_arch_type == MACH_TYPE_TNETV107X)
+#else
+# define machine_is_tnetv107x()	(0)
+#endif
+
 /*
  * These have not yet been registered
  */

diff --git a/include/asm-blackfin/config.h b/include/asm-blackfin/config.h
index 6623fb7..25794dd 100644
--- a/include/asm-blackfin/config.h
+++ b/include/asm-blackfin/config.h

@@ -14,6 +14,10 @@
 # error CONFIG_BFIN_CPU: your board config needs to define this
 #endif
 
+#ifndef CONFIG_BFIN_SCRATCH_REG
+# define CONFIG_BFIN_SCRATCH_REG retn
+#endif
+
 /* Make sure the structure is properly aligned */
 #if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
 # error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
@@ -120,11 +124,7 @@
 # define CONFIG_SYS_PROMPT "bfin> "
 #endif
 #ifndef CONFIG_SYS_CBSIZE
-# ifdef CONFIG_CMD_KGDB
-#  define CONFIG_SYS_CBSIZE 1024
-# else
-#  define CONFIG_SYS_CBSIZE 256
-# endif
+# define CONFIG_SYS_CBSIZE 1024
 #endif
 #ifndef CONFIG_SYS_BARGSIZE
 # define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE

diff --git a/include/asm-blackfin/global_data.h b/include/asm-blackfin/global_data.h
index 5c9903b..3194b72 100644
--- a/include/asm-blackfin/global_data.h
+++ b/include/asm-blackfin/global_data.h

@@ -66,6 +66,6 @@
 #define	GD_FLG_LOGINIT	0x00020	/* Log Buf has been initialized	 */
 #define GD_FLG_DISABLE_CONSOLE	0x00040		/* Disable console (in & out)	 */
 
-#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P5")
+#define DECLARE_GLOBAL_DATA_PTR     register gd_t * volatile gd asm ("P3")
 
 #endif

diff --git a/include/asm-i386/errno.h b/include/asm-i386/errno.h
new file mode 100644
index 0000000..4c82b50
--- /dev/null
+++ b/include/asm-i386/errno.h

@@ -0,0 +1 @@
+#include <asm-generic/errno.h>

diff --git a/include/asm-i386/ic/sc520.h b/include/asm-i386/ic/sc520.h
index bf39516..57c9904 100644
--- a/include/asm-i386/ic/sc520.h
+++ b/include/asm-i386/ic/sc520.h

@@ -24,179 +24,243 @@
 #ifndef _ASM_IC_SC520_H_
 #define _ASM_IC_SC520_H_ 1
 
-/* Memory mapped configuration registers, MMCR */
-#define SC520_REVID		0x0000	/* ElanSC520 Microcontroller Revision ID Register */
-#define SC520_CPUCTL		0x0002	/* Am5x86 CPU Control Register */
-#define SC520_DRCCTL		0x0010	/* SDRAM Control Register */
-#define SC520_DRCTMCTL		0x0012	/* SDRAM Timing Control Register */
-#define SC520_DRCCFG		0x0014	/* SDRAM Bank Configuration Register*/
-#define SC520_DRCBENDADR	0x0018	/* SDRAM Bank 0-3 Ending Address Register*/
-#define SC520_ECCCTL		0x0020	/* ECC Control Register */
-#define SC520_ECCSTA		0x0021	/* ECC Status Register */
-#define SC520_ECCCKBPOS		0x0022	/* ECC Check Bit Position Register */
-#define SC520_ECCSBADD		0x0024	/* ECC Single-Bit Error Address Register */
+#ifndef __ASSEMBLY__
+
+void init_sc520(void);
+unsigned long init_sc520_dram(void);
+
+/* Memory mapped configuration registers */
+typedef struct sc520_mmcr {
+	u16 revid;	/* ElanSC520 microcontroller revision id */
+	u8  cpuctl;	/* am5x86 CPU control  */
+
+	u8  pad_0x003[0x0d];
+
+	u8  drcctl;		/* SDRAM control */
+	u8  pad_0x011[0x01];
+	u8  drctmctl;		/* SDRAM timing control */
+	u8  pad_0x013[0x01];
+	u16 drccfg;		/* SDRAM bank configuration*/
+	u8  pad_0x016[0x02];
+	u32 drcbendadr;		/* SDRAM bank 0-3 ending address*/
+	u8  pad_0x01c[0x04];
+	u8  eccctl;		/* ECC control */
+	u8  eccsta;		/* ECC status */
+	u8  eccckbpos;		/* ECC check bit position */
+	u8  ecccktest;		/* ECC Check Code Test */
+	u32 eccsbadd;		/* ECC single-bit error address */
+	u32 eccmbadd;		/* ECC multi-bit error address */
+
+	u8  pad_0x02c[0x14];
+
+	u8  dbctl;		/* SDRAM buffer control */
+
+	u8  pad_0x041[0x0f];
+
+	u16 bootcsctl;		/* /BOOTCS control */
+	u8  pad_0x052[0x02];
+	u16 romcs1ctl;		/* /ROMCS1 control */
+	u16 romcs2ctl;		/* /ROMCS2 control */
+
+	u8  pad_0x058[0x08];
+
+	u16 hbctl;		/* host bridge control */
+	u16 hbtgtirqctl;	/* host bridge target interrupt control */
+	u16 hbtgtirqsta;	/* host bridge target interrupt status */
+	u16 hbmstirqctl;	/* host bridge target interrupt control */
+	u16 hbmstirqsta;	/* host bridge master interrupt status */
+	u8  pad_0x06a[0x02];
+	u32 mstintadd;		/* host bridge master interrupt address */
+
+	u8  sysarbctl;		/* system arbiter control */
+	u8  pciarbsta;		/* PCI bus arbiter status */
+	u16 sysarbmenb;		/* system arbiter master enable */
+	u32 arbprictl;		/* arbiter priority control */
+
+	u8  pad_0x078[0x08];
+
+	u8  adddecctl;		/* address decode control */
+	u8  pad_0x081[0x01];
+	u16 wpvsta;		/* write-protect violation status */
+	u8  pad_0x084[0x04];
+	u32 par[16];		/* programmable address regions */
+
+	u8  pad_0x0c8[0x0b38];
+
+	u8  gpecho;		/* GP echo mode */
+	u8  gpcsdw;		/* GP chip select data width */
+	u16 gpcsqual;		/* GP chip select qualification */
+	u8  pad_0xc04[0x4];
+	u8  gpcsrt;		/* GP chip select recovery time */
+	u8  gpcspw;		/* GP chip select pulse width */
+	u8  gpcsoff;		/* GP chip select offset */
+	u8  gprdw;		/* GP read pulse width */
+	u8  gprdoff;		/* GP read offset */
+	u8  gpwrw;		/* GP write pulse width */
+	u8  gpwroff;		/* GP write offset */
+	u8  gpalew;		/* GP ale pulse width */
+	u8  gpaleoff;		/* GP ale offset */
+
+	u8  pad_0xc11[0x0f];
+
+	u16 piopfs15_0;		/* PIO15-PIO0 pin function select */
+	u16 piopfs31_16;	/* PIO31-PIO16 pin function select */
+	u8  cspfs;		/* chip select pin function select */
+	u8  pad_0xc25[0x01];
+	u8  clksel;		/* clock select */
+	u8  pad_0xc27[0x01];
+	u16 dsctl;		/* drive strength control */
+	u16 piodir15_0;		/* PIO15-PIO0 direction */
+	u16 piodir31_16;	/* PIO31-PIO16 direction */
+	u8  pad_0xc2e[0x02];
+	u16 piodata15_0	;	/* PIO15-PIO0 data */
+	u16 piodata31_16;	/* PIO31-PIO16 data */
+	u16 pioset15_0;		/* PIO15-PIO0 set */
+	u16 pioset31_16;	/* PIO31-PIO16 set */
+	u16 pioclr15_0;		/* PIO15-PIO0 clear */
+	u16 pioclr31_16;	/* PIO31-PIO16 clear */
+
+	u8  pad_0xc3c[0x24];
+
+	u16 swtmrmilli;		/* software timer millisecond count */
+	u16 swtmrmicro;		/* software timer microsecond count */
+	u8  swtmrcfg;		/* software timer configuration */
+
+	u8  pad_0xc65[0x0b];
+
+	u8  gptmrsta;		/* GP timers status register */
+	u8  pad_0xc71;
+	u16 gptmr0ctl;		/* GP timer 0 mode/control */
+	u16 gptmr0cnt;		/* GP timer 0 count */
+	u16 gptmr0maxcmpa;	/* GP timer 0 maxcount compare A */
+	u16 gptmr0maxcmpb;	/* GP timer 0 maxcount compare B */
+	u16 gptmr1ctl;		/* GP timer 1 mode/control */
+	u16 gptmr1cnt;		/* GP timer 1 count */
+	u16 gptmr1maxcmpa;	/* GP timer 1 maxcount compare A */
+	u16 gptmr1maxcmpb;	/* GP timer 1 maxcount compare B*/
+	u16 gptmr2ctl;		/* GP timer 2 mode/control */
+	u16 gptmr2cnt;		/* GP timer 2 count */
+	u8  pad_0xc86[0x08];
+	u16 gptmr2maxcmpa;	/* GP timer 2 maxcount compare A */
+
+	u8  pad_0xc90[0x20];
+
+	u16 wdtmrctl;		/* watchdog timer control */
+	u16 wdtmrcntl;		/* watchdog timer count low */
+	u16 wdtmrcnth;		/* watchdog timer count high */
+
+	u8  pad_0xcb6[0x0a];
+
+	u8  uart1ctl;		/* UART 1 general control */
+	u8  uart1sta;		/* UART 1 general status */
+	u8  uart1fcrshad;	/* UART 1 FIFO control shadow */
+	u8  pad_0xcc3[0x01];
+	u8  uart2ctl;		/* UART 2 general control */
+	u8  uart2sta;		/* UART 2 general status */
+	u8  uart2fcrshad;	/* UART 2 FIFO control shadow */
+
+	u8  pad_0xcc7[0x09];
+
+	u8  ssictl;		/* SSI control */
+	u8  ssixmit;		/* SSI transmit */
+	u8  ssicmd;		/* SSI command */
+	u8  ssista;		/* SSI status */
+	u8  ssircv;		/* SSI receive */
+
+	u8  pad_0xcd5[0x2b];
+
+	u8  picicr;		/* interrupt control */
+	u8  pad_0xd01[0x01];
+	u8  pic_mode[3];	/* PIC interrupt mode */
+	u8  pad_0xd05[0x03];
+	u16 swint16_1;		/* software interrupt 16-1 control */
+	u8  swint22_17;		/* software interrupt 22-17/NMI control */
+	u8  pad_0xd0b[0x05];
+	u16 intpinpol;		/* interrupt pin polarity */
+	u8  pad_0xd12[0x02];
+	u16 pcihostmap;		/* PCI host bridge interrupt mapping */
+	u8  pad_0xd16[0x02];
+	u16 eccmap;		/* ECC interrupt mapping */
+	u8  gp_tmr_int_map[3];	/* GP timer interrupt mapping */
+	u8  pad_0xd1d[0x03];
+	u8  pit_int_map[3];	/* PIT interrupt mapping */
+	u8  pad_0xd23[0x05];
+	u8  uart_int_map[2];	/* UART interrupt mapping */
+	u8  pad_0xd2a[0x06];
+	u8  pci_int_map[4];	/* PCI interrupt mapping (A through D)*/
+	u8  pad_0xd34[0x0c];
+	u8  dmabcintmap;	/* DMA buffer chaining interrupt mapping */
+	u8  ssimap;		/* SSI interrupt mapping register */
+	u8  wdtmap;		/* watchdog timer interrupt mapping */
+	u8  rtcmap;		/* RTC interrupt mapping register */
+	u8  wpvmap;		/* write-protect interrupt mapping */
+	u8  icemap;		/* AMDebug JTAG Rx/Tx interrupt mapping */
+	u8  ferrmap;		/* floating point error interrupt mapping */
+	u8  pad_0xd47[0x09];
+	u8  gp_int_map[11];	/* GP IRQ interrupt mapping */
+
+	u8  pad_0xd5b[0x15];
+
+	u8  sysinfo;		/* system board information */
+	u8  pad_0xd71[0x01];
+	u8  rescfg;		/* reset configuration */
+	u8  pad_0xd73[0x01];
+	u8  ressta;		/* reset status */
+
+	u8  pad_0xd75[0x0b];
+
+	u8  gpdmactl;		/* GP-DMA Control */
+	u8  gpdmammio;		/* GP-DMA memory-mapped I/O */
+	u16 gpdmaextchmapa;	/* GP-DMA resource channel map a */
+	u16 gpdmaextchmapb;	/* GP-DMA resource channel map b */
+	u8  gp_dma_ext_pg_0;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_1;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_2;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_3;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_5;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_6;	/* GP-DMA channel extended page 0 */
+	u8  gp_dma_ext_pg_7;	/* GP-DMA channel extended page 0 */
+	u8  pad_0xd8d[0x03];
+	u8  gpdmaexttc3;	/* GP-DMA channel 3 extender transfer count */
+	u8  gpdmaexttc5;	/* GP-DMA channel 5 extender transfer count */
+	u8  gpdmaexttc6;	/* GP-DMA channel 6 extender transfer count */
+	u8  gpdmaexttc7;	/* GP-DMA channel 7 extender transfer count */
+	u8  pad_0xd94[0x4];
+	u8  gpdmabcctl;		/* buffer chaining control */
+	u8  gpdmabcsta;		/* buffer chaining status */
+	u8  gpdmabsintenb;	/* buffer chaining interrupt enable */
+	u8  gpdmabcval;		/* buffer chaining valid */
+	u8  pad_0xd9c[0x04];
+	u16 gpdmanxtaddl3;	/* GP-DMA channel 3 next address low */
+	u16 gpdmanxtaddh3;	/* GP-DMA channel 3 next address high */
+	u16 gpdmanxtaddl5;	/* GP-DMA channel 5 next address low */
+	u16 gpdmanxtaddh5;	/* GP-DMA channel 5 next address high */
+	u16 gpdmanxtaddl6;	/* GP-DMA channel 6 next address low */
+	u16 gpdmanxtaddh6;	/* GP-DMA channel 6 next address high */
+	u16 gpdmanxtaddl7;	/* GP-DMA channel 7 next address low */
+	u16 gpdmanxtaddh7;	/* GP-DMA channel 7 next address high */
+	u16 gpdmanxttcl3;	/* GP-DMA channel 3 next transfer count low */
+	u16 gpdmanxttch3;	/* GP-DMA channel 3 next transfer count high */
+	u16 gpdmanxttcl5;	/* GP-DMA channel 5 next transfer count low */
+	u16 gpdmanxttch5;	/* GP-DMA channel 5 next transfer count high */
+	u16 gpdmanxttcl6;	/* GP-DMA channel 6 next transfer count low */
+	u16 gpdmanxttch6;	/* GP-DMA channel 6 next transfer count high */
+	u16 gpdmanxttcl7;	/* GP-DMA channel 7 next transfer count low */
+	u16 gpdmanxttch7;	/* GP-DMA channel 7 next transfer count high */
+
+	u8  pad_0xdc0[0x0240];
+} sc520_mmcr_t;
+
+extern volatile sc520_mmcr_t *sc520_mmcr;
+
+#endif
+
+/* MMCR Offsets (required for assembler code */
 #define SC520_DBCTL		0x0040	/* SDRAM Buffer Control Register */
-#define SC520_BOOTCSCTL		0x0050	/* /BOOTCS Control Register */
-#define SC520_ROMCS1CTL		0x0054	/* /ROMCS1 Control Register */
-#define SC520_ROMCS2CTL		0x0056	/* /ROMCS2 Control Register */
-#define SC520_HBCTL		0x0060	/* Host Bridge Control Register */
-#define SC520_HBTGTIRQCTL	0x0062	/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBTGTIRQSTA	0x0064	/* Host Bridge Target Interrupt Status Register */
-#define SC520_HBMSTIRQCTL	0x0066	/* Host Bridge Target Interrupt Control Register */
-#define SC520_HBMSTIRQSTA	0x0068	/* Host Bridge Master Interrupt Status Register */
-#define SC520_MSTINTADD		0x006c	/* Host Bridge Master Interrupt Address Register */
-#define SC520_SYSARBCTL		0x0070	/* System Arbiter Control Register */
-#define SC520_PCIARBSTA		0x0071	/* PCI Bus Arbiter Status Register */
-#define SC520_SYSARBMENB	0x0072	/* System Arbiter Master Enable Register */
-#define SC520_ARBPRICTL		0x0074	/* Arbiter Priority Control Register */
-#define SC520_ADDDECCTL		0x0080	/* Address Decode Control Register */
-#define SC520_WPVSTA		0x0082	/* Write-Protect Violation Status Register */
-#define SC520_PAR0		0x0088	/* Programmable Address Region 0 Register */
-#define SC520_PAR1		0x008c	/* Programmable Address Region 1 Register */
-#define SC520_PAR2		0x0090	/* Programmable Address Region 2 Register */
-#define SC520_PAR3		0x0094	/* Programmable Address Region 3 Register */
-#define SC520_PAR4		0x0098	/* Programmable Address Region 4 Register */
-#define SC520_PAR5		0x009c	/* Programmable Address Region 5 Register */
-#define SC520_PAR6		0x00a0	/* Programmable Address Region 6 Register */
-#define SC520_PAR7		0x00a4	/* Programmable Address Region 7 Register */
-#define SC520_PAR8		0x00a8	/* Programmable Address Region 8 Register */
-#define SC520_PAR9		0x00ac	/* Programmable Address Region 9 Register */
-#define SC520_PAR10		0x00b0	/* Programmable Address Region 10 Register */
-#define SC520_PAR11		0x00b4	/* Programmable Address Region 11 Register */
-#define SC520_PAR12		0x00b8	/* Programmable Address Region 12 Register */
-#define SC520_PAR13		0x00bc	/* Programmable Address Region 13 Register */
 #define SC520_PAR14		0x00c0	/* Programmable Address Region 14 Register */
 #define SC520_PAR15		0x00c4	/* Programmable Address Region 15 Register */
-#define SC520_GPECHO		0x0c00	/* GP Echo Mode Register */
-#define SC520_GPCSDW		0x0c01	/* GP Chip Select Data Width Register */
-#define SC520_GPCSQUAL		0x0c02	/* GP Chip Select Qualification Register */
-#define SC520_GPCSRT		0x0c08	/* GP Chip Select Recovery Time Register */
-#define SC520_GPCSPW		0x0c09	/* GP Chip Select Pulse Width Register */
-#define SC520_GPCSOFF		0x0c0a	/* GP Chip Select Offset Register */
-#define SC520_GPRDW		0x0c0b	/* GP Read Pulse Width Register */
-#define SC520_GPRDOFF		0x0c0c	/* GP Read Offset Register */
-#define SC520_GPWRW		0x0c0d	/* GP Write Pulse Width Register */
-#define SC520_GPWROFF		0x0c0e	/* GP Write Offset Register */
-#define SC520_GPALEW		0x0c0f	/* GP ALE Pulse Width Register */
-#define SC520_GPALEOFF		0x0c10	/* GP ALE Offset Register */
-#define SC520_PIOPFS15_0	0x0c20	/* PIO15-PIO0 Pin Function Select */
-#define SC520_PIOPFS31_16	0x0c22	/* PIO31-PIO16 Pin Function Select */
-#define SC520_CSPFS		0x0c24	/* Chip Select Pin Function Select */
-#define SC520_CLKSEL		0x0c26	/* Clock Select */
-#define SC520_DSCTL		0x0c28	/* Drive Strength Control */
-#define SC520_PIODIR15_0	0x0c2a	/* PIO15-PIO0 Direction */
-#define SC520_PIODIR31_16	0x0c2c	/* PIO31-PIO16 Direction */
-#define SC520_PIODATA15_0	0x0c30	/* PIO15-PIO0 Data */
-#define SC520_PIODATA31_16	0x0c32	/* PIO31-PIO16 Data */
-#define SC520_PIOSET15_0	0x0c34	/* PIO15-PIO0 Set */
-#define SC520_PIOSET31_16	0x0c36	/* PIO31-PIO16 Set */
-#define SC520_PIOCLR15_0	0x0c38	/* PIO15-PIO0 Clear */
-#define SC520_PIOCLR31_16	0x0c3a	/* PIO31-PIO16 Clear */
-#define SC520_SWTMRMILLI	0x0c60	/* Software Timer Millisecond Count */
-#define SC520_SWTMRMICRO	0x0c62	/* Software Timer Microsecond Count */
-#define SC520_SWTMRCFG		0x0c64	/* Software Timer Configuration */
-#define SC520_GPTMRSTA		0x0c70	/* GP Timers Status Register */
-#define SC520_GPTMR0CTL		0x0c72	/* GP Timer 0 Mode/Control Register */
-#define SC520_GPTMR0CNT		0x0c74	/* GP Timer 0 Count Register */
-#define SC520_GPTMR0MAXCMPA	0x0c76	/* GP Timer 0 Maxcount Compare A Register */
-#define SC520_GPTMR0MAXCMPB	0x0c78	/* GP Timer 0 Maxcount Compare B Register */
-#define SC520_GPTMR1CTL		0x0c7a	/* GP Timer 1 Mode/Control Register */
-#define SC520_GPTMR1CNT		0x0c7c	/* GP Timer 1 Count Register */
-#define SC520_GPTMR1MAXCMPA	0x0c7e	/* GP Timer 1 Maxcount Compare Register A */
-#define SC520_GPTMR1MAXCMPB	0x0c80	/* GP Timer 1 Maxcount Compare B Register */
-#define SC520_GPTMR2CTL		0x0c82	/* GP Timer 2 Mode/Control Register */
-#define SC520_GPTMR2CNT		0x0c84	/* GP Timer 2 Count Register */
-#define SC520_GPTMR2MAXCMPA	0x0c8e	/* GP Timer 2 Maxcount Compare A Register */
-#define SC520_WDTMRCTL		0x0cb0	/* Watchdog Timer Control Register */
-#define SC520_WDTMRCNTL		0x0cb2	/* Watchdog Timer Count Low Register */
-#define SC520_WDTMRCNTH		0x0cb4	/* Watchdog Timer Count High Register */
-#define SC520_UART1CTL		0x0cc0	/* UART 1 General Control Register */
-#define SC520_UART1STA		0x0cc1	/* UART 1 General Status Register */
-#define SC520_UART1FCRSHAD	0x0cc2	/* UART 1 FIFO Control Shadow Register */
-#define SC520_UART2CTL		0x0cc4	/* UART 2 General Control Register */
-#define SC520_UART2STA		0x0cc5	/* UART 2 General Status Register */
-#define SC520_UART2FCRSHAD	0x0cc6	/* UART 2 FIFO Control Shadow Register */
-#define SC520_SSICTL		0x0cd0	/* SSI Control */
-#define SC520_SSIXMIT		0x0cd1	/* SSI Transmit */
-#define SC520_SSICMD		0x0cd2	/* SSI Command */
-#define SC520_SSISTA		0x0cd3	/* SSI Status */
-#define SC520_SSIRCV		0x0cd4	/* SSI Receive */
-#define SC520_PICICR		0x0d00	/* Interrupt Control Register */
-#define SC520_MPICMODE		0x0d02	/* Master PIC Interrupt Mode Register */
-#define SC520_SL1PICMODE	0x0d03	/* Slave 1 PIC Interrupt Mode Register */
-#define SC520_SL2PICMODE	0x0d04	/* Slave 2 PIC Interrupt Mode Register */
-#define SC520_SWINT16_1		0x0d08	/* Software Interrupt 16-1 Control Register */
-#define SC520_SWINT22_17	0x0d0a	/* Software Interrupt 22-17/NMI Control Register */
-#define SC520_INTPINPOL		0x0d10	/* Interrupt Pin Polarity Register */
-#define SC520_PCIHOSTMAP	0x0d14	/* PCI Host Bridge Interrupt Mappin Register */
-#define SC520_ECCMAP		0x0d18	/* ECC Interrupt Mapping Register */
-#define SC520_GPTMR0MAP		0x0d1a	/* GP Timer 0 Interrupt Mapping Register */
-#define SC520_GPTMR1MAP		0x0d1b	/* GP Timer 1 Interrupt Mapping Register */
-#define SC520_GPTMR2MAP		0x0d1c	/* GP Timer 2 Interrupt Mapping Register */
-#define SC520_PIT0MAP		0x0d20	/* PIT0 Interrupt Mapping Register */
-#define SC520_PIT1MAP		0x0d21	/* PIT1 Interrupt Mapping Register */
-#define SC520_PIT2MAP		0x0d22	/* PIT2 Interrupt Mapping Register */
-#define SC520_UART1MAP		0x0d28	/* UART 1 Interrupt Mapping Register */
-#define SC520_UART2MAP		0x0d29	/* UART 2 Interrupt Mapping Register */
-#define SC520_PCIINTAMAP	0x0d30	/* PCI Interrupt A Mapping Register */
-#define SC520_PCIINTBMAP	0x0d31	/* PCI Interrupt B Mapping Register */
-#define SC520_PCIINTCMAP	0x0d32	/* PCI Interrupt C Mapping Register */
-#define SC520_PCIINTDMAP	0x0d33	/* PCI Interrupt D Mapping Register */
-#define SC520_DMABCINTMAP	0x0d40	/* DMA Buffer Chaining Interrupt Mapping Register */
-#define SC520_SSIMAP		0x0d41	/* SSI Interrupt Mapping Register */
-#define SC520_WDTMAP		0x0d42	/* Watchdog Timer Interrupt Mapping Register */
-#define SC520_RTCMAP		0x0d43	/* RTC Interrupt Mapping Register */
-#define SC520_WPVMAP		0x0d44	/* Write-Protect Interrupt Mapping Register */
-#define SC520_ICEMAP		0x0d45	/* AMDebug JTAG RX/TX Interrupt Mapping Register */
-#define SC520_FERRMAP		0x0d46	/* Floating Point Error Interrupt Mapping Register */
-#define SC520_GP0IMAP		0x0d50	/* GPIRQ0 Interrupt Mapping Register */
-#define SC520_GP1IMAP		0x0d51	/* GPIRQ1 Interrupt Mapping Register */
-#define SC520_GP2IMAP		0x0d52	/* GPIRQ2 Interrupt Mapping Register */
-#define SC520_GP3IMAP		0x0d53	/* GPIRQ3 Interrupt Mapping Register */
-#define SC520_GP4IMAP		0x0d54	/* GPIRQ4 Interrupt Mapping Register */
-#define SC520_GP5IMAP		0x0d55	/* GPIRQ5 Interrupt Mapping Register */
-#define SC520_GP6IMAP		0x0d56	/* GPIRQ6 Interrupt Mapping Register */
-#define SC520_GP7IMAP		0x0d57	/* GPIRQ7 Interrupt Mapping Register */
-#define SC520_GP8IMAP		0x0d58	/* GPIRQ8 Interrupt Mapping Register */
-#define SC520_GP9IMAP		0x0d59	/* GPIRQ9 Interrupt Mapping Register */
-#define SC520_GP10IMAP		0x0d5a	/* GPIRQ10 Interrupt Mapping Register */
-#define SC520_SYSINFO		0x0d70	/* System Board Information Register */
-#define SC520_RESCFG		0x0d72	/* Reset Configuration Register */
-#define SC520_RESSTA		0x0d74	/* Reset Status Register */
-#define SC520_GPDMAMMIO		0x0d81	/* GP-DMA Memory-Mapped I/O Register */
-#define SC520_GPDMAEXTCHMAPA	0x0d82	/* GP-DMA Resource Channel Map A */
-#define SC520_GPDMAEXTCHMAPB	0x0d84	/* GP-DMA Resource Channel Map B */
-#define SC520_GPDMAEXTPG0	0x0d86	/* GP-DMA Channel 0 Extended Page */
-#define SC520_GPDMAEXTPG1	0x0d87	/* GP-DMA Channel 1 Extended Page */
-#define SC520_GPDMAEXTPG2	0x0d88	/* GP-DMA Channel 2 Extended Page */
-#define SC520_GPDMAEXTPG3	0x0d89	/* GP-DMA Channel 3 Extended Page */
-#define SC520_GPDMAEXTPG5	0x0d8a	/* GP-DMA Channel 5 Extended Page */
-#define SC520_GPDMAEXTPG6	0x0d8b	/* GP-DMA Channel 6 Extended Page */
-#define SC520_GPDMAEXTPG7	0x0d8c	/* GP-DMA Channel 7 Extended Page */
-#define SC520_GPDMAEXTTC3	0x0d90	/* GP-DMA Channel 3 Extender Transfer count */
-#define SC520_GPDMAEXTTC5	0x0d91	/* GP-DMA Channel 5 Extender Transfer count */
-#define SC520_GPDMAEXTTC6	0x0d92	/* GP-DMA Channel 6 Extender Transfer count */
-#define SC520_GPDMAEXTTC7	0x0d93	/* GP-DMA Channel 7 Extender Transfer count */
-#define SC520_GPDMABCCTL	0x0d98	/* Buffer Chaining Control */
-#define SC520_GPDMABCSTA	0x0d99	/* Buffer Chaining Status */
-#define SC520_GPDMABSINTENB	0x0d9a	/* Buffer Chaining Interrupt Enable */
-#define SC520_GPDMABCVAL	0x0d9b	/* Buffer Chaining Valid */
-#define SC520_GPDMANXTADDL3	0x0da0	/* GP-DMA Channel 3 Next Address Low */
-#define SC520_GPDMANXTADDH3	0x0da2	/* GP-DMA Channel 3 Next Address High */
-#define SC520_GPDMANXTADDL5	0x0da4	/* GP-DMA Channel 5 Next Address Low */
-#define SC520_GPDMANXTADDH5	0x0da6	/* GP-DMA Channel 5 Next Address High */
-#define SC520_GPDMANXTADDL6	0x0da8	/* GP-DMA Channel 6 Next Address Low */
-#define SC520_GPDMANXTADDH6	0x0daa	/* GP-DMA Channel 6 Next Address High */
-#define SC520_GPDMANXTADDL7	0x0dac	/* GP-DMA Channel 7 Next Address Low */
-#define SC520_GPDMANXTADDH7	0x0dae	/* GP-DMA Channel 7 Next Address High */
-#define SC520_GPDMANXTTCL3	0x0db0	/* GP-DMA Channel 3 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH3	0x0db2	/* GP-DMA Channel 3 Next Transfer Count High */
-#define SC520_GPDMANXTTCL5	0x0db4	/* GP-DMA Channel 5 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH5	0x0db6	/* GP-DMA Channel 5 Next Transfer Count High */
-#define SC520_GPDMANXTTCL6	0x0db8	/* GP-DMA Channel 6 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH6	0x0dba	/* GP-DMA Channel 6 Next Transfer Count High */
-#define SC520_GPDMANXTTCL7	0x0dbc	/* GP-DMA Channel 7 Next Transfer Count Low */
-#define SC520_GPDMANXTTCH7	0x0dbe	/* GP-DMA Channel 7 Next Transfer Count High */
+#define SC520_SWTMRMILLI	0x0c60  /* Software Timer Millisecond Count */
+#define SC520_SWTMRMICRO	0x0c62  /* Software Timer Microsecond Count */
 
 /* MMCR Register bits (not all of them :) ) */
 
@@ -221,7 +285,6 @@
 #define SSISTA_BSY		0x02	/* SSI Busy */
 #define SSISTA_TC_INT		0x01	/* SSI Transaction Complete Interrupt */
 
-
 /* BITS for SC520_ADDDECCTL: */
 #define WPV_INT_ENB		0x80	/* Write-Protect Violation Interrupt Enable */
 #define IO_HOLE_DEST_PCI	0x10	/* I/O Hole Access Destination */
@@ -233,7 +296,6 @@
 #define SC520_REG_ADDR		0x00000cf8
 #define SC520_REG_DATA		0x00000cfc
 
-
 #define SC520_ISA_MEM_PHYS	0x00000000
 #define SC520_ISA_MEM_BUS	0x00000000
 #define SC520_ISA_MEM_SIZE	0x01000000
@@ -282,15 +344,4 @@
 #define SC520_IRQ14 9
 #define SC520_IRQ15 10
 
-/* utility functions */
-void write_mmcr_byte(u16 mmcr, u8 data);
-void write_mmcr_word(u16 mmcr, u16 data);
-void write_mmcr_long(u16 mmcr, u32 data);
-u8 read_mmcr_byte(u16 mmcr);
-u16 read_mmcr_word(u16 mmcr);
-u32 read_mmcr_long(u16 mmcr);
-
-void init_sc520(void);
-unsigned long init_sc520_dram(void);
-
 #endif

diff --git a/include/compiler.h b/include/compiler.h
index 272fd3c..e602cce 100644
--- a/include/compiler.h
+++ b/include/compiler.h

@@ -122,4 +122,7 @@
 
 #endif
 
+/* compiler options */
+#define uninitialized_var(x)		x = x
+
 #endif

diff --git a/include/configs/bf537-stamp.h b/include/configs/bf537-stamp.h
index 98300db..74b9ecd 100644
--- a/include/configs/bf537-stamp.h
+++ b/include/configs/bf537-stamp.h

@@ -178,9 +178,28 @@
 /*
  * CF-CARD IDE-HDD Support
  */
-/* #define CONFIG_BFIN_TRUE_IDE */	/* Add CF flash card support */
-/* #define CONFIG_BFIN_CF_IDE */	/* Add CF flash card support */
-/* #define CONFIG_BFIN_HDD_IDE */	/* Add IDE Disk Drive (HDD) support */
+
+/*
+ * Add CF flash card support in TRUE-IDE Mode (CF-IDE-NAND Card)
+ * Strange address mapping Blackfin A13 connects to CF_A0
+ */
+
+/* #define CONFIG_BFIN_TRUE_IDE */
+
+/*
+ * Add CF flash card support in Common Memory Mode (CF-IDE-NAND Card)
+ * This should be the preferred mode
+ */
+
+/* #define CONFIG_BFIN_CF_IDE */
+
+/*
+ * Add IDE Disk Drive (HDD) support
+ * See example interface here:
+ * http://docs.blackfin.uclinux.org/doku.php?id=linux-kernel:drivers:ide-blackfin
+ */
+
+/* #define CONFIG_BFIN_HDD_IDE */
 
 #if defined(CONFIG_BFIN_CF_IDE) || \
     defined(CONFIG_BFIN_HDD_IDE) || \
@@ -218,7 +237,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0020	/* data I/O */
 #define CONFIG_SYS_ATA_REG_OFFSET	0x0020	/* normal register accesses */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x001C	/* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.Ax */
+#define CONFIG_SYS_ATA_STRIDE		2	/* CF.A0 --> Blackfin.A13 */
 
 #elif defined(CONFIG_BFIN_CF_IDE)
 #define CONFIG_SYS_ATA_BASE_ADDR	0x20211800
@@ -226,7 +245,7 @@
 #define CONFIG_SYS_ATA_DATA_OFFSET	0x0000	/* data I/O */
 #define CONFIG_SYS_ATA_REG_OFFSET	0x0000	/* normal register accesses */
 #define CONFIG_SYS_ATA_ALT_OFFSET	0x000E	/* alternate registers */
-#define CONFIG_SYS_ATA_STRIDE		1	/* CF.A0 --> Blackfin.Ax */
+#define CONFIG_SYS_ATA_STRIDE		1	/* CF_A0=0, with /CE1 /CE2 odd/even byte selects */
 
 #elif defined(CONFIG_BFIN_HDD_IDE)
 #define CONFIG_SYS_ATA_BASE_ADDR	0x20314000

diff --git a/include/configs/bfin_adi_common.h b/include/configs/bfin_adi_common.h
index 1ca2e51..00bfc6e 100644
--- a/include/configs/bfin_adi_common.h
+++ b/include/configs/bfin_adi_common.h

@@ -12,6 +12,13 @@
 # include <config_cmd_default.h>
 # if ADI_CMDS_NETWORK
 #  define CONFIG_CMD_DHCP
+#  define CONFIG_BOOTP_SUBNETMASK
+#  define CONFIG_BOOTP_GATEWAY
+#  define CONFIG_BOOTP_DNS
+#  define CONFIG_BOOTP_NTPSERVER
+#  define CONFIG_BOOTP_RANDOM_DELAY
+#  define CONFIG_KEEP_SERVERADDR
+#  define CONFIG_CMD_DNS
 #  define CONFIG_CMD_PING
 #  ifdef CONFIG_BFIN_MAC
 #   define CONFIG_CMD_MII
@@ -46,6 +53,9 @@
 # endif
 # ifdef CONFIG_RTC_BFIN
 #  define CONFIG_CMD_DATE
+#  if ADI_CMDS_NETWORK
+#   define CONFIG_CMD_SNTP
+#  endif
 # endif
 # ifdef CONFIG_SPI
 #  define CONFIG_CMD_EEPROM
@@ -77,6 +87,9 @@
 #  define CONFIG_CMD_SPIBOOTLDR
 # endif
 #endif
+#ifdef CONFIG_CMD_NAND
+# define CONFIG_SYS_64BIT_VSPRINTF
+#endif
 
 /*
  * Console Settings
@@ -160,8 +173,8 @@
 		"nand write $(loadaddr) 0 0x40000"
 # else
 #  define UBOOT_ENV_UPDATE \
-		"protect off 0x20000000 0x2003FFFF;" \
-		"erase 0x20000000 0x2003FFFF;" \
+		"protect off 0x20000000 +$(filesize);" \
+		"erase 0x20000000 +$(filesize);" \
 		"cp.b $(loadaddr) 0x20000000 $(filesize)"
 # endif
 # define NETWORK_ENV_SETTINGS \

diff --git a/include/configs/cm-bf537u.h b/include/configs/cm-bf537u.h
new file mode 100644
index 0000000..d1870a8
--- /dev/null
+++ b/include/configs/cm-bf537u.h

@@ -0,0 +1,150 @@
+/*
+ * U-boot - Configuration file for CM-BF537U board
+ */
+
+#ifndef __CONFIG_CM_BF537U_H__
+#define __CONFIG_CM_BF537U_H__
+
+#include <asm/config-pre.h>
+
+
+/*
+ * Processor Settings
+ */
+#define CONFIG_BFIN_CPU             bf537-0.2
+#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_BYPASS
+
+
+/*
+ * Clock Settings
+ *	CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
+ *	SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
+ */
+/* CONFIG_CLKIN_HZ is any value in Hz					*/
+#define CONFIG_CLKIN_HZ			30000000
+/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN		*/
+/*                                                1 = CLKIN / 2		*/
+#define CONFIG_CLKIN_HALF		0
+/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass	*/
+/*                                                1 = bypass PLL	*/
+#define CONFIG_PLL_BYPASS		0
+/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL		*/
+/* Values can range from 0-63 (where 0 means 64)			*/
+#define CONFIG_VCO_MULT			18
+/* CCLK_DIV controls the core clock divider				*/
+/* Values can be 1, 2, 4, or 8 ONLY					*/
+#define CONFIG_CCLK_DIV			1
+/* SCLK_DIV controls the system clock divider				*/
+/* Values can range from 1-15						*/
+#define CONFIG_SCLK_DIV			5
+/* Core voltage */
+#define CONFIG_VR_CTL_VAL (VLEV_110 | GAIN_20 | FREQ_1000)
+
+
+/*
+ * Memory Settings
+ */
+#define CONFIG_MEM_ADD_WDTH	9
+#define CONFIG_MEM_SIZE		32
+
+#define CONFIG_EBIU_SDRRC_VAL	0x3f8
+#define CONFIG_EBIU_SDGCTL_VAL	0x9111cd
+
+#define CONFIG_EBIU_AMGCTL_VAL	(AMBEN_ALL)
+#define CONFIG_EBIU_AMBCTL0_VAL	(B1WAT_7 | B1RAT_11 | B1HT_2 | B1ST_3 | B0WAT_7 | B0RAT_11 | B0HT_2 | B0ST_3)
+#define CONFIG_EBIU_AMBCTL1_VAL	(B3WAT_7 | B3RAT_11 | B3HT_2 | B3ST_3 | B2WAT_7 | B2RAT_11 | B2HT_2 | B2ST_3)
+
+#define CONFIG_SYS_MONITOR_LEN	(256 * 1024)
+#define CONFIG_SYS_MALLOC_LEN	(128 * 1024)
+
+
+/*
+ * Network Settings
+ */
+#ifndef __ADSPBF534__
+#define ADI_CMDS_NETWORK	1
+#define CONFIG_NET_MULTI
+/* The next 3 lines are for use with SMSC on EXT-BF5xx-USB-ETH2 */
+#define CONFIG_SMC911X	1
+#define CONFIG_SMC911X_BASE	0x24000000
+#define CONFIG_SMC911X_16_BIT
+#endif
+#define CONFIG_HOSTNAME		cm-bf537u
+/* Uncomment next line to use fixed MAC address */
+/* #define CONFIG_ETHADDR	02:80:ad:20:31:e8 */
+
+
+/*
+ * Flash Settings
+ */
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#define CONFIG_SYS_FLASH_BASE		0x20000000
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_PROTECTION
+#define CONFIG_SYS_MAX_FLASH_BANKS	1
+#define CONFIG_SYS_MAX_FLASH_SECT	35
+
+
+/*
+ * Env Storage Settings
+ */
+#define CONFIG_ENV_IS_IN_FLASH	1
+#define CONFIG_ENV_OFFSET	0x4000
+#define CONFIG_ENV_SIZE		0x2000
+#define CONFIG_ENV_SECT_SIZE	0x20000
+#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS)
+#define ENV_IS_EMBEDDED
+#else
+#define ENV_IS_EMBEDDED_CUSTOM
+#endif
+#ifdef ENV_IS_EMBEDDED
+/* WARNING - the following is hand-optimized to fit within
+ * the sector before the environment sector. If it throws
+ * an error during compilation remove an object here to get
+ * it linked after the configuration sector.
+ */
+# define LDS_BOARD_TEXT \
+	cpu/blackfin/traps.o		(.text .text.*); \
+	cpu/blackfin/interrupt.o	(.text .text.*); \
+	cpu/blackfin/serial.o		(.text .text.*); \
+	common/dlmalloc.o		(.text .text.*); \
+	lib_generic/crc32.o		(.text .text.*); \
+	. = DEFINED(env_offset) ? env_offset : .; \
+	common/env_embedded.o		(.text .text.*);
+#endif
+
+
+/*
+ * I2C Settings
+ */
+#define CONFIG_BFIN_TWI_I2C	1
+#define CONFIG_HARD_I2C		1
+#define CONFIG_SYS_I2C_SPEED	50000
+#define CONFIG_SYS_I2C_SLAVE	0
+
+
+/*
+ * Misc Settings
+ */
+#define CONFIG_BAUDRATE		115200
+#define CONFIG_MISC_INIT_R
+#define CONFIG_RTC_BFIN
+#define CONFIG_UART_CONSOLE	0
+
+
+/*
+ * Pull in common ADI header for remaining command/environment setup
+ */
+#include <configs/bfin_adi_common.h>
+
+#undef CONFIG_BOOTCOMMAND
+#define CONFIG_BOOTCOMMAND	"run flashboot"
+
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	NAND_ENV_SETTINGS \
+	NETWORK_ENV_SETTINGS \
+	"flashboot=flread 20040000 1000000 280000; bootm 0x1000000\0"
+
+#endif

diff --git a/include/configs/eNET.h b/include/configs/eNET.h
index dde4c83..243a554 100644
--- a/include/configs/eNET.h
+++ b/include/configs/eNET.h

@@ -86,6 +86,7 @@
 #define CONFIG_CMD_MISC		/* Misc functions like sleep etc*/
 #undef CONFIG_CMD_NET		/* bootp, tftpboot, rarpboot	*/
 #undef CONFIG_CMD_NFS		/* NFS support			*/
+#define CONFIG_CMD_PCI		/* PCI support			*/
 #define CONFIG_CMD_RUN		/* run command in env variable	*/
 #define CONFIG_CMD_SAVEENV	/* saveenv			*/
 #define CONFIG_CMD_SETGETDCR	/* DCR support on 4xx		*/
@@ -188,26 +189,24 @@
   * Environment configuration
   */
 #define CONFIG_ENV_IS_IN_FLASH		1
-#define CONFIG_ENV_OFFSET		0x20000 /*   Offset   of Environment Sector */
-#define CONFIG_ENV_SIZE			0x08000 /* Total Size of Environment Sector */
 #define CONFIG_ENV_SECT_SIZE		0x20000 /* Total Size of Environment Sector */
-#define CONFIG_ENV_ADDR			(CONFIG_SYS_FLASH_BASE_1 + \
-					 CONFIG_ENV_OFFSET)
-#define CONFIG_ENV_OFFSET_REDUND	(CONFIG_ENV_OFFSET + \
+#define CONFIG_ENV_SIZE			CONFIG_ENV_SECT_SIZE
+#define CONFIG_ENV_ADDR			CONFIG_SYS_FLASH_BASE_1
+/* Redundant Copy */
+#define CONFIG_ENV_ADDR_REDUND		(CONFIG_SYS_FLASH_BASE_1 + \
 					 CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_SIZE_REDUND		(CONFIG_ENV_SIZE)
+#define CONFIG_ENV_SIZE_REDUND		CONFIG_ENV_SECT_SIZE
 
 
  /*-----------------------------------------------------------------------
   * PCI configuration
   */
-#undef CONFIG_PCI                                /* include pci support */
-#undef CONFIG_PCI_PNP                            /* pci plug-and-play */
-#undef CONFIG_PCI_SCAN_SHOW
-#undef CONFIG_SYS_FIRST_PCI_IRQ
-#undef CONFIG_SYS_SECOND_PCI_IRQ
-#undef CONFIG_SYS_THIRD_PCI_IRQ
-#undef CONFIG_SYS_FORTH_PCI_IRQ
+#define CONFIG_PCI                                /* include pci support */
+#define CONFIG_PCI_PNP                            /* pci plug-and-play */
+#define CONFIG_SYS_FIRST_PCI_IRQ   10
+#define CONFIG_SYS_SECOND_PCI_IRQ  9
+#define CONFIG_SYS_THIRD_PCI_IRQ   11
+#define CONFIG_SYS_FORTH_PCI_IRQ   15
 
 /*-----------------------------------------------------------------------
  * Hardware watchdog configuration

diff --git a/include/configs/galaxy5200.h b/include/configs/galaxy5200.h
index 8d530d8..a5b5a03 100644
--- a/include/configs/galaxy5200.h
+++ b/include/configs/galaxy5200.h

@@ -211,6 +211,11 @@
 #define CONFIG_SYS_CS1_SIZE		0x90000
 #define CONFIG_SYS_CS1_CFG		0x0002d900
 
+/* Chip Select configuration for Epson S1D13513 */
+#define CONFIG_SYS_CS3_START		0x10000000
+#define CONFIG_SYS_CS3_SIZE		0x400000
+#define CONFIG_SYS_CS3_CFG		0xffff3d10
+
 /*
  * Ethernet configuration
  */

diff --git a/include/configs/sc520_cdp.h b/include/configs/sc520_cdp.h
index 3e2bb02..214a9af 100644
--- a/include/configs/sc520_cdp.h
+++ b/include/configs/sc520_cdp.h

@@ -30,7 +30,6 @@
 
 #define CONFIG_SKIP_RELOCATE_UBOOT
 
-#define GRUSS_TESTING
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -85,11 +84,7 @@
 #include <config_cmd_default.h>
 
 #define CONFIG_CMD_PCI
-#ifndef GRUSS_TESTING
 #define CONFIG_CMD_SATA
-#else
-#undef CONFIG_CMD_SATA
-#endif
 #define CONFIG_CMD_JFFS2
 #define CONFIG_CMD_NET
 #define CONFIG_CMD_EEPROM
@@ -181,17 +176,10 @@
 /************************************************************
 *SATA/Native Stuff
 ************************************************************/
-#ifndef GRUSS_TESTING
 #define CONFIG_SYS_SATA_MAXBUS         2       /*Max Sata buses supported */
 #define CONFIG_SYS_SATA_DEVS_PER_BUS   2      /*Max no. of devices per bus/port */
 #define CONFIG_SYS_SATA_MAX_DEVICE     (CONFIG_SYS_SATA_MAXBUS* CONFIG_SYS_SATA_DEVS_PER_BUS)
 #define CONFIG_ATA_PIIX		1       /*Supports ata_piix driver */
-#else
-#undef CONFIG_SYS_SATA_MAXBUS
-#undef CONFIG_SYS_SATA_DEVS_PER_BUS
-#undef CONFIG_SYS_SATA_MAX_DEVICE
-#undef CONFIG_ATA_PIIX
-#endif
 
 
 /************************************************************
@@ -204,11 +192,9 @@
 /************************************************************
  * Video/Keyboard support
  ************************************************************/
-#ifndef GRUSS_TESTING
 #define CONFIG_VIDEO			/* To enable video controller support */
-#else
-#undef CONFIG_VIDEO
-#endif
+#define PCI_VIDEO_VENDOR_ID 0		/*Use the appropriate vendor ID*/
+#define PCI_VIDEO_DEVICE_ID 0		/*Use the appropriate Device ID*/
 #define CONFIG_I8042_KBD
 #define CONFIG_SYS_ISA_IO 0
 
@@ -221,7 +207,6 @@
 /*
  * PCI stuff
  */
-#ifndef GRUSS_TESTING
 #define CONFIG_PCI                                /* include pci support */
 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 #define CONFIG_PCI_SCAN_SHOW
@@ -230,11 +215,6 @@
 #define	CONFIG_SYS_SECOND_PCI_IRQ  9
 #define CONFIG_SYS_THIRD_PCI_IRQ   11
 #define	CONFIG_SYS_FORTH_PCI_IRQ   15
-#else
-#undef CONFIG_PCI
-#undef CONFIG_PCI_PNP
-#undef CONFIG_PCI_SCAN_SHOW
-#endif
 
 
 #endif	/* __CONFIG_H */

diff --git a/include/configs/sc520_spunk.h b/include/configs/sc520_spunk.h
index d42ef84..f3fc960 100644
--- a/include/configs/sc520_spunk.h
+++ b/include/configs/sc520_spunk.h

@@ -37,6 +37,7 @@
 
 #define CONFIG_X86		1	/* This is a X86 CPU		*/
 #define CONFIG_SYS_SC520	1	/* Include support for AMD SC520 */
+#define CONFIG_SYS_SC520_SSI
 
 #define CONFIG_SYS_SDRAM_PRECHARGE_DELAY 6     /* 6T */
 #define CONFIG_SYS_SDRAM_REFRESH_RATE    78    /* 7.8uS (choices are 7.8, 15.6, 31.2 or 62.5uS) */
@@ -218,6 +219,7 @@
 #define CONFIG_SYS_PCMCIA_CIS_WIN_SIZE     0x00100000
 #define CONFIG_SYS_PCMCIA_IO_WIN           0xe000
 #define CONFIG_SYS_PCMCIA_IO_WIN_SIZE      16
+#define CONFIG_PCMCIA_SLOT_A /* TODO: Check this */
 
 /************************************************************
  * DISK Partition support

diff --git a/include/ds1722.h b/include/ds1722.h
new file mode 100644
index 0000000..44f0830
--- /dev/null
+++ b/include/ds1722.h

@@ -0,0 +1,32 @@
+/*
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _DS1722_H_
+#define _DS1722_H_
+
+#define DS1722_RESOLUTION_8BIT	0x0
+#define DS1722_RESOLUTION_9BIT	0x1
+#define DS1722_RESOLUTION_10BIT	0x2
+#define DS1722_RESOLUTION_11BIT	0x3
+#define DS1722_RESOLUTION_12BIT	0x4
+
+int ds1722_probe(int dev);
+
+#endif /* _DS1722_H_ */

diff --git a/include/malloc.h b/include/malloc.h
index a38464e..3e145ad 100644
--- a/include/malloc.h
+++ b/include/malloc.h

@@ -937,6 +937,14 @@
 struct mallinfo mALLINFo();
 #endif
 
+/*
+ * Begin and End of memory area for malloc(), and current "brk"
+ */
+extern ulong mem_malloc_start;
+extern ulong mem_malloc_end;
+extern ulong mem_malloc_brk;
+
+void mem_malloc_init(ulong start, ulong size);
 
 #ifdef __cplusplus
 };  /* end of extern "C" */

diff --git a/include/ubi_uboot.h b/include/ubi_uboot.h
index 74312ab..60f6a5f 100644
--- a/include/ubi_uboot.h
+++ b/include/ubi_uboot.h

@@ -15,6 +15,7 @@
 #define __UBOOT_UBI_H
 
 #include <common.h>
+#include <compiler.h>
 #include <malloc.h>
 #include <div64.h>
 #include <linux/crc32.h>
@@ -51,9 +52,6 @@
 #undef CONFIG_MTD_UBI_DEBUG_MSG_BLD
 #define CONFIG_MTD_UBI_DEBUG_DISABLE_BGT
 
-/* compiler options */
-#define uninitialized_var(x)		x = x
-
 /* build.c */
 #define get_device(...)
 #define put_device(...)

diff --git a/lib_arm/board.c b/lib_arm/board.c
index fa87d51..a0e56d5 100644
--- a/lib_arm/board.c
+++ b/lib_arm/board.c

@@ -82,37 +82,6 @@
 #include <i2c.h>
 #endif
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static ulong mem_malloc_start = 0;
-static ulong mem_malloc_end = 0;
-static ulong mem_malloc_brk = 0;
-
-static
-void mem_malloc_init (ulong dest_addr)
-{
-	mem_malloc_start = dest_addr;
-	mem_malloc_end = dest_addr + CONFIG_SYS_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-
-	memset ((void *) mem_malloc_start, 0,
-			mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-
-	return ((void *) old);
-}
-
 
 /************************************************************************
  * Coloured LED functionality
@@ -320,7 +289,8 @@
 	}
 
 	/* armboot_start is defined in the board-specific linker script */
-	mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN);
+	mem_malloc_init (_armboot_start - CONFIG_SYS_MALLOC_LEN,
+			CONFIG_SYS_MALLOC_LEN);
 
 #ifndef CONFIG_SYS_NO_FLASH
 	/* configure available FLASH banks */

diff --git a/lib_arm/config.mk b/lib_arm/config.mk
index 705dfc3..3c078df 100644
--- a/lib_arm/config.mk
+++ b/lib_arm/config.mk

@@ -23,6 +23,16 @@
 
 CROSS_COMPILE ?= arm-linux-
 
+ifeq ($(BOARD),omap2420h4)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+ifeq ($(SOC),omap3)
+STANDALONE_LOAD_ADDR = 0x80300000
+else
+STANDALONE_LOAD_ADDR = 0xc100000
+endif
+endif
+
 PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__
 
 # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb:

diff --git a/lib_avr32/board.c b/lib_avr32/board.c
index e2b0a2e..29999d8 100644
--- a/lib_avr32/board.c
+++ b/lib_avr32/board.c

@@ -41,13 +41,6 @@
 
 unsigned long monitor_flash_len;
 
-/*
- * Begin and end of memory area for malloc(), and current "brk"
- */
-static unsigned long mem_malloc_start = 0;
-static unsigned long mem_malloc_end = 0;
-static unsigned long mem_malloc_brk = 0;
-
 /* Weak aliases for optional board functions */
 static int __do_nothing(void)
 {
@@ -56,35 +49,6 @@
 int board_postclk_init(void) __attribute__((weak, alias("__do_nothing")));
 int board_early_init_r(void) __attribute__((weak, alias("__do_nothing")));
 
-/* The malloc area is right below the monitor image in RAM */
-static void mem_malloc_init(void)
-{
-	unsigned long monitor_addr;
-
-	monitor_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
-	mem_malloc_end = monitor_addr;
-	mem_malloc_start = mem_malloc_end - CONFIG_SYS_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-
-	printf("malloc: Using memory from 0x%08lx to 0x%08lx\n",
-	       mem_malloc_start, mem_malloc_end);
-
-	memset ((void *)mem_malloc_start, 0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk(ptrdiff_t increment)
-{
-	unsigned long old = mem_malloc_brk;
-	unsigned long new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end))
-		return NULL;
-
-	mem_malloc_brk = new;
-	return ((void *)old);
-}
-
 #ifdef CONFIG_SYS_DMA_ALLOC_LEN
 #include <asm/arch/cacheflush.h>
 #include <asm/io.h>
@@ -331,7 +295,10 @@
 #endif
 
 	timer_init();
-	mem_malloc_init();
+
+	/* The malloc area is right below the monitor image in RAM */
+	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
+			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN);
 	malloc_bin_reloc();
 	dma_alloc_init();
 

diff --git a/lib_avr32/config.mk b/lib_avr32/config.mk
index c258b4b..1121ca1 100644
--- a/lib_avr32/config.mk
+++ b/lib_avr32/config.mk

@@ -23,5 +23,7 @@
 
 CROSS_COMPILE ?= avr32-linux-
 
+STANDALONE_LOAD_ADDR = 0x00000000
+
 PLATFORM_RELFLAGS	+= -ffixed-r5 -fPIC -mno-init-got -mrelax
 PLATFORM_LDFLAGS	+= --relax

diff --git a/lib_blackfin/board.c b/lib_blackfin/board.c
index b957a9d..1053f69 100644
--- a/lib_blackfin/board.c
+++ b/lib_blackfin/board.c

@@ -44,29 +44,6 @@
 #endif
 }
 
-static void *mem_malloc_start, *mem_malloc_end, *mem_malloc_brk;
-
-static void mem_malloc_init(void)
-{
-	mem_malloc_start = (void *)CONFIG_SYS_MALLOC_BASE;
-	mem_malloc_end = (void *)(CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN);
-	mem_malloc_brk = mem_malloc_start;
-	memset(mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk(ptrdiff_t increment)
-{
-	void *old = mem_malloc_brk;
-	void *new = old + increment;
-
-	if (new < mem_malloc_start || new > mem_malloc_end)
-		return NULL;
-
-	mem_malloc_brk = new;
-
-	return old;
-}
-
 static int display_banner(void)
 {
 	printf("\n\n%s\n\n", version_string);
@@ -93,25 +70,25 @@
 #ifdef CONFIG_DEBUG_EARLY_SERIAL
 	bd_t *bd;
 	bd = gd->bd;
-	printf(" gd: %x\n", gd);
-	printf(" |-flags: %x\n", gd->flags);
-	printf(" |-board_type: %x\n", gd->board_type);
-	printf(" |-baudrate: %i\n", gd->baudrate);
-	printf(" |-have_console: %x\n", gd->have_console);
-	printf(" |-ram_size: %x\n", gd->ram_size);
-	printf(" |-reloc_off: %x\n", gd->reloc_off);
-	printf(" |-env_addr: %x\n", gd->env_addr);
-	printf(" |-env_valid: %x\n", gd->env_valid);
-	printf(" |-jt(%x): %x\n", gd->jt, *(gd->jt));
-	printf(" \\-bd: %x\n", gd->bd);
+	printf(" gd: %p\n", gd);
+	printf(" |-flags: %lx\n", gd->flags);
+	printf(" |-board_type: %lx\n", gd->board_type);
+	printf(" |-baudrate: %lu\n", gd->baudrate);
+	printf(" |-have_console: %lx\n", gd->have_console);
+	printf(" |-ram_size: %lx\n", gd->ram_size);
+	printf(" |-reloc_off: %lx\n", gd->reloc_off);
+	printf(" |-env_addr: %lx\n", gd->env_addr);
+	printf(" |-env_valid: %lx\n", gd->env_valid);
+	printf(" |-jt(%p): %p\n", gd->jt, *(gd->jt));
+	printf(" \\-bd: %p\n", gd->bd);
 	printf("   |-bi_baudrate: %x\n", bd->bi_baudrate);
-	printf("   |-bi_ip_addr: %x\n", bd->bi_ip_addr);
-	printf("   |-bi_boot_params: %x\n", bd->bi_boot_params);
-	printf("   |-bi_memstart: %x\n", bd->bi_memstart);
-	printf("   |-bi_memsize: %x\n", bd->bi_memsize);
-	printf("   |-bi_flashstart: %x\n", bd->bi_flashstart);
-	printf("   |-bi_flashsize: %x\n", bd->bi_flashsize);
-	printf("   \\-bi_flashoffset: %x\n", bd->bi_flashoffset);
+	printf("   |-bi_ip_addr: %lx\n", bd->bi_ip_addr);
+	printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
+	printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
+	printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
+	printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
+	printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
+	printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
 #endif
 }
 
@@ -325,7 +302,7 @@
 #endif
 
 	/* initialize malloc() area */
-	mem_malloc_init();
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 	malloc_bin_reloc();
 
 #if	!defined(CONFIG_SYS_NO_FLASH)

diff --git a/lib_blackfin/config.mk b/lib_blackfin/config.mk
index a7e3658..ce2fe67 100644
--- a/lib_blackfin/config.mk
+++ b/lib_blackfin/config.mk

@@ -23,12 +23,14 @@
 
 CROSS_COMPILE ?= bfin-uclinux-
 
+STANDALONE_LOAD_ADDR = 0x1000
+
 CONFIG_BFIN_CPU := $(strip $(subst ",,$(CONFIG_BFIN_CPU)))
 CONFIG_BFIN_BOOT_MODE := $(strip $(subst ",,$(CONFIG_BFIN_BOOT_MODE)))
 CONFIG_ENV_OFFSET := $(strip $(subst ",,$(CONFIG_ENV_OFFSET)))
 CONFIG_ENV_SIZE := $(strip $(subst ",,$(CONFIG_ENV_SIZE)))
 
-PLATFORM_RELFLAGS += -ffixed-P5 -fomit-frame-pointer -mno-fdpic
+PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
 PLATFORM_CPPFLAGS += -DCONFIG_BLACKFIN
 
 LDFLAGS += --gc-sections

diff --git a/lib_generic/zlib.c b/lib_generic/zlib.c
index 1b6db32..8fe3bd0 100644
--- a/lib_generic/zlib.c
+++ b/lib_generic/zlib.c

@@ -27,6 +27,7 @@
 #define ZLIB_INTERNAL
 
 #include "u-boot/zlib.h"
+#include <common.h>
 /* To avoid a build time warning */
 #ifdef STDC
 #include <malloc.h>
@@ -83,10 +84,10 @@
 
 /* Diagnostic functions */
 #ifdef DEBUG
-#include <stdio.h>
 	extern int z_verbose;
 	extern void z_error    OF((char *m));
 #define Assert(cond,msg) {if(!(cond)) z_error(msg);}
+#define fprintf(fp,...)	printf(__VA_ARGS__)
 #define Trace(x) {if (z_verbose>=0) fprintf x ;}
 #define Tracev(x) {if (z_verbose>0) fprintf x ;}
 #define Tracevv(x) {if (z_verbose>1) fprintf x ;}
@@ -2000,7 +2001,7 @@
     char *m;
 {
 	fprintf(stderr, "%s\n", m);
-	exit(1);
+	hang ();
 }
 #endif
 

diff --git a/lib_i386/Makefile b/lib_i386/Makefile
index ec6f236..bb9b330 100644
--- a/lib_i386/Makefile
+++ b/lib_i386/Makefile

@@ -32,8 +32,8 @@
 COBJS-y	+= bios_setup.o
 COBJS-y	+= board.o
 COBJS-y	+= bootm.o
-COBJS-y	+= pci.o
-COBJS-y	+= pci_type1.o
+COBJS-$(CONFIG_PCI) += pci.o
+COBJS-$(CONFIG_PCI) += pci_type1.o
 COBJS-y	+= realmode.o
 COBJS-y	+= video_bios.o
 COBJS-y	+= video.o

diff --git a/lib_i386/board.c b/lib_i386/board.c
index 54ef6e7..0262b5e 100644
--- a/lib_i386/board.c
+++ b/lib_i386/board.c

@@ -73,14 +73,6 @@
 const char version_string[] =
 	U_BOOT_VERSION" (" U_BOOT_DATE " - " U_BOOT_TIME ")";
 
-
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static ulong mem_malloc_start = 0;
-static ulong mem_malloc_end = 0;
-static ulong mem_malloc_brk = 0;
-
 static int mem_malloc_init(void)
 {
 	/* start malloc area right after the stack */
@@ -96,19 +88,6 @@
 	return 0;
 }
 
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-
-	return ((void *) old);
-}
-
 /************************************************************************
  * Init Utilities							*
  ************************************************************************

diff --git a/lib_i386/config.mk b/lib_i386/config.mk
index 5fe36d5..4b990e0 100644
--- a/lib_i386/config.mk
+++ b/lib_i386/config.mk

@@ -23,4 +23,6 @@
 
 CROSS_COMPILE ?= i386-linux-
 
+STANDALONE_LOAD_ADDR = 0x40000
+
 PLATFORM_CPPFLAGS += -DCONFIG_I386 -D__I386__

diff --git a/lib_i386/pcat_timer.c b/lib_i386/pcat_timer.c
index e282f64..c351b23 100644
--- a/lib_i386/pcat_timer.c
+++ b/lib_i386/pcat_timer.c

@@ -25,10 +25,13 @@
 #include <asm/io.h>
 #include <asm/i8254.h>
 #include <asm/ibmpc.h>
+#include <asm/interrupt.h>
 
 #define TIMER0_VALUE 0x04aa /* 1kHz 1.9318MHz / 1000 */
 #define TIMER2_VALUE 0x0a8e /* 440Hz */
 
+static int timer_init_done = 0;
+
 int timer_init(void)
 {
 	/* initialize timer 0 and 2
@@ -52,6 +55,8 @@
 	irq_install_handler (0, timer_isr, NULL);
 	unmask_irq (0);
 
+	timer_init_done = 1;
+
 	return 0;
 }
 

diff --git a/lib_i386/pci.c b/lib_i386/pci.c
index 4331b04..9020e7c 100644
--- a/lib_i386/pci.c
+++ b/lib_i386/pci.c

@@ -26,7 +26,6 @@
 #include <asm/io.h>
 #include <asm/pci.h>
 
-#ifdef CONFIG_PCI
 #undef PCI_ROM_SCAN_VERBOSE
 
 int pci_shadow_rom(pci_dev_t dev, unsigned char *dest)
@@ -60,7 +59,7 @@
 	       vendor, device, class_code);
 #endif
 	/* Enable the rom addess decoder */
-	pci_write_config_dword(dev, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK);
+	pci_write_config_dword(dev, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
 	pci_read_config_dword(dev, PCI_ROM_ADDRESS, &addr_reg);
 
 	if (!addr_reg) {
@@ -151,5 +150,3 @@
 
 	return res;
 }
-
-#endif

diff --git a/lib_i386/pci_type1.c b/lib_i386/pci_type1.c
index 8da8c1c..225ae4a 100644
--- a/lib_i386/pci_type1.c
+++ b/lib_i386/pci_type1.c

@@ -11,9 +11,6 @@
  */
 
 #include <common.h>
-
-#ifdef CONFIG_PCI
-
 #include <asm/io.h>
 #include <pci.h>
 
@@ -52,5 +49,3 @@
 	hose->cfg_addr = (unsigned int *) cfg_addr;
 	hose->cfg_data = (unsigned char *) cfg_data;
 }
-
-#endif

diff --git a/lib_i386/video_bios.c b/lib_i386/video_bios.c
index ce96a3e..c8060e6 100644
--- a/lib_i386/video_bios.c
+++ b/lib_i386/video_bios.c

@@ -76,18 +76,22 @@
 }
 #endif
 
+#ifdef CONFIG_VIDEO
+
 #define PCI_CLASS_VIDEO             3
 #define PCI_CLASS_VIDEO_STD         0
 #define PCI_CLASS_VIDEO_PROG_IF_VGA 0
 
+static struct pci_device_id supported[] = {
+	{PCI_VIDEO_VENDOR_ID, PCI_VIDEO_DEVICE_ID},
+	{}
+};
 
 static u32 probe_pci_video(void)
 {
 	pci_dev_t devbusfn;
 
-	if ((devbusfn = pci_find_class(PCI_CLASS_VIDEO,
-				       PCI_CLASS_VIDEO_STD,
-				       PCI_CLASS_VIDEO_PROG_IF_VGA, 0)) != -1) {
+	if ((devbusfn = pci_find_devices(supported, 0) != -1)) {
 		u32 old;
 		u32 addr;
 
@@ -103,7 +107,7 @@
 
 		/* Test the ROM decoder, do the device support a rom? */
 		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &old);
-		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, PCI_ROM_ADDRESS_MASK);
+		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, (u32)PCI_ROM_ADDRESS_MASK);
 		pci_read_config_dword(devbusfn, PCI_ROM_ADDRESS, &addr);
 		pci_write_config_dword(devbusfn, PCI_ROM_ADDRESS, old);
 
@@ -133,11 +137,6 @@
 	return 0;
 }
 
-
-#endif
-
-#ifdef CONFIG_VIDEO
-
 static int probe_isa_video(void)
 {
 	u32 ptr;
@@ -220,3 +219,4 @@
 
 }
 #endif
+#endif

diff --git a/lib_m68k/board.c b/lib_m68k/board.c
index 483c9b6..3d88530 100644
--- a/lib_m68k/board.c
+++ b/lib_m68k/board.c

@@ -101,48 +101,12 @@
 
 ulong monitor_flash_len;
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static	ulong	mem_malloc_start = 0;
-static	ulong	mem_malloc_end	 = 0;
-static	ulong	mem_malloc_brk	 = 0;
-
 /************************************************************************
  * Utilities								*
  ************************************************************************
  */
 
 /*
- * The Malloc area is immediately below the monitor copy in DRAM
- */
-static void mem_malloc_init (void)
-{
-	ulong dest_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
-
-	mem_malloc_end = dest_addr;
-	mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-
-	memset ((void *) mem_malloc_start,
-		0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) ||
-	    (new > mem_malloc_end) ) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *)old);
-}
-
-/*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
  * requirements are just _too_ different. To get rid of the resulting
@@ -518,8 +482,9 @@
 	 */
 	trap_init (CONFIG_SYS_SDRAM_BASE);
 
-	/* initialize malloc() area */
-	mem_malloc_init ();
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	mem_malloc_init (CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
+			TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
 	malloc_bin_reloc ();
 
 #if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/lib_m68k/config.mk b/lib_m68k/config.mk
index f41d1b3..749c389 100644
--- a/lib_m68k/config.mk
+++ b/lib_m68k/config.mk

@@ -23,5 +23,8 @@
 
 CROSS_COMPILE ?= m68k-elf-
 
+clibdir = $(shell dirname `$(CC) $(CFLAGS) -print-file-name=libc.a`)
+STANDALONE_LOAD_ADDR = 0x20000 -L $(clibdir)
+
 PLATFORM_CPPFLAGS += -DCONFIG_M68K -D__M68K__
 PLATFORM_LDFLAGS  += -n

diff --git a/lib_microblaze/board.c b/lib_microblaze/board.c
index cfed5fe..200ea5d 100644
--- a/lib_microblaze/board.c
+++ b/lib_microblaze/board.c

@@ -47,38 +47,6 @@
 #endif
 
 /*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static ulong mem_malloc_start;
-static ulong mem_malloc_end;
-static ulong mem_malloc_brk;
-
-/*
- * The Malloc area is immediately below the monitor copy in DRAM
- * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
- * as our monitory code is run from SDRAM
- */
-static void mem_malloc_init (void)
-{
-	mem_malloc_end = (CONFIG_SYS_MALLOC_BASE + CONFIG_SYS_MALLOC_LEN);
-	mem_malloc_start = CONFIG_SYS_MALLOC_BASE;
-	mem_malloc_brk = mem_malloc_start;
-	memset ((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *)old);
-}
-
-/*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
  * requirements are just _too_ different. To get rid of the resulting
@@ -122,8 +90,12 @@
 	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
 	gd->flags |= GD_FLG_RELOC;      /* tell others: relocation done */
 
-	/* Initialise malloc() area */
-	mem_malloc_init ();
+	/*
+	 * The Malloc area is immediately below the monitor copy in DRAM
+	 * aka CONFIG_SYS_MONITOR_BASE - Note there is no need for reloc_off
+	 * as our monitory code is run from SDRAM
+	 */
+	mem_malloc_init (CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 
 	for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) {
 		WATCHDOG_RESET ();

diff --git a/lib_microblaze/config.mk b/lib_microblaze/config.mk
index 68e7e21..c3c9f95 100644
--- a/lib_microblaze/config.mk
+++ b/lib_microblaze/config.mk

@@ -26,4 +26,6 @@
 
 CROSS_COMPILE ?= mb-
 
+STANDALONE_LOAD_ADDR = 0x80F00000
+
 PLATFORM_CPPFLAGS += -ffixed-r31 -D__microblaze__

diff --git a/lib_mips/board.c b/lib_mips/board.c
index aa5b129..f62a46a 100644
--- a/lib_mips/board.c
+++ b/lib_mips/board.c

@@ -60,13 +60,6 @@
 static char *failed = "*** failed ***\n";
 
 /*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static ulong mem_malloc_start;
-static ulong mem_malloc_end;
-static ulong mem_malloc_brk;
-
-/*
  * mips_io_port_base is the begin of the address space to which x86 style
  * I/O ports are mapped.
  */
@@ -81,34 +74,6 @@
 }
 int board_early_init_f(void) __attribute__((weak, alias("__board_early_init_f")));
 
-/*
- * The Malloc area is immediately below the monitor copy in DRAM
- */
-static void mem_malloc_init (void)
-{
-	ulong dest_addr = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
-
-	mem_malloc_end = dest_addr;
-	mem_malloc_start = dest_addr - TOTAL_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-
-	memset ((void *) mem_malloc_start,
-		0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *) old);
-}
-
 
 static int init_func_ram (void)
 {
@@ -370,8 +335,9 @@
 
 	bd = gd->bd;
 
-	/* initialize malloc() area */
-	mem_malloc_init();
+	/* The Malloc area is immediately below the monitor copy in DRAM */
+	mem_malloc_init(CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
+			TOTAL_MALLOC_LEN, TOTAL_MALLOC_LEN);
 	malloc_bin_reloc();
 
 #ifndef CONFIG_SYS_NO_FLASH

diff --git a/lib_mips/config.mk b/lib_mips/config.mk
index c785677..aa06761 100644
--- a/lib_mips/config.mk
+++ b/lib_mips/config.mk

@@ -23,6 +23,8 @@
 
 CROSS_COMPILE ?= mips_4KC-
 
+STANDALONE_LOAD_ADDR = 0x80200000 -T mips.lds
+
 PLATFORM_CPPFLAGS += -DCONFIG_MIPS -D__MIPS__
 
 #

diff --git a/lib_nios/board.c b/lib_nios/board.c
index cd23457..72713a8 100644
--- a/lib_nios/board.c
+++ b/lib_nios/board.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <stdio_dev.h>
 #include <watchdog.h>
+#include <malloc.h>
 #include <net.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -51,38 +52,6 @@
 extern void malloc_bin_reloc (void);
 typedef int (init_fnc_t) (void);
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static	ulong	mem_malloc_start = 0;
-static	ulong	mem_malloc_end	 = 0;
-static	ulong	mem_malloc_brk	 = 0;
-
-/*
- * The Malloc area is immediately below the monitor copy in RAM
- */
-static void mem_malloc_init (void)
-{
-	mem_malloc_start = CONFIG_SYS_MALLOC_BASE;
-	mem_malloc_end = mem_malloc_start + CONFIG_SYS_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-	memset ((void *) mem_malloc_start,
-		0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *) old);
-}
-
 
 /************************************************************************
  * Initialization sequence						*
@@ -143,7 +112,9 @@
 	}
 
 	WATCHDOG_RESET ();
-	mem_malloc_init();
+
+	/* The Malloc area is immediately below the monitor copy in RAM */
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 	malloc_bin_reloc();
 
 	WATCHDOG_RESET ();

diff --git a/lib_nios/config.mk b/lib_nios/config.mk
index 3ed7170..d48aa6d 100644
--- a/lib_nios/config.mk
+++ b/lib_nios/config.mk

@@ -24,4 +24,6 @@
 
 CROSS_COMPILE ?= nios-elf-
 
+STANDALONE_LOAD_ADDR = 0x00800000 -L $(gcclibdir)/m32 -T nios.lds
+
 PLATFORM_CPPFLAGS += -m32 -DCONFIG_NIOS -D__NIOS__ -ffixed-g7 -gstabs

diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index b142c59..c6b36f4 100644
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c

@@ -27,6 +27,7 @@
 #include <common.h>
 #include <stdio_dev.h>
 #include <watchdog.h>
+#include <malloc.h>
 #include <net.h>
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
@@ -54,38 +55,6 @@
 extern void malloc_bin_reloc (void);
 typedef int (init_fnc_t) (void);
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static	ulong	mem_malloc_start = 0;
-static	ulong	mem_malloc_end	 = 0;
-static	ulong	mem_malloc_brk	 = 0;
-
-/*
- * The Malloc area is immediately below the monitor copy in RAM
- */
-static void mem_malloc_init (void)
-{
-	mem_malloc_start = CONFIG_SYS_MALLOC_BASE;
-	mem_malloc_end = mem_malloc_start + CONFIG_SYS_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-	memset ((void *) mem_malloc_start,
-		0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *) old);
-}
-
 
 /************************************************************************
  * Initialization sequence						*
@@ -149,7 +118,9 @@
 	}
 
 	WATCHDOG_RESET ();
-	mem_malloc_init();
+
+	/* The Malloc area is immediately below the monitor copy in RAM */
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE, CONFIG_SYS_MALLOC_LEN);
 	malloc_bin_reloc();
 
 	WATCHDOG_RESET ();

diff --git a/lib_nios2/config.mk b/lib_nios2/config.mk
index 59931c2..34ee697 100644
--- a/lib_nios2/config.mk
+++ b/lib_nios2/config.mk

@@ -24,5 +24,7 @@
 
 CROSS_COMPILE ?= nios2-elf-
 
+STANDALONE_LOAD_ADDR = 0x02000000 -L $(gcclibdir) -T nios2.lds
+
 PLATFORM_CPPFLAGS += -DCONFIG_NIOS2 -D__NIOS2__
 PLATFORM_CPPFLAGS += -ffixed-r15 -G0

diff --git a/lib_ppc/board.c b/lib_ppc/board.c
index 9faf7f2..d9a12a1 100644
--- a/lib_ppc/board.c
+++ b/lib_ppc/board.c

@@ -136,47 +136,12 @@
 #include <bedbug/type.h>
 #endif
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static	ulong	mem_malloc_start = 0;
-static	ulong	mem_malloc_end	 = 0;
-static	ulong	mem_malloc_brk	 = 0;
-
 /************************************************************************
  * Utilities								*
  ************************************************************************
  */
 
 /*
- * The Malloc area is immediately below the monitor copy in DRAM
- */
-static void mem_malloc_init (void)
-{
-#if !defined(CONFIG_RELOC_FIXUP_WORKS)
-	mem_malloc_end = CONFIG_SYS_MONITOR_BASE + gd->reloc_off;
-#endif
-	mem_malloc_start = mem_malloc_end - TOTAL_MALLOC_LEN;
-	mem_malloc_brk = mem_malloc_start;
-
-	memset ((void *) mem_malloc_start,
-		0,
-		mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk (ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *) old);
-}
-
-/*
  * All attempts to come up with a "common" initialization sequence
  * that works for all boards and architectures failed: some of the
  * requirements are just _too_ different. To get rid of the resulting
@@ -669,6 +634,7 @@
 #ifndef CONFIG_ENV_IS_NOWHERE
 	extern char * env_name_spec;
 #endif
+	ulong malloc_start;
 
 #ifndef CONFIG_SYS_NO_FLASH
 	ulong flash_size;
@@ -679,11 +645,14 @@
 
 	gd->flags |= GD_FLG_RELOC;	/* tell others: relocation done */
 
+	/* The Malloc area is immediately below the monitor copy in DRAM */
 #if defined(CONFIG_RELOC_FIXUP_WORKS)
 	gd->reloc_off = 0;
-	mem_malloc_end = dest_addr;
+	malloc_start = dest_addr - TOTAL_MALLOC_LEN;
 #else
 	gd->reloc_off = dest_addr - CONFIG_SYS_MONITOR_BASE;
+	malloc_start = CONFIG_SYS_MONITOR_BASE + gd->reloc_off -
+			TOTAL_MALLOC_LEN;
 #endif
 
 #ifdef CONFIG_SERIAL_MULTI
@@ -778,8 +747,7 @@
 
 	asm ("sync ; isync");
 
-	/* initialize malloc() area */
-	mem_malloc_init ();
+	mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN);
 	malloc_bin_reloc ();
 
 #if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/lib_ppc/config.mk b/lib_ppc/config.mk
index d91ef7f..010d874 100644
--- a/lib_ppc/config.mk
+++ b/lib_ppc/config.mk

@@ -23,6 +23,8 @@
 
 CROSS_COMPILE ?= ppc_8xx-
 
+STANDALONE_LOAD_ADDR = 0x40000
+
 PLATFORM_CPPFLAGS += -DCONFIG_PPC -D__powerpc__
 PLATFORM_LDFLAGS  += -n
 

diff --git a/lib_sh/board.c b/lib_sh/board.c
index 829455d..5d61f0d 100644
--- a/lib_sh/board.c
+++ b/lib_sh/board.c

@@ -38,34 +38,6 @@
 
 unsigned long monitor_flash_len = CONFIG_SYS_MONITOR_LEN;
 
-static unsigned long mem_malloc_start;
-static unsigned long mem_malloc_end;
-static unsigned long mem_malloc_brk;
-
-static void mem_malloc_init(void)
-{
-
-	mem_malloc_start = (TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE - CONFIG_SYS_MALLOC_LEN);
-	mem_malloc_end = (mem_malloc_start + CONFIG_SYS_MALLOC_LEN - 16);
-	mem_malloc_brk = mem_malloc_start;
-	memset((void *) mem_malloc_start, 0,
-		(mem_malloc_end - mem_malloc_start));
-}
-
-void *sbrk(ptrdiff_t increment)
-{
-	unsigned long old = mem_malloc_brk;
-	unsigned long new = old + increment;
-
-	if ((new < mem_malloc_start) ||
-	    (new > mem_malloc_end)) {
-		return NULL;
-	}
-
-	mem_malloc_brk = new;
-	return (void *) old;
-}
-
 static int sh_flash_init(void)
 {
 	DECLARE_GLOBAL_DATA_PTR;
@@ -114,7 +86,8 @@
 
 static int sh_mem_env_init(void)
 {
-	mem_malloc_init();
+	mem_malloc_init(TEXT_BASE - CONFIG_SYS_GBL_DATA_SIZE -
+			CONFIG_SYS_MALLOC_LEN, CONFIG_SYS_MALLOC_LEN - 16);
 	malloc_bin_reloc();
 	env_relocate();
 	jumptable_init();

diff --git a/lib_sh/config.mk b/lib_sh/config.mk
index 67d7e9e..fa5369f 100644
--- a/lib_sh/config.mk
+++ b/lib_sh/config.mk

@@ -23,6 +23,11 @@
 
 CROSS_COMPILE ?= sh4-linux-
 
+STANDALONE_LOAD_ADDR = 0x8C000000
+ifeq ($(CPU),sh2)
+STANDALONE_LOAD_ADDR += -EB
+endif
+
 PLATFORM_CPPFLAGS += -DCONFIG_SH -D__SH__
 PLATFORM_LDFLAGS += -e $(TEXT_BASE) --defsym reloc_dst=$(TEXT_BASE)
 

diff --git a/lib_sparc/board.c b/lib_sparc/board.c
index d40834b..6aadb56 100644
--- a/lib_sparc/board.c
+++ b/lib_sparc/board.c

@@ -74,43 +74,6 @@
 
 ulong monitor_flash_len;
 
-/*
- * Begin and End of memory area for malloc(), and current "brk"
- */
-static ulong mem_malloc_start = 0;
-static ulong mem_malloc_end = 0;
-static ulong mem_malloc_brk = 0;
-
-/************************************************************************
- * Utilities								*
- ************************************************************************
- */
-
-/*
- * The Malloc area is immediately below the monitor copy in RAM
- */
-static void mem_malloc_init(void)
-{
-	mem_malloc_start = CONFIG_SYS_MALLOC_BASE;
-	mem_malloc_end = CONFIG_SYS_MALLOC_END;
-	mem_malloc_brk = mem_malloc_start;
-	memset((void *)mem_malloc_start, 0, mem_malloc_end - mem_malloc_start);
-}
-
-void *sbrk(ptrdiff_t increment)
-{
-	ulong old = mem_malloc_brk;
-	ulong new = old + increment;
-
-	if ((new < mem_malloc_start) || (new > mem_malloc_end)) {
-		return (NULL);
-	}
-	mem_malloc_brk = new;
-	return ((void *)old);
-}
-
-/***********************************************************************/
-
 /************************************************************************
  * Init Utilities							*
  ************************************************************************
@@ -331,8 +294,9 @@
 	 */
 	interrupt_init();
 
-	/* initialize malloc() area */
-	mem_malloc_init();
+	/* The Malloc area is immediately below the monitor copy in RAM */
+	mem_malloc_init(CONFIG_SYS_MALLOC_BASE,
+			CONFIG_SYS_MALLOC_END - CONFIG_SYS_MALLOC_BASE);
 	malloc_bin_reloc();
 
 #if !defined(CONFIG_SYS_NO_FLASH)

diff --git a/lib_sparc/config.mk b/lib_sparc/config.mk
index 07b528c..4de6515 100644
--- a/lib_sparc/config.mk
+++ b/lib_sparc/config.mk

@@ -23,4 +23,6 @@
 
 CROSS_COMPILE ?= sparc-elf-
 
+STANDALONE_LOAD_ADDR = 0x00000000 -L $(gcclibdir) -T sparc.lds
+
 PLATFORM_CPPFLAGS += -DCONFIG_SPARC -D__sparc__

diff --git a/tools/mkimage.c b/tools/mkimage.c
index 02cdb95..7fd9fd1 100644
--- a/tools/mkimage.c
+++ b/tools/mkimage.c

@@ -4,7 +4,6 @@
  * (C) Copyright 2000-2004
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as

diff --git a/tools/mkimage.h b/tools/mkimage.h
index 70c53ad..c077dc9 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h

@@ -2,7 +2,6 @@
  * (C) Copyright 2000-2004
  * DENX Software Engineering
  * Wolfgang Denk, wd@denx.de
- * All rights reserved.
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as