powerpc/85xx: Add support for Freescale P1023/P1017 Processors
Add P1023 (dual core) & P1017 (single core) specific information:
* SERDES Table
* Added P1023/P1017 to cpu_type_list and SVR list
(fixed issue with P1013 not being sorted correctly).
* Added P1023/P1027 to config_mpc85xx.h
* Added new LAW type introduced on P1023/P1017
* Updated a few immap register/defines unique to P1023/P1017
Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h
index b014ec6..9437301 100644
--- a/arch/powerpc/include/asm/config_mpc85xx.h
+++ b/arch/powerpc/include/asm/config_mpc85xx.h
@@ -121,6 +121,16 @@
#define CONFIG_TSECV2
#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#elif defined(CONFIG_P1017)
+#define CONFIG_MAX_CPUS 1
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_QMAN_NUM_PORTALS 3
+#define CONFIG_SYS_BMAN_NUM_PORTALS 3
+
#elif defined(CONFIG_P1020)
#define CONFIG_MAX_CPUS 2
#define CONFIG_SYS_FSL_NUM_LAWS 12
@@ -144,6 +154,16 @@
#define CONFIG_SYS_FSL_ERRATUM_ESDHC111
#define CONFIG_FSL_SATA_ERRATUM_A001
+#elif defined(CONFIG_P1023)
+#define CONFIG_MAX_CPUS 2
+#define CONFIG_SYS_FSL_NUM_LAWS 12
+#define CONFIG_SYS_FSL_SEC_COMPAT 4
+#define CONFIG_SYS_NUM_FMAN 1
+#define CONFIG_SYS_NUM_FM1_DTSEC 2
+#define CONFIG_NUM_DDR_CONTROLLERS 1
+#define CONFIG_SYS_QMAN_NUM_PORTALS 3
+#define CONFIG_SYS_BMAN_NUM_PORTALS 3
+
#elif defined(CONFIG_P2010)
#define CONFIG_MAX_CPUS 1
#define CONFIG_SYS_FSL_NUM_LAWS 12
diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h
index ae45f9b..13caffd 100644
--- a/arch/powerpc/include/asm/fsl_law.h
+++ b/arch/powerpc/include/asm/fsl_law.h
@@ -83,6 +83,7 @@
LAW_TRGT_IF_DDR_INTRLV = 0x0b,
LAW_TRGT_IF_RIO = 0x0c,
LAW_TRGT_IF_RIO_2 = 0x0d,
+ LAW_TRGT_IF_DPAA_SWP_SRAM = 0x0e,
LAW_TRGT_IF_DDR = 0x0f,
LAW_TRGT_IF_DDR_2 = 0x16, /* 2nd controller */
};
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index f239e59..ce27fec 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1865,8 +1865,13 @@
#define MPC85xx_PORBMSR_HA_SHIFT 16
u32 porimpscr; /* POR I/O impedance status & control */
u32 pordevsr; /* POR I/O device status regsiter */
+#if defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_SGMII1_DIS 0x10000000
+#define MPC85xx_PORDEVSR_SGMII2_DIS 0x08000000
+#else
#define MPC85xx_PORDEVSR_SGMII1_DIS 0x20000000
#define MPC85xx_PORDEVSR_SGMII2_DIS 0x10000000
+#endif
#define MPC85xx_PORDEVSR_SGMII3_DIS 0x08000000
#define MPC85xx_PORDEVSR_SGMII4_DIS 0x04000000
#define MPC85xx_PORDEVSR_SRDS2_IO_SEL 0x38000000
@@ -1874,6 +1879,9 @@
#if defined(CONFIG_P1013) || defined(CONFIG_P1022)
#define MPC85xx_PORDEVSR_IO_SEL 0x007c0000
#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 18
+#elif defined(CONFIG_P1017) || defined(CONFIG_P1023)
+#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
+#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21
#else
#if defined(CONFIG_P1010)
#define MPC85xx_PORDEVSR_IO_SEL 0x00600000
@@ -2247,6 +2255,12 @@
#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100
#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000
#define CONFIG_SYS_MPC85xx_CPM_OFFSET 0x80000
+#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000
+#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000
+#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000
+#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000
+#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000
+#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000
#endif
#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000
diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h
index fcee1a2..d8b8f34 100644
--- a/arch/powerpc/include/asm/processor.h
+++ b/arch/powerpc/include/asm/processor.h
@@ -1048,12 +1048,16 @@
#define SVR_P1013_E 0x80EF00
#define SVR_P1014 0x80F101
#define SVR_P1014_E 0x80F901
+#define SVR_P1017 0x80F700
+#define SVR_P1017_E 0x80FF00
#define SVR_P1020 0x80E400
#define SVR_P1020_E 0x80EC00
#define SVR_P1021 0x80E401
#define SVR_P1021_E 0x80EC01
#define SVR_P1022 0x80E600
#define SVR_P1022_E 0x80EE00
+#define SVR_P1023 0x80F600
+#define SVR_P1023_E 0x80FE00
#define SVR_P2010 0x80E300
#define SVR_P2010_E 0x80EB00
#define SVR_P2020 0x80E200
