73b5396b25c52463aa71c782316e2d77a4b8d5ed - u-boot

commit: 73b5396b25c52463aa71c782316e2d77a4b8d5ed
[log]
author: York Sun <yorksun@freescale.com>
Fri Aug 17 08:22:37 2012 +0000
committer: Andy Fleming <afleming@freescale.com>
Thu Aug 23 12:16:55 2012 -0500
tree: b6e82b205f1dc1a2d4a1eac37ec136cbe22822fa
parent: 744713a6a3ca19c77585a9452829a2e2a55693ad [diff]

powerpc/mpc8xxx: Add fine timing support for DDR3

When the DDR3 speed goes higher, we need to utilize fine offset
from SPD.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>

arch/powerpc/cpu/mpc8xxx/ddr/ddr3_dimm_params.c[diff]
arch/powerpc/cpu/mpc8xxx/ddr/interactive.c[diff]
arch/powerpc/include/asm/fsl_ddr_dimm_params.h[diff]
include/ddr_spd.h[diff]

4 files changed

tree: b6e82b205f1dc1a2d4a1eac37ec136cbe22822fa