Patch by Pantelis Antoniou, 5 May 2004:
- Intracom board update.
- Add Codec POST.
diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index b720ec5..1d12eb4 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -65,8 +65,8 @@
#undef CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND \
"tftpboot; " \
- "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
- "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
+ "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
+ "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \
"bootm"
#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
@@ -108,18 +108,22 @@
/* POST support */
#define CONFIG_POST (CFG_POST_MEMORY | \
+ CFG_POST_CODEC | \
CFG_POST_DSP )
#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \
- CFG_CMD_NAND | \
+ CFG_CMD_CDP | \
CFG_CMD_DHCP | \
- CFG_CMD_PING | \
- CFG_CMD_MII | \
- CFG_CMD_PCMCIA | CFG_CMD_IDE | CFG_CMD_FAT | \
CFG_CMD_DIAG | \
+ CFG_CMD_FAT | \
+ CFG_CMD_IDE | \
+ CFG_CMD_JFFS2 | \
+ CFG_CMD_MII | \
+ CFG_CMD_NAND | \
CFG_CMD_NFS | \
- CFG_CMD_CDP \
- )
+ CFG_CMD_PCMCIA | \
+ CFG_CMD_PING | \
+ 0)
#define CONFIG_BOARD_EARLY_INIT_F 1
#define CONFIG_MISC_INIT_R
@@ -339,18 +343,20 @@
*-----------------------------------------------------------------------
* Set clock output, timebase and RTC source and divider,
* power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
*/
#define SCCR_MASK SCCR_EBDF11
#if MPC8XX_HZ > 66666666
-#define CFG_SCCR (SCCR_TBS | \
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL001 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00 | SCCR_EBDF01)
#else
-#define CFG_SCCR (SCCR_TBS | \
+#define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \
SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
- SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
+ SCCR_DFNL111 | SCCR_DFNH000 | SCCR_DFLCD000 | \
SCCR_DFALCD00)
#endif
@@ -604,10 +610,11 @@
/* NAND */
#define CFG_NAND_BASE NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
#define CFG_MAX_NAND_DEVICE 1
-#define NAND_NO_RB
+/* #define NAND_NO_RB */
#define SECTORSIZE 512
#define ADDR_COLUMN 1
@@ -677,6 +684,17 @@
#define READ_NAND(adr) \
((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
+#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */
+#define CONFIG_JFFS2_NAND_DEV 0 /* nand device jffs2 lives on */
+#define CONFIG_JFFS2_NAND_OFF (2 * 1024 * 1024) /* start of jffs2 partition */
+#define CONFIG_JFFS2_NAND_SIZE (1*1024*1024) /* size of jffs2 partition */
+#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
/*****************************************************************************/
#if 1
