Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux) Patch by Stefan Roese, 08 Aug 2005
diff --git a/cpu/ppc4xx/405gp_enet.c b/cpu/ppc4xx/405gp_enet.c index b60d122..968f0ce 100644 --- a/cpu/ppc4xx/405gp_enet.c +++ b/cpu/ppc4xx/405gp_enet.c
@@ -227,7 +227,7 @@ while (mfdcr (malmcr) & MAL_CR_MMSR) { }; -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) out32 (ZMII_FER, 0); udelay(100); /* set RII mode */ @@ -464,7 +464,7 @@ out32(ZMII_SSR, in32(ZMII_SSR) | 0x10000000); else out32(ZMII_SSR, in32(ZMII_SSR) & ~0x10000000); -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); /* set speed */ if (speed == _100BASET) {
diff --git a/cpu/ppc4xx/405gp_pci.c b/cpu/ppc4xx/405gp_pci.c index ebbcfd5..89be137 100644 --- a/cpu/ppc4xx/405gp_pci.c +++ b/cpu/ppc4xx/405gp_pci.c
@@ -437,7 +437,7 @@ * The PCI initialization sequence enable bit must be set ... if not abort * pci setup since updating the bit requires chip reset. *--------------------------------------------------------------------------*/ -#if defined (CONFIG_440_GX) || defined (CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined (CONFIG_440GX) || defined (CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_sdstp1,strap); if ( (strap & 0x00010000) == 0 ){ printf("PCI: SDR0_STRP1[PISE] not set.\n"); @@ -495,7 +495,7 @@ out16r( PCIX0_CLS, 0x00060000 ); /* Bridge, host bridge */ #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) out32r( PCIX0_BRDGOPT1, 0x04000060 ); /* PLB Rq pri highest */ out32r( PCIX0_BRDGOPT2, in32(PCIX0_BRDGOPT2) | 0x83 ); /* Enable host config, clear Timeout, ensure int src1 */ #elif defined(PCIX0_BRDGOPT1) @@ -531,7 +531,7 @@ #ifdef CONFIG_PCI_SCAN_SHOW printf("PCI: Bus Dev VenId DevId Class Int\n"); #endif -#if !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR) +#if !defined(CONFIG_440EP) && !defined(CONFIG_440GR) out16r( PCIX0_CMD, in16r( PCIX0_CMD ) | PCI_COMMAND_MASTER); #endif hose->last_busno = pci_hose_scan(hose);
diff --git a/cpu/ppc4xx/440gx_enet.c b/cpu/ppc4xx/440gx_enet.c index f4004fb..63227fa 100644 --- a/cpu/ppc4xx/440gx_enet.c +++ b/cpu/ppc4xx/440gx_enet.c
@@ -175,7 +175,7 @@ extern int phy_setup_aneg (unsigned char addr); extern int miiphy_reset (unsigned char addr); -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) int ppc_440x_eth_setup_bridge(int devnum, bd_t * bis) { unsigned long pfc1; @@ -279,7 +279,7 @@ unsigned short devnum; unsigned short reg_short; sys_info_t sysinfo; -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) int ethgroup; #endif @@ -323,7 +323,7 @@ /* MAL Channel RESET */ /* 1st reset MAL channel */ /* Note: writing a 0 to a channel has no effect */ -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) mtdcr (maltxcarr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); #else mtdcr (maltxcarr, (MAL_TXRX_CASR >> hw_p->devnum)); @@ -362,9 +362,9 @@ out32 (ZMII_FER, 0); udelay (100); -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) out32 (ZMII_FER, (ZMII_FER_RMII | ZMII_FER_MDI) << ZMII_FER_V (devnum)); -#elif defined(CONFIG_440_GX) +#elif defined(CONFIG_440GX) ethgroup = ppc_440x_eth_setup_bridge(devnum, bis); #else if ((devnum == 0) || (devnum == 1)) { @@ -391,7 +391,7 @@ failsafe--; } -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) /* Whack the M1 register */ mode_reg = 0x0; mode_reg &= ~0x00000038; @@ -406,7 +406,7 @@ mode_reg |= EMAC_M1_OBCI_GT100; out32 (EMAC_M1 + hw_p->hw_addr, mode_reg); -#endif /* defined(CONFIG_440_GX) */ +#endif /* defined(CONFIG_440GX) */ /* wait for PHY to complete auto negotiation */ reg_short = 0; @@ -418,7 +418,7 @@ case 1: reg = CONFIG_PHY1_ADDR; break; -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) case 2: reg = CONFIG_PHY2_ADDR; break; @@ -441,7 +441,7 @@ if (hw_p->first_init == 0) { miiphy_reset (reg); -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) #if defined(CONFIG_CIS8201_PHY) /* * Cicada 8201 PHY needs to have an extended register whacked @@ -512,7 +512,7 @@ (int) speed, (duplex == HALF) ? "HALF" : "FULL"); } -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) mfsdr(sdr_mfr, reg); if (speed == 100) { reg = (reg & ~SDR0_MFR_ZMII_MODE_MASK) | SDR0_MFR_ZMII_MODE_RMII_100M; @@ -541,7 +541,7 @@ } /* set the Mal configuration reg */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) mtdcr (malmcr, MAL_CR_PLBB | MAL_CR_OPBBL | MAL_CR_LEA | MAL_CR_PLBLT_DEFAULT | MAL_CR_EOPIE | 0x00330000); #else @@ -642,7 +642,7 @@ switch (devnum) { case 1: /* setup MAL tx & rx channel pointers */ -#if defined (CONFIG_440_EP) || defined (CONFIG_440_GR) +#if defined (CONFIG_440EP) || defined (CONFIG_440GR) mtdcr (maltxctp2r, hw_p->tx); #else mtdcr (maltxctp1r, hw_p->tx); @@ -653,7 +653,7 @@ /* set RX buffer size */ mtdcr (malrcbs1, ENET_MAX_MTU_ALIGNED / 16); break; -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) case 2: /* setup MAL tx & rx channel pointers */ mtdcr (maltxbattr, 0x0); @@ -672,7 +672,7 @@ /* set RX buffer size */ mtdcr (malrcbs3, ENET_MAX_MTU_ALIGNED / 16); break; -#endif /*CONFIG_440_GX */ +#endif /*CONFIG_440GX */ case 0: default: /* setup MAL tx & rx channel pointers */ @@ -686,7 +686,7 @@ } /* Enable MAL transmit and receive channels */ -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) mtdcr (maltxcasr, (MAL_TXRX_CASR >> (hw_p->devnum*2))); #else mtdcr (maltxcasr, (MAL_TXRX_CASR >> hw_p->devnum)); @@ -836,7 +836,7 @@ unsigned long mal_rx_eob; unsigned long my_uic0msr, my_uic1msr; -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) unsigned long my_uic2msr; #endif EMAC_440GX_HW_PST hw_p; @@ -856,7 +856,7 @@ my_uic0msr = mfdcr (uic0msr); my_uic1msr = mfdcr (uic1msr); -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) my_uic2msr = mfdcr (uic2msr); #endif if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) @@ -866,7 +866,7 @@ /* not for us */ return (rc); } -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) if (!(my_uic0msr & (UIC_MRE | UIC_MTE)) && !(my_uic2msr & (UIC_ETH2 | UIC_ETH3))) { /* not for us */ @@ -922,7 +922,7 @@ return (rc); /* we had errors so get out */ } } -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) if (hw_p->devnum == 2) { if (UIC_ETH2 & my_uic2msr) { /* look for EMAC errors */ emac_isr = in32 (EMAC_ISR + hw_p->hw_addr); @@ -958,7 +958,7 @@ return (rc); /* we had errors so get out */ } } -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ /* handle MAX TX EOB interrupt from a tx */ if (my_uic0msr & UIC_MTE) { mal_rx_eob = mfdcr (maltxeobisr); @@ -987,14 +987,14 @@ case 1: mtdcr (uic1sr, UIC_ETH1); break; -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) case 2: mtdcr (uic2sr, UIC_ETH2); break; case 3: mtdcr (uic2sr, UIC_ETH3); break; -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ default: break; } @@ -1184,7 +1184,7 @@ int eth_num = 0; EMAC_440GX_HW_PST hw = NULL; -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) unsigned long pfc1; mfsdr (sdr_pfc1, pfc1); @@ -1197,7 +1197,7 @@ #if defined(CONFIG_PHY1_ADDR) bis->bi_phynum[1] = CONFIG_PHY1_ADDR; #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) bis->bi_phynum[2] = CONFIG_PHY2_ADDR; bis->bi_phynum[3] = CONFIG_PHY3_ADDR; bis->bi_phymode[0] = 0; @@ -1205,7 +1205,7 @@ bis->bi_phymode[2] = 2; bis->bi_phymode[3] = 2; -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) ppc_440x_eth_setup_bridge(0, bis); #endif #endif
diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index 3a4b5d0..a9bb89a 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c
@@ -178,7 +178,7 @@ case PVR_440GX_RC: puts("GX Rev. C"); break; -#if defined(CONFIG_440_GR) +#if defined(CONFIG_440GR) case PVR_440EP_RA: puts("GR Rev. A"); break;
diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 74f0135..68e1a45 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c
@@ -188,7 +188,7 @@ unsigned long val; val = mfspr(tcr); -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) val |= 0xb8000000; /* generate system reset after 1.34 seconds */ #else val |= 0xf0000000; /* generate system reset after 2.684 seconds */
diff --git a/cpu/ppc4xx/interrupts.c b/cpu/ppc4xx/interrupts.c index c0e51f9..1d8dc7c 100644 --- a/cpu/ppc4xx/interrupts.c +++ b/cpu/ppc4xx/interrupts.c
@@ -54,12 +54,12 @@ void uic1_interrupt( void * parms); /* UIC1 handler */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) static struct irq_action irq_vecs2[32]; /* For UIC2 */ void uic0_interrupt( void * parms); /* UIC0 handler */ void uic2_interrupt( void * parms); /* UIC2 handler */ -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #endif /* CONFIG_440 */ @@ -115,11 +115,11 @@ irq_vecs1[vec].handler = NULL; irq_vecs1[vec].arg = NULL; irq_vecs1[vec].count = 0; -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) irq_vecs2[vec].handler = NULL; irq_vecs2[vec].arg = NULL; irq_vecs2[vec].count = 0; -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #endif } @@ -162,14 +162,14 @@ set_evpr(0x00000000); #if defined(CONFIG_440) -#if !defined(CONFIG_440_GX) +#if !defined(CONFIG_440GX) /* Install the UIC1 handlers */ irq_install_handler(VECNUM_UIC1NC, uic1_interrupt, 0); irq_install_handler(VECNUM_UIC1C, uic1_interrupt, 0); #endif #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) /* Take the GX out of compatibility mode * Travis Sawyer, 9 Mar 2004 * NOTE: 440gx user manual inconsistency here @@ -195,7 +195,7 @@ /* * Handle external interrupts */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) void external_interrupt(struct pt_regs *regs) { ulong uic_msr; @@ -219,7 +219,7 @@ return; -} /* external_interrupt CONFIG_440_GX */ +} /* external_interrupt CONFIG_440GX */ #else @@ -266,7 +266,7 @@ } #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) /* Handler for UIC0 interrupt */ void uic0_interrupt( void * parms) { @@ -310,7 +310,7 @@ } } -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #if defined(CONFIG_440) /* Handler for UIC1 interrupt */ @@ -357,7 +357,7 @@ } #endif /* defined(CONFIG_440) */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) /* Handler for UIC1 interrupt */ void uic2_interrupt( void * parms) { @@ -400,7 +400,7 @@ vec++; } } -#endif /* defined(CONFIG_440_GX) */ +#endif /* defined(CONFIG_440GX) */ /****************************************************************************/ @@ -414,7 +414,7 @@ int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) if ((vec > 31) && (vec < 64)) { i = vec - 32; irqa = irq_vecs1; @@ -422,12 +422,12 @@ i = vec - 64; irqa = irq_vecs2; } -#else /* CONFIG_440_GX */ +#else /* CONFIG_440GX */ if (vec > 31) { i = vec - 32; irqa = irq_vecs1; } -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #endif /* CONFIG_440 */ /* @@ -441,13 +441,13 @@ irqa[i].arg = arg; #if defined(CONFIG_440) -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); else if (vec > 63) mtdcr (uic2er, mfdcr (uic2er) | (0x80000000 >> i)); else -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ if (vec > 31) mtdcr (uic1er, mfdcr (uic1er) | (0x80000000 >> i)); else @@ -464,7 +464,7 @@ int i = vec; #if defined(CONFIG_440) -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) if ((vec > 31) && (vec < 64)) { irqa = irq_vecs1; i = vec - 32; @@ -472,7 +472,7 @@ irqa = irq_vecs2; i = vec - 64; } -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ if (vec > 31) { irqa = irq_vecs1; i = vec - 32; @@ -485,13 +485,13 @@ #endif #if defined(CONFIG_440) -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) if ((vec > 31) && (vec < 64)) mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); else if (vec > 63) mtdcr (uic2er, mfdcr (uic2er) & ~(0x80000000 >> i)); else -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ if (vec > 31) mtdcr (uic1er, mfdcr (uic1er) & ~(0x80000000 >> i)); else @@ -553,7 +553,7 @@ printf("\n"); #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) printf ("\nUIC 2\n"); printf ("Nr Routine Arg Count\n");
diff --git a/cpu/ppc4xx/miiphy_440.c b/cpu/ppc4xx/miiphy_440.c index bbe535a..6320fea 100644 --- a/cpu/ppc4xx/miiphy_440.c +++ b/cpu/ppc4xx/miiphy_440.c
@@ -165,13 +165,13 @@ } sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) sta_reg |= EMAC_STACR_READ; #else sta_reg = (sta_reg | EMAC_STACR_READ) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; #endif sta_reg = sta_reg | (addr << 5); /* Phy address */ @@ -225,13 +225,13 @@ sta_reg = 0; sta_reg = reg; /* reg address */ /* set clock (50Mhz) and read flags */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) sta_reg |= EMAC_STACR_WRITE; #else sta_reg = (sta_reg | EMAC_STACR_WRITE) & ~EMAC_STACR_CLK_100MHZ; #endif -#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440_GX) +#if defined(CONFIG_PHY_CLK_FREQ) && !defined(CONFIG_440GX) sta_reg = sta_reg | CONFIG_PHY_CLK_FREQ; /* Set clock frequency (PLB freq. dependend) */ #endif sta_reg = sta_reg | ((unsigned long) addr << 5); /* Phy address */
diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index 92f8ddb..8cf7dab 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c
@@ -269,14 +269,14 @@ #if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405EP) #if defined(CONFIG_440) -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000300 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000400 #else #define UART0_BASE CFG_PERIPHERAL_BASE + 0x00000200 #define UART1_BASE CFG_PERIPHERAL_BASE + 0x00000300 #endif -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) #define CR0_MASK 0xdfffffff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 @@ -284,7 +284,7 @@ #define CR0_MASK 0x3fff0000 #define CR0_EXTCLK_ENA 0x00600000 #define CR0_UDIV_POS 16 -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #elif defined(CONFIG_405EP) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 @@ -306,17 +306,17 @@ #if defined(CONFIG_UART1_CONSOLE) #define ACTING_UART0_BASE UART1_BASE #define ACTING_UART1_BASE UART0_BASE -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) #define UART0_SDR sdr_uart1 #define UART1_SDR sdr_uart0 -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #else #define ACTING_UART0_BASE UART0_BASE #define ACTING_UART1_BASE UART1_BASE -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) #define UART0_SDR sdr_uart0 #define UART1_SDR sdr_uart1 -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #endif #if defined(CONFIG_405EP) && defined(CFG_EXT_SERIAL_CLOCK) @@ -436,7 +436,7 @@ unsigned long tmp; #endif -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) { mfsdr(UART0_SDR,reg); @@ -451,7 +451,7 @@ #endif #else reg = mfdcr(cntrl0) & ~CR0_MASK; -#endif /* CONFIG_440_GX */ +#endif /* CONFIG_440GX */ #ifdef CFG_EXT_SERIAL_CLOCK reg |= CR0_EXTCLK_ENA; udiv = 1; @@ -465,7 +465,7 @@ serial_divs (gd->baudrate, &udiv, &bdiv); #endif -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) reg |= udiv << CR0_UDIV_POS; /* set the UART divisor */ #if defined(CONFIG_SERIAL_MULTI) if (UART0_BASE == dev_base) {
diff --git a/cpu/ppc4xx/spd_sdram.c b/cpu/ppc4xx/spd_sdram.c index e2eab62..a8cfcd4 100644 --- a/cpu/ppc4xx/spd_sdram.c +++ b/cpu/ppc4xx/spd_sdram.c
@@ -734,7 +734,7 @@ */ check_volt_type(dimm_populated, iic0_dimm_addr, num_dimm_banks); -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) /* * Soft-reset SDRAM controller. */
diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 7a4af75..469f97d 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c
@@ -195,7 +195,7 @@ #elif defined(CONFIG_440) -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) void get_sys_info (sys_info_t *sysInfo) { unsigned long temp; @@ -283,7 +283,7 @@ return sys_info.freqPCI; } -#elif !defined(CONFIG_440_GX) +#elif !defined(CONFIG_440GX) void get_sys_info (sys_info_t * sysInfo) { unsigned long strp0;
diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 730f3ca..003c5b6 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S
@@ -166,7 +166,7 @@ mtspr srr1,r0 mtspr csrr0,r0 mtspr csrr1,r0 -#if defined (CONFIG_440_GX) /* NOTE: 440GX adds machine check status regs */ +#if defined (CONFIG_440GX) /* NOTE: 440GX adds machine check status regs */ mtspr mcsrr0,r0 mtspr mcsrr1,r0 mfspr r1, mcsr @@ -340,11 +340,11 @@ mtspr tcr,r0 /* disable all */ mtspr esr,r0 /* clear exception syndrome register */ mtxer r0 /* clear integer exception register */ -#if !defined(CONFIG_440_GX) +#if !defined(CONFIG_440GX) lis r1,0x0002 /* set CE bit (Critical Exceptions) */ ori r1,r1,0x1000 /* set ME bit (Machine Exceptions) */ mtmsr r1 /* change MSR */ -#elif !defined(CONFIG_440_EP) && !defined(CONFIG_440_GR) +#elif !defined(CONFIG_440EP) && !defined(CONFIG_440GR) bl __440gx_msr_set b __440gx_msr_continue @@ -377,7 +377,7 @@ /* Setup the internal SRAM */ /*----------------------------------------------------------------*/ li r0,0 -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) /* Clear Dcache to use as RAM */ addis r3,r0,CFG_INIT_RAM_ADDR@h ori r3,r3,CFG_INIT_RAM_ADDR@l @@ -394,7 +394,7 @@ addi r3,r3,32 bdnz ..d_ag #else -#if defined (CONFIG_440_GX) +#if defined (CONFIG_440GX) mtdcr l2_cache_cfg,r0 /* Ensure L2 Cache is off */ #endif mtdcr isram0_sb1cr,r0 /* Disable bank 1 */ @@ -409,7 +409,7 @@ mtdcr isram0_pmeg,r1 lis r1,0x8000 /* BAS = 8000_0000 */ -#if defined(CONFIG_440_GX) +#if defined(CONFIG_440GX) ori r1,r1,0x0980 /* first 64k */ mtdcr isram0_sb0cr,r1 lis r1,0x8001 @@ -975,7 +975,7 @@ invalidate_dcache: addi r6,0,0x0000 /* clear GPR 6 */ /* Do loop for # of dcache congruence classes. */ -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) lis r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS for large sized cache */ ori r7, r7, (CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l #else @@ -1001,7 +1001,7 @@ mtdccr r10 /* do loop for # of congruence classes. */ -#if defined(CONFIG_440_GX) || defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440GX) || defined(CONFIG_440EP) || defined(CONFIG_440GR) lis r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@ha /* TBS: for large cache sizes */ ori r10,r10,(CFG_DCACHE_SIZE / CFG_CACHELINE_SIZE / 2)@l lis r11,(CFG_DCACHE_SIZE / 2)@ha /* D cache set size - 2 way sets */ @@ -1228,7 +1228,7 @@ */ .globl relocate_code relocate_code: -#if defined(CONFIG_440_EP) || defined(CONFIG_440_GR) +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) dccci 0,0 /* Invalidate data cache, now no longer our stack */ sync addi r1,r0,0x0000 /* Tlb entry #0 */
diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index d53909e..bb57658 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c
@@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#ifdef CONFIG_440_EP +#ifdef CONFIG_440EP #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else
diff --git a/cpu/ppc4xx/usbdev.c b/cpu/ppc4xx/usbdev.c index 4741f73..8262c54 100644 --- a/cpu/ppc4xx/usbdev.c +++ b/cpu/ppc4xx/usbdev.c
@@ -3,7 +3,7 @@ #include <common.h> #include <asm/processor.h> -#ifdef CONFIG_440_EP +#ifdef CONFIG_440EP #include <usb.h> #include "usbdev.h" @@ -211,4 +211,4 @@ NULL); } -#endif /*CONFIG_440_EP */ +#endif /*CONFIG_440EP */